1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 /* ************************************************************
17 * include files
18 * ************************************************************ */
19 #include "mp_precomp.h"
20 #include "phydm_precomp.h"
21
22 void
phydm_h2C_debug(void * p_dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)23 phydm_h2C_debug(
24 void *p_dm_void,
25 u32 *const dm_value,
26 u32 *_used,
27 char *output,
28 u32 *_out_len
29 )
30 {
31 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
32 u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
33 u8 phydm_h2c_id = (u8)dm_value[0];
34 u8 i;
35 u32 used = *_used;
36 u32 out_len = *_out_len;
37
38 PHYDM_SNPRINTF((output + used, out_len - used, "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id));
39 for (i = 0; i < H2C_MAX_LENGTH; i++) {
40
41 h2c_parameter[i] = (u8)dm_value[i + 1];
42 PHYDM_SNPRINTF((output + used, out_len - used, "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]));
43 }
44
45 odm_fill_h2c_cmd(p_dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
46
47 *_used = used;
48 *_out_len = out_len;
49 }
50
51 void
phydm_fw_fix_rate(void * p_dm_void,u8 en,u8 macid,u8 bw,u8 rate)52 phydm_fw_fix_rate(
53 void *p_dm_void,
54 u8 en,
55 u8 macid,
56 u8 bw,
57 u8 rate
58
59 )
60 {
61 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
62 u32 reg_u32_tmp;
63
64 if (p_dm->support_ic_type & PHYDM_IC_8051_SERIES) {
65
66 reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;
67 odm_set_bb_reg(p_dm, 0x4a0, MASKDWORD, reg_u32_tmp);
68
69 } else {
70
71 if (en == 1)
72 reg_u32_tmp = (0x60 << 24) | (macid << 16) | (bw << 8) | rate;
73 else
74 reg_u32_tmp = 0x40000000;
75
76 odm_set_bb_reg(p_dm, 0x450, MASKDWORD, reg_u32_tmp);
77 }
78 if (en == 1) {
79 PHYDM_DBG(p_dm, ODM_COMP_API, ("FW fix TX rate[id =%d], %dM, Rate(%d)=", macid, (20 << bw), rate));
80 phydm_print_rate(p_dm, rate, ODM_COMP_API);
81 } else {
82 PHYDM_DBG(p_dm, ODM_COMP_API, ("Auto Rate\n"));
83 }
84 }
85
86 void
phydm_ra_debug(void * p_dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)87 phydm_ra_debug(
88 void *p_dm_void,
89 char input[][16],
90 u32 *_used,
91 char *output,
92 u32 *_out_len
93 )
94 {
95 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
96 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
97 u32 used = *_used;
98 u32 out_len = *_out_len;
99 char help[] = "-h";
100 u32 var1[5] = {0};
101 u8 i = 0;
102 u32 reg_u32_tmp;
103
104 for (i = 0; i < 5; i++) {
105 if (input[i + 1])
106 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
107 }
108
109 if ((strcmp(input[1], help) == 0)) {
110 PHYDM_SNPRINTF((output + used, out_len - used, "{1} {0:-,1:+} {ofst}: set offset\n"));
111 PHYDM_SNPRINTF((output + used, out_len - used, "{1} {100}: show offset\n"));
112 PHYDM_SNPRINTF((output + used, out_len - used, "{2} {en} {macid} {bw} {rate}: fw fix rate\n"));
113
114 } else if (var1[0] == 1) { /*Adjust PCR offset*/
115
116 if (var1[1] == 100) {
117 PHYDM_SNPRINTF((output + used, out_len - used, "[Get] RA_ofst=((%s%d))\n",
118 ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset));
119
120 } else if (var1[1] == 0) {
121 p_ra_table->RA_offset_direction = 0;
122 p_ra_table->RA_threshold_offset = (u8)var1[2];
123 PHYDM_SNPRINTF((output + used, out_len - used, "[Set] RA_ofst=((-%d))\n", p_ra_table->RA_threshold_offset));
124 } else if (var1[1] == 1) {
125 p_ra_table->RA_offset_direction = 1;
126 p_ra_table->RA_threshold_offset = (u8)var1[2];
127 PHYDM_SNPRINTF((output + used, out_len - used, "[Set] RA_ofst=((+%d))\n", p_ra_table->RA_threshold_offset));
128 }
129
130 } else if (var1[0] == 2) { /*FW fix rate*/
131
132 PHYDM_SNPRINTF((output + used, out_len - used,
133 "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}", var1[1], var1[2], var1[3], var1[4]));
134
135 phydm_fw_fix_rate(p_dm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u8)var1[4]);
136
137 } else {
138 PHYDM_SNPRINTF((output + used, out_len - used, "[Set] Error\n"));
139 /**/
140 }
141 *_used = used;
142 *_out_len = out_len;
143 }
144
145
146
147 void
odm_c2h_ra_para_report_handler(void * p_dm_void,u8 * cmd_buf,u8 cmd_len)148 odm_c2h_ra_para_report_handler(
149 void *p_dm_void,
150 u8 *cmd_buf,
151 u8 cmd_len
152 )
153 {
154 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
155 #if (defined(CONFIG_RA_DBG_CMD))
156 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
157 #endif
158
159 u8 para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/
160 #if (defined(CONFIG_RA_DBG_CMD))
161 u8 rate_type_start = cmd_buf[1];
162 u8 rate_type_length = cmd_len - 2;
163 #endif
164 u8 i;
165
166
167 PHYDM_DBG(p_dm, DBG_RA, ("[ From FW C2H RA Para ] cmd_buf[0]= (( %d ))\n", cmd_buf[0]));
168
169 #if (defined(CONFIG_RA_DBG_CMD))
170 if (para_idx == RADBG_RTY_PENALTY) {
171 PHYDM_DBG(p_dm, DBG_RA, (" |rate index| |RTY Penality index|\n"));
172
173 for (i = 0 ; i < (rate_type_length) ; i++) {
174 if (p_ra_table->is_ra_dbg_init)
175 p_ra_table->RTY_P_default[rate_type_start + i] = cmd_buf[2 + i];
176
177 p_ra_table->RTY_P[rate_type_start + i] = cmd_buf[2 + i];
178 PHYDM_DBG(p_dm, DBG_RA, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RTY_P[rate_type_start + i]));
179 }
180
181 } else if (para_idx == RADBG_N_HIGH) {
182 /**/
183 PHYDM_DBG(p_dm, DBG_RA, (" |rate index| |N-High|\n"));
184
185
186 } else if (para_idx == RADBG_N_LOW) {
187 PHYDM_DBG(p_dm, DBG_RA, (" |rate index| |N-Low|\n"));
188 /**/
189 } else if (para_idx == RADBG_RATE_UP_RTY_RATIO) {
190 PHYDM_DBG(p_dm, DBG_RA, (" |rate index| |rate Up RTY Ratio|\n"));
191
192 for (i = 0; i < (rate_type_length); i++) {
193 if (p_ra_table->is_ra_dbg_init)
194 p_ra_table->RATE_UP_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i];
195
196 p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i];
197 PHYDM_DBG(p_dm, DBG_RA, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i]));
198 }
199 } else if (para_idx == RADBG_RATE_DOWN_RTY_RATIO) {
200 PHYDM_DBG(p_dm, DBG_RA, (" |rate index| |rate Down RTY Ratio|\n"));
201
202 for (i = 0; i < (rate_type_length); i++) {
203 if (p_ra_table->is_ra_dbg_init)
204 p_ra_table->RATE_DOWN_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i];
205
206 p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i];
207 PHYDM_DBG(p_dm, DBG_RA, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i]));
208 }
209 } else
210 #endif
211 if (para_idx == RADBG_DEBUG_MONITOR1) {
212 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("-------------------------------\n"));
213 if (p_dm->support_ic_type & PHYDM_IC_3081_SERIES) {
214
215 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "RSSI =", cmd_buf[1]));
216 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "rate =", cmd_buf[2] & 0x7f));
217 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "SGI =", (cmd_buf[2] & 0x80) >> 7));
218 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "BW =", cmd_buf[3]));
219 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "BW_max =", cmd_buf[4]));
220 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "multi_rate0 =", cmd_buf[5]));
221 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "multi_rate1 =", cmd_buf[6]));
222 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "DISRA =", cmd_buf[7]));
223 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "VHT_EN =", cmd_buf[8]));
224 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "SGI_support =", cmd_buf[9]));
225 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "try_ness =", cmd_buf[10]));
226 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "pre_rate =", cmd_buf[11]));
227 } else {
228 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "RSSI =", cmd_buf[1]));
229 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %x\n", "BW =", cmd_buf[2]));
230 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "DISRA =", cmd_buf[3]));
231 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "VHT_EN =", cmd_buf[4]));
232 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "Hightest rate =", cmd_buf[5]));
233 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "Lowest rate =", cmd_buf[6]));
234 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "SGI_support =", cmd_buf[7]));
235 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "Rate_ID =", cmd_buf[8]));
236 }
237 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("-------------------------------\n"));
238 } else if (para_idx == RADBG_DEBUG_MONITOR2) {
239 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("-------------------------------\n"));
240 if (p_dm->support_ic_type & PHYDM_IC_3081_SERIES) {
241 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "rate_id =", cmd_buf[1]));
242 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "highest_rate =", cmd_buf[2]));
243 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "lowest_rate =", cmd_buf[3]));
244
245 for (i = 4; i <= 11; i++)
246 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("RAMASK = 0x%x\n", cmd_buf[i]));
247 } else {
248 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %x%x %x%x %x%x %x%x\n", "RA Mask:",
249 cmd_buf[8], cmd_buf[7], cmd_buf[6], cmd_buf[5], cmd_buf[4], cmd_buf[3], cmd_buf[2], cmd_buf[1]));
250 }
251 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("-------------------------------\n"));
252 } else if (para_idx == RADBG_DEBUG_MONITOR3) {
253
254 for (i = 0; i < (cmd_len - 1); i++)
255 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("content[%d] = %d\n", i, cmd_buf[1 + i]));
256 } else if (para_idx == RADBG_DEBUG_MONITOR4)
257 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s {%d.%d}\n", "RA version =", cmd_buf[1], cmd_buf[2]));
258 else if (para_idx == RADBG_DEBUG_MONITOR5) {
259 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "Current rate =", cmd_buf[1]));
260 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "Retry ratio =", cmd_buf[2]));
261 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s %d\n", "rate down ratio =", cmd_buf[3]));
262 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x\n", "highest rate =", cmd_buf[4]));
263 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s {0x%x 0x%x}\n", "Muti-try =", cmd_buf[5], cmd_buf[6]));
264 PHYDM_DBG(p_dm, DBG_FW_TRACE, ("%5s 0x%x%x%x%x%x\n", "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], cmd_buf[7]));
265 }
266 }
267
268 void
phydm_ra_dynamic_retry_count(void * p_dm_void)269 phydm_ra_dynamic_retry_count(
270 void *p_dm_void
271 )
272 {
273 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
274
275 if (!(p_dm->support_ability & ODM_BB_DYNAMIC_ARFR))
276 return;
277
278 /*PHYDM_DBG(p_dm, DBG_RA, ("p_dm->pre_b_noisy = %d\n", p_dm->pre_b_noisy ));*/
279 if (p_dm->pre_b_noisy != p_dm->noisy_decision) {
280
281 if (p_dm->noisy_decision) {
282 PHYDM_DBG(p_dm, DBG_RA, ("Noisy Env. RA fallback\n"));
283 odm_set_mac_reg(p_dm, 0x430, MASKDWORD, 0x0);
284 odm_set_mac_reg(p_dm, 0x434, MASKDWORD, 0x04030201);
285 } else {
286 PHYDM_DBG(p_dm, DBG_RA, ("Clean Env. RA fallback\n"));
287 odm_set_mac_reg(p_dm, 0x430, MASKDWORD, 0x01000000);
288 odm_set_mac_reg(p_dm, 0x434, MASKDWORD, 0x06050402);
289 }
290 p_dm->pre_b_noisy = p_dm->noisy_decision;
291 }
292 }
293
294 void
phydm_print_rate(void * p_dm_void,u8 rate,u32 dbg_component)295 phydm_print_rate(
296 void *p_dm_void,
297 u8 rate,
298 u32 dbg_component
299 )
300 {
301 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
302 u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
303 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
304 u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0;
305 u8 b_sgi = (rate & 0x80) >> 7;
306
307 PHYDM_DBG_F(p_dm, dbg_component, ("( %s%s%s%s%d%s%s)\n",
308 ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "",
309 ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "",
310 ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "",
311 (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
312 (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M) ? legacy_table[rate_idx] : 0)),
313 (b_sgi) ? "-S" : " ",
314 (rate_idx >= ODM_RATEMCS0) ? "" : "M"));
315 }
316
317 void
phydm_c2h_ra_report_handler(void * p_dm_void,u8 * cmd_buf,u8 cmd_len)318 phydm_c2h_ra_report_handler(
319 void *p_dm_void,
320 u8 *cmd_buf,
321 u8 cmd_len
322 )
323 {
324 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
325 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
326 u8 macid = cmd_buf[1];
327 u8 rate = cmd_buf[0];
328 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
329 u8 rate_order;
330 struct cmn_sta_info *p_sta = p_dm->p_phydm_sta_info[macid];
331
332 if (cmd_len >=6) {
333 p_ra_table->ra_ratio[macid] = cmd_buf[6];
334 PHYDM_DBG(p_dm, DBG_RA, ("RA retry ratio: [%d]:", p_ra_table->ra_ratio[macid]));
335 /**/
336 } else if (cmd_len >= 4) {
337 if (cmd_buf[3] == 0) {
338 PHYDM_DBG(p_dm, DBG_RA, ("TX Init-rate Update[%d]:", macid));
339 /**/
340 } else if (cmd_buf[3] == 0xff) {
341 PHYDM_DBG(p_dm, DBG_RA, ("FW Level: Fix rate[%d]:", macid));
342 /**/
343 } else if (cmd_buf[3] == 1) {
344 PHYDM_DBG(p_dm, DBG_RA, ("Try Success[%d]:", macid));
345 /**/
346 } else if (cmd_buf[3] == 2) {
347 PHYDM_DBG(p_dm, DBG_RA, ("Try Fail & Try Again[%d]:", macid));
348 /**/
349 } else if (cmd_buf[3] == 3) {
350 PHYDM_DBG(p_dm, DBG_RA, ("rate Back[%d]:", macid));
351 /**/
352 } else if (cmd_buf[3] == 4) {
353 PHYDM_DBG(p_dm, DBG_RA, ("start rate by RSSI[%d]:", macid));
354 /**/
355 } else if (cmd_buf[3] == 5) {
356 PHYDM_DBG(p_dm, DBG_RA, ("Try rate[%d]:", macid));
357 /**/
358 }
359 } else {
360 PHYDM_DBG(p_dm, DBG_RA, ("Tx rate Update[%d]:", macid));
361 /**/
362 }
363
364 /*phydm_print_rate(p_dm, pre_rate_idx, DBG_RA);*/
365 /*PHYDM_DBG(p_dm, DBG_RA, (">\n",macid );*/
366 phydm_print_rate(p_dm, rate, DBG_RA);
367 if (macid >= 128) {
368 u8 gid_index = macid - 128;
369 p_ra_table->mu1_rate[gid_index] = rate;
370 }
371
372 /*p_ra_table->link_tx_rate[macid] = rate;*/
373
374 if (is_sta_active(p_sta)) {
375 p_sta->ra_info.curr_tx_rate = rate;
376 /**/
377 }
378
379 /*trigger power training*/
380 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
381
382 rate_order = phydm_rate_order_compute(p_dm, rate_idx);
383
384 if ((p_dm->is_one_entry_only) ||
385 ((rate_order > p_ra_table->highest_client_tx_order) && (p_ra_table->power_tracking_flag == 1))
386 ) {
387 halrf_update_pwr_track(p_dm, rate_idx);
388 p_ra_table->power_tracking_flag = 0;
389 }
390
391 #endif
392
393 /*trigger dynamic rate ID*/
394 /*#if (defined(CONFIG_RA_DYNAMIC_RATE_ID))*/ /*dino will refine here later*/
395 #if 0
396 if (p_dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))
397 phydm_update_rate_id(p_dm, rate, macid);
398 #endif
399
400 }
401
402 void
odm_ra_post_action_on_assoc(void * p_dm_void)403 odm_ra_post_action_on_assoc(
404 void *p_dm_void
405 )
406 {
407 #if 0
408 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
409
410 p_dm->h2c_rarpt_connect = 1;
411 phydm_rssi_monitor_check(p_dm);
412 p_dm->h2c_rarpt_connect = 0;
413 #endif
414 }
415
416 void
phydm_modify_RA_PCR_threshold(void * p_dm_void,u8 RA_offset_direction,u8 RA_threshold_offset)417 phydm_modify_RA_PCR_threshold(
418 void *p_dm_void,
419 u8 RA_offset_direction,
420 u8 RA_threshold_offset
421
422 )
423 {
424 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
425 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
426
427 p_ra_table->RA_offset_direction = RA_offset_direction;
428 p_ra_table->RA_threshold_offset = RA_threshold_offset;
429 PHYDM_DBG(p_dm, DBG_RA, ("Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset));
430 }
431
432 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
433
434 void
odm_refresh_rate_adaptive_mask_mp(void * p_dm_void)435 odm_refresh_rate_adaptive_mask_mp(
436 void *p_dm_void
437 )
438 {
439 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
440 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
441 struct _ADAPTER *p_adapter = p_dm->adapter;
442 struct _ADAPTER *p_target_adapter = NULL;
443 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
444 PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(p_adapter);
445 struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(p_adapter);
446 PMGNT_INFO p_loop_mgnt_info = &(p_loop_adapter->MgntInfo);
447 HAL_DATA_TYPE *p_loop_hal_data = GET_HAL_DATA(p_loop_adapter);
448
449 u32 i;
450 struct sta_info *p_entry;
451 u8 ratr_state_new;
452
453 PHYDM_DBG(p_dm, DBG_RA_MASK, ("%s ======>\n", __func__));
454
455 if (p_adapter->bDriverStopped) {
456 PHYDM_DBG(p_dm, DBG_RA_MASK, ("driver is going to unload\n"));
457 return;
458 }
459
460 if (!p_hal_data->bUseRAMask) {
461 PHYDM_DBG(p_dm, DBG_RA_MASK, ("driver does not control rate adaptive mask\n"));
462 return;
463 }
464
465 /* if default port is connected, update RA table for default port (infrastructure mode only) */
466 /* Need to consider other ports for P2P cases*/
467
468 while(p_loop_adapter){
469
470 p_loop_mgnt_info = &(p_loop_adapter->MgntInfo);
471 p_loop_hal_data = GET_HAL_DATA(p_loop_adapter);
472
473 if (p_loop_mgnt_info->mAssoc && (!ACTING_AS_AP(p_loop_adapter))) {
474 odm_refresh_ldpc_rts_mp(p_loop_adapter, p_dm, p_loop_mgnt_info->mMacId, p_loop_mgnt_info->IOTPeer, p_loop_hal_data->UndecoratedSmoothedPWDB);
475 /*PHYDM_DBG(p_dm, DBG_RA_MASK, ("Infrasture mode\n"));*/
476
477 ratr_state_new = phydm_rssi_lv_dec(p_dm, p_loop_hal_data->UndecoratedSmoothedPWDB, p_loop_mgnt_info->Ratr_State);
478
479 if ((p_loop_mgnt_info->Ratr_State != ratr_state_new) || (p_ra_table->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD)) {
480
481 p_ra_table->up_ramask_cnt = 0;
482 PHYDM_PRINT_ADDR(p_dm, DBG_RA_MASK, ("Target AP addr :"), p_loop_mgnt_info->Bssid);
483 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Update RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n\n",
484 p_mgnt_info->Ratr_State, ratr_state_new, p_loop_hal_data->UndecoratedSmoothedPWDB));
485
486 p_loop_mgnt_info->Ratr_State = ratr_state_new;
487 p_adapter->HalFunc.UpdateHalRAMaskHandler(p_loop_adapter, p_loop_mgnt_info->mMacId, NULL, ratr_state_new);
488 } else {
489 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Stay in RA level = (( %d ))\n\n", ratr_state_new));
490 /**/
491 }
492 }
493
494 p_loop_adapter = GetNextExtAdapter(p_loop_adapter);
495 }
496
497 /* */
498 /* The following part configure AP/VWifi/IBSS rate adaptive mask. */
499 /* */
500
501 if (p_mgnt_info->mIbss) /* Target: AP/IBSS peer. */
502 p_target_adapter = GetDefaultAdapter(p_adapter);
503 else
504 p_target_adapter = GetFirstAPAdapter(p_adapter);
505
506 /* if extension port (softap) is started, updaet RA table for more than one clients associate */
507 if (p_target_adapter != NULL) {
508 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
509
510 p_entry = AsocEntry_EnumStation(p_target_adapter, i);
511
512 if (is_sta_active((&GET_STA_INFO(p_entry)))) {
513
514 odm_refresh_ldpc_rts_mp(p_target_adapter, p_dm, GET_STA_INFO(p_entry).mac_id, p_entry->IOTPeer, GET_STA_INFO(p_entry).rssi_stat.rssi);
515
516 ratr_state_new = phydm_rssi_lv_dec(p_dm, GET_STA_INFO(p_entry).rssi_stat.rssi, GET_STA_INFO(p_entry).ra_info.rssi_level);
517
518 if ((GET_STA_INFO(p_entry).ra_info.rssi_level != ratr_state_new) || (p_ra_table->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD)) {
519
520 p_ra_table->up_ramask_cnt = 0;
521 PHYDM_PRINT_ADDR(p_dm, DBG_RA_MASK, ("Target AP addr :"), GET_STA_INFO(p_entry).mac_addr);
522 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n",
523 GET_STA_INFO(p_entry).ra_info.rssi_level, ratr_state_new, GET_STA_INFO(p_entry).rssi_stat.rssi));
524
525 GET_STA_INFO(p_entry).ra_info.rssi_level = ratr_state_new;
526 p_adapter->HalFunc.UpdateHalRAMaskHandler(p_target_adapter, GET_STA_INFO(p_entry).mac_id, p_entry, ratr_state_new);
527 } else {
528 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Stay in RA level = (( %d ))\n\n", ratr_state_new));
529 /**/
530 }
531
532 }
533 }
534 }
535 }
536
537 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
538
539 void
odm_refresh_rate_adaptive_mask_ap(void * p_dm_void)540 odm_refresh_rate_adaptive_mask_ap(
541 void *p_dm_void
542 )
543 {
544 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
545 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
546 struct rtl8192cd_priv *priv = p_dm->priv;
547 struct aid_obj *aidarray;
548 u32 i;
549 struct sta_info *p_entry;
550 struct cmn_sta_info *p_sta;
551 u8 ratr_state_new;
552
553 if (priv->up_time % 2)
554 return;
555
556 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
557 p_entry = p_dm->p_odm_sta_info[i];
558 p_sta = p_dm->p_phydm_sta_info[i];
559
560 if (is_sta_active(p_sta)) {
561
562 #if defined(UNIVERSAL_REPEATER) || defined(MBSSID)
563 aidarray = container_of(p_entry, struct aid_obj, station);
564 priv = aidarray->priv;
565 #endif
566
567 if (!priv->pmib->dot11StationConfigEntry.autoRate)
568 continue;
569
570 ratr_state_new = phydm_rssi_lv_dec(p_dm, (u32)p_sta->rssi_stat.rssi, p_sta->ra_info.rssi_level);
571
572 if ((p_sta->ra_info.rssi_level != ratr_state_new) || (p_ra_table->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD)) {
573
574 p_ra_table->up_ramask_cnt = 0;
575 PHYDM_PRINT_ADDR(p_dm, DBG_RA_MASK, ("Target AP addr :"), p_sta->mac_addr);
576 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", p_sta->ra_info.rssi_level, ratr_state_new, p_sta->rssi_stat.rssi));
577
578 p_sta->ra_info.rssi_level = ratr_state_new;
579 phydm_gen_ramask_h2c_AP(p_dm, priv, p_entry, p_sta->ra_info.rssi_level);
580 } else {
581 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Stay in RA level = (( %d ))\n\n", ratr_state_new));
582 /**/
583 }
584 }
585 }
586 }
587 #endif
588
589 void
phydm_rate_adaptive_mask_init(void * p_dm_void)590 phydm_rate_adaptive_mask_init(
591 void *p_dm_void
592 )
593 {
594 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
595 struct _rate_adaptive_table_ *p_ra_t = &p_dm->dm_ra_table;
596
597 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
598 PMGNT_INFO p_mgnt_info = &p_dm->adapter->MgntInfo;
599 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm->adapter);
600
601 p_mgnt_info->Ratr_State = DM_RATR_STA_INIT;
602
603 if (p_mgnt_info->DM_Type == dm_type_by_driver)
604 p_hal_data->bUseRAMask = true;
605 else
606 p_hal_data->bUseRAMask = false;
607
608 #endif
609
610 p_ra_t->ldpc_thres = 35;
611 p_ra_t->up_ramask_cnt = 0;
612 p_ra_t->up_ramask_cnt_tmp = 0;
613
614 }
615
616 void
phydm_refresh_rate_adaptive_mask(void * p_dm_void)617 phydm_refresh_rate_adaptive_mask(
618 void *p_dm_void
619 )
620 {
621 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
622 struct _rate_adaptive_table_ *p_ra_t = &p_dm->dm_ra_table;
623
624 PHYDM_DBG(p_dm, DBG_RA_MASK, ("%s ======>\n", __func__));
625
626 if (!(p_dm->support_ability & ODM_BB_RA_MASK)) {
627 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Return: Not support\n"));
628 return;
629 }
630
631 if (!p_dm->is_linked)
632 return;
633
634 p_ra_t->up_ramask_cnt++;
635 /*p_ra_t->up_ramask_cnt_tmp++;*/
636
637
638 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
639
640 odm_refresh_rate_adaptive_mask_mp(p_dm);
641
642 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
643
644 odm_refresh_rate_adaptive_mask_ap(p_dm);
645
646 #else /*(DM_ODM_SUPPORT_TYPE == ODM_CE)*/
647
648 phydm_ra_mask_watchdog(p_dm);
649
650 #endif
651
652 }
653
654 void
phydm_show_sta_info(void * p_dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len,u32 input_num)655 phydm_show_sta_info(
656 void *p_dm_void,
657 char input[][16],
658 u32 *_used,
659 char *output,
660 u32 *_out_len,
661 u32 input_num
662 )
663 {
664 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
665 struct cmn_sta_info *p_sta = NULL;
666 struct ra_sta_info *p_ra = NULL;
667 #ifdef CONFIG_BEAMFORMING
668 struct bf_cmn_info *p_bf = NULL;
669 #endif
670 char help[] = "-h";
671 u32 var1[10] = {0};
672 u32 used = *_used;
673 u32 out_len = *_out_len;
674 u32 i, macid_start, macid_end;
675 u8 tatal_sta_num = 0;
676
677 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
678
679 if ((strcmp(input[1], help) == 0)) {
680 PHYDM_SNPRINTF((output + used, out_len - used, "All STA: {1}\n"));
681 PHYDM_SNPRINTF((output + used, out_len - used, "STA[macid]: {2} {macid}\n"));
682 return;
683 } else if (var1[0] == 1) {
684 macid_start = 0;
685 macid_end = ODM_ASSOCIATE_ENTRY_NUM;
686 } else if (var1[0] == 2) {
687 macid_start = var1[1];
688 macid_end = var1[1];
689 } else {
690 PHYDM_SNPRINTF((output + used, out_len - used, "Warning input value!\n"));
691 return;
692 }
693
694 for (i = macid_start; i < macid_end; i++) {
695
696 p_sta = p_dm->p_phydm_sta_info[i];
697
698
699 if (!is_sta_active(p_sta))
700 continue;
701
702 p_ra = &(p_sta->ra_info);
703 #ifdef CONFIG_BEAMFORMING
704 p_bf = &(p_sta->bf_info);
705 #endif
706
707 tatal_sta_num++;
708
709 PHYDM_SNPRINTF((output + used, out_len - used, "==[MACID: %d]============>\n", p_sta->mac_id));
710 PHYDM_SNPRINTF((output + used, out_len - used, "AID:%d\n", p_sta->aid));
711 PHYDM_SNPRINTF((output + used, out_len - used, "ADDR:%x-%x-%x-%x-%x-%x\n",
712 p_sta->mac_addr[5], p_sta->mac_addr[4], p_sta->mac_addr[3], p_sta->mac_addr[2], p_sta->mac_addr[1], p_sta->mac_addr[0]));
713 PHYDM_SNPRINTF((output + used, out_len - used, "DM_ctrl:0x%x\n", p_sta->dm_ctrl));
714 PHYDM_SNPRINTF((output + used, out_len - used, "BW:%d, MIMO_Type:0x%x\n", p_sta->bw_mode, p_sta->mimo_type));
715 PHYDM_SNPRINTF((output + used, out_len - used, "STBC_en:%d, LDPC_en=%d\n", p_sta->stbc_en, p_sta->ldpc_en));
716
717 /*[RSSI Info]*/
718 PHYDM_SNPRINTF((output + used, out_len - used, "RSSI{All, OFDM, CCK}={%d, %d, %d}\n",
719 p_sta->rssi_stat.rssi, p_sta->rssi_stat.rssi_ofdm, p_sta->rssi_stat.rssi_cck));
720
721 /*[RA Info]*/
722 PHYDM_SNPRINTF((output + used, out_len - used, "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n",
723 p_ra->rate_id, p_ra->rssi_level, p_ra->ra_bw_mode, p_ra->is_support_sgi));
724
725 PHYDM_SNPRINTF((output + used, out_len - used, "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n",
726 p_ra->is_vht_enable, p_sta->support_wireless_set, p_sta->sm_ps));
727
728 PHYDM_SNPRINTF((output + used, out_len - used, "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n",
729 p_ra->disable_ra, p_ra->disable_pt, p_ra->txrx_state, p_ra->is_noisy));
730
731 PHYDM_SNPRINTF((output + used, out_len - used, "TX{Rate, BW}={%d, %d}, RTY:%d\n",
732 p_ra->curr_tx_rate, p_ra->curr_tx_bw, p_ra->curr_retry_ratio));
733
734 PHYDM_SNPRINTF((output + used, out_len - used, "RA_MAsk:0x%llx\n", p_ra->ramask));
735
736 /*[TP]*/
737 PHYDM_SNPRINTF((output + used, out_len - used, "TP{TX,RX}={%d, %d}\n",
738 p_sta->tx_moving_average_tp, p_sta->rx_moving_average_tp));
739
740 #ifdef CONFIG_BEAMFORMING
741 /*[Beamforming]*/
742 PHYDM_SNPRINTF((output + used, out_len - used, "CAP{HT,VHT}={0x%x, 0x%x}\n",
743 p_bf->ht_beamform_cap, p_bf->vht_beamform_cap));
744 PHYDM_SNPRINTF((output + used, out_len - used, "{p_aid,g_id}={0x%x, 0x%x}\n\n",
745 p_bf->p_aid, p_bf->g_id));
746 #endif
747 }
748
749 if (tatal_sta_num == 0) {
750 PHYDM_SNPRINTF((output + used, out_len - used, "No Linked STA\n"));
751 }
752
753 *_used = used;
754 *_out_len = out_len;
755 }
756
757 #ifdef PHYDM_3RD_REFORM_RA_MASK
758
759 u8
phydm_get_tx_stream_num(void * p_dm_void,enum rf_type mimo_type)760 phydm_get_tx_stream_num(
761 void *p_dm_void,
762 enum rf_type mimo_type
763
764 )
765 {
766 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
767 u8 tx_num = 1;
768
769 if (mimo_type == RF_1T1R || mimo_type == RF_1T2R)
770 tx_num = 1;
771 else if (mimo_type == RF_2T2R || mimo_type == RF_2T3R || mimo_type == RF_2T4R)
772 tx_num = 2;
773 else if (mimo_type == RF_3T3R || mimo_type == RF_3T4R)
774 tx_num = 3;
775 else if (mimo_type == RF_4T4R)
776 tx_num = 4;
777 else {
778 PHYDM_DBG(p_dm, DBG_RA, ("[Warrning] no mimo_type is found\n"));
779 }
780 return tx_num;
781 }
782
783 u64
phydm_get_bb_mod_ra_mask(void * p_dm_void,u8 macid)784 phydm_get_bb_mod_ra_mask(
785 void *p_dm_void,
786 u8 macid
787 )
788 {
789 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
790 struct cmn_sta_info *p_sta = p_dm->p_phydm_sta_info[macid];
791 struct ra_sta_info *p_ra = NULL;
792 enum channel_width bw = 0;
793 enum wireless_set wireless_mode = 0;
794 u8 tx_stream_num = 1;
795 u8 rssi_lv = 0;
796 u64 ra_mask_bitmap = 0;
797
798 if (is_sta_active(p_sta)) {
799
800 p_ra = &(p_sta->ra_info);
801 bw = p_ra->ra_bw_mode;
802 wireless_mode = p_sta->support_wireless_set;
803 tx_stream_num = phydm_get_tx_stream_num(p_dm, p_sta->mimo_type);
804 rssi_lv = p_ra->rssi_level;
805 ra_mask_bitmap = p_ra->ramask;
806 } else {
807 PHYDM_DBG(p_dm, DBG_RA, ("[Warning] %s invalid sta_info\n", __func__));
808 return 0;
809 }
810
811 PHYDM_DBG(p_dm, DBG_RA, ("macid=%d ori_RA_Mask= 0x%llx\n", macid, ra_mask_bitmap));
812 PHYDM_DBG(p_dm, DBG_RA, ("wireless_mode=0x%x, tx_stream_num=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n",
813 wireless_mode, tx_stream_num, bw, p_sta->sm_ps, rssi_lv));
814
815 if (p_sta->sm_ps == SM_PS_STATIC) /*mimo_ps_enable*/
816 tx_stream_num = 1;
817
818
819 /*[Modify RA Mask by Wireless Mode]*/
820
821 if (wireless_mode == WIRELESS_CCK) /*B mode*/
822 ra_mask_bitmap &= 0x0000000f;
823 else if (wireless_mode == WIRELESS_OFDM) /*G mode*/
824 ra_mask_bitmap &= 0x00000ff0;
825 else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM)) /*BG mode*/
826 ra_mask_bitmap &= 0x00000ff5;
827 else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
828 /*N_2G*/
829 if (tx_stream_num == 1) {
830 if (bw == CHANNEL_WIDTH_40)
831 ra_mask_bitmap &= 0x000ff015;
832 else
833 ra_mask_bitmap &= 0x000ff005;
834 } else if (tx_stream_num == 2) {
835
836 if (bw == CHANNEL_WIDTH_40)
837 ra_mask_bitmap &= 0x0ffff015;
838 else
839 ra_mask_bitmap &= 0x0ffff005;
840 } else if (tx_stream_num == 3)
841 ra_mask_bitmap &= 0xffffff015;
842 } else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/
843
844 if (tx_stream_num == 1) {
845 if (bw == CHANNEL_WIDTH_40)
846 ra_mask_bitmap &= 0x000ff030;
847 else
848 ra_mask_bitmap &= 0x000ff010;
849 } else if (tx_stream_num == 2) {
850
851 if (bw == CHANNEL_WIDTH_40)
852 ra_mask_bitmap &= 0x0ffff030;
853 else
854 ra_mask_bitmap &= 0x0ffff010;
855 } else if (tx_stream_num == 3)
856 ra_mask_bitmap &= 0xffffff010;
857 } else if (wireless_mode == (WIRELESS_CCK |WIRELESS_OFDM | WIRELESS_VHT)) {
858 /*AC_2G*/
859 if (tx_stream_num == 1)
860 ra_mask_bitmap &= 0x003ff015;
861 else if (tx_stream_num == 2)
862 ra_mask_bitmap &= 0xfffff015;
863 else if (tx_stream_num == 3)
864 ra_mask_bitmap &= 0x3fffffff010;
865
866
867 if (bw == CHANNEL_WIDTH_20) {/* AC 20MHz doesn't support MCS9 */
868 ra_mask_bitmap &= 0x1ff7fdfffff;
869 }
870 } else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*AC_5G*/
871
872 if (tx_stream_num == 1)
873 ra_mask_bitmap &= 0x003ff010;
874 else if (tx_stream_num == 2)
875 ra_mask_bitmap &= 0xfffff010;
876 else if (tx_stream_num == 3)
877 ra_mask_bitmap &= 0x3fffffff010;
878
879 if (bw == CHANNEL_WIDTH_20) /* AC 20MHz doesn't support MCS9 */
880 ra_mask_bitmap &= 0x1ff7fdfffff;
881 } else {
882 PHYDM_DBG(p_dm, DBG_RA, ("[Warrning] No RA mask is found\n"));
883 /**/
884 }
885
886 PHYDM_DBG(p_dm, DBG_RA, ("Mod by mode=0x%llx\n", ra_mask_bitmap));
887
888
889 /*[Modify RA Mask by RSSI level]*/
890 if (wireless_mode != WIRELESS_CCK) {
891
892 if (rssi_lv == 0)
893 ra_mask_bitmap &= 0xffffffff;
894 else if (rssi_lv == 1)
895 ra_mask_bitmap &= 0xfffffff0;
896 else if (rssi_lv == 2)
897 ra_mask_bitmap &= 0xffffefe0;
898 else if (rssi_lv == 3)
899 ra_mask_bitmap &= 0xffffcfc0;
900 else if (rssi_lv == 4)
901 ra_mask_bitmap &= 0xffff8f80;
902 else if (rssi_lv >= 5)
903 ra_mask_bitmap &= 0xffff0f00;
904
905 }
906 PHYDM_DBG(p_dm, DBG_RA, ("Mod by RSSI=0x%llx\n", ra_mask_bitmap));
907
908 return ra_mask_bitmap;
909 }
910
911 u8
phydm_get_rate_id(void * p_dm_void,u8 macid)912 phydm_get_rate_id(
913 void *p_dm_void,
914 u8 macid
915 )
916 {
917 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
918 struct cmn_sta_info *p_sta = p_dm->p_phydm_sta_info[macid];
919 struct ra_sta_info *p_ra =NULL;
920 enum channel_width bw = 0;
921 enum wireless_set wireless_mode = 0;
922 u8 tx_stream_num = 1;
923 u8 rate_id_idx = PHYDM_BGN_20M_1SS;
924
925 if (is_sta_active(p_sta)) {
926
927 p_ra = &(p_sta->ra_info);
928 bw = p_ra->ra_bw_mode;
929 wireless_mode = p_sta->support_wireless_set;
930 tx_stream_num = phydm_get_tx_stream_num(p_dm, p_sta->mimo_type);
931
932 } else {
933 PHYDM_DBG(p_dm, DBG_RA, ("[Warning] %s: invalid sta_info\n", __func__));
934 return 0;
935 }
936
937 PHYDM_DBG(p_dm, DBG_RA, ("macid=%d, wireless_set=0x%x, tx_stream_num=%d, BW=0x%x\n",
938 macid, wireless_mode, tx_stream_num, bw));
939
940 if (wireless_mode == WIRELESS_CCK) /*B mode*/
941 rate_id_idx = PHYDM_B_20M;
942 else if (wireless_mode == WIRELESS_OFDM) /*G mode*/
943 rate_id_idx = PHYDM_G;
944 else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM)) /*BG mode*/
945 rate_id_idx = PHYDM_BG;
946 else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*GN mode*/
947
948 if (tx_stream_num == 1)
949 rate_id_idx = PHYDM_GN_N1SS;
950 else if (tx_stream_num == 2)
951 rate_id_idx = PHYDM_GN_N2SS;
952 else if (tx_stream_num == 3)
953 rate_id_idx = PHYDM_ARFR5_N_3SS;
954 } else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) { /*BGN mode*/
955
956
957 if (bw == CHANNEL_WIDTH_40) {
958
959 if (tx_stream_num == 1)
960 rate_id_idx = PHYDM_BGN_40M_1SS;
961 else if (tx_stream_num == 2)
962 rate_id_idx = PHYDM_BGN_40M_2SS;
963 else if (tx_stream_num == 3)
964 rate_id_idx = PHYDM_ARFR5_N_3SS;
965
966 } else {
967
968 if (tx_stream_num == 1)
969 rate_id_idx = PHYDM_BGN_20M_1SS;
970 else if (tx_stream_num == 2)
971 rate_id_idx = PHYDM_BGN_20M_2SS;
972 else if (tx_stream_num == 3)
973 rate_id_idx = PHYDM_ARFR5_N_3SS;
974 }
975 } else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*AC mode*/
976
977 if (tx_stream_num == 1)
978 rate_id_idx = PHYDM_ARFR1_AC_1SS;
979 else if (tx_stream_num == 2)
980 rate_id_idx = PHYDM_ARFR0_AC_2SS;
981 else if (tx_stream_num == 3)
982 rate_id_idx = PHYDM_ARFR4_AC_3SS;
983 } else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) { /*AC 2.4G mode*/
984
985 if (bw >= CHANNEL_WIDTH_80) {
986 if (tx_stream_num == 1)
987 rate_id_idx = PHYDM_ARFR1_AC_1SS;
988 else if (tx_stream_num == 2)
989 rate_id_idx = PHYDM_ARFR0_AC_2SS;
990 else if (tx_stream_num == 3)
991 rate_id_idx = PHYDM_ARFR4_AC_3SS;
992 } else {
993
994 if (tx_stream_num == 1)
995 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
996 else if (tx_stream_num == 2)
997 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
998 else if (tx_stream_num == 3)
999 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1000 }
1001 } else {
1002 PHYDM_DBG(p_dm, DBG_RA, ("[Warrning] No rate_id is found\n"));
1003 rate_id_idx = 0;
1004 }
1005
1006 PHYDM_DBG(p_dm, DBG_RA, ("Rate_ID=((0x%x))\n", rate_id_idx));
1007
1008 return rate_id_idx;
1009 }
1010
1011 void
phydm_ra_h2c(void * p_dm_void,u8 macid,u8 dis_ra,u8 dis_pt,u8 no_update_bw,u8 init_ra_lv,u64 ra_mask)1012 phydm_ra_h2c(
1013 void *p_dm_void,
1014 u8 macid,
1015 u8 dis_ra,
1016 u8 dis_pt,
1017 u8 no_update_bw,
1018 u8 init_ra_lv,
1019 u64 ra_mask
1020 )
1021 {
1022 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1023 struct cmn_sta_info *p_sta = p_dm->p_phydm_sta_info[macid];
1024 struct ra_sta_info *p_ra = NULL;
1025 u8 h2c_val[H2C_MAX_LENGTH] = {0};
1026
1027 if (is_sta_active(p_sta)) {
1028 p_ra = &(p_sta->ra_info);
1029 } else {
1030 PHYDM_DBG(p_dm, DBG_RA, ("[Warning] %s invalid sta_info\n", __func__));
1031 return;
1032 }
1033
1034 PHYDM_DBG(p_dm, DBG_RA, ("%s ======>\n", __func__));
1035 PHYDM_DBG(p_dm, DBG_RA, ("MACID=%d\n", p_sta->mac_id));
1036
1037 h2c_val[0] = p_sta->mac_id;
1038 h2c_val[1] = (p_ra->rate_id & 0x1f) | ((init_ra_lv & 0x3) << 5) | (p_ra->is_support_sgi << 7);
1039 h2c_val[2] = (u8)((p_ra->ra_bw_mode) | (((p_sta->ldpc_en) ? 1 : 0) << 2) |
1040 ((no_update_bw & 0x1) << 3) | (p_ra->is_vht_enable << 4) |
1041 ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7));
1042
1043 h2c_val[3] = (u8)(ra_mask & 0xff);
1044 h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8);
1045 h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16);
1046 h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24);
1047
1048 PHYDM_DBG(p_dm, DBG_RA, ("PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n",
1049 h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], h2c_val[1], h2c_val[0]));
1050
1051 odm_fill_h2c_cmd(p_dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val);
1052
1053 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1054 if (p_dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
1055
1056 h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff);
1057 h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8);
1058 h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16);
1059 h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24);
1060
1061 PHYDM_DBG(p_dm, DBG_RA, ("PHYDM h2c[0x46]=0x%x %x %x %x %x %x %x\n",
1062 h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], h2c_val[1], h2c_val[0]));
1063
1064 odm_fill_h2c_cmd(p_dm, PHYDM_RA_MASK_ABOVE_3SS, 5, h2c_val);
1065 }
1066 #endif
1067 }
1068
1069 void
phydm_ra_registed(void * p_dm_void,u8 macid,u8 rssi_from_assoc)1070 phydm_ra_registed(
1071 void *p_dm_void,
1072 u8 macid,
1073 u8 rssi_from_assoc
1074 )
1075 {
1076 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1077 struct _rate_adaptive_table_ *p_ra_t = &p_dm->dm_ra_table;
1078 struct cmn_sta_info *p_sta = p_dm->p_phydm_sta_info[macid];
1079 struct ra_sta_info *p_ra = NULL;
1080 u8 init_ra_lv;
1081 u64 ra_mask;
1082
1083 if (is_sta_active(p_sta)) {
1084 p_ra = &(p_sta->ra_info);
1085 } else {
1086 PHYDM_DBG(p_dm, DBG_RA, ("[Warning] %s invalid sta_info\n", __func__));
1087 return;
1088 }
1089
1090 PHYDM_DBG(p_dm, DBG_RA, ("%s ======>\n", __func__));
1091 PHYDM_DBG(p_dm, DBG_RA, ("MACID=%d\n", p_sta->mac_id));
1092
1093
1094 #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
1095 if (p_dm->support_ic_type == ODM_RTL8188E)
1096 phydm_get_rate_id_88e(p_dm, macid);
1097 else
1098 #endif
1099 {
1100 p_ra->rate_id = phydm_get_rate_id(p_dm, macid);
1101 }
1102
1103 /*p_ra->is_vht_enable = (p_sta->support_wireless_set | WIRELESS_VHT) ? 1 : 0;*/
1104 /*p_ra->disable_ra = 0;*/
1105 /*p_ra->disable_pt = 0;*/
1106 ra_mask = phydm_get_bb_mod_ra_mask(p_dm, macid);
1107
1108
1109 if (rssi_from_assoc > 40)
1110 init_ra_lv = 3;
1111 else if (rssi_from_assoc > 20)
1112 init_ra_lv = 2;
1113 else
1114 init_ra_lv = 1;
1115
1116 if (p_ra_t->record_ra_info)
1117 p_ra_t->record_ra_info(p_dm, macid, p_sta, ra_mask);
1118
1119 #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
1120 if (p_dm->support_ic_type == ODM_RTL8188E)
1121 /*Driver RA*/
1122 odm_ra_update_rate_info_8188e(p_dm, macid, p_ra->rate_id, (u32)ra_mask, p_ra->is_support_sgi);
1123 else
1124 #endif
1125 {
1126 /*FW RA*/
1127 phydm_ra_h2c(p_dm, macid, p_ra->disable_ra, p_ra->disable_pt, 0, init_ra_lv, ra_mask);
1128 }
1129
1130
1131
1132 }
1133
1134 void
phydm_ra_offline(void * p_dm_void,u8 macid)1135 phydm_ra_offline(
1136 void *p_dm_void,
1137 u8 macid
1138 )
1139 {
1140 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1141 struct _rate_adaptive_table_ *p_ra_t = &p_dm->dm_ra_table;
1142 struct cmn_sta_info *p_sta = p_dm->p_phydm_sta_info[macid];
1143 struct ra_sta_info *p_ra = NULL;
1144
1145 if (is_sta_active(p_sta)) {
1146 p_ra = &(p_sta->ra_info);
1147 } else {
1148 PHYDM_DBG(p_dm, DBG_RA, ("[Warning] %s invalid sta_info\n", __func__));
1149 return;
1150 }
1151
1152 PHYDM_DBG(p_dm, DBG_RA, ("%s ======>\n", __func__));
1153 PHYDM_DBG(p_dm, DBG_RA, ("MACID=%d\n", p_sta->mac_id));
1154
1155 odm_memory_set(p_dm, &(p_ra->rate_id), 0, sizeof(struct ra_sta_info));
1156 p_ra->disable_ra = 1;
1157 p_ra->disable_pt = 1;
1158
1159 if (p_ra_t->record_ra_info)
1160 p_ra_t->record_ra_info(p_dm, macid, p_sta, 0);
1161
1162 if (p_dm->support_ic_type != ODM_RTL8188E)
1163 phydm_ra_h2c(p_dm, macid, p_ra->disable_ra, p_ra->disable_pt, 0, 0, 0);
1164 }
1165
1166 void
phydm_ra_mask_watchdog(void * p_dm_void)1167 phydm_ra_mask_watchdog(
1168 void *p_dm_void
1169 )
1170 {
1171 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1172 struct _rate_adaptive_table_ *p_ra_t = &p_dm->dm_ra_table;
1173 struct cmn_sta_info *p_sta = NULL;
1174 struct ra_sta_info *p_ra = NULL;
1175 u8 macid;
1176 u64 ra_mask;
1177 u8 rssi_lv_new;
1178
1179 if (!(p_dm->support_ability & ODM_BB_RA_MASK))
1180 return;
1181
1182 if (((!p_dm->is_linked)) || (p_dm->phydm_sys_up_time % 2) == 1)
1183 return;
1184
1185 PHYDM_DBG(p_dm, DBG_RA_MASK, ("%s ======>\n", __func__));
1186
1187 p_ra_t->up_ramask_cnt++;
1188
1189 for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
1190
1191 p_sta = p_dm->p_phydm_sta_info[macid];
1192
1193 if (!is_sta_active(p_sta))
1194 continue;
1195
1196 p_ra = &(p_sta->ra_info);
1197
1198 if (p_ra->disable_ra)
1199 continue;
1200
1201
1202 /*to be modified*/
1203 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
1204 if ((p_dm->support_ic_type == ODM_RTL8812) ||
1205 ((p_dm->support_ic_type == ODM_RTL8821) && (p_dm->cut_version == ODM_CUT_A))
1206 ) {
1207
1208 if (p_sta->rssi_stat.rssi < p_ra_t->ldpc_thres) {
1209
1210 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1211 set_ra_ldpc_8812(p_sta, true); /*LDPC TX enable*/
1212 #endif
1213 PHYDM_DBG(p_dm, DBG_RA_MASK, ("RSSI=%d, ldpc_en =TRUE\n", p_sta->rssi_stat.rssi));
1214
1215 } else if (p_sta->rssi_stat.rssi > (p_ra_t->ldpc_thres + 3)) {
1216
1217 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1218 set_ra_ldpc_8812(p_sta, false); /*LDPC TX disable*/
1219 #endif
1220 PHYDM_DBG(p_dm, DBG_RA_MASK, ("RSSI=%d, ldpc_en =FALSE\n", p_sta->rssi_stat.rssi));
1221 }
1222 }
1223 #endif
1224
1225 rssi_lv_new = phydm_rssi_lv_dec(p_dm, (u32)p_sta->rssi_stat.rssi, p_ra->rssi_level);
1226
1227 if ((p_ra->rssi_level != rssi_lv_new) ||
1228 (p_ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD)) {
1229
1230 PHYDM_DBG(p_dm, DBG_RA_MASK, ("RSSI LV:((%d))->((%d))\n", p_ra->rssi_level, rssi_lv_new));
1231
1232 p_ra->rssi_level = rssi_lv_new;
1233 p_ra_t->up_ramask_cnt = 0;
1234
1235 ra_mask = phydm_get_bb_mod_ra_mask(p_dm, macid);
1236
1237 if (p_ra_t->record_ra_info)
1238 p_ra_t->record_ra_info(p_dm, macid, p_sta, ra_mask);
1239
1240 #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
1241 if (p_dm->support_ic_type == ODM_RTL8188E)
1242 /*Driver RA*/
1243 odm_ra_update_rate_info_8188e(p_dm, macid, p_ra->rate_id, (u32)ra_mask, p_ra->is_support_sgi);
1244 else
1245 #endif
1246 {
1247 /*FW RA*/
1248 phydm_ra_h2c(p_dm, macid, p_ra->disable_ra, p_ra->disable_pt, 1, 0, ra_mask);
1249 }
1250 }
1251 }
1252
1253 }
1254 #endif
1255
1256 u8
phydm_vht_en_mapping(void * p_dm_void,u32 wireless_mode)1257 phydm_vht_en_mapping(
1258 void *p_dm_void,
1259 u32 wireless_mode
1260 )
1261 {
1262 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1263 u8 vht_en_out = 0;
1264
1265 if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) ||
1266 (wireless_mode == PHYDM_WIRELESS_MODE_AC_24G) ||
1267 (wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)
1268 ) {
1269 vht_en_out = 1;
1270 /**/
1271 }
1272
1273 PHYDM_DBG(p_dm, DBG_RA, ("wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", wireless_mode, vht_en_out));
1274 return vht_en_out;
1275 }
1276
1277 u8
phydm_rate_id_mapping(void * p_dm_void,u32 wireless_mode,u8 rf_type,u8 bw)1278 phydm_rate_id_mapping(
1279 void *p_dm_void,
1280 u32 wireless_mode,
1281 u8 rf_type,
1282 u8 bw
1283 )
1284 {
1285 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1286 u8 rate_id_idx = 0;
1287
1288 PHYDM_DBG(p_dm, DBG_RA, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
1289 wireless_mode, rf_type, bw));
1290
1291
1292 switch (wireless_mode) {
1293
1294 case PHYDM_WIRELESS_MODE_N_24G:
1295 {
1296
1297 if (bw == CHANNEL_WIDTH_40) {
1298
1299 if (rf_type == RF_1T1R)
1300 rate_id_idx = PHYDM_BGN_40M_1SS;
1301 else if (rf_type == RF_2T2R)
1302 rate_id_idx = PHYDM_BGN_40M_2SS;
1303 else
1304 rate_id_idx = PHYDM_ARFR5_N_3SS;
1305
1306 } else {
1307
1308 if (rf_type == RF_1T1R)
1309 rate_id_idx = PHYDM_BGN_20M_1SS;
1310 else if (rf_type == RF_2T2R)
1311 rate_id_idx = PHYDM_BGN_20M_2SS;
1312 else
1313 rate_id_idx = PHYDM_ARFR5_N_3SS;
1314 }
1315 }
1316 break;
1317
1318 case PHYDM_WIRELESS_MODE_N_5G:
1319 {
1320 if (rf_type == RF_1T1R)
1321 rate_id_idx = PHYDM_GN_N1SS;
1322 else if (rf_type == RF_2T2R)
1323 rate_id_idx = PHYDM_GN_N2SS;
1324 else
1325 rate_id_idx = PHYDM_ARFR5_N_3SS;
1326 }
1327
1328 break;
1329
1330 case PHYDM_WIRELESS_MODE_G:
1331 rate_id_idx = PHYDM_BG;
1332 break;
1333
1334 case PHYDM_WIRELESS_MODE_A:
1335 rate_id_idx = PHYDM_G;
1336 break;
1337
1338 case PHYDM_WIRELESS_MODE_B:
1339 rate_id_idx = PHYDM_B_20M;
1340 break;
1341
1342
1343 case PHYDM_WIRELESS_MODE_AC_5G:
1344 case PHYDM_WIRELESS_MODE_AC_ONLY:
1345 {
1346 if (rf_type == RF_1T1R)
1347 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1348 else if (rf_type == RF_2T2R)
1349 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1350 else
1351 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1352 }
1353 break;
1354
1355 case PHYDM_WIRELESS_MODE_AC_24G:
1356 {
1357 /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/
1358 if (bw >= CHANNEL_WIDTH_80) {
1359 if (rf_type == RF_1T1R)
1360 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1361 else if (rf_type == RF_2T2R)
1362 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1363 else
1364 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1365 } else {
1366
1367 if (rf_type == RF_1T1R)
1368 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
1369 else if (rf_type == RF_2T2R)
1370 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
1371 else
1372 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1373 }
1374 }
1375 break;
1376
1377 default:
1378 rate_id_idx = 0;
1379 break;
1380 }
1381
1382 PHYDM_DBG(p_dm, DBG_RA, ("RA rate ID = (( 0x%x ))\n", rate_id_idx));
1383
1384 return rate_id_idx;
1385 }
1386
1387 void
phydm_update_hal_ra_mask(void * p_dm_void,u32 wireless_mode,u8 rf_type,u8 bw,u8 mimo_ps_enable,u8 disable_cck_rate,u32 * ratr_bitmap_msb_in,u32 * ratr_bitmap_lsb_in,u8 tx_rate_level)1388 phydm_update_hal_ra_mask(
1389 void *p_dm_void,
1390 u32 wireless_mode,
1391 u8 rf_type,
1392 u8 bw,
1393 u8 mimo_ps_enable,
1394 u8 disable_cck_rate,
1395 u32 *ratr_bitmap_msb_in,
1396 u32 *ratr_bitmap_lsb_in,
1397 u8 tx_rate_level
1398 )
1399 {
1400 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1401 u32 ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in;
1402
1403 /*PHYDM_DBG(p_dm, DBG_RA_MASK, ("phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type));*/
1404 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));
1405
1406 switch (wireless_mode) {
1407
1408 case PHYDM_WIRELESS_MODE_B:
1409 {
1410 ratr_bitmap &= 0x0000000f;
1411 }
1412 break;
1413
1414 case PHYDM_WIRELESS_MODE_G:
1415 {
1416 ratr_bitmap &= 0x00000ff5;
1417 }
1418 break;
1419
1420 case PHYDM_WIRELESS_MODE_A:
1421 {
1422 ratr_bitmap &= 0x00000ff0;
1423 }
1424 break;
1425
1426 case PHYDM_WIRELESS_MODE_N_24G:
1427 case PHYDM_WIRELESS_MODE_N_5G:
1428 {
1429 if (mimo_ps_enable)
1430 rf_type = RF_1T1R;
1431
1432 if (rf_type == RF_1T1R) {
1433
1434 if (bw == CHANNEL_WIDTH_40)
1435 ratr_bitmap &= 0x000ff015;
1436 else
1437 ratr_bitmap &= 0x000ff005;
1438 } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
1439
1440 if (bw == CHANNEL_WIDTH_40)
1441 ratr_bitmap &= 0x0ffff015;
1442 else
1443 ratr_bitmap &= 0x0ffff005;
1444 } else { /*3T*/
1445
1446 ratr_bitmap &= 0xfffff015;
1447 ratr_bitmap_msb &= 0xf;
1448 }
1449 }
1450 break;
1451
1452 case PHYDM_WIRELESS_MODE_AC_24G:
1453 {
1454 if (rf_type == RF_1T1R)
1455 ratr_bitmap &= 0x003ff015;
1456 else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R)
1457 ratr_bitmap &= 0xfffff015;
1458 else {/*3T*/
1459
1460 ratr_bitmap &= 0xfffff010;
1461 ratr_bitmap_msb &= 0x3ff;
1462 }
1463
1464 if (bw == CHANNEL_WIDTH_20) {/* AC 20MHz doesn't support MCS9 */
1465 ratr_bitmap &= 0x7fdfffff;
1466 ratr_bitmap_msb &= 0x1ff;
1467 }
1468 }
1469 break;
1470
1471 case PHYDM_WIRELESS_MODE_AC_5G:
1472 {
1473 if (rf_type == RF_1T1R)
1474 ratr_bitmap &= 0x003ff010;
1475 else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R)
1476 ratr_bitmap &= 0xfffff010;
1477 else {/*3T*/
1478
1479 ratr_bitmap &= 0xfffff010;
1480 ratr_bitmap_msb &= 0x3ff;
1481 }
1482
1483 if (bw == CHANNEL_WIDTH_20) {/* AC 20MHz doesn't support MCS9 */
1484 ratr_bitmap &= 0x7fdfffff;
1485 ratr_bitmap_msb &= 0x1ff;
1486 }
1487 }
1488 break;
1489
1490 default:
1491 break;
1492 }
1493
1494 if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
1495
1496 if (tx_rate_level == 0)
1497 ratr_bitmap &= 0xffffffff;
1498 else if (tx_rate_level == 1)
1499 ratr_bitmap &= 0xfffffff0;
1500 else if (tx_rate_level == 2)
1501 ratr_bitmap &= 0xffffefe0;
1502 else if (tx_rate_level == 3)
1503 ratr_bitmap &= 0xffffcfc0;
1504 else if (tx_rate_level == 4)
1505 ratr_bitmap &= 0xffff8f80;
1506 else if (tx_rate_level >= 5)
1507 ratr_bitmap &= 0xffff0f00;
1508
1509 }
1510
1511 if (disable_cck_rate)
1512 ratr_bitmap &= 0xfffffff0;
1513
1514 PHYDM_DBG(p_dm, DBG_RA_MASK, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
1515 wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level));
1516
1517 /*PHYDM_DBG(p_dm, DBG_RA_MASK, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/
1518
1519 *ratr_bitmap_lsb_in = ratr_bitmap;
1520 *ratr_bitmap_msb_in = ratr_bitmap_msb;
1521 PHYDM_DBG(p_dm, DBG_RA_MASK, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in));
1522
1523 }
1524
1525 u8
phydm_rssi_lv_dec(void * p_dm_void,u32 rssi,u8 ratr_state)1526 phydm_rssi_lv_dec(
1527 void *p_dm_void,
1528 u32 rssi,
1529 u8 ratr_state
1530 )
1531 {
1532 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1533 u8 rssi_lv_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
1534 u8 new_rssi_lv = 0;
1535 u8 i;
1536
1537 PHYDM_DBG(p_dm, DBG_RA_MASK, ("curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n",
1538 ratr_state, rssi_lv_table[0], rssi_lv_table[1], rssi_lv_table[2], rssi_lv_table[3], rssi_lv_table[4], rssi_lv_table[5]));
1539
1540 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
1541
1542 if (i >= (ratr_state))
1543 rssi_lv_table[i] += RA_FLOOR_UP_GAP;
1544 }
1545
1546 PHYDM_DBG(p_dm, DBG_RA_MASK, ("RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n",
1547 rssi, rssi_lv_table[0], rssi_lv_table[1], rssi_lv_table[2], rssi_lv_table[3], rssi_lv_table[4], rssi_lv_table[5]));
1548
1549 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
1550
1551 if (rssi < rssi_lv_table[i]) {
1552 new_rssi_lv = i;
1553 break;
1554 }
1555 }
1556 return new_rssi_lv;
1557 }
1558
1559 u8
phydm_rate_order_compute(void * p_dm_void,u8 rate_idx)1560 phydm_rate_order_compute(
1561 void *p_dm_void,
1562 u8 rate_idx
1563 )
1564 {
1565 u8 rate_order = 0;
1566
1567 if (rate_idx >= ODM_RATEVHTSS4MCS0) {
1568
1569 rate_idx -= ODM_RATEVHTSS4MCS0;
1570 /**/
1571 } else if (rate_idx >= ODM_RATEVHTSS3MCS0) {
1572
1573 rate_idx -= ODM_RATEVHTSS3MCS0;
1574 /**/
1575 } else if (rate_idx >= ODM_RATEVHTSS2MCS0) {
1576
1577 rate_idx -= ODM_RATEVHTSS2MCS0;
1578 /**/
1579 } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
1580
1581 rate_idx -= ODM_RATEVHTSS1MCS0;
1582 /**/
1583 } else if (rate_idx >= ODM_RATEMCS24) {
1584
1585 rate_idx -= ODM_RATEMCS24;
1586 /**/
1587 } else if (rate_idx >= ODM_RATEMCS16) {
1588
1589 rate_idx -= ODM_RATEMCS16;
1590 /**/
1591 } else if (rate_idx >= ODM_RATEMCS8) {
1592
1593 rate_idx -= ODM_RATEMCS8;
1594 /**/
1595 }
1596 rate_order = rate_idx;
1597
1598 return rate_order;
1599
1600 }
1601
1602 void
phydm_ra_common_info_update(void * p_dm_void)1603 phydm_ra_common_info_update(
1604 void *p_dm_void
1605 )
1606 {
1607 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1608 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
1609 struct cmn_sta_info *p_sta = NULL;
1610 u16 macid;
1611 u8 rate_order_tmp;
1612 u8 cnt = 0;
1613
1614 p_ra_table->highest_client_tx_order = 0;
1615 p_ra_table->power_tracking_flag = 1;
1616
1617 if (p_dm->number_linked_client != 0) {
1618 for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
1619
1620 p_sta = p_dm->p_phydm_sta_info[macid];
1621
1622 if (is_sta_active(p_sta)) {
1623
1624 rate_order_tmp = phydm_rate_order_compute(p_dm, (p_sta->ra_info.curr_tx_rate & 0x7f));
1625
1626 if (rate_order_tmp >= (p_ra_table->highest_client_tx_order)) {
1627 p_ra_table->highest_client_tx_order = rate_order_tmp;
1628 p_ra_table->highest_client_tx_rate_order = macid;
1629 }
1630
1631 cnt++;
1632
1633 if (cnt == p_dm->number_linked_client)
1634 break;
1635 }
1636 }
1637 PHYDM_DBG(p_dm, DBG_RA, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (p_ra_table->highest_client_tx_rate_order), (p_ra_table->highest_client_tx_order)));
1638 }
1639 }
1640
1641 void
phydm_ra_info_watchdog(void * p_dm_void)1642 phydm_ra_info_watchdog(
1643 void *p_dm_void
1644 )
1645 {
1646 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1647
1648 phydm_ra_common_info_update(p_dm);
1649 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
1650 phydm_ra_dynamic_retry_limit(p_dm);
1651 #endif
1652 phydm_ra_dynamic_retry_count(p_dm);
1653 phydm_refresh_rate_adaptive_mask(p_dm);
1654
1655 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1656 odm_refresh_basic_rate_mask(p_dm);
1657 #endif
1658 }
1659
1660 void
phydm_ra_info_init(void * p_dm_void)1661 phydm_ra_info_init(
1662 void *p_dm_void
1663 )
1664 {
1665 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1666 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
1667
1668 p_ra_table->highest_client_tx_rate_order = 0;
1669 p_ra_table->highest_client_tx_order = 0;
1670 p_ra_table->RA_threshold_offset = 0;
1671 p_ra_table->RA_offset_direction = 0;
1672
1673 #if (RTL8822B_SUPPORT == 1)
1674 if (p_dm->support_ic_type == ODM_RTL8822B) {
1675 u32 ret_value;
1676
1677 ret_value = odm_get_bb_reg(p_dm, 0x4c8, MASKBYTE2);
1678 odm_set_bb_reg(p_dm, 0x4cc, MASKBYTE3, (ret_value - 1));
1679 }
1680 #endif
1681
1682 #ifdef CONFIG_RA_DYNAMIC_RTY_LIMIT
1683 phydm_ra_dynamic_retry_limit_init(p_dm);
1684 #endif
1685
1686 #ifdef CONFIG_RA_DYNAMIC_RATE_ID
1687 phydm_ra_dynamic_rate_id_init(p_dm);
1688 #endif
1689
1690 #ifdef CONFIG_RA_DBG_CMD
1691 odm_ra_para_adjust_init(p_dm);
1692 #endif
1693
1694 phydm_rate_adaptive_mask_init(p_dm);
1695
1696 }
1697
1698 u8
odm_find_rts_rate(void * p_dm_void,u8 tx_rate,boolean is_erp_protect)1699 odm_find_rts_rate(
1700 void *p_dm_void,
1701 u8 tx_rate,
1702 boolean is_erp_protect
1703 )
1704 {
1705 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1706 u8 rts_ini_rate = ODM_RATE6M;
1707
1708 if (is_erp_protect) /* use CCK rate as RTS*/
1709 rts_ini_rate = ODM_RATE1M;
1710 else {
1711 switch (tx_rate) {
1712 case ODM_RATEVHTSS3MCS9:
1713 case ODM_RATEVHTSS3MCS8:
1714 case ODM_RATEVHTSS3MCS7:
1715 case ODM_RATEVHTSS3MCS6:
1716 case ODM_RATEVHTSS3MCS5:
1717 case ODM_RATEVHTSS3MCS4:
1718 case ODM_RATEVHTSS3MCS3:
1719 case ODM_RATEVHTSS2MCS9:
1720 case ODM_RATEVHTSS2MCS8:
1721 case ODM_RATEVHTSS2MCS7:
1722 case ODM_RATEVHTSS2MCS6:
1723 case ODM_RATEVHTSS2MCS5:
1724 case ODM_RATEVHTSS2MCS4:
1725 case ODM_RATEVHTSS2MCS3:
1726 case ODM_RATEVHTSS1MCS9:
1727 case ODM_RATEVHTSS1MCS8:
1728 case ODM_RATEVHTSS1MCS7:
1729 case ODM_RATEVHTSS1MCS6:
1730 case ODM_RATEVHTSS1MCS5:
1731 case ODM_RATEVHTSS1MCS4:
1732 case ODM_RATEVHTSS1MCS3:
1733 case ODM_RATEMCS15:
1734 case ODM_RATEMCS14:
1735 case ODM_RATEMCS13:
1736 case ODM_RATEMCS12:
1737 case ODM_RATEMCS11:
1738 case ODM_RATEMCS7:
1739 case ODM_RATEMCS6:
1740 case ODM_RATEMCS5:
1741 case ODM_RATEMCS4:
1742 case ODM_RATEMCS3:
1743 case ODM_RATE54M:
1744 case ODM_RATE48M:
1745 case ODM_RATE36M:
1746 case ODM_RATE24M:
1747 rts_ini_rate = ODM_RATE24M;
1748 break;
1749 case ODM_RATEVHTSS3MCS2:
1750 case ODM_RATEVHTSS3MCS1:
1751 case ODM_RATEVHTSS2MCS2:
1752 case ODM_RATEVHTSS2MCS1:
1753 case ODM_RATEVHTSS1MCS2:
1754 case ODM_RATEVHTSS1MCS1:
1755 case ODM_RATEMCS10:
1756 case ODM_RATEMCS9:
1757 case ODM_RATEMCS2:
1758 case ODM_RATEMCS1:
1759 case ODM_RATE18M:
1760 case ODM_RATE12M:
1761 rts_ini_rate = ODM_RATE12M;
1762 break;
1763 case ODM_RATEVHTSS3MCS0:
1764 case ODM_RATEVHTSS2MCS0:
1765 case ODM_RATEVHTSS1MCS0:
1766 case ODM_RATEMCS8:
1767 case ODM_RATEMCS0:
1768 case ODM_RATE9M:
1769 case ODM_RATE6M:
1770 rts_ini_rate = ODM_RATE6M;
1771 break;
1772 case ODM_RATE11M:
1773 case ODM_RATE5_5M:
1774 case ODM_RATE2M:
1775 case ODM_RATE1M:
1776 rts_ini_rate = ODM_RATE1M;
1777 break;
1778 default:
1779 rts_ini_rate = ODM_RATE6M;
1780 break;
1781 }
1782 }
1783
1784 if (*p_dm->p_band_type == ODM_BAND_5G) {
1785 if (rts_ini_rate < ODM_RATE6M)
1786 rts_ini_rate = ODM_RATE6M;
1787 }
1788 return rts_ini_rate;
1789
1790 }
1791
1792 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1793
1794 void
odm_refresh_basic_rate_mask(void * p_dm_void)1795 odm_refresh_basic_rate_mask(
1796 void *p_dm_void
1797 )
1798 {
1799 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1800 struct _ADAPTER *adapter = p_dm->adapter;
1801 static u8 stage = 0;
1802 u8 cur_stage = 0;
1803 OCTET_STRING os_rate_set;
1804 PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter);
1805 u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
1806
1807 if (p_dm->support_ic_type != ODM_RTL8812 && p_dm->support_ic_type != ODM_RTL8821)
1808 return;
1809
1810 if (p_dm->is_linked == false) /* unlink Default port information */
1811 cur_stage = 0;
1812 else if (p_dm->rssi_min < 40) /* link RSSI < 40% */
1813 cur_stage = 1;
1814 else if (p_dm->rssi_min > 45) /* link RSSI > 45% */
1815 cur_stage = 3;
1816 else
1817 cur_stage = 2; /* link 25% <= RSSI <= 30% */
1818
1819 if (cur_stage != stage) {
1820 if (cur_stage == 1) {
1821 FillOctetString(os_rate_set, rate_set, 5);
1822 FilterSupportRate(p_mgnt_info->mBrates, &os_rate_set, false);
1823 phydm_set_hw_reg_handler_interface(p_dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);
1824 } else if (cur_stage == 3 && (stage == 1 || stage == 2))
1825 phydm_set_hw_reg_handler_interface(p_dm, HW_VAR_BASIC_RATE, (u8 *)(&p_mgnt_info->mBrates));
1826 }
1827
1828 stage = cur_stage;
1829 }
1830
1831 void
odm_refresh_ldpc_rts_mp(struct _ADAPTER * p_adapter,struct PHY_DM_STRUCT * p_dm,u8 m_mac_id,u8 iot_peer,s32 undecorated_smoothed_pwdb)1832 odm_refresh_ldpc_rts_mp(
1833 struct _ADAPTER *p_adapter,
1834 struct PHY_DM_STRUCT *p_dm,
1835 u8 m_mac_id,
1836 u8 iot_peer,
1837 s32 undecorated_smoothed_pwdb
1838 )
1839 {
1840 boolean is_ctl_ldpc = false;
1841 struct _rate_adaptive_table_ *p_ra_t = &p_dm->dm_ra_table;
1842
1843 if (p_dm->support_ic_type != ODM_RTL8821 && p_dm->support_ic_type != ODM_RTL8812)
1844 return;
1845
1846 if ((p_dm->support_ic_type == ODM_RTL8821) && (p_dm->cut_version == ODM_CUT_A))
1847 is_ctl_ldpc = true;
1848 else if (p_dm->support_ic_type == ODM_RTL8812 &&
1849 iot_peer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP)
1850 is_ctl_ldpc = true;
1851
1852 if (is_ctl_ldpc) {
1853 if (undecorated_smoothed_pwdb < (p_ra_t->ldpc_thres - 5))
1854 MgntSet_TX_LDPC(p_adapter, m_mac_id, true);
1855 else if (undecorated_smoothed_pwdb > p_ra_t->ldpc_thres)
1856 MgntSet_TX_LDPC(p_adapter, m_mac_id, false);
1857 }
1858 }
1859
1860 void
odm_rate_adaptive_state_ap_init(void * PADAPTER_VOID,struct cmn_sta_info * p_entry)1861 odm_rate_adaptive_state_ap_init(
1862 void *PADAPTER_VOID,
1863 struct cmn_sta_info*p_entry
1864 )
1865 {
1866 struct _ADAPTER *adapter = (struct _ADAPTER *)PADAPTER_VOID;
1867 p_entry->ra_info.rssi_level = DM_RATR_STA_INIT;
1868 }
1869
1870 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
1871
1872 void
phydm_gen_ramask_h2c_AP(void * p_dm_void,struct rtl8192cd_priv * priv,struct sta_info * p_entry,u8 rssi_level)1873 phydm_gen_ramask_h2c_AP(
1874 void *p_dm_void,
1875 struct rtl8192cd_priv *priv,
1876 struct sta_info *p_entry,
1877 u8 rssi_level
1878 )
1879 {
1880 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1881
1882 if (p_dm->support_ic_type == ODM_RTL8812) {
1883
1884 #if (RTL8812A_SUPPORT == 1)
1885 UpdateHalRAMask8812(priv, p_entry, rssi_level);
1886 /**/
1887 #endif
1888 } else if (p_dm->support_ic_type == ODM_RTL8188E) {
1889
1890 #if (RTL8188E_SUPPORT == 1)
1891 #ifdef TXREPORT
1892 add_RATid(priv, p_entry);
1893 /**/
1894 #endif
1895 #endif
1896 } else {
1897 #ifdef CONFIG_WLAN_HAL
1898 GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, p_entry, rssi_level);
1899 #endif
1900 }
1901 }
1902
1903 #endif
1904
1905 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
1906
1907 void
phydm_retry_limit_table_bound(void * p_dm_void,u8 * retry_limit,u8 offset)1908 phydm_retry_limit_table_bound(
1909 void *p_dm_void,
1910 u8 *retry_limit,
1911 u8 offset
1912 )
1913 {
1914 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1915 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
1916
1917 if (*retry_limit > offset) {
1918
1919 *retry_limit -= offset;
1920
1921 if (*retry_limit < p_ra_table->retrylimit_low)
1922 *retry_limit = p_ra_table->retrylimit_low;
1923 else if (*retry_limit > p_ra_table->retrylimit_high)
1924 *retry_limit = p_ra_table->retrylimit_high;
1925 } else
1926 *retry_limit = p_ra_table->retrylimit_low;
1927 }
1928
1929 void
phydm_reset_retry_limit_table(void * p_dm_void)1930 phydm_reset_retry_limit_table(
1931 void *p_dm_void
1932 )
1933 {
1934 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1935 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
1936 u8 i;
1937
1938 u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {
1939 1, 1, 2, 4, /*CCK*/
1940 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
1941 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/
1942 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/
1943 };
1944 u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {
1945 1, 1, 2, 4, /*CCK*/
1946 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
1947 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/
1948 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/
1949 };
1950
1951 memcpy(&(p_ra_table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX);
1952 memcpy(&(p_ra_table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX);
1953
1954 for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
1955 phydm_retry_limit_table_bound(p_dm, &(p_ra_table->per_rate_retrylimit_20M[i]), 0);
1956 phydm_retry_limit_table_bound(p_dm, &(p_ra_table->per_rate_retrylimit_40M[i]), 0);
1957 }
1958 }
1959
1960 void
phydm_ra_dynamic_retry_limit_init(void * p_dm_void)1961 phydm_ra_dynamic_retry_limit_init(
1962 void *p_dm_void
1963 )
1964 {
1965 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1966 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
1967
1968 p_ra_table->retry_descend_num = RA_RETRY_DESCEND_NUM;
1969 p_ra_table->retrylimit_low = RA_RETRY_LIMIT_LOW;
1970 p_ra_table->retrylimit_high = RA_RETRY_LIMIT_HIGH;
1971
1972 phydm_reset_retry_limit_table(p_dm);
1973
1974 }
1975
1976 void
phydm_ra_dynamic_retry_limit(void * p_dm_void)1977 phydm_ra_dynamic_retry_limit(
1978 void *p_dm_void
1979 )
1980 {
1981
1982 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1983 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
1984 u8 i, retry_offset;
1985 u32 ma_rx_tp;
1986
1987
1988 if (p_dm->pre_number_active_client == p_dm->number_active_client) {
1989
1990 PHYDM_DBG(p_dm, DBG_RA, (" pre_number_active_client == number_active_client\n"));
1991 return;
1992
1993 } else {
1994 if (p_dm->number_active_client == 1) {
1995 phydm_reset_retry_limit_table(p_dm);
1996 PHYDM_DBG(p_dm, DBG_RA, ("one client only->reset to default value\n"));
1997 } else {
1998
1999 retry_offset = p_dm->number_active_client * p_ra_table->retry_descend_num;
2000
2001 for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
2002
2003 phydm_retry_limit_table_bound(p_dm, &(p_ra_table->per_rate_retrylimit_20M[i]), retry_offset);
2004 phydm_retry_limit_table_bound(p_dm, &(p_ra_table->per_rate_retrylimit_40M[i]), retry_offset);
2005 }
2006 }
2007 }
2008 }
2009 #endif
2010
2011 #if (defined(CONFIG_RA_DYNAMIC_RATE_ID))
2012 void
phydm_ra_dynamic_rate_id_on_assoc(void * p_dm_void,u8 wireless_mode,u8 init_rate_id)2013 phydm_ra_dynamic_rate_id_on_assoc(
2014 void *p_dm_void,
2015 u8 wireless_mode,
2016 u8 init_rate_id
2017 )
2018 {
2019 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2020
2021 PHYDM_DBG(p_dm, DBG_RA, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", p_dm->rf_type, wireless_mode, init_rate_id));
2022
2023 if ((p_dm->rf_type == RF_2T2R) || (p_dm->rf_type == RF_2T3R) || (p_dm->rf_type == RF_2T4R)) {
2024
2025 if ((p_dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&
2026 (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))
2027 ) {
2028 PHYDM_DBG(p_dm, DBG_RA, ("[ON ASSOC] set N-2SS ARFR5 table\n"));
2029 odm_set_mac_reg(p_dm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
2030 odm_set_mac_reg(p_dm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
2031 } else if ((p_dm->support_ic_type & (ODM_RTL8812)) &&
2032 (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))
2033 ) {
2034 PHYDM_DBG(p_dm, DBG_RA, ("[ON ASSOC] set AC-2SS ARFR0 table\n"));
2035 odm_set_mac_reg(p_dm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/
2036 odm_set_mac_reg(p_dm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/
2037 }
2038 }
2039
2040 }
2041
2042 void
phydm_ra_dynamic_rate_id_init(void * p_dm_void)2043 phydm_ra_dynamic_rate_id_init(
2044 void *p_dm_void
2045 )
2046 {
2047 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2048
2049 if (p_dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
2050
2051 odm_set_mac_reg(p_dm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
2052 odm_set_mac_reg(p_dm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
2053
2054 odm_set_mac_reg(p_dm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/
2055 odm_set_mac_reg(p_dm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/
2056 }
2057 }
2058
2059 void
phydm_update_rate_id(void * p_dm_void,u8 rate,u8 platform_macid)2060 phydm_update_rate_id(
2061 void *p_dm_void,
2062 u8 rate,
2063 u8 platform_macid
2064 )
2065 {
2066 #if 0
2067
2068 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2069 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
2070 u8 current_tx_ss;
2071 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
2072 u8 wireless_mode;
2073 u8 phydm_macid;
2074 struct sta_info *p_entry;
2075 struct cmn_sta_info *p_sta;
2076
2077
2078 #if 0
2079 if (rate_idx >= ODM_RATEVHTSS2MCS0) {
2080 PHYDM_DBG(p_dm, DBG_RA, ("rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0)));
2081 /*dummy for SD4 check patch*/
2082 } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
2083 PHYDM_DBG(p_dm, DBG_RA, ("rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0)));
2084 /*dummy for SD4 check patch*/
2085 } else if (rate_idx >= ODM_RATEMCS0) {
2086 PHYDM_DBG(p_dm, DBG_RA, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEMCS0)));
2087 /*dummy for SD4 check patch*/
2088 } else {
2089 PHYDM_DBG(p_dm, DBG_RA, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx));
2090 /*dummy for SD4 check patch*/
2091 }
2092 #endif
2093
2094 phydm_macid = p_dm->phydm_macid_table[platform_macid];
2095 p_entry = p_dm->p_odm_sta_info[phydm_macid];
2096 p_sta = p_dm->p_phydm_sta_info[phydm_macid];
2097
2098 if (is_sta_active(p_sta)) {
2099 wireless_mode = p_entry->wireless_mode;
2100
2101 if ((p_dm->rf_type == RF_2T2R) || (p_dm->rf_type == RF_2T3R) || (p_dm->rf_type == RF_2T4R)) {
2102
2103 if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/
2104 if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/
2105
2106 p_sta->ra_info.rate_id = ARFR_5_RATE_ID;
2107 PHYDM_DBG(p_dm, DBG_RA, ("ARFR_5\n"));
2108 }
2109 } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/
2110 if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/
2111
2112 p_sta->ra_info.rate_id = ARFR_0_RATE_ID;
2113 PHYDM_DBG(p_dm, DBG_RA, ("ARFR_0\n"));
2114 }
2115 } else
2116 p_sta->ra_info.rate_id = ARFR_0_RATE_ID;
2117
2118 PHYDM_DBG(p_dm, DBG_RA, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, p_sta->ra_info.rate_id));
2119 }
2120 }
2121 #endif
2122 }
2123
2124 #endif
2125
2126 #if (defined(CONFIG_RA_DBG_CMD))
2127 void
odm_ra_para_adjust_send_h2c(void * p_dm_void)2128 odm_ra_para_adjust_send_h2c(
2129 void *p_dm_void
2130 )
2131 {
2132
2133 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2134 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
2135 u8 h2c_parameter[6] = {0};
2136
2137 h2c_parameter[0] = RA_FIRST_MACID;
2138
2139 if (p_ra_table->ra_para_feedback_req) { /*h2c_parameter[5]=1 ; ask FW for all RA parameters*/
2140 PHYDM_DBG(p_dm, DBG_RA, ("[H2C] Ask FW for RA parameter\n"));
2141 h2c_parameter[5] |= BIT(1); /*ask FW to report RA parameters*/
2142 h2c_parameter[1] = p_ra_table->para_idx; /*p_ra_table->para_idx;*/
2143 p_ra_table->ra_para_feedback_req = 0;
2144 } else {
2145 PHYDM_DBG(p_dm, DBG_RA, ("[H2C] Send H2C to FW for modifying RA parameter\n"));
2146
2147 h2c_parameter[1] = p_ra_table->para_idx;
2148 h2c_parameter[2] = p_ra_table->rate_idx;
2149 /* [8 bit]*/
2150 if (p_ra_table->para_idx == RADBG_RTY_PENALTY || p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO || p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) {
2151 h2c_parameter[3] = p_ra_table->value;
2152 h2c_parameter[4] = 0;
2153 }
2154 /* [16 bit]*/
2155 else {
2156 h2c_parameter[3] = (u8)(((p_ra_table->value_16) & 0xf0) >> 4); /*byte1*/
2157 h2c_parameter[4] = (u8)((p_ra_table->value_16) & 0x0f); /*byte0*/
2158 }
2159 }
2160 PHYDM_DBG(p_dm, DBG_RA, (" h2c_parameter[1] = 0x%x\n", h2c_parameter[1]));
2161 PHYDM_DBG(p_dm, DBG_RA, (" h2c_parameter[2] = 0x%x\n", h2c_parameter[2]));
2162 PHYDM_DBG(p_dm, DBG_RA, (" h2c_parameter[3] = 0x%x\n", h2c_parameter[3]));
2163 PHYDM_DBG(p_dm, DBG_RA, (" h2c_parameter[4] = 0x%x\n", h2c_parameter[4]));
2164 PHYDM_DBG(p_dm, DBG_RA, (" h2c_parameter[5] = 0x%x\n", h2c_parameter[5]));
2165
2166 odm_fill_h2c_cmd(p_dm, ODM_H2C_RA_PARA_ADJUST, 6, h2c_parameter);
2167
2168 }
2169
2170
2171 void
odm_ra_para_adjust(void * p_dm_void)2172 odm_ra_para_adjust(
2173 void *p_dm_void
2174 )
2175 {
2176 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2177 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
2178 u8 rate_idx = p_ra_table->rate_idx;
2179 u8 value = p_ra_table->value;
2180 u8 pre_value = 0xff;
2181
2182 if (p_ra_table->para_idx == RADBG_RTY_PENALTY) {
2183 pre_value = p_ra_table->RTY_P[rate_idx];
2184 p_ra_table->RTY_P[rate_idx] = value;
2185 p_ra_table->RTY_P_modify_note[rate_idx] = 1;
2186 } else if (p_ra_table->para_idx == RADBG_N_HIGH) {
2187
2188 } else if (p_ra_table->para_idx == RADBG_N_LOW) {
2189
2190 } else if (p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO) {
2191 pre_value = p_ra_table->RATE_UP_RTY_RATIO[rate_idx];
2192 p_ra_table->RATE_UP_RTY_RATIO[rate_idx] = value;
2193 p_ra_table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1;
2194 } else if (p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) {
2195 pre_value = p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx];
2196 p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx] = value;
2197 p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1;
2198 }
2199 PHYDM_DBG(p_dm, DBG_RA, ("Change RA Papa[%d], rate[ %d ], ((%d)) -> ((%d))\n", p_ra_table->para_idx, rate_idx, pre_value, value));
2200 odm_ra_para_adjust_send_h2c(p_dm);
2201 }
2202
2203 void
phydm_ra_print_msg(void * p_dm_void,u8 * value,u8 * value_default,u8 * modify_note)2204 phydm_ra_print_msg(
2205 void *p_dm_void,
2206 u8 *value,
2207 u8 *value_default,
2208 u8 *modify_note
2209 )
2210 {
2211 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2212 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
2213 u32 i;
2214
2215 PHYDM_DBG(p_dm, DBG_RA, (" |rate index| |Current-value| |Default-value| |Modify?|\n"));
2216 for (i = 0 ; i <= (p_ra_table->rate_length); i++) {
2217 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2218 PHYDM_DBG(p_dm, DBG_RA, (" [ %d ] %20d %25d %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . ")));
2219 #else
2220 PHYDM_DBG(p_dm, DBG_RA, (" [ %d ] %10d %14d %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . ")));
2221 #endif
2222 }
2223
2224 }
2225
2226 void
odm_RA_debug(void * p_dm_void,u32 * const dm_value)2227 odm_RA_debug(
2228 void *p_dm_void,
2229 u32 *const dm_value
2230 )
2231 {
2232 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2233 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
2234
2235 p_ra_table->is_ra_dbg_init = false;
2236
2237 if (dm_value[0] == 100) { /*1 Print RA Parameters*/
2238 u8 default_pointer_value;
2239 u8 *pvalue;
2240 u8 *pvalue_default;
2241 u8 *pmodify_note;
2242
2243 pvalue = pvalue_default = pmodify_note = &default_pointer_value;
2244
2245 PHYDM_DBG(p_dm, DBG_RA, ("\n------------------------------------------------------------------------------------\n"));
2246
2247 if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/
2248 PHYDM_DBG(p_dm, DBG_RA, (" [1] RTY_PENALTY\n"));
2249 pvalue = &(p_ra_table->RTY_P[0]);
2250 pvalue_default = &(p_ra_table->RTY_P_default[0]);
2251 pmodify_note = (u8 *)&(p_ra_table->RTY_P_modify_note[0]);
2252 } else if (dm_value[1] == RADBG_N_HIGH) /* [2]*/
2253 PHYDM_DBG(p_dm, DBG_RA, (" [2] N_HIGH\n"));
2254
2255 else if (dm_value[1] == RADBG_N_LOW) /*[3]*/
2256 PHYDM_DBG(p_dm, DBG_RA, (" [3] N_LOW\n"));
2257
2258 else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/
2259 PHYDM_DBG(p_dm, DBG_RA, (" [8] RATE_UP_RTY_RATIO\n"));
2260 pvalue = &(p_ra_table->RATE_UP_RTY_RATIO[0]);
2261 pvalue_default = &(p_ra_table->RATE_UP_RTY_RATIO_default[0]);
2262 pmodify_note = (u8 *)&(p_ra_table->RATE_UP_RTY_RATIO_modify_note[0]);
2263 } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/
2264 PHYDM_DBG(p_dm, DBG_RA, (" [9] RATE_DOWN_RTY_RATIO\n"));
2265 pvalue = &(p_ra_table->RATE_DOWN_RTY_RATIO[0]);
2266 pvalue_default = &(p_ra_table->RATE_DOWN_RTY_RATIO_default[0]);
2267 pmodify_note = (u8 *)&(p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[0]);
2268 }
2269
2270 phydm_ra_print_msg(p_dm, pvalue, pvalue_default, pmodify_note);
2271 PHYDM_DBG(p_dm, DBG_RA, ("\n------------------------------------------------------------------------------------\n\n"));
2272
2273 } else if (dm_value[0] == 101) {
2274 p_ra_table->para_idx = (u8)dm_value[1];
2275
2276 p_ra_table->ra_para_feedback_req = 1;
2277 odm_ra_para_adjust_send_h2c(p_dm);
2278 } else {
2279 p_ra_table->para_idx = (u8)dm_value[0];
2280 p_ra_table->rate_idx = (u8)dm_value[1];
2281 p_ra_table->value = (u8)dm_value[2];
2282
2283 odm_ra_para_adjust(p_dm);
2284 }
2285 }
2286
2287 void
odm_ra_para_adjust_init(void * p_dm_void)2288 odm_ra_para_adjust_init(
2289 void *p_dm_void
2290 )
2291 {
2292 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
2293 struct _rate_adaptive_table_ *p_ra_table = &p_dm->dm_ra_table;
2294 u8 i;
2295 u8 ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO};
2296 u8 rate_size_ht_1ss = 20, rate_size_ht_2ss = 28, rate_size_ht_3ss = 36; /*4+8+8+8+8 =36*/
2297 u8 rate_size_vht_1ss = 10, rate_size_vht_2ss = 20, rate_size_vht_3ss = 30; /*10 + 10 +10 =30*/
2298 #if 0
2299 /* RTY_PENALTY = 1, u8 */
2300 /* N_HIGH = 2, */
2301 /* N_LOW = 3, */
2302 /* RATE_UP_TABLE = 4, */
2303 /* RATE_DOWN_TABLE = 5, */
2304 /* TRYING_NECESSARY = 6, */
2305 /* DROPING_NECESSARY = 7, */
2306 /* RATE_UP_RTY_RATIO = 8, u8 */
2307 /* RATE_DOWN_RTY_RATIO= 9, u8 */
2308 /* ALL_PARA = 0xff */
2309
2310 #endif
2311 PHYDM_DBG(p_dm, DBG_RA, ("odm_ra_para_adjust_init\n"));
2312
2313 /* JJ ADD 20161014 */
2314 if (p_dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D | ODM_RTL8710B))
2315 p_ra_table->rate_length = rate_size_ht_1ss;
2316 else if (p_dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F))
2317 p_ra_table->rate_length = rate_size_ht_2ss;
2318 else if (p_dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C))
2319 p_ra_table->rate_length = rate_size_ht_1ss + rate_size_vht_1ss;
2320 else if (p_dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B))
2321 p_ra_table->rate_length = rate_size_ht_2ss + rate_size_vht_2ss;
2322 else if (p_dm->support_ic_type == ODM_RTL8814A)
2323 p_ra_table->rate_length = rate_size_ht_3ss + rate_size_vht_3ss;
2324 else
2325 p_ra_table->rate_length = rate_size_ht_1ss;
2326
2327 p_ra_table->is_ra_dbg_init = true;
2328 for (i = 0; i < 3; i++) {
2329 p_ra_table->ra_para_feedback_req = 1;
2330 p_ra_table->para_idx = ra_para_pool_u8[i];
2331 odm_ra_para_adjust_send_h2c(p_dm);
2332 }
2333 }
2334
2335 #endif /*#if (defined(CONFIG_RA_DBG_CMD))*/
2336
2337
2338