1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __REG3_INFO_H__ 3 #define __REG3_INFO_H__ 4 5 #include "rga_drv.h" 6 7 /* sys reg */ 8 #define RGA3_SYS_CTRL 0x000 9 #define RGA3_CMD_CTRL 0x004 10 #define RGA3_CMD_ADDR 0x008 11 #define RGA3_MI_GROUP_CTRL 0x00c 12 #define RGA3_ARQOS_CTRL 0x010 13 #define RGA3_VERSION_NUM 0x018 14 #define RGA3_VERSION_TIM 0x01c 15 #define RGA3_INT_EN 0x020 16 #define RGA3_INT_RAW 0x024 17 #define RGA3_INT_MSK 0x028 18 #define RGA3_INT_CLR 0x02c 19 #define RGA3_RO_SRST 0x030 20 #define RGA3_STATUS0 0x034 21 #define RGA3_SCAN_CNT 0x038 22 #define RGA3_CMD_STATE 0x040 23 24 /* cmd reg */ 25 #define RGA3_WIN0_RD_CTRL_OFFSET 0x000 26 #define RGA3_WIN0_Y_BASE_OFFSET 0x010 27 #define RGA3_WIN0_U_BASE_OFFSET 0x014 28 #define RGA3_WIN0_V_BASE_OFFSET 0x018 29 #define RGA3_WIN0_VIR_STRIDE_OFFSET 0x01c 30 #define RGA3_WIN0_FBC_OFF_OFFSET 0x020 31 #define RGA3_WIN0_SRC_SIZE_OFFSET 0x024 32 #define RGA3_WIN0_ACT_OFF_OFFSET 0x028 33 #define RGA3_WIN0_ACT_SIZE_OFFSET 0x02c 34 #define RGA3_WIN0_DST_SIZE_OFFSET 0x030 35 #define RGA3_WIN0_SCL_FAC_OFFSET 0x034 36 #define RGA3_WIN0_UV_VIR_STRIDE_OFFSET 0x038 37 #define RGA3_WIN1_RD_CTRL_OFFSET 0x040 38 #define RGA3_WIN1_Y_BASE_OFFSET 0x050 39 #define RGA3_WIN1_U_BASE_OFFSET 0x054 40 #define RGA3_WIN1_V_BASE_OFFSET 0x058 41 #define RGA3_WIN1_VIR_STRIDE_OFFSET 0x05c 42 #define RGA3_WIN1_FBC_OFF_OFFSET 0x060 43 #define RGA3_WIN1_SRC_SIZE_OFFSET 0x064 44 #define RGA3_WIN1_ACT_OFF_OFFSET 0x068 45 #define RGA3_WIN1_ACT_SIZE_OFFSET 0x06c 46 #define RGA3_WIN1_DST_SIZE_OFFSET 0x070 47 #define RGA3_WIN1_SCL_FAC_OFFSET 0x074 48 #define RGA3_WIN1_UV_VIR_STRIDE_OFFSET 0x078 49 #define RGA3_OVLP_CTRL_OFFSET 0x080 50 #define RGA3_OVLP_OFF_OFFSET 0x084 51 #define RGA3_OVLP_TOP_KEY_MIN_OFFSET 0x088 52 #define RGA3_OVLP_TOP_KEY_MAX_OFFSET 0x08c 53 #define RGA3_OVLP_TOP_CTRL_OFFSET 0x090 54 #define RGA3_OVLP_BOT_CTRL_OFFSET 0x094 55 #define RGA3_OVLP_TOP_ALPHA_OFFSET 0x098 56 #define RGA3_OVLP_BOT_ALPHA_OFFSET 0x09c 57 #define RGA3_WR_CTRL_OFFSET 0x0a0 58 #define RGA3_WR_FBCE_CTRL_OFFSET 0x0a4 59 #define RGA3_WR_VIR_STRIDE_OFFSET 0x0a8 60 #define RGA3_WR_PL_VIR_STRIDE_OFFSET 0x0ac 61 #define RGA3_WR_Y_BASE_OFFSET 0x0b0 62 #define RGA3_WR_U_BASE_OFFSET 0x0b4 63 #define RGA3_WR_V_BASE_OFFSET 0x0b8 64 65 /* RGA3_SYS_CTRL */ 66 #define m_RGA3_SYS_CTRL_FRMEND_AUTO_RSTN_EN (0x1 << 11) 67 #define m_RGA3_SYS_CTRL_RGA_BIC_MODE (0x3 << 9) 68 #define m_RGA3_SYS_CTRL_RGA_RAM_CLK_ON (0x1 << 8) 69 #define m_RGA3_SYS_CTRL_CCLK_SRESET (0x1 << 4) 70 #define m_RGA3_SYS_CTRL_ACLK_SRESET (0x1 << 3) 71 #define m_RGA3_SYS_CTRL_RGA_LGC_CLK_ON (0x1 << 2) 72 #define m_RGA3_SYS_CTRL_CMD_MODE (0x1 << 1) 73 #define m_RGA3_SYS_CTRL_RGA_SART (0x1 << 0) 74 75 #define s_RGA3_SYS_CTRL_RGA_BIC_MODE(x) ((x & 0x3) << 9) 76 #define s_RGA3_SYS_CTRL_CCLK_SRESET(x) ((x & 0x1) << 4) 77 #define s_RGA3_SYS_CTRL_ACLK_SRESET(x) ((x & 0x1) << 3) 78 #define s_RGA3_SYS_CTRL_CMD_MODE(x) ((x & 0x1) << 1) 79 80 /* TODO: RGA3_INT_EN/RGA3_INT_RAW/RGA3_INT_MSK/RGA3_INT_CLR */ 81 #define m_RGA3_INT_WIN1_VOR_FIFO_REN_ERR (0x1 << 29) 82 #define m_RGA3_INT_WIN1_VOR_FIFO_WEN_ERR (0x1 << 28) 83 #define m_RGA3_INT_WIN1_HOR_FIFO_REN_ERR (0x1 << 27) 84 #define m_RGA3_INT_WIN1_HOR_FIFO_WEN_ERR (0x1 << 26) 85 #define m_RGA3_INT_WIN1_IN_FIFO_REB_ERR (0x1 << 25) 86 #define m_RGA3_INT_WIN1_IN_FIFO_WEN_ERR (0x1 << 24) 87 #define m_RGA3_INT_WIN0_VOR_FIFO_REN_ERR (0x1 << 21) 88 #define m_RGA3_INT_WIN0_VOR_FIFO_WEN_ERR (0x1 << 20) 89 #define m_RGA3_INT_WIN0_HOR_FIFO_REN_ERR (0x1 << 19) 90 #define m_RGA3_INT_WIN0_HOR_FIFO_WEN_ERR (0x1 << 18) 91 #define m_RGA3_INT_WIN0_IN_FIFO_REB_ERR (0x1 << 17) 92 #define m_RGA3_INT_WIN0_IN_FIFO_WEN_ERR (0x1 << 16) 93 #define m_RGA3_INT_RGA_MI_WR_BUS_ERR (0x1 << 15) 94 #define m_RGA3_INT_RGA_MI_WR_IN_HERR (0x1 << 14) 95 //The signal is invalid, it will be pulled up every time, no need to care. 96 // #define m_RGA3_INT_RGA_MI_WR_IN_VERR (0x1 << 13) 97 #define m_RGA3_INT_WIN1_V_ERR (0x1 << 11) 98 #define m_RGA3_INT_WIN1_H_ERR (0x1 << 10) 99 #define m_RGA3_INT_WIN1_FBCD_DEC_ERR (0x1 << 9) 100 #define m_RGA3_INT_WIN1_RD_FRM_END (0x1 << 8) //not error 101 #define m_RGA3_INT_WIN0_V_ERR (0x1 << 7) 102 #define m_RGA3_INT_WIN0_H_ERR (0x1 << 6) 103 #define m_RGA3_INT_WIN0_FBCD_DEC_ERR (0x1 << 5) 104 #define m_RGA3_INT_WIN0_RD_FRM_END (0x1 << 4) //not error 105 #define m_RGA3_INT_CMD_LINE_FINISH (0x1 << 3) //not error 106 #define m_RGA3_INT_RAG_MI_RD_BUS_ERR (0x1 << 2) 107 #define m_RGA3_INT_RGA_MMU_INTR (0x1 << 1) 108 #define m_RGA3_INT_FRM_DONE (0x1 << 0) //not error 109 110 #define m_RGA3_INT_ERROR_MASK \ 111 ( \ 112 m_RGA3_INT_RGA_MMU_INTR | \ 113 m_RGA3_INT_RAG_MI_RD_BUS_ERR | \ 114 m_RGA3_INT_WIN0_FBCD_DEC_ERR | \ 115 m_RGA3_INT_WIN0_H_ERR | \ 116 m_RGA3_INT_WIN0_V_ERR | \ 117 m_RGA3_INT_WIN1_FBCD_DEC_ERR | \ 118 m_RGA3_INT_WIN1_H_ERR | \ 119 m_RGA3_INT_WIN1_V_ERR | \ 120 m_RGA3_INT_RGA_MI_WR_IN_HERR | \ 121 m_RGA3_INT_RGA_MI_WR_BUS_ERR | \ 122 m_RGA3_INT_WIN0_IN_FIFO_WEN_ERR | \ 123 m_RGA3_INT_WIN0_IN_FIFO_REB_ERR | \ 124 m_RGA3_INT_WIN0_HOR_FIFO_WEN_ERR | \ 125 m_RGA3_INT_WIN0_HOR_FIFO_REN_ERR| \ 126 m_RGA3_INT_WIN0_VOR_FIFO_WEN_ERR | \ 127 m_RGA3_INT_WIN0_VOR_FIFO_REN_ERR | \ 128 m_RGA3_INT_WIN1_IN_FIFO_WEN_ERR | \ 129 m_RGA3_INT_WIN1_IN_FIFO_REB_ERR | \ 130 m_RGA3_INT_WIN1_HOR_FIFO_WEN_ERR | \ 131 m_RGA3_INT_WIN1_HOR_FIFO_REN_ERR| \ 132 m_RGA3_INT_WIN1_VOR_FIFO_WEN_ERR | \ 133 m_RGA3_INT_WIN1_VOR_FIFO_REN_ERR \ 134 ) 135 136 /* RGA3_CMD_CTRL */ 137 #define m_RGA3_CMD_CTRL_CMD_INCR_NUM (0x3ff << 3) 138 #define m_RGA3_CMD_CTRL_CMD_STOP_MODE (0x1 << 2) 139 #define m_RGA3_CMD_CTRL_CMD_INCR_VALID_P (0x1 << 1) 140 #define m_RGA3_CMD_CTRL_CMD_LINE_ST_P (0x1 << 0) 141 142 /* RGA3_RO_SRST */ 143 #define m_RGA3_RO_SRST_RO_RST_DONE (0x3f << 0) 144 145 /* RGA3_CMD_STATE */ 146 #define m_RGA3_CMD_STATE_CMD_CNT_CUR (0xfff << 16) 147 #define m_RGA3_CMD_STATE_CMD_WORKING (0x1 << 0) 148 149 /* RGA3_WIN0_RD_CTRL */ 150 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE (0x1 << 0) 151 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE (0x3 << 1) 152 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT (0xf << 4) 153 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_FORMAT (0x3 << 8) 154 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT (0x1 << 10) 155 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE (0x1 << 11) 156 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PIX_SWAP (0x1 << 12) 157 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP (0x1 << 13) 158 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT (0x1 << 16) 159 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR (0x1 << 17) 160 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR (0x1 << 18) 161 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY (0x1 << 20) 162 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP (0x1 << 21) 163 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY (0x1 << 22) 164 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP (0x1 << 23) 165 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN (0x1 << 24) 166 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN (0x1 << 25) 167 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_CSC_MODE (0x3 << 26) 168 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PERF_OPT_DIS (0x1 << 29) 169 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_ALIGN_DIS (0x1 << 30) 170 171 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE(x) ((x & 0x1) << 0) 172 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE(x) ((x & 0x3) << 1) 173 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT(x) ((x & 0xf) << 4) 174 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_FORMAT(x) ((x & 0x3) << 8) 175 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT(x) ((x & 0x1) << 10) 176 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE(x) ((x & 0x1) << 11) 177 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIX_SWAP(x) ((x & 0x1) << 12) 178 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP(x) ((x & 0x1) << 13) 179 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT(x) ((x & 0x1) << 16) 180 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR(x) ((x & 0x1) << 17) 181 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR(x) ((x & 0x1) << 18) 182 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x) ((x & 0x1) << 20) 183 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x) ((x & 0x1) << 21) 184 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(x) ((x & 0x1) << 22) 185 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(x) ((x & 0x1) << 23) 186 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN(x) ((x & 0x1) << 24) 187 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN(x) ((x & 0x1) << 25) 188 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_CSC_MODE(x) ((x & 0x3) << 26) 189 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PERF_OPT_DIS(x) ((x & 0x1) << 29) 190 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_ALIGN_DIS(x) ((x & 0x1) << 30) 191 192 /* RGA3_WIN0_FBC_OFF */ 193 #define m_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_XOFF (0x1fff << 0) 194 #define m_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_YOFF (0x1fff << 16) 195 196 #define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_XOFF(x) ((x & 0x1fff) << 0) 197 #define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_YOFF(x) ((x & 0x1fff) << 16) 198 199 /* RGA3_WIN0_SRC_SIZE */ 200 #define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_WIDTH (0x1fff << 0) 201 #define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_HEIGHT (0x1fff << 16) 202 203 #define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_WIDTH(x) ((x & 0x1fff) << 0) 204 #define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_HEIGHT(x) ((x & 0x1fff) << 16) 205 206 /* RGA3_WIN0_ACT_OFF */ 207 #define m_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_XOFF (0x1fff << 0) 208 #define m_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_YOFF (0x1fff << 16) 209 210 #define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_XOFF(x) ((x & 0x1fff) << 0) 211 #define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_YOFF(x) ((x & 0x1fff) << 16) 212 213 /* RGA3_WIN0_ACT_SIZE */ 214 #define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH (0x1fff << 0) 215 #define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT (0x1fff << 16) 216 217 #define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH(x) ((x & 0x1fff) << 0) 218 #define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT(x) ((x & 0x1fff) << 16) 219 220 /* RGA3_WIN0_DST_SIZE */ 221 #define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH (0x1fff << 0) 222 #define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT (0x1fff << 16) 223 224 #define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH(x) ((x & 0x1fff) << 0) 225 #define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT(x) ((x & 0x1fff) << 16) 226 227 /* RGA3_WIN0_SCL_FAC */ 228 #define m_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC (0xffff << 0) 229 #define m_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC (0xffff << 16) 230 231 #define s_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC(x) ((x & 0xffff) << 0) 232 #define s_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC(x) ((x & 0xffff) << 16) 233 234 /* RGA3_WIN1_RD_CTRL */ 235 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE (0x1 << 0) 236 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE (0x3 << 1) 237 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT (0xf << 4) 238 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_FORMAT (0x3 << 8) 239 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT (0x1 << 10) 240 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE (0x1 << 11) 241 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PIX_SWAP (0x1 << 12) 242 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP (0x1 << 13) 243 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT (0x1 << 16) 244 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR (0x1 << 17) 245 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR (0x1 << 18) 246 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY (0x1 << 20) 247 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP (0x1 << 21) 248 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY (0x1 << 22) 249 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP (0x1 << 23) 250 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN (0x1 << 24) 251 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN (0x1 << 25) 252 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_CSC_MODE (0x3 << 26) 253 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PERF_OPT_DIS (0x1 << 29) 254 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_ALIGN_DIS (0x1 << 30) 255 256 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE(x) ((x & 0x1) << 0) 257 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE(x) ((x & 0x3) << 1) 258 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT(x) ((x & 0xf) << 4) 259 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_FORMAT(x) ((x & 0x3) << 8) 260 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT(x) ((x & 0x1) << 10) 261 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE(x) ((x & 0x1) << 11) 262 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIX_SWAP(x) ((x & 0x1) << 12) 263 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP(x) ((x & 0x1) << 13) 264 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT(x) ((x & 0x1) << 16) 265 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR(x) ((x & 0x1) << 17) 266 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR(x) ((x & 0x1) << 18) 267 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY(x) ((x & 0x1) << 20) 268 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP(x) ((x & 0x1) << 21) 269 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY(x) ((x & 0x1) << 22) 270 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP(x) ((x & 0x1) << 23) 271 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN(x) ((x & 0x1) << 24) 272 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN(x) ((x & 0x1) << 25) 273 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_CSC_MODE(x) ((x & 0x3) << 26) 274 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PERF_OPT_DIS(x) ((x & 0x1) << 29) 275 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_ALIGN_DIS(x) ((x & 0x1) << 30) 276 277 /* RGA3_WIN1_FBC_OFF */ 278 #define m_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_XOFF (0x1fff << 0) 279 #define m_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_YOFF (0x1fff << 16) 280 281 #define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_XOFF(x) ((x & 0x1fff) << 0) 282 #define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_YOFF(x) ((x & 0x1fff) << 16) 283 284 /* RGA3_WIN1_SRC_SIZE */ 285 #define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_WIDTH (0x1fff << 0) 286 #define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_HEIGHT (0x1fff << 16) 287 288 #define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_WIDTH(x) ((x & 0x1fff) << 0) 289 #define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_HEIGHT(x) ((x & 0x1fff) << 16) 290 291 /* RGA3_WIN1_ACT_OFF */ 292 #define m_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_XOFF (0x1fff << 0) 293 #define m_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_YOFF (0x1fff << 16) 294 295 #define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_XOFF(x) ((x & 0x1fff) << 0) 296 #define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_YOFF(x) ((x & 0x1fff) << 16) 297 298 /* RGA3_WIN1_ACT_SIZE */ 299 #define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH (0x1fff << 0) 300 #define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT (0x1fff << 16) 301 302 #define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH(x) ((x & 0x1fff) << 0) 303 #define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT(x) ((x & 0x1fff) << 16) 304 305 /* RGA3_WIN1_DST_SIZE */ 306 #define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH (0x1fff << 0) 307 #define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT (0x1fff << 16) 308 309 #define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH(x) ((x & 0x1fff) << 0) 310 #define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT(x) ((x & 0x1fff) << 16) 311 312 /* RGA3_WIN1_SCL_FAC */ 313 #define m_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC (0xffff << 0) 314 #define m_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC (0xffff << 16) 315 316 #define s_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC(x) ((x & 0xffff) << 0) 317 #define s_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC(x) ((x & 0xffff) << 16) 318 319 /* RGA3_OVLP_CTRL */ 320 #define m_RGA3_OVLP_CTRL_SW_OVLP_MODE (0x3 << 0) 321 #define m_RGA3_OVLP_CTRL_SW_OVLP_FIELD (0x1 << 2) 322 #define m_RGA3_OVLP_CTRL_SW_TOP_SWAP (0x1 << 3) 323 #define m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN (0x1 << 4) 324 #define m_RGA3_OVLP_CTRL_SW_TOP_KEY_EN (0x7FFF << 5) 325 #define m_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN (0x1 << 20) 326 #define m_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN (0x1 << 21) 327 #define m_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE (0x3 << 22) 328 329 #define s_RGA3_OVLP_CTRL_SW_OVLP_MODE(x) ((x & 0x3) << 0) 330 #define s_RGA3_OVLP_CTRL_SW_OVLP_FIELD(x) ((x & 0x1) << 2) 331 #define s_RGA3_OVLP_CTRL_SW_TOP_SWAP(x) ((x & 0x1) << 3) 332 #define s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(x) ((x & 0x1) << 4) 333 #define s_RGA3_OVLP_CTRL_SW_TOP_KEY_EN(x) ((x & 0x7FFF) << 5) 334 #define s_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN(x) ((x & 0x1) << 20) 335 #define s_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN(x) ((x & 0x1) << 21) 336 #define s_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE(x) ((x & 0x3) << 22) 337 338 /* RGA3_OVLP_OFF */ 339 #define m_RGA3_OVLP_OFF_SW_OVLP_XOFF (0x1fff << 0) 340 #define m_RGA3_OVLP_OFF_SW_OVLP_YOFF (0x1fff << 16) 341 342 #define s_RGA3_OVLP_OFF_SW_OVLP_XOFF(x) ((x & 0x1fff) << 0) 343 #define s_RGA3_OVLP_OFF_SW_OVLP_YOFF(x) ((x & 0x1fff) << 16) 344 345 /* RGA3_OVLP_TOP_KEY_MIN */ 346 #define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN (0x3ff << 0) 347 #define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN (0x3ff << 10) 348 #define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN (0x3ff << 20) 349 350 #define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN(x) ((x & 0x3f)f << 0) 351 #define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN(x) ((x & 0x3ff) << 10) 352 #define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN(x) ((x & 0x3ff) << 20) 353 354 /* RGA3_OVLP_TOP_KEY_MAX */ 355 #define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX (0x3ff << 0) 356 #define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX (0x3ff << 10) 357 #define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX (0x3ff << 20) 358 359 #define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX(x) ((x & 0x3ff) << 0) 360 #define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX(x) ((x & 0x3ff) << 10) 361 #define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX(x) ((x & 0x3ff) << 20) 362 363 /* RGA3_OVLP_TOP_CTRL */ 364 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0 (0x1 << 0) 365 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0 (0x1 << 1) 366 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0 (0x3 << 2) 367 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0 (0x1 << 4) 368 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0 (0x7 << 5) 369 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA (0xff << 16) 370 371 #define s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0(x) ((x & 0x1) << 0) 372 #define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0(x) ((x & 0x1) << 1) 373 #define s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0(x) ((x & 0x3) << 2) 374 #define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0(x) ((x & 0x1) << 4) 375 #define s_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0(x) ((x & 0x7) << 5) 376 #define s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA(x) ((x & 0xff) << 16) 377 378 /* RGA3_OVLP_BOT_CTRL */ 379 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0 (0x1 << 0) 380 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0 (0x1 << 1) 381 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0 (0x3 << 2) 382 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0 (0x1 << 4) 383 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0 (0x7 << 5) 384 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA (0xff << 16) 385 386 #define s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0(x) ((x & 0x1) << 0) 387 #define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0(x) ((x & 0x1) << 1) 388 #define s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0(x) ((x & 0x3) << 2) 389 #define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0(x) ((x & 0x1) << 4) 390 #define s_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0(x) ((x & 0x7) << 5) 391 #define s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA(x) ((x & 0xff) << 16) 392 393 /* RGA3_OVLP_TOP_ALPHA */ 394 #define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1 (0x1 << 1) 395 #define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1 (0x3 << 2) 396 #define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1 (0x1 << 4) 397 #define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1 (0x7 << 5) 398 399 #define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1(x) ((x & 0x1) << 1) 400 #define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1(x) ((x & 0x3) << 2) 401 #define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1(x) ((x & 0x1) << 4) 402 #define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1(x) ((x & 0x7) << 5) 403 404 /* RGA3_OVLP_BOT_ALPHA */ 405 #define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1 (0x1 << 1) 406 #define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1 (0x3 << 2) 407 #define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1 (0x1 << 4) 408 #define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1 (0x7 << 5) 409 410 #define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1(x) ((x & 0x1) << 1) 411 #define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1(x) ((x & 0x3) << 2) 412 #define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1(x) ((x & 0x1) << 4) 413 #define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1(x) ((x & 0x7) << 5) 414 415 /* RGA3_WR_CTRL */ 416 #define m_RGA3_WR_CTRL_SW_WR_MODE (0x3 << 0) 417 #define m_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN (0x1 << 2) 418 #define m_RGA3_WR_CTRL_SW_WR_PIC_FORMAT (0xf << 4) 419 #define m_RGA3_WR_CTRL_SW_WR_FORMAT (0x3 << 8) 420 #define m_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT (0x1 << 10) 421 #define m_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE (0x1 << 11) 422 #define m_RGA3_WR_CTRL_SW_WR_PIX_SWAP (0x1 << 12) 423 #define m_RGA3_WR_CTRL_SW_OUTSTANDING_MAX (0x3f << 13) 424 #define m_RGA3_WR_CTRL_SW_WR_YC_SWAP (0x1 << 20) 425 426 #define s_RGA3_WR_CTRL_SW_WR_MODE(x) ((x & 0x3) << 0) 427 #define s_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN(x) ((x & 0x1) << 2) 428 #define s_RGA3_WR_CTRL_SW_WR_PIC_FORMAT(x) ((x & 0xf) << 4) 429 #define s_RGA3_WR_CTRL_SW_WR_FORMAT(x) ((x & 0x3) << 8) 430 #define s_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT(x) ((x & 0x1) << 10) 431 #define s_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE(x) ((x & 0x1) << 11) 432 #define s_RGA3_WR_CTRL_SW_WR_PIX_SWAP(x) ((x & 0x1) << 12) 433 #define s_RGA3_WR_CTRL_SW_OUTSTANDING_MAX(x) ((x & 0x3f) << 13) 434 #define s_RGA3_WR_CTRL_SW_WR_YC_SWAP(x) ((x & 0x1) << 20) 435 436 /* RGA3_WR_FBCE_CTRL */ 437 #define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS (0x1 << 0) 438 #define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_HOFF_DISS (0x1 << 1) 439 #define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK (0x3f << 2) 440 #define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK (0x3f << 8) 441 #define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS (0x1 << 31) 442 443 #define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS(x) ((x & 0x1) << 0) 444 #define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_HOFF_DISS(x) ((x & 0x1) << 1) 445 #define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK(x) ((x & 0x3f) << 2) 446 #define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK(x) ((x & 0x3f) << 8) 447 #define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS(x) ((x & 0x1) << 31) 448 449 /* RGA3_MMU_STATUS read_only */ 450 #define m_RGA3_MMU_STATUS_PAGING_ENABLED (0x1 << 0) 451 #define m_RGA3_MMU_STATUS_PAGE_FAULT_ACTIVE (0x1 << 1) 452 #define m_RGA3_MMU_STATUS_STAIL_ACTIVE (0x1 << 2) 453 #define m_RGA3_MMU_STATUS_MMU_IDLE (0x1 << 3) 454 #define m_RGA3_MMU_STATUS_REPLAY_BUFFER_EMPTY (0x1 << 4) 455 #define m_RGA3_MMU_STATUS_PAGE_FAULT_IS_WRITE (0x1 << 5) 456 #define m_RGA3_MMU_STATUS_PAGE_FAULT_BUS_ID (0x1f << 6) 457 458 /* RGA3_MMU_INT_RAWSTAT read_only */ 459 #define m_RGA3_MMU_INT_RAWSTAT_READ_BUS_ERROR (0x1 << 0) 460 #define m_RGA3_MMU_INT_RAWSTAT_PAGE_FAULT (0x1 << 1) 461 462 /* RGA3_MMU_INT_CLEAR write_only */ 463 #define m_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR (0x1 << 0) 464 #define m_RGA3_MMU_INT_CLEAR_PAGE_FAULT (0x1 << 1) 465 466 #define s_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR(x) ((x & 0x1) << 0) 467 #define s_RGA3_MMU_INT_CLEAR_PAGE_FAULT(x) ((x & 0x1) << 1) 468 469 /* RGA3_MMU_INT_MASK */ 470 #define m_RGA3_MMU_INT_MASK_READ_BUS_ERROR (0x1 << 0) 471 #define m_RGA3_MMU_INT_MASK_PAGE_FAULT (0x1 << 1) 472 473 #define s_RGA3_MMU_INT_MASK_READ_BUS_ERROR(x) ((x & 0x1) << 0) 474 #define s_RGA3_MMU_INT_MASK_PAGE_FAULT(x) ((x & 0x1) << 1) 475 476 /* RGA3_MMU_INT_STATUS read_only */ 477 #define m_RGA3_MMU_INT_STATUS_READ_BUS_ERROR (0x1 << 0) 478 #define m_RGA3_MMU_INT_STATUS_PAGE_FAULT (0x1 << 1) 479 480 /* RGA3_MMU_AUTO_GATING */ 481 #define m_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING (0x1 << 1) 482 #define m_RGA3_MMU_AUTO_GATING_MMU_CFG_MODE (0x1 << 1) 483 #define m_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE (0x1 << 31) 484 485 #define s_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING(x) ((x & 0x1) << 1) 486 #define s_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE(x) ((x & 0x1) << 31) 487 488 #define RGA3_ROT_BIT_ROT_90 BIT(0) 489 #define RGA3_ROT_BIT_X_MIRROR BIT(1) 490 #define RGA3_ROT_BIT_Y_MIRROR BIT(2) 491 492 union rga3_color_ctrl { 493 uint32_t value; 494 struct { 495 uint32_t color_mode:1; 496 uint32_t alpha_mode:1; 497 uint32_t blend_mode:2; 498 uint32_t alpha_cal_mode:1; 499 uint32_t factor_mode:3; 500 501 uint32_t reserved:8; 502 503 uint32_t global_alpha:8; 504 } bits; 505 }; 506 507 union rga3_alpha_ctrl { 508 uint32_t value; 509 struct { 510 uint32_t reserved:1; 511 uint32_t alpha_mode:1; 512 uint32_t blend_mode:2; 513 uint32_t alpha_cal_mode:1; 514 uint32_t factor_mode:3; 515 } bits; 516 }; 517 518 extern const struct rga_backend_ops rga3_ops; 519 520 #endif 521 522