1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __REG2_INFO_H__ 3 #define __REG2_INFO_H__ 4 5 6 //#include "chip_register.h" 7 8 //#include "rga_struct.h" 9 #include "rga2.h" 10 11 #ifndef MIN 12 #define MIN(X, Y) ((X)<(Y)?(X):(Y)) 13 #endif 14 15 #ifndef MAX 16 #define MAX(X, Y) ((X)>(Y)?(X):(Y)) 17 #endif 18 19 #ifndef ABS 20 #define ABS(X) (((X) < 0) ? (-(X)) : (X)) 21 #endif 22 23 #ifndef CLIP 24 #define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x)) 25 #endif 26 27 #define rRGA_SYS_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_SYS_CTRL_OFFSET )) 28 #define rRGA_CMD_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_CTRL_OFFSET )) 29 #define rRGA_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_BASE_OFFSET )) 30 #define rRGA_STATUS (*(volatile u32 *)(RGA2_BASE + RGA2_STATUS_OFFSET )) 31 #define rRGA_INT (*(volatile u32 *)(RGA2_BASE + RGA2_INT_OFFSET )) 32 #define rRGA_MMU_CTRL0 (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CTRL0_OFFSET )) 33 #define rRGA_MMU_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CMD_BASE_OFFSET)) 34 #define rRGA_CMD_ADDR (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_ADDR)) 35 36 /*RGA_INT*/ 37 #define m_RGA2_INT_ALL_CMD_DONE_INT_EN ( 1<<10 ) 38 #define m_RGA2_INT_MMU_INT_EN ( 1<<9 ) 39 #define m_RGA2_INT_ERROR_INT_EN ( 1<<8 ) 40 #define m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 ) 41 #define m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 ) 42 #define m_RGA2_INT_MMU_INT_CLEAR ( 1<<5 ) 43 #define m_RGA2_INT_ERROR_INT_CLEAR ( 1<<4 ) 44 #define m_RGA2_INT_CUR_CMD_DONE_INT_FLAG ( 1<<3 ) 45 #define m_RGA2_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 ) 46 #define m_RGA2_INT_MMU_INT_FLAG ( 1<<1 ) 47 #define m_RGA2_INT_ERROR_INT_FLAG ( 1<<0 ) 48 49 #define s_RGA2_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 ) 50 #define s_RGA2_INT_MMU_INT_EN(x) ( (x&0x1)<<9 ) 51 #define s_RGA2_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 ) 52 #define s_RGA2_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 ) 53 #define s_RGA2_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 ) 54 #define s_RGA2_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 ) 55 #define s_RGA2_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 ) 56 57 58 59 /* RGA_MODE_CTRL */ 60 #define m_RGA2_MODE_CTRL_SW_RENDER_MODE ( 0x7<<0 ) 61 #define m_RGA2_MODE_CTRL_SW_BITBLT_MODE ( 0x1<<3 ) 62 #define m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT ( 0x1<<4 ) 63 #define m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET ( 0x1<<5 ) 64 #define m_RGA2_MODE_CTRL_SW_GRADIENT_SAT ( 0x1<<6 ) 65 #define m_RGA2_MODE_CTRL_SW_INTR_CF_E ( 0x1<<7 ) 66 67 #define s_RGA2_MODE_CTRL_SW_RENDER_MODE(x) ( (x&0x7)<<0 ) 68 #define s_RGA2_MODE_CTRL_SW_BITBLT_MODE(x) ( (x&0x1)<<3 ) 69 #define s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(x) ( (x&0x1)<<4 ) 70 #define s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(x) ( (x&0x1)<<5 ) 71 #define s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(x) ( (x&0x1)<<6 ) 72 #define s_RGA2_MODE_CTRL_SW_INTR_CF_E(x) ( (x&0x1)<<7 ) 73 74 /* RGA_SRC_INFO */ 75 #define m_RGA2_SRC_INFO_SW_SRC_FMT ( 0xf<<0 ) 76 #define m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP ( 0x1<<4 ) 77 #define m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP ( 0x1<<5 ) 78 #define m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP ( 0x1<<6 ) 79 #define m_RGA2_SRC_INFO_SW_SW_CP_ENDAIN ( 0x1<<7 ) 80 #define m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE ( 0x3<<8 ) 81 #define m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE ( 0x3<<10 ) 82 #define m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE ( 0x3<<12 ) 83 #define m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE ( 0x3<<14 ) 84 #define m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE ( 0x3<<16 ) 85 #define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE ( 0x1<<18 ) 86 #define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E ( 0xf<<19 ) 87 #define m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E ( 0x1<<23 ) 88 #define m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER ( 0x3<<24 ) 89 #define m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL ( 0x1<<26 ) 90 #define m_RGA2_SRC_INFO_SW_SW_YUV10_E ( 0x1<<27 ) 91 #define m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E ( 0x1<<28 ) 92 93 94 95 96 97 #define s_RGA2_SRC_INFO_SW_SRC_FMT(x) ( (x&0xf)<<0 ) 98 #define s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(x) ( (x&0x1)<<4 ) 99 #define s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(x) ( (x&0x1)<<5 ) 100 #define s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(x) ( (x&0x1)<<6 ) 101 #define s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(x) ( (x&0x1)<<7 ) 102 #define s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(x) ( (x&0x3)<<8 ) 103 #define s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(x) ( (x&0x3)<<10 ) 104 #define s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE(x) ( (x&0x3)<<12 ) 105 #define s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE(x) ( (x&0x3)<<14 ) 106 #define s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(x) ( (x&0x3)<<16 ) 107 108 #define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(x) ( (x&0x1)<<18 ) 109 #define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(x) ( (x&0xf)<<19 ) 110 #define s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E(x) ( (x&0x1)<<23 ) 111 #define s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER(x) ( (x&0x3)<<24 ) 112 #define s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL(x) ( (x&0x1)<<26 ) 113 #define s_RGA2_SRC_INFO_SW_SW_YUV10_E(x) ( (x&0x1)<<27 ) 114 #define s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E(x) ( (x&0x1)<<28 ) 115 116 /* RGA_SRC_VIR_INFO */ 117 #define m_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE ( 0x7fff<<0 ) //modify 118 #define m_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE ( 0x3ff<<16 ) //modify 119 120 #define s_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE(x) ( (x&0x7fff)<<0 ) //modify 121 #define s_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE(x) ( (x&0x3ff)<<16 ) //modify 122 123 124 /* RGA_SRC_ACT_INFO */ 125 #define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH ( 0x1fff<<0 ) 126 #define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT ( 0x1fff<<16 ) 127 128 #define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH(x) ( (x&0x1fff)<<0 ) 129 #define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT(x) ( (x&0x1fff<)<16 ) 130 131 132 /* RGA_DST_INFO */ 133 #define m_RGA2_DST_INFO_SW_DST_FMT ( 0xf<<0 ) 134 #define m_RGA2_DST_INFO_SW_DST_RB_SWAP ( 0x1<<4 ) 135 #define m_RGA2_DST_INFO_SW_ALPHA_SWAP ( 0x1<<5 ) 136 #define m_RGA2_DST_INFO_SW_DST_UV_SWAP ( 0x1<<6 ) 137 #define m_RGA2_DST_INFO_SW_SRC1_FMT ( 0x7<<7 ) 138 #define m_RGA2_DST_INFO_SW_SRC1_RB_SWP ( 0x1<<10) 139 #define m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP ( 0x1<<11) 140 #define m_RGA2_DST_INFO_SW_DITHER_UP_E ( 0x1<<12) 141 #define m_RGA2_DST_INFO_SW_DITHER_DOWN_E ( 0x1<<13) 142 #define m_RGA2_DST_INFO_SW_DITHER_MODE ( 0x3<<14) 143 #define m_RGA2_DST_INFO_SW_DST_CSC_MODE ( 0x3<<16) //add 144 #define m_RGA2_DST_INFO_SW_CSC_CLIP_MODE ( 0x1<<18) 145 #define m_RGA2_DST_INFO_SW_DST_CSC_MODE_2 ( 0x1<<19) //add 146 #define m_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN ( 0x1<<24) 147 #define m_RGA2_DST_INFO_SW_DST_FMT_Y4_EN ( 0x1<<25) 148 #define m_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN ( 0x1<<26) 149 #define m_RGA2_DST_INFO_SW_SRC1_CSC_MODE ( 0x3<<20) //add 150 #define m_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE ( 0x1<<22) 151 152 #define s_RGA2_DST_INFO_SW_DST_FMT(x) ( (x&0xf)<<0 ) 153 #define s_RGA2_DST_INFO_SW_DST_RB_SWAP(x) ( (x&0x1)<<4 ) 154 #define s_RGA2_DST_INFO_SW_ALPHA_SWAP(x) ( (x&0x1)<<5 ) 155 #define s_RGA2_DST_INFO_SW_DST_UV_SWAP(x) ( (x&0x1)<<6 ) 156 #define s_RGA2_DST_INFO_SW_SRC1_FMT(x) ( (x&0x7)<<7 ) 157 #define s_RGA2_DST_INFO_SW_SRC1_RB_SWP(x) ( (x&0x1)<<10) 158 #define s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(x) ( (x&0x1)<<11) 159 #define s_RGA2_DST_INFO_SW_DITHER_UP_E(x) ( (x&0x1)<<12) 160 #define s_RGA2_DST_INFO_SW_DITHER_DOWN_E(x) ( (x&0x1)<<13) 161 #define s_RGA2_DST_INFO_SW_DITHER_MODE(x) ( (x&0x3)<<14) 162 #define s_RGA2_DST_INFO_SW_DST_CSC_MODE(x) ( (x&0x3)<<16) //add 163 #define s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(x) ( (x&0x1)<<18) 164 #define s_RGA2_DST_INFO_SW_DST_CSC_MODE_2(x) ( (x&0x1)<<19) //add 165 #define s_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN(x) ( (x&0x1)<<24) 166 #define s_RGA2_DST_INFO_SW_DST_FMT_Y4_EN(x) ( (x&0x1)<<25) 167 #define s_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN(x) ( (x&0x1)<<26) 168 #define s_RGA2_DST_INFO_SW_SRC1_CSC_MODE(x) ( (x&0x3)<<20) //add 169 #define s_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE(x) ( (x&0x1)<<22) 170 171 172 /* RGA_ALPHA_CTRL0 */ 173 #define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0 ( 0x1<<0 ) 174 #define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL ( 0x1<<1 ) 175 #define m_RGA2_ALPHA_CTRL0_SW_ROP_MODE ( 0x3<<2 ) 176 #define m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA ( 0xff<<4 ) 177 #define m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA ( 0xff<<12 ) 178 #define m_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN ( 0x1<<20 ) //add 179 180 #define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(x) ( (x&0x1)<<0 ) 181 #define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL(x) ( (x&0x1)<<1 ) 182 #define s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(x) ( (x&0x3)<<2 ) 183 #define s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA(x) ( (x&0xff)<<4 ) 184 #define s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA(x) ( (x&0xff)<<12 ) 185 #define s_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN(x) ( (x&0x1)<<20 ) //add 186 187 188 189 /* RGA_ALPHA_CTRL1 */ 190 #define m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0 ( 0x1<<0 ) 191 #define m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0 ( 0x1<<1 ) 192 #define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0 ( 0x7<<2 ) 193 #define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0 ( 0x7<<5 ) 194 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0 ( 0x1<<8 ) 195 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0 ( 0x1<<9 ) 196 #define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0 ( 0x3<<10) 197 #define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0 ( 0x3<<12) 198 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0 ( 0x1<<14) 199 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0 ( 0x1<<15) 200 #define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1 ( 0x7<<16) 201 #define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1 ( 0x7<<19) 202 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1 ( 0x1<<22) 203 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1 ( 0x1<<23) 204 #define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1 ( 0x3<<24) 205 #define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1 ( 0x3<<26) 206 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1 ( 0x1<<28) 207 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1 ( 0x1<<29) 208 209 #define s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0(x) ( (x&0x1)<<0 ) 210 #define s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0(x) ( (x&0x1)<<1 ) 211 #define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0(x) ( (x&0x7)<<2 ) 212 #define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0(x) ( (x&0x7)<<5 ) 213 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0(x) ( (x&0x1)<<8 ) 214 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0(x) ( (x&0x1)<<9 ) 215 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(x) ( (x&0x3)<<10) 216 #define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0(x) ( (x&0x3)<<12) 217 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0(x) ( (x&0x1)<<14) 218 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0(x) ( (x&0x1)<<15) 219 #define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1(x) ( (x&0x7)<<16) 220 #define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1(x) ( (x&0x7)<<19) 221 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1(x) ( (x&0x1)<<22) 222 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1(x) ( (x&0x1)<<23) 223 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(x) ( (x&0x3)<<24) 224 #define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(x) ( (x&0x3)<<26) 225 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(x) ( (x&0x1)<<28) 226 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(x) ( (x&0x1)<<29) 227 228 229 230 /* RGA_MMU_CTRL1 */ 231 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_EN ( 0x1<<0 ) 232 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH ( 0x1<<1 ) 233 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN ( 0x1<<2 ) 234 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR ( 0x1<<3 ) 235 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN ( 0x1<<4 ) 236 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH ( 0x1<<5 ) 237 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN ( 0x1<<6 ) 238 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR ( 0x1<<7 ) 239 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_EN ( 0x1<<8 ) 240 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH ( 0x1<<9 ) 241 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN ( 0x1<<10 ) 242 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR ( 0x1<<11 ) 243 #define m_RGA2_MMU_CTRL1_SW_ELS_MMU_EN ( 0x1<<12 ) 244 #define m_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH ( 0x1<<13 ) 245 246 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_EN(x) ( (x&0x1)<<0 ) 247 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH(x) ( (x&0x1)<<1 ) 248 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN(x) ( (x&0x1)<<2 ) 249 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR(x) ( (x&0x1)<<3 ) 250 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN(x) ( (x&0x1)<<4 ) 251 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH(x) ( (x&0x1)<<5 ) 252 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN(x) ( (x&0x1)<<6 ) 253 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR(x) ( (x&0x1)<<7 ) 254 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_EN(x) ( (x&0x1)<<8 ) 255 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH(x) ( (x&0x1)<<9 ) 256 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN(x) ( (x&0x1)<<10 ) 257 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR(x) ( (x&0x1)<<11 ) 258 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x) ( (x&0x1)<<12 ) 259 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ( (x&0x1)<<13 ) 260 261 262 #define RGA2_SYS_CTRL_OFFSET 0x0 263 #define RGA2_CMD_CTRL_OFFSET 0x4 264 #define RGA2_CMD_BASE_OFFSET 0x8 265 #define RGA2_STATUS_OFFSET 0xc 266 #define RGA2_INT_OFFSET 0x10 267 #define RGA2_MMU_CTRL0_OFFSET 0x14 268 #define RGA2_MMU_CMD_BASE_OFFSET 0x18 269 /* dst full csc */ 270 #define RGA2_DST_CSC_00_OFFSET 0x0 271 #define RGA2_DST_CSC_01_OFFSET 0x4 272 #define RGA2_DST_CSC_02_OFFSET 0x8 273 #define RGA2_DST_CSC_OFF0_OFFSET 0xc 274 #define RGA2_DST_CSC_10_OFFSET 0x10 275 #define RGA2_DST_CSC_11_OFFSET 0x14 276 #define RGA2_DST_CSC_12_OFFSET 0x18 277 #define RGA2_DST_CSC_OFF1_OFFSET 0x1c 278 #define RGA2_DST_CSC_20_OFFSET 0x20 279 #define RGA2_DST_CSC_21_OFFSET 0x24 280 #define RGA2_DST_CSC_22_OFFSET 0x28 281 #define RGA2_DST_CSC_OFF2_OFFSET 0x2c 282 283 #define RGA2_MODE_CTRL_OFFSET 0x00 284 #define RGA2_SRC_INFO_OFFSET 0x04 285 #define RGA2_SRC_BASE0_OFFSET 0x08 286 #define RGA2_SRC_BASE1_OFFSET 0x0c 287 #define RGA2_SRC_BASE2_OFFSET 0x10 288 #define RGA2_SRC_BASE3_OFFSET 0x14 289 #define RGA2_SRC_VIR_INFO_OFFSET 0x18 290 #define RGA2_SRC_ACT_INFO_OFFSET 0x1c 291 #define RGA2_SRC_X_FACTOR_OFFSET 0x20 292 #define RGA2_SRC_Y_FACTOR_OFFSET 0x24 293 #define RGA2_SRC_BG_COLOR_OFFSET 0x28 294 #define RGA2_SRC_FG_COLOR_OFFSET 0x2c 295 #define RGA2_SRC_TR_COLOR0_OFFSET 0x30 296 #define RGA2_CF_GR_A_OFFSET 0x30 // repeat 297 #define RGA2_SRC_TR_COLOR1_OFFSET 0x34 298 #define RGA2_CF_GR_B_OFFSET 0x34 // repeat 299 #define RGA2_DST_INFO_OFFSET 0x38 300 #define RGA2_DST_BASE0_OFFSET 0x3c 301 #define RGA2_DST_BASE1_OFFSET 0x40 302 #define RGA2_DST_BASE2_OFFSET 0x44 303 #define RGA2_DST_VIR_INFO_OFFSET 0x48 304 #define RGA2_DST_ACT_INFO_OFFSET 0x4c 305 #define RGA2_ALPHA_CTRL0_OFFSET 0x50 306 #define RGA2_ALPHA_CTRL1_OFFSET 0x54 307 #define RGA2_FADING_CTRL_OFFSET 0x58 308 #define RGA2_PAT_CON_OFFSET 0x5c 309 #define RGA2_ROP_CTRL0_OFFSET 0x60 310 #define RGA2_CF_GR_G_OFFSET 0x60 // repeat 311 #define RGA2_DST_Y4MAP_LUT0_OFFSET 0x60 // repeat 312 #define RGA2_DST_QUANTIZE_SCALE_OFFSET 0x60 // repeat 313 #define RGA2_ROP_CTRL1_OFFSET 0x64 314 #define RGA2_CF_GR_R_OFFSET 0x64 // repeat 315 #define RGA2_DST_Y4MAP_LUT1_OFFSET 0x64 // repeat 316 #define RGA2_DST_QUANTIZE_OFFSET_OFFSET 0x64 // repeat 317 #define RGA2_MASK_BASE_OFFSET 0x68 318 #define RGA2_MMU_CTRL1_OFFSET 0x6c 319 #define RGA2_MMU_SRC_BASE_OFFSET 0x70 320 #define RGA2_MMU_SRC1_BASE_OFFSET 0x74 321 #define RGA2_MMU_DST_BASE_OFFSET 0x78 322 #define RGA2_MMU_ELS_BASE_OFFSET 0x7c 323 324 int RGA2_gen_reg_info(unsigned char *base, unsigned char *csc_base, struct rga2_req *msg); 325 void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req); 326 void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req); 327 328 329 330 #endif 331 332