1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_HDMI_H_ 8 #define _ROCKCHIP_HDMI_H_ 9 10 #define HDMI_DESIGN_ID 0x0000 11 #define HDMI_REVISION_ID 0x0001 12 #define HDMI_PRODUCT_ID0 0x0002 13 #define HDMI_PRODUCT_ID1 0x0003 14 #define HDMI_CONFIG0_ID 0x0004 15 #define HDMI_CONFIG1_ID 0x0005 16 #define HDMI_CONFIG2_ID 0x0006 17 #define HDMI_CONFIG3_ID 0x0007 18 19 /* Interrupt Registers */ 20 #define HDMI_IH_FC_STAT0 0x0100 21 #define HDMI_IH_FC_STAT1 0x0101 22 #define HDMI_IH_FC_STAT2 0x0102 23 #define HDMI_IH_AS_STAT0 0x0103 24 #define HDMI_IH_PHY_STAT0 0x0104 25 #define HDMI_IH_I2CM_STAT0 0x0105 26 #define m_SCDC_READREQ BIT(2) 27 #define m_I2CM_DONE BIT(1) 28 #define m_I2CM_ERROR BIT(0) 29 #define HDMI_IH_CEC_STAT0 0x0106 30 #define HDMI_IH_VP_STAT0 0x0107 31 #define HDMI_IH_I2CMPHY_STAT0 0x0108 32 #define HDMI_IH_AHBDMAAUD_STAT0 0x0109 33 34 #define HDMI_IH_MUTE_FC_STAT0 0x0180 35 #define HDMI_IH_MUTE_FC_STAT1 0x0181 36 #define HDMI_IH_MUTE_FC_STAT2 0x0182 37 #define HDMI_IH_MUTE_AS_STAT0 0x0183 38 #define HDMI_IH_MUTE_PHY_STAT0 0x0184 39 #define HDMI_IH_MUTE_I2CM_STAT0 0x0185 40 #define HDMI_IH_MUTE_CEC_STAT0 0x0186 41 #define HDMI_IH_MUTE_VP_STAT0 0x0187 42 #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 43 #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 44 #define HDMI_IH_MUTE 0x01FF 45 46 /* Video Sample Registers */ 47 #define HDMI_TX_INVID0 0x0200 48 #define HDMI_TX_INSTUFFING 0x0201 49 #define HDMI_TX_GYDATA0 0x0202 50 #define HDMI_TX_GYDATA1 0x0203 51 #define HDMI_TX_RCRDATA0 0x0204 52 #define HDMI_TX_RCRDATA1 0x0205 53 #define HDMI_TX_BCBDATA0 0x0206 54 #define HDMI_TX_BCBDATA1 0x0207 55 56 /* Video Packetizer Registers */ 57 #define HDMI_VP_STATUS 0x0800 58 #define HDMI_VP_PR_CD 0x0801 59 #define HDMI_VP_STUFF 0x0802 60 #define HDMI_VP_REMAP 0x0803 61 #define HDMI_VP_CONF 0x0804 62 #define HDMI_VP_STAT 0x0805 63 #define HDMI_VP_INT 0x0806 64 #define HDMI_VP_MASK 0x0807 65 #define HDMI_VP_POL 0x0808 66 67 /* Frame Composer Registers */ 68 #define HDMI_FC_INVIDCONF 0x1000 69 #define HDMI_FC_INHACTV0 0x1001 70 #define HDMI_FC_INHACTV1 0x1002 71 #define HDMI_FC_INHBLANK0 0x1003 72 #define HDMI_FC_INHBLANK1 0x1004 73 #define HDMI_FC_INVACTV0 0x1005 74 #define HDMI_FC_INVACTV1 0x1006 75 #define HDMI_FC_INVBLANK 0x1007 76 #define HDMI_FC_HSYNCINDELAY0 0x1008 77 #define HDMI_FC_HSYNCINDELAY1 0x1009 78 #define HDMI_FC_HSYNCINWIDTH0 0x100A 79 #define HDMI_FC_HSYNCINWIDTH1 0x100B 80 #define HDMI_FC_VSYNCINDELAY 0x100C 81 #define HDMI_FC_VSYNCINWIDTH 0x100D 82 #define HDMI_FC_INFREQ0 0x100E 83 #define HDMI_FC_INFREQ1 0x100F 84 #define HDMI_FC_INFREQ2 0x1010 85 #define HDMI_FC_CTRLDUR 0x1011 86 #define HDMI_FC_EXCTRLDUR 0x1012 87 #define HDMI_FC_EXCTRLSPAC 0x1013 88 #define HDMI_FC_CH0PREAM 0x1014 89 #define HDMI_FC_CH1PREAM 0x1015 90 #define HDMI_FC_CH2PREAM 0x1016 91 #define HDMI_FC_AVICONF3 0x1017 92 #define HDMI_FC_GCP 0x1018 93 #define HDMI_FC_AVICONF0 0x1019 94 #define HDMI_FC_AVICONF1 0x101A 95 #define HDMI_FC_AVICONF2 0x101B 96 #define HDMI_FC_AVIVID 0x101C 97 #define HDMI_FC_AVIETB0 0x101D 98 #define HDMI_FC_AVIETB1 0x101E 99 #define HDMI_FC_AVISBB0 0x101F 100 #define HDMI_FC_AVISBB1 0x1020 101 #define HDMI_FC_AVIELB0 0x1021 102 #define HDMI_FC_AVIELB1 0x1022 103 #define HDMI_FC_AVISRB0 0x1023 104 #define HDMI_FC_AVISRB1 0x1024 105 #define HDMI_FC_AUDICONF0 0x1025 106 #define HDMI_FC_AUDICONF1 0x1026 107 #define HDMI_FC_AUDICONF2 0x1027 108 #define HDMI_FC_AUDICONF3 0x1028 109 #define HDMI_FC_VSDIEEEID0 0x1029 110 #define HDMI_FC_VSDSIZE 0x102A 111 #define HDMI_FC_VSDIEEEID1 0x1030 112 #define HDMI_FC_VSDIEEEID2 0x1031 113 #define HDMI_FC_VSDPAYLOAD0 0x1032 114 #define HDMI_FC_VSDPAYLOAD1 0x1033 115 #define HDMI_FC_VSDPAYLOAD2 0x1034 116 #define HDMI_FC_VSDPAYLOAD3 0x1035 117 #define HDMI_FC_VSDPAYLOAD4 0x1036 118 #define HDMI_FC_VSDPAYLOAD5 0x1037 119 #define HDMI_FC_VSDPAYLOAD6 0x1038 120 #define HDMI_FC_VSDPAYLOAD7 0x1039 121 #define HDMI_FC_VSDPAYLOAD8 0x103A 122 #define HDMI_FC_VSDPAYLOAD9 0x103B 123 #define HDMI_FC_VSDPAYLOAD10 0x103C 124 #define HDMI_FC_VSDPAYLOAD11 0x103D 125 #define HDMI_FC_VSDPAYLOAD12 0x103E 126 #define HDMI_FC_VSDPAYLOAD13 0x103F 127 #define HDMI_FC_VSDPAYLOAD14 0x1040 128 #define HDMI_FC_VSDPAYLOAD15 0x1041 129 #define HDMI_FC_VSDPAYLOAD16 0x1042 130 #define HDMI_FC_VSDPAYLOAD17 0x1043 131 #define HDMI_FC_VSDPAYLOAD18 0x1044 132 #define HDMI_FC_VSDPAYLOAD19 0x1045 133 #define HDMI_FC_VSDPAYLOAD20 0x1046 134 #define HDMI_FC_VSDPAYLOAD21 0x1047 135 #define HDMI_FC_VSDPAYLOAD22 0x1048 136 #define HDMI_FC_VSDPAYLOAD23 0x1049 137 #define HDMI_FC_SPDVENDORNAME0 0x104A 138 #define HDMI_FC_SPDVENDORNAME1 0x104B 139 #define HDMI_FC_SPDVENDORNAME2 0x104C 140 #define HDMI_FC_SPDVENDORNAME3 0x104D 141 #define HDMI_FC_SPDVENDORNAME4 0x104E 142 #define HDMI_FC_SPDVENDORNAME5 0x104F 143 #define HDMI_FC_SPDVENDORNAME6 0x1050 144 #define HDMI_FC_SPDVENDORNAME7 0x1051 145 #define HDMI_FC_SDPPRODUCTNAME0 0x1052 146 #define HDMI_FC_SDPPRODUCTNAME1 0x1053 147 #define HDMI_FC_SDPPRODUCTNAME2 0x1054 148 #define HDMI_FC_SDPPRODUCTNAME3 0x1055 149 #define HDMI_FC_SDPPRODUCTNAME4 0x1056 150 #define HDMI_FC_SDPPRODUCTNAME5 0x1057 151 #define HDMI_FC_SDPPRODUCTNAME6 0x1058 152 #define HDMI_FC_SDPPRODUCTNAME7 0x1059 153 #define HDMI_FC_SDPPRODUCTNAME8 0x105A 154 #define HDMI_FC_SDPPRODUCTNAME9 0x105B 155 #define HDMI_FC_SDPPRODUCTNAME10 0x105C 156 #define HDMI_FC_SDPPRODUCTNAME11 0x105D 157 #define HDMI_FC_SDPPRODUCTNAME12 0x105E 158 #define HDMI_FC_SDPPRODUCTNAME13 0x105F 159 #define HDMI_FC_SDPPRODUCTNAME14 0x1060 160 #define HDMI_FC_SPDPRODUCTNAME15 0x1061 161 #define HDMI_FC_SPDDEVICEINF 0x1062 162 #define HDMI_FC_AUDSCONF 0x1063 163 #define HDMI_FC_AUDSSTAT 0x1064 164 #define HDMI_FC_AUDSCHNLS0 0x1067 165 #define HDMI_FC_AUDSCHNLS1 0x1068 166 #define HDMI_FC_AUDSCHNLS2 0x1069 167 #define HDMI_FC_AUDSCHNLS3 0x106a 168 #define HDMI_FC_AUDSCHNLS4 0x106b 169 #define HDMI_FC_AUDSCHNLS5 0x106c 170 #define HDMI_FC_AUDSCHNLS6 0x106d 171 #define HDMI_FC_AUDSCHNLS7 0x106e 172 #define HDMI_FC_AUDSCHNLS8 0x106f 173 #define HDMI_FC_DATACH0FILL 0x1070 174 #define HDMI_FC_DATACH1FILL 0x1071 175 #define HDMI_FC_DATACH2FILL 0x1072 176 #define HDMI_FC_CTRLQHIGH 0x1073 177 #define HDMI_FC_CTRLQLOW 0x1074 178 #define HDMI_FC_ACP0 0x1075 179 #define HDMI_FC_ACP28 0x1076 180 #define HDMI_FC_ACP27 0x1077 181 #define HDMI_FC_ACP26 0x1078 182 #define HDMI_FC_ACP25 0x1079 183 #define HDMI_FC_ACP24 0x107A 184 #define HDMI_FC_ACP23 0x107B 185 #define HDMI_FC_ACP22 0x107C 186 #define HDMI_FC_ACP21 0x107D 187 #define HDMI_FC_ACP20 0x107E 188 #define HDMI_FC_ACP19 0x107F 189 #define HDMI_FC_ACP18 0x1080 190 #define HDMI_FC_ACP17 0x1081 191 #define HDMI_FC_ACP16 0x1082 192 #define HDMI_FC_ACP15 0x1083 193 #define HDMI_FC_ACP14 0x1084 194 #define HDMI_FC_ACP13 0x1085 195 #define HDMI_FC_ACP12 0x1086 196 #define HDMI_FC_ACP11 0x1087 197 #define HDMI_FC_ACP10 0x1088 198 #define HDMI_FC_ACP9 0x1089 199 #define HDMI_FC_ACP8 0x108A 200 #define HDMI_FC_ACP7 0x108B 201 #define HDMI_FC_ACP6 0x108C 202 #define HDMI_FC_ACP5 0x108D 203 #define HDMI_FC_ACP4 0x108E 204 #define HDMI_FC_ACP3 0x108F 205 #define HDMI_FC_ACP2 0x1090 206 #define HDMI_FC_ACP1 0x1091 207 #define HDMI_FC_ISCR1_0 0x1092 208 #define HDMI_FC_ISCR1_16 0x1093 209 #define HDMI_FC_ISCR1_15 0x1094 210 #define HDMI_FC_ISCR1_14 0x1095 211 #define HDMI_FC_ISCR1_13 0x1096 212 #define HDMI_FC_ISCR1_12 0x1097 213 #define HDMI_FC_ISCR1_11 0x1098 214 #define HDMI_FC_ISCR1_10 0x1099 215 #define HDMI_FC_ISCR1_9 0x109A 216 #define HDMI_FC_ISCR1_8 0x109B 217 #define HDMI_FC_ISCR1_7 0x109C 218 #define HDMI_FC_ISCR1_6 0x109D 219 #define HDMI_FC_ISCR1_5 0x109E 220 #define HDMI_FC_ISCR1_4 0x109F 221 #define HDMI_FC_ISCR1_3 0x10A0 222 #define HDMI_FC_ISCR1_2 0x10A1 223 #define HDMI_FC_ISCR1_1 0x10A2 224 #define HDMI_FC_ISCR2_15 0x10A3 225 #define HDMI_FC_ISCR2_14 0x10A4 226 #define HDMI_FC_ISCR2_13 0x10A5 227 #define HDMI_FC_ISCR2_12 0x10A6 228 #define HDMI_FC_ISCR2_11 0x10A7 229 #define HDMI_FC_ISCR2_10 0x10A8 230 #define HDMI_FC_ISCR2_9 0x10A9 231 #define HDMI_FC_ISCR2_8 0x10AA 232 #define HDMI_FC_ISCR2_7 0x10AB 233 #define HDMI_FC_ISCR2_6 0x10AC 234 #define HDMI_FC_ISCR2_5 0x10AD 235 #define HDMI_FC_ISCR2_4 0x10AE 236 #define HDMI_FC_ISCR2_3 0x10AF 237 #define HDMI_FC_ISCR2_2 0x10B0 238 #define HDMI_FC_ISCR2_1 0x10B1 239 #define HDMI_FC_ISCR2_0 0x10B2 240 #define HDMI_FC_DATAUTO0 0x10B3 241 #define HDMI_FC_DATAUTO1 0x10B4 242 #define HDMI_FC_DATAUTO2 0x10B5 243 #define HDMI_FC_DATMAN 0x10B6 244 #define HDMI_FC_DATAUTO3 0x10B7 245 #define HDMI_FC_RDRB0 0x10B8 246 #define HDMI_FC_RDRB1 0x10B9 247 #define HDMI_FC_RDRB2 0x10BA 248 #define HDMI_FC_RDRB3 0x10BB 249 #define HDMI_FC_RDRB4 0x10BC 250 #define HDMI_FC_RDRB5 0x10BD 251 #define HDMI_FC_RDRB6 0x10BE 252 #define HDMI_FC_RDRB7 0x10BF 253 #define HDMI_FC_STAT0 0x10D0 254 #define HDMI_FC_INT0 0x10D1 255 #define HDMI_FC_MASK0 0x10D2 256 #define HDMI_FC_POL0 0x10D3 257 #define HDMI_FC_STAT1 0x10D4 258 #define HDMI_FC_INT1 0x10D5 259 #define HDMI_FC_MASK1 0x10D6 260 #define HDMI_FC_POL1 0x10D7 261 #define HDMI_FC_STAT2 0x10D8 262 #define HDMI_FC_INT2 0x10D9 263 #define HDMI_FC_MASK2 0x10DA 264 #define HDMI_FC_POL2 0x10DB 265 #define HDMI_FC_PRCONF 0x10E0 266 #define HDMI_FC_SCRAMBLER_CTRL 0x10E1 267 268 #define HDMI_FC_GMD_STAT 0x1100 269 #define HDMI_FC_GMD_EN 0x1101 270 #define HDMI_FC_GMD_UP 0x1102 271 #define HDMI_FC_GMD_CONF 0x1103 272 #define HDMI_FC_GMD_HB 0x1104 273 #define HDMI_FC_GMD_PB0 0x1105 274 #define HDMI_FC_GMD_PB1 0x1106 275 #define HDMI_FC_GMD_PB2 0x1107 276 #define HDMI_FC_GMD_PB3 0x1108 277 #define HDMI_FC_GMD_PB4 0x1109 278 #define HDMI_FC_GMD_PB5 0x110A 279 #define HDMI_FC_GMD_PB6 0x110B 280 #define HDMI_FC_GMD_PB7 0x110C 281 #define HDMI_FC_GMD_PB8 0x110D 282 #define HDMI_FC_GMD_PB9 0x110E 283 #define HDMI_FC_GMD_PB10 0x110F 284 #define HDMI_FC_GMD_PB11 0x1110 285 #define HDMI_FC_GMD_PB12 0x1111 286 #define HDMI_FC_GMD_PB13 0x1112 287 #define HDMI_FC_GMD_PB14 0x1113 288 #define HDMI_FC_GMD_PB15 0x1114 289 #define HDMI_FC_GMD_PB16 0x1115 290 #define HDMI_FC_GMD_PB17 0x1116 291 #define HDMI_FC_GMD_PB18 0x1117 292 #define HDMI_FC_GMD_PB19 0x1118 293 #define HDMI_FC_GMD_PB20 0x1119 294 #define HDMI_FC_GMD_PB21 0x111A 295 #define HDMI_FC_GMD_PB22 0x111B 296 #define HDMI_FC_GMD_PB23 0x111C 297 #define HDMI_FC_GMD_PB24 0x111D 298 #define HDMI_FC_GMD_PB25 0x111E 299 #define HDMI_FC_GMD_PB26 0x111F 300 #define HDMI_FC_GMD_PB27 0x1120 301 302 #define HDMI_FC_DBGFORCE 0x1200 303 #define HDMI_FC_DBGAUD0CH0 0x1201 304 #define HDMI_FC_DBGAUD1CH0 0x1202 305 #define HDMI_FC_DBGAUD2CH0 0x1203 306 #define HDMI_FC_DBGAUD0CH1 0x1204 307 #define HDMI_FC_DBGAUD1CH1 0x1205 308 #define HDMI_FC_DBGAUD2CH1 0x1206 309 #define HDMI_FC_DBGAUD0CH2 0x1207 310 #define HDMI_FC_DBGAUD1CH2 0x1208 311 #define HDMI_FC_DBGAUD2CH2 0x1209 312 #define HDMI_FC_DBGAUD0CH3 0x120A 313 #define HDMI_FC_DBGAUD1CH3 0x120B 314 #define HDMI_FC_DBGAUD2CH3 0x120C 315 #define HDMI_FC_DBGAUD0CH4 0x120D 316 #define HDMI_FC_DBGAUD1CH4 0x120E 317 #define HDMI_FC_DBGAUD2CH4 0x120F 318 #define HDMI_FC_DBGAUD0CH5 0x1210 319 #define HDMI_FC_DBGAUD1CH5 0x1211 320 #define HDMI_FC_DBGAUD2CH5 0x1212 321 #define HDMI_FC_DBGAUD0CH6 0x1213 322 #define HDMI_FC_DBGAUD1CH6 0x1214 323 #define HDMI_FC_DBGAUD2CH6 0x1215 324 #define HDMI_FC_DBGAUD0CH7 0x1216 325 #define HDMI_FC_DBGAUD1CH7 0x1217 326 #define HDMI_FC_DBGAUD2CH7 0x1218 327 #define HDMI_FC_DBGTMDS0 0x1219 328 #define HDMI_FC_DBGTMDS1 0x121A 329 #define HDMI_FC_DBGTMDS2 0x121B 330 331 /* HDMI Source PHY Registers */ 332 #define HDMI_PHY_CONF0 0x3000 333 #define HDMI_PHY_TST0 0x3001 334 #define HDMI_PHY_TST1 0x3002 335 #define HDMI_PHY_TST2 0x3003 336 #define HDMI_PHY_STAT0 0x3004 337 #define HDMI_PHY_INT0 0x3005 338 #define HDMI_PHY_MASK0 0x3006 339 #define HDMI_PHY_POL0 0x3007 340 341 /* HDMI Master PHY Registers */ 342 #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 343 #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 344 #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 345 #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 346 #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 347 #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 348 #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 349 #define HDMI_PHY_I2CM_INT_ADDR 0x3027 350 #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 351 #define HDMI_PHY_I2CM_DIV_ADDR 0x3029 352 #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a 353 #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b 354 #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c 355 #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d 356 #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e 357 #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f 358 #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 359 #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 360 #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 361 362 /* Audio Sampler Registers */ 363 #define HDMI_AUD_CONF0 0x3100 364 #define HDMI_AUD_CONF1 0x3101 365 #define HDMI_AUD_INT 0x3102 366 #define HDMI_AUD_CONF2 0x3103 367 #define HDMI_AUD_N1 0x3200 368 #define HDMI_AUD_N2 0x3201 369 #define HDMI_AUD_N3 0x3202 370 #define HDMI_AUD_CTS1 0x3203 371 #define HDMI_AUD_CTS2 0x3204 372 #define HDMI_AUD_CTS3 0x3205 373 #define HDMI_AUD_INPUTCLKFS 0x3206 374 #define HDMI_AUD_SPDIFINT 0x3302 375 #define HDMI_AUD_CONF0_HBR 0x3400 376 #define HDMI_AUD_HBR_STATUS 0x3401 377 #define HDMI_AUD_HBR_INT 0x3402 378 #define HDMI_AUD_HBR_POL 0x3403 379 #define HDMI_AUD_HBR_MASK 0x3404 380 381 /* 382 * Generic Parallel Audio Interface Registers 383 * Not used as GPAUD interface is not enabled in hw 384 */ 385 #define HDMI_GP_CONF0 0x3500 386 #define HDMI_GP_CONF1 0x3501 387 #define HDMI_GP_CONF2 0x3502 388 #define HDMI_GP_STAT 0x3503 389 #define HDMI_GP_INT 0x3504 390 #define HDMI_GP_MASK 0x3505 391 #define HDMI_GP_POL 0x3506 392 393 /* Audio DMA Registers */ 394 #define HDMI_AHB_DMA_CONF0 0x3600 395 #define HDMI_AHB_DMA_START 0x3601 396 #define HDMI_AHB_DMA_STOP 0x3602 397 #define HDMI_AHB_DMA_THRSLD 0x3603 398 #define HDMI_AHB_DMA_STRADDR0 0x3604 399 #define HDMI_AHB_DMA_STRADDR1 0x3605 400 #define HDMI_AHB_DMA_STRADDR2 0x3606 401 #define HDMI_AHB_DMA_STRADDR3 0x3607 402 #define HDMI_AHB_DMA_STPADDR0 0x3608 403 #define HDMI_AHB_DMA_STPADDR1 0x3609 404 #define HDMI_AHB_DMA_STPADDR2 0x360a 405 #define HDMI_AHB_DMA_STPADDR3 0x360b 406 #define HDMI_AHB_DMA_BSTADDR0 0x360c 407 #define HDMI_AHB_DMA_BSTADDR1 0x360d 408 #define HDMI_AHB_DMA_BSTADDR2 0x360e 409 #define HDMI_AHB_DMA_BSTADDR3 0x360f 410 #define HDMI_AHB_DMA_MBLENGTH0 0x3610 411 #define HDMI_AHB_DMA_MBLENGTH1 0x3611 412 #define HDMI_AHB_DMA_STAT 0x3612 413 #define HDMI_AHB_DMA_INT 0x3613 414 #define HDMI_AHB_DMA_MASK 0x3614 415 #define HDMI_AHB_DMA_POL 0x3615 416 #define HDMI_AHB_DMA_CONF1 0x3616 417 #define HDMI_AHB_DMA_BUFFSTAT 0x3617 418 #define HDMI_AHB_DMA_BUFFINT 0x3618 419 #define HDMI_AHB_DMA_BUFFMASK 0x3619 420 #define HDMI_AHB_DMA_BUFFPOL 0x361a 421 422 /* Main Controller Registers */ 423 #define HDMI_MC_SFRDIV 0x4000 424 #define HDMI_MC_CLKDIS 0x4001 425 #define HDMI_MC_SWRSTZ 0x4002 426 #define HDMI_MC_OPCTRL 0x4003 427 #define HDMI_MC_FLOWCTRL 0x4004 428 #define HDMI_MC_PHYRSTZ 0x4005 429 #define HDMI_MC_LOCKONCLOCK 0x4006 430 #define HDMI_MC_HEACPHY_RST 0x4007 431 432 /* Color Space Converter Registers */ 433 #define HDMI_CSC_CFG 0x4100 434 #define HDMI_CSC_SCALE 0x4101 435 #define HDMI_CSC_COEF_A1_MSB 0x4102 436 #define HDMI_CSC_COEF_A1_LSB 0x4103 437 #define HDMI_CSC_COEF_A2_MSB 0x4104 438 #define HDMI_CSC_COEF_A2_LSB 0x4105 439 #define HDMI_CSC_COEF_A3_MSB 0x4106 440 #define HDMI_CSC_COEF_A3_LSB 0x4107 441 #define HDMI_CSC_COEF_A4_MSB 0x4108 442 #define HDMI_CSC_COEF_A4_LSB 0x4109 443 #define HDMI_CSC_COEF_B1_MSB 0x410A 444 #define HDMI_CSC_COEF_B1_LSB 0x410B 445 #define HDMI_CSC_COEF_B2_MSB 0x410C 446 #define HDMI_CSC_COEF_B2_LSB 0x410D 447 #define HDMI_CSC_COEF_B3_MSB 0x410E 448 #define HDMI_CSC_COEF_B3_LSB 0x410F 449 #define HDMI_CSC_COEF_B4_MSB 0x4110 450 #define HDMI_CSC_COEF_B4_LSB 0x4111 451 #define HDMI_CSC_COEF_C1_MSB 0x4112 452 #define HDMI_CSC_COEF_C1_LSB 0x4113 453 #define HDMI_CSC_COEF_C2_MSB 0x4114 454 #define HDMI_CSC_COEF_C2_LSB 0x4115 455 #define HDMI_CSC_COEF_C3_MSB 0x4116 456 #define HDMI_CSC_COEF_C3_LSB 0x4117 457 #define HDMI_CSC_COEF_C4_MSB 0x4118 458 #define HDMI_CSC_COEF_C4_LSB 0x4119 459 460 /* HDCP Encryption Engine Registers */ 461 #define HDMI_A_HDCPCFG0 0x5000 462 #define HDMI_A_HDCPCFG1 0x5001 463 #define HDMI_A_HDCPOBS0 0x5002 464 #define HDMI_A_HDCPOBS1 0x5003 465 #define HDMI_A_HDCPOBS2 0x5004 466 #define HDMI_A_HDCPOBS3 0x5005 467 #define HDMI_A_APIINTCLR 0x5006 468 #define HDMI_A_APIINTSTAT 0x5007 469 #define HDMI_A_APIINTMSK 0x5008 470 #define HDMI_A_VIDPOLCFG 0x5009 471 #define HDMI_A_OESSWCFG 0x500A 472 #define HDMI_A_TIMER1SETUP0 0x500B 473 #define HDMI_A_TIMER1SETUP1 0x500C 474 #define HDMI_A_TIMER2SETUP0 0x500D 475 #define HDMI_A_TIMER2SETUP1 0x500E 476 #define HDMI_A_100MSCFG 0x500F 477 #define HDMI_A_2SCFG0 0x5010 478 #define HDMI_A_2SCFG1 0x5011 479 #define HDMI_A_5SCFG0 0x5012 480 #define HDMI_A_5SCFG1 0x5013 481 #define HDMI_A_SRMVERLSB 0x5014 482 #define HDMI_A_SRMVERMSB 0x5015 483 #define HDMI_A_SRMCTRL 0x5016 484 #define HDMI_A_SFRSETUP 0x5017 485 #define HDMI_A_I2CHSETUP 0x5018 486 #define HDMI_A_INTSETUP 0x5019 487 #define HDMI_A_PRESETUP 0x501A 488 #define HDMI_A_SRM_BASE 0x5020 489 490 /* HDCP Registers */ 491 #define HDMI_HDCPREG_RMCTL 0x780e 492 #define HDMI_HDCPREG_RMSTS 0x780f 493 #define HDMI_HDCPREG_SEED0 0x7810 494 #define HDMI_HDCPREG_SEED1 0x7811 495 #define HDMI_HDCPREG_DPK0 0x7812 496 #define HDMI_HDCPREG_DPK1 0x7813 497 #define HDMI_HDCPREG_DPK2 0x7814 498 #define HDMI_HDCPREG_DPK3 0x7815 499 #define HDMI_HDCPREG_DPK4 0x7816 500 #define HDMI_HDCPREG_DPK5 0x7817 501 #define HDMI_HDCPREG_DPK6 0x7818 502 #define HDMI_HDCP2REG_CTRL 0x7904 503 #define HDMI_HDCP2REG_MASK 0x790c 504 #define HDMI_HDCP2REG_MUTE 0x790e 505 506 /* CEC Engine Registers */ 507 #define HDMI_CEC_CTRL 0x7D00 508 #define HDMI_CEC_STAT 0x7D01 509 #define HDMI_CEC_MASK 0x7D02 510 #define HDMI_CEC_POLARITY 0x7D03 511 #define HDMI_CEC_INT 0x7D04 512 #define HDMI_CEC_ADDR_L 0x7D05 513 #define HDMI_CEC_ADDR_H 0x7D06 514 #define HDMI_CEC_TX_CNT 0x7D07 515 #define HDMI_CEC_RX_CNT 0x7D08 516 #define HDMI_CEC_TX_DATA0 0x7D10 517 #define HDMI_CEC_TX_DATA1 0x7D11 518 #define HDMI_CEC_TX_DATA2 0x7D12 519 #define HDMI_CEC_TX_DATA3 0x7D13 520 #define HDMI_CEC_TX_DATA4 0x7D14 521 #define HDMI_CEC_TX_DATA5 0x7D15 522 #define HDMI_CEC_TX_DATA6 0x7D16 523 #define HDMI_CEC_TX_DATA7 0x7D17 524 #define HDMI_CEC_TX_DATA8 0x7D18 525 #define HDMI_CEC_TX_DATA9 0x7D19 526 #define HDMI_CEC_TX_DATA10 0x7D1a 527 #define HDMI_CEC_TX_DATA11 0x7D1b 528 #define HDMI_CEC_TX_DATA12 0x7D1c 529 #define HDMI_CEC_TX_DATA13 0x7D1d 530 #define HDMI_CEC_TX_DATA14 0x7D1e 531 #define HDMI_CEC_TX_DATA15 0x7D1f 532 #define HDMI_CEC_RX_DATA0 0x7D20 533 #define HDMI_CEC_RX_DATA1 0x7D21 534 #define HDMI_CEC_RX_DATA2 0x7D22 535 #define HDMI_CEC_RX_DATA3 0x7D23 536 #define HDMI_CEC_RX_DATA4 0x7D24 537 #define HDMI_CEC_RX_DATA5 0x7D25 538 #define HDMI_CEC_RX_DATA6 0x7D26 539 #define HDMI_CEC_RX_DATA7 0x7D27 540 #define HDMI_CEC_RX_DATA8 0x7D28 541 #define HDMI_CEC_RX_DATA9 0x7D29 542 #define HDMI_CEC_RX_DATA10 0x7D2a 543 #define HDMI_CEC_RX_DATA11 0x7D2b 544 #define HDMI_CEC_RX_DATA12 0x7D2c 545 #define HDMI_CEC_RX_DATA13 0x7D2d 546 #define HDMI_CEC_RX_DATA14 0x7D2e 547 #define HDMI_CEC_RX_DATA15 0x7D2f 548 #define HDMI_CEC_LOCK 0x7D30 549 #define HDMI_CEC_WKUPCTRL 0x7D31 550 551 /* I2C Master Registers (E-DDC) */ 552 #define HDMI_I2CM_SLAVE 0x7E00 553 #define HDMI_I2CM_ADDRESS 0x7E01 554 #define HDMI_I2CM_DATAO 0x7E02 555 #define HDMI_I2CM_DATAI 0x7E03 556 #define HDMI_I2CM_OPERATION 0x7E04 557 #define HDMI_I2CM_INT 0x7E05 558 #define HDMI_I2CM_CTLINT 0x7E06 559 #define HDMI_I2CM_DIV 0x7E07 560 #define HDMI_I2CM_SEGADDR 0x7E08 561 #define HDMI_I2CM_SOFTRSTZ 0x7E09 562 #define HDMI_I2CM_SEGPTR 0x7E0A 563 #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B 564 #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C 565 #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D 566 #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E 567 #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F 568 #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 569 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 570 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 571 #define HDMI_I2CM_SDA_HOLD 0x7E13 572 #define HDMI_I2CM_SCDC_READ_UPDATE 0x7E14 573 #define HDMI_I2CM_READ_REQ_EN_MSK BIT(4) 574 #define HDMI_I2CM_READ_REQ_EN_OFFSET 4 575 #define HDMI_I2CM_READ_UPDATE_MSK BIT(0) 576 #define HDMI_I2CM_READ_UPDATE_OFFSET 0 577 #define HDMI_I2CM_I2CM_UPRD_VSYNC_EN_MSK BIT(5) 578 #define HDMI_I2CM_I2CM_UPRD_VSYNC_EN_OFFSET 5 579 #define HDMI_I2CM_READ_BUFF0 0x7E20 580 #define HDMI_I2CM_SCDC_UPDATE0 0x7E30 581 #define HDMI_I2CM_SCDC_UPDATE1 0x7E31 582 #define DDC_I2C_EDID_ADDR 0x50 583 #define DDC_I2C_SEG_ADDR 0x30 584 #define DDC_I2C_SCDC_ADDR 0x54 585 #define HDMI_EDID_BLOCK_SIZE 128 586 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME 9625 587 #define EDID_I2C_MIN_SS_SCL_LOW_TIME 10000 588 #define I2C_DIV_FACTOR 1000000 589 590 /* SCDC Registers */ 591 #define SCDC_SINK_VERSION 0x01 592 #define SCDC_SOURCE_VERSION 0x02 593 594 #define SCDC_UPDATE_0 0x10 595 #define SCDC_READ_REQUEST_TEST BIT(2) 596 #define SCDC_CED_UPDATE BIT(1) 597 #define SCDC_STATUS_UPDATE BIT(0) 598 #define SCDC_UPDATE_1 0x11 599 600 #define SCDC_TMDS_CONFIG 0x20 601 #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 BIT(1) 602 #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1) 603 #define SCDC_SCRAMBLING_ENABLE BIT(0) 604 #define SCDC_SCRAMBLER_STATUS 0x21 605 #define SCDC_SCRAMBLING_STATUS BIT(0) 606 607 #define SCDC_CONFIG_0 0x30 608 #define SCDC_READ_REQUEST_ENABLE BIT(0) 609 610 #define SCDC_STATUS_FLAGS_0 0x40 611 #define SCDC_CH2_LOCK BIT(3) 612 #define SCDC_CH1_LOCK BIT(2) 613 #define SCDC_CH0_LOCK BIT(1) 614 #define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK) 615 #define SCDC_CLOCK_DETECT BIT(0) 616 #define SCDC_STATUS_FLAGS_1 0x41 617 618 #define SCDC_ERR_DET_0_L 0x50 619 #define SCDC_ERR_DET_0_H 0x51 620 #define SCDC_ERR_DET_1_L 0x52 621 #define SCDC_ERR_DET_1_H 0x53 622 #define SCDC_ERR_DET_2_L 0x54 623 #define SCDC_ERR_DET_2_H 0x55 624 #define SCDC_CHANNEL_VALID BIT(7) 625 #define SCDC_ERR_DET_CHECKSUM 0x56 626 627 #define SCDC_TEST_CONFIG_0 0xc0 628 #define SCDC_TEST_READ_REQUEST BIT(7) 629 #define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f) 630 631 #define SCDC_MANUFACTURER_IEEE_OUI 0xd0 632 #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3 633 #define SCDC_DEVICE_ID 0xd3 634 #define SCDC_DEVICE_ID_SIZE 8 635 #define SCDC_DEVICE_HARDWARE_REVISION 0xdb 636 #define SCDC_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf) 637 #define SCDC_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf) 638 #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc 639 #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd 640 641 #define SCDC_MANUFACTURER_SPECIFIC 0xde 642 #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34 643 644 enum { 645 /* PRODUCT_ID0 field values */ 646 HDMI_PRODUCT_ID0_HDMI_TX = 0xa0, 647 648 /* PRODUCT_ID1 field values */ 649 HDMI_PRODUCT_ID1_HDCP = 0xc0, 650 HDMI_PRODUCT_ID1_HDMI_RX = 0x02, 651 HDMI_PRODUCT_ID1_HDMI_TX = 0x01, 652 653 /* CONFIG0_ID field values */ 654 HDMI_CONFIG0_I2S = 0x10, 655 656 /* CONFIG1_ID field values */ 657 HDMI_CONFIG1_AHB = 0x01, 658 659 /* CONFIG3_ID field values */ 660 HDMI_CONFIG3_AHBAUDDMA = 0x02, 661 HDMI_CONFIG3_GPAUD = 0x01, 662 663 /* IH_FC_INT2 field values */ 664 HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, 665 HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, 666 HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, 667 668 /* IH_FC_STAT2 field values */ 669 HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, 670 HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, 671 HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, 672 673 /* IH_PHY_STAT0 field values */ 674 HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, 675 HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, 676 HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8, 677 HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4, 678 HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, 679 HDMI_IH_PHY_STAT0_HPD = 0x1, 680 681 /* IH_I2CM_STAT0 and IH_MUTE_I2CM_STAT0 field values */ 682 HDMI_IH_I2CM_STAT0_DONE = 0x2, 683 HDMI_IH_I2CM_STAT0_ERROR = 0x1, 684 685 /* IH_MUTE_I2CMPHY_STAT0 field values */ 686 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, 687 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, 688 689 /* IH_AHBDMAAUD_STAT0 field values */ 690 HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, 691 HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, 692 HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08, 693 HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04, 694 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, 695 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, 696 697 /* IH_MUTE_FC_STAT2 field values */ 698 HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, 699 HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, 700 HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, 701 702 /* IH_MUTE_AHBDMAAUD_STAT0 field values */ 703 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, 704 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, 705 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08, 706 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04, 707 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02, 708 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, 709 710 /* IH_MUTE field values */ 711 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, 712 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, 713 714 /* TX_INVID0 field values */ 715 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80, 716 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80, 717 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, 718 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F, 719 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, 720 721 /* TX_INSTUFFING field values */ 722 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4, 723 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, 724 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0, 725 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2, 726 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, 727 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0, 728 HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, 729 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, 730 HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0, 731 732 /* VP_PR_CD field values */ 733 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0, 734 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, 735 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F, 736 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, 737 738 /* VP_STUFF field values */ 739 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, 740 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, 741 HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10, 742 HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4, 743 HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8, 744 HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3, 745 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, 746 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, 747 HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0, 748 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, 749 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, 750 HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0, 751 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, 752 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, 753 HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0, 754 755 /* VP_CONF field values */ 756 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, 757 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, 758 HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00, 759 HDMI_VP_CONF_PP_EN_ENMASK = 0x20, 760 HDMI_VP_CONF_PP_EN_ENABLE = 0x20, 761 HDMI_VP_CONF_PP_EN_DISABLE = 0x00, 762 HDMI_VP_CONF_PR_EN_MASK = 0x10, 763 HDMI_VP_CONF_PR_EN_ENABLE = 0x10, 764 HDMI_VP_CONF_PR_EN_DISABLE = 0x00, 765 HDMI_VP_CONF_YCC422_EN_MASK = 0x8, 766 HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8, 767 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, 768 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, 769 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, 770 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0, 771 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, 772 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, 773 HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, 774 HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0, 775 776 /* VP_REMAP field values */ 777 HDMI_VP_REMAP_MASK = 0x3, 778 HDMI_VP_REMAP_YCC422_24bit = 0x2, 779 HDMI_VP_REMAP_YCC422_20bit = 0x1, 780 HDMI_VP_REMAP_YCC422_16bit = 0x0, 781 782 /* FC_INVIDCONF field values */ 783 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, 784 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, 785 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, 786 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, 787 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, 788 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 789 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, 790 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, 791 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 792 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, 793 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, 794 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, 795 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, 796 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, 797 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, 798 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, 799 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, 800 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, 801 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, 802 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, 803 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, 804 805 /* FC_AUDICONF0 field values */ 806 HDMI_FC_AUDICONF0_CC_OFFSET = 4, 807 HDMI_FC_AUDICONF0_CC_MASK = 0x70, 808 HDMI_FC_AUDICONF0_CT_OFFSET = 0, 809 HDMI_FC_AUDICONF0_CT_MASK = 0xF, 810 811 /* FC_AUDICONF1 field values */ 812 HDMI_FC_AUDICONF1_SS_OFFSET = 3, 813 HDMI_FC_AUDICONF1_SS_MASK = 0x18, 814 HDMI_FC_AUDICONF1_SF_OFFSET = 0, 815 HDMI_FC_AUDICONF1_SF_MASK = 0x7, 816 817 /* FC_AUDICONF3 field values */ 818 HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5, 819 HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60, 820 HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4, 821 HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10, 822 HDMI_FC_AUDICONF3_LSV_OFFSET = 0, 823 HDMI_FC_AUDICONF3_LSV_MASK = 0xF, 824 825 /* FC_AUDSCHNLS0 field values */ 826 HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4, 827 HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30, 828 HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0, 829 HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01, 830 831 /* FC_AUDSCHNLS3-6 field values */ 832 HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0, 833 HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f, 834 HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4, 835 HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0, 836 HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0, 837 HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f, 838 HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4, 839 HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0, 840 841 HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0, 842 HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f, 843 HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4, 844 HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0, 845 HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0, 846 HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f, 847 HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4, 848 HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0, 849 850 /* HDMI_FC_AUDSCHNLS7 field values */ 851 HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, 852 HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, 853 HDMI_FC_AUDSCHNLS7_SAMPFREQ_OFFSET = 0, 854 HDMI_FC_AUDSCHNLS7_SAMPFREQ_MASK = 0x0f, 855 856 /* HDMI_FC_AUDSCHNLS8 field values */ 857 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, 858 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, 859 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, 860 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, 861 862 /* HDMI_FC_AUDSCHNLS Sample Rate */ 863 HDMI_FC_AUDSCHNLS_32K = 0x3, 864 HDMI_FC_AUDSCHNLS_441K = 0x0, 865 HDMI_FC_AUDSCHNLS_48K = 0x2, 866 HDMI_FC_AUDSCHNLS_882K = 0x8, 867 HDMI_FC_AUDSCHNLS_96K = 0xa, 868 HDMI_FC_AUDSCHNLS_1764K = 0xc, 869 HDMI_FC_AUDSCHNLS_192K = 0xe, 870 871 /* FC_AUDSCONF field values */ 872 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, 873 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, 874 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1, 875 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0, 876 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, 877 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, 878 879 /* FC_STAT2 field values */ 880 HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, 881 HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, 882 HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, 883 884 /* FC_INT2 field values */ 885 HDMI_FC_INT2_OVERFLOW_MASK = 0x03, 886 HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, 887 HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, 888 889 /* FC_MASK2 field values */ 890 HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, 891 HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, 892 HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, 893 894 /* FC_PRCONF field values */ 895 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, 896 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, 897 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F, 898 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, 899 900 /* FC_AVICONF0-FC_AVICONF3 field values */ 901 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, 902 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, 903 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, 904 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, 905 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, 906 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, 907 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, 908 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C, 909 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, 910 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, 911 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, 912 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C, 913 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, 914 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, 915 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, 916 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, 917 918 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F, 919 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, 920 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, 921 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A, 922 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B, 923 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, 924 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, 925 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, 926 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, 927 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0, 928 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, 929 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, 930 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, 931 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0, 932 933 HDMI_FC_AVICONF2_SCALING_MASK = 0x03, 934 HDMI_FC_AVICONF2_SCALING_NONE = 0x00, 935 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, 936 HDMI_FC_AVICONF2_SCALING_VERT = 0x02, 937 HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03, 938 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C, 939 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, 940 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, 941 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, 942 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, 943 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, 944 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, 945 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, 946 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, 947 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, 948 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, 949 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, 950 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, 951 952 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, 953 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, 954 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, 955 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, 956 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, 957 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C, 958 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, 959 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, 960 961 /* FC_DBGFORCE field values */ 962 HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, 963 HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, 964 965 /* FC_DATAUTO0 field values */ 966 HDMI_FC_DATAUTO0_VSD_MASK = 0x08, 967 HDMI_FC_DATAUTO0_VSD_OFFSET = 3, 968 969 /* PHY_CONF0 field values */ 970 HDMI_PHY_CONF0_PDZ_MASK = 0x80, 971 HDMI_PHY_CONF0_PDZ_OFFSET = 7, 972 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, 973 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, 974 HDMI_PHY_CONF0_SVSRET_MASK = 0x20, 975 HDMI_PHY_CONF0_SVSRET_OFFSET = 5, 976 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, 977 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, 978 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, 979 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, 980 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, 981 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, 982 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, 983 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, 984 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, 985 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, 986 987 /* PHY_TST0 field values */ 988 HDMI_PHY_TST0_TSTCLR_MASK = 0x20, 989 HDMI_PHY_TST0_TSTCLR_OFFSET = 5, 990 HDMI_PHY_TST0_TSTEN_MASK = 0x10, 991 HDMI_PHY_TST0_TSTEN_OFFSET = 4, 992 HDMI_PHY_TST0_TSTCLK_MASK = 0x1, 993 HDMI_PHY_TST0_TSTCLK_OFFSET = 0, 994 995 /* PHY_STAT0 field values */ 996 HDMI_PHY_RX_SENSE3 = 0x80, 997 HDMI_PHY_RX_SENSE2 = 0x40, 998 HDMI_PHY_RX_SENSE1 = 0x20, 999 HDMI_PHY_RX_SENSE0 = 0x10, 1000 HDMI_PHY_HPD = 0x02, 1001 HDMI_PHY_TX_PHY_LOCK = 0x01, 1002 1003 /* PHY_I2CM_SLAVE_ADDR field values */ 1004 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, 1005 HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, 1006 1007 /* PHY_I2CM_OPERATION_ADDR field values */ 1008 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, 1009 HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, 1010 1011 /* HDMI_PHY_I2CM_INT_ADDR */ 1012 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, 1013 HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, 1014 1015 /* HDMI_PHY_I2CM_CTLINT_ADDR */ 1016 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, 1017 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, 1018 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, 1019 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, 1020 1021 /* AUD_CONF0 field values */ 1022 HDMI_AUD_CONF0_SW_RESET = 0x80, 1023 HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE = 0x21, 1024 HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE = 0x23, 1025 HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE = 0x27, 1026 HDMI_AUD_CONF0_I2S_8CHANNEL_ENABLE = 0x2F, 1027 HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F, 1028 1029 /* AUD_INT field values */ 1030 HDMI_AUD_INT_FIFO_EMPTY_MSK = BIT(3), 1031 HDMI_AUD_INT_FIFO_FULL_MSK = BIT(2), 1032 1033 /* AUD_CONF1 field values */ 1034 HDMI_AUD_CONF1_MODE_I2S = 0x00, 1035 HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02, 1036 HDMI_AUD_CONF1_MODE_LEFT_J = 0x04, 1037 HDMI_AUD_CONF1_WIDTH_16 = 0x10, 1038 HDMI_AUD_CONF1_WIDTH_21 = 0x15, 1039 HDMI_AUD_CONF1_WIDTH_24 = 0x18, 1040 1041 /* AUD_CONF2 filed values */ 1042 HDMI_AUD_CONF2_HBR = 0x1, 1043 HDMI_AUD_CONF2_NLPCM = 0x2, 1044 HDMI_AUD_CONF2_INSERT_PCUV = 0x04, 1045 1046 /* AUD_CTS3 field values */ 1047 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, 1048 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, 1049 HDMI_AUD_CTS3_N_SHIFT_1 = 0, 1050 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, 1051 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, 1052 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, 1053 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, 1054 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, 1055 /* note that the CTS3 MANUAL bit has been removed from our part. */ 1056 HDMI_AUD_CTS3_CTS_MANUAL = 0x10, 1057 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, 1058 1059 /* HDMI_AUD_INPUTCLKFS field values */ 1060 HDMI_AUD_INPUTCLKFS_128FS = 0, 1061 HDMI_AUD_INPUTCLKFS_256FS = 1, 1062 HDMI_AUD_INPUTCLKFS_512FS = 2, 1063 HDMI_AUD_INPUTCLKFS_64FS = 4, 1064 1065 /* AHB_DMA_CONF0 field values */ 1066 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7, 1067 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80, 1068 HDMI_AHB_DMA_CONF0_HBR = 0x10, 1069 HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3, 1070 HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08, 1071 HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1, 1072 HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06, 1073 HDMI_AHB_DMA_CONF0_INCR4 = 0x0, 1074 HDMI_AHB_DMA_CONF0_INCR8 = 0x2, 1075 HDMI_AHB_DMA_CONF0_INCR16 = 0x4, 1076 HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1, 1077 1078 /* HDMI_AHB_DMA_START field values */ 1079 HDMI_AHB_DMA_START_START_OFFSET = 0, 1080 HDMI_AHB_DMA_START_START_MASK = 0x01, 1081 1082 /* HDMI_AHB_DMA_STOP field values */ 1083 HDMI_AHB_DMA_STOP_STOP_OFFSET = 0, 1084 HDMI_AHB_DMA_STOP_STOP_MASK = 0x01, 1085 1086 /* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */ 1087 HDMI_AHB_DMA_DONE = 0x80, 1088 HDMI_AHB_DMA_RETRY_SPLIT = 0x40, 1089 HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20, 1090 HDMI_AHB_DMA_ERROR = 0x10, 1091 HDMI_AHB_DMA_FIFO_THREMPTY = 0x04, 1092 HDMI_AHB_DMA_FIFO_FULL = 0x02, 1093 HDMI_AHB_DMA_FIFO_EMPTY = 0x01, 1094 1095 /* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */ 1096 HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02, 1097 HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, 1098 1099 /* MC_CLKDIS field values */ 1100 HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, 1101 HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, 1102 HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, 1103 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, 1104 HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, 1105 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, 1106 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, 1107 1108 /* MC_SWRSTZ field values */ 1109 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, 1110 1111 /* MC_FLOWCTRL field values */ 1112 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, 1113 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, 1114 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, 1115 1116 /* MC_PHYRSTZ field values */ 1117 HDMI_MC_PHYRSTZ_PHYRSTZ = 0x01, 1118 1119 /* MC_HEACPHY_RST field values */ 1120 HDMI_MC_HEACPHY_RST_ASSERT = 0x1, 1121 HDMI_MC_HEACPHY_RST_DEASSERT = 0x0, 1122 1123 /* CSC_CFG field values */ 1124 HDMI_CSC_CFG_INTMODE_MASK = 0x30, 1125 HDMI_CSC_CFG_INTMODE_OFFSET = 4, 1126 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, 1127 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, 1128 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, 1129 HDMI_CSC_CFG_DECMODE_MASK = 0x3, 1130 HDMI_CSC_CFG_DECMODE_OFFSET = 0, 1131 HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, 1132 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, 1133 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, 1134 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, 1135 1136 /* CSC_SCALE field values */ 1137 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, 1138 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, 1139 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, 1140 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, 1141 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, 1142 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, 1143 1144 /* A_HDCPCFG0 field values */ 1145 HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80, 1146 HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80, 1147 HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00, 1148 HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40, 1149 HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40, 1150 HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00, 1151 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20, 1152 HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20, 1153 HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00, 1154 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10, 1155 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10, 1156 HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00, 1157 HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8, 1158 HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8, 1159 HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0, 1160 HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4, 1161 HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4, 1162 HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0, 1163 HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2, 1164 HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2, 1165 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0, 1166 HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1, 1167 HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1, 1168 HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0, 1169 1170 /* A_HDCPCFG1 field values */ 1171 HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8, 1172 HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8, 1173 HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0, 1174 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4, 1175 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4, 1176 HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0, 1177 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2, 1178 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2, 1179 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0, 1180 HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1, 1181 HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0, 1182 1183 /* A_VIDPOLCFG field values */ 1184 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60, 1185 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5, 1186 HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10, 1187 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10, 1188 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0, 1189 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8, 1190 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8, 1191 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0, 1192 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2, 1193 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2, 1194 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, 1195 1196 /* I2CM_OPERATION field values */ 1197 HDMI_I2CM_OPERATION_BUS_CLEAR = 0x20, 1198 HDMI_I2CM_OPERATION_WRITE = 0x10, 1199 HDMI_I2CM_OPERATION_READ8_EXT = 0x8, 1200 HDMI_I2CM_OPERATION_READ8 = 0x4, 1201 HDMI_I2CM_OPERATION_READ_EXT = 0x2, 1202 HDMI_I2CM_OPERATION_READ = 0x1, 1203 1204 /* I2CM_INT field values */ 1205 HDMI_I2CM_INT_DONE_POL = 0x8, 1206 HDMI_I2CM_INT_DONE_MASK = 0x4, 1207 1208 /* I2CM_CTLINT field values */ 1209 HDMI_I2CM_CTLINT_NAC_POL = 0x80, 1210 HDMI_I2CM_CTLINT_NAC_MASK = 0x40, 1211 HDMI_I2CM_CTLINT_ARB_POL = 0x8, 1212 HDMI_I2CM_CTLINT_ARB_MASK = 0x4, 1213 1214 /* I2CM_DIV field values */ 1215 HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, 1216 HDMI_I2CM_DIV_FAST_MODE = 0x8, 1217 HDMI_I2CM_DIV_STD_MODE = 0, 1218 1219 /* HDMI_MC_SWRSTZ filed values */ 1220 HDMI_MC_SWRSTZ_I2S_RESET_MSK = BIT(3), 1221 }; 1222 1223 enum { 1224 HDMI_MC_CLKDIS_HDCPCLK_MASK = 0x40, 1225 HDMI_MC_CLKDIS_HDCPCLK_ENABLE = 0x00, 1226 1227 HDMI_A_SRMCTRL_SHA1_FAIL_MASK = 0X08, 1228 HDMI_A_SRMCTRL_SHA1_FAIL_DISABLE = 0X00, 1229 HDMI_A_SRMCTRL_SHA1_FAIL_ENABLE = 0X08, 1230 1231 HDMI_A_SRMCTRL_KSV_UPDATE_MASK = 0X04, 1232 HDMI_A_SRMCTRL_KSV_UPDATE_DISABLE = 0X00, 1233 HDMI_A_SRMCTRL_KSV_UPDATE_ENABLE = 0X04, 1234 1235 HDMI_A_SRMCTRL_KSV_MEM_REQ_MASK = 0X01, 1236 HDMI_A_SRMCTRL_KSV_MEM_REQ_DISABLE = 0X00, 1237 HDMI_A_SRMCTRL_KSV_MEM_REQ_ENABLE = 0X01, 1238 1239 HDMI_A_SRMCTRL_KSV_MEM_ACCESS_MASK = 0X02, 1240 HDMI_A_SRMCTRL_KSV_MEM_ACCESS_DISABLE = 0X00, 1241 HDMI_A_SRMCTRL_KSV_MEM_ACCESS_ENABLE = 0X02, 1242 1243 HDMI_A_SRM_BASE_MAX_DEVS_EXCEEDED = 0x80, 1244 HDMI_A_SRM_BASE_DEVICE_COUNT = 0x7f, 1245 1246 HDMI_A_SRM_BASE_MAX_CASCADE_EXCEEDED = 0x08, 1247 1248 HDMI_A_APIINTSTAT_KSVSHA1_CALC_INT = 0x02, 1249 1250 /* HDCPREG_RMSTS field values */ 1251 DPK_WR_OK_STS = 0x40, 1252 1253 HDMI_A_HDCP22_MASK = 0x40, 1254 1255 HDMI_HDCP2_OVR_EN_MASK = 0x02, 1256 HDMI_HDCP2_OVR_ENABLE = 0x02, 1257 HDMI_HDCP2_OVR_DISABLE = 0x00, 1258 1259 HDMI_HDCP2_FORCE_MASK = 0x04, 1260 HDMI_HDCP2_FORCE_ENABLE = 0x04, 1261 HDMI_HDCP2_FORCE_DISABLE = 0x00, 1262 }; 1263 1264 enum { 1265 DW_HDMI_HDCP_KSV_LEN = 8, 1266 DW_HDMI_HDCP_SHA_LEN = 20, 1267 DW_HDMI_HDCP_DPK_LEN = 280, 1268 DW_HDMI_HDCP_KEY_LEN = 308, 1269 DW_HDMI_HDCP_SEED_LEN = 2, 1270 }; 1271 1272 /* 1273 * HDMI 3D TX PHY registers 1274 */ 1275 #define HDMI_3D_TX_PHY_PWRCTRL 0x00 1276 #define HDMI_3D_TX_PHY_SERDIVCTRL 0x01 1277 #define HDMI_3D_TX_PHY_SERCKCTRL 0x02 1278 #define HDMI_3D_TX_PHY_SERCKKILLCTRL 0x03 1279 #define HDMI_3D_TX_PHY_TXRESCTRL 0x04 1280 #define HDMI_3D_TX_PHY_CKCALCTRL 0x05 1281 #define HDMI_3D_TX_PHY_CPCE_CTRL 0x06 1282 #define HDMI_3D_TX_PHY_TXCLKMEASCTRL 0x07 1283 #define HDMI_3D_TX_PHY_TXMEASCTRL 0x08 1284 #define HDMI_3D_TX_PHY_CKSYMTXCTRL 0x09 1285 #define HDMI_3D_TX_PHY_CMPSEQCTRL 0x0a 1286 #define HDMI_3D_TX_PHY_CMPPWRCTRL 0x0b 1287 #define HDMI_3D_TX_PHY_CMPMODECTRL 0x0c 1288 #define HDMI_3D_TX_PHY_MEASCTRL 0x0d 1289 #define HDMI_3D_TX_PHY_VLEVCTRL 0x0e 1290 #define HDMI_3D_TX_PHY_D2ACTRL 0x0f 1291 #define HDMI_3D_TX_PHY_CURRCTRL 0x10 1292 #define HDMI_3D_TX_PHY_DRVANACTRL 0x11 1293 #define HDMI_3D_TX_PHY_PLLMEASCTRL 0x12 1294 #define HDMI_3D_TX_PHY_PLLPHBYCTRL 0x13 1295 #define HDMI_3D_TX_PHY_GRP_CTRL 0x14 1296 #define HDMI_3D_TX_PHY_GMPCTRL 0x15 1297 #define HDMI_3D_TX_PHY_MPLLMEASCTRL 0x16 1298 #define HDMI_3D_TX_PHY_MSM_CTRL 0x17 1299 #define HDMI_3D_TX_PHY_SCRPB_STATUS 0x18 1300 #define HDMI_3D_TX_PHY_TXTERM 0x19 1301 #define HDMI_3D_TX_PHY_PTRPT_ENBL 0x1a 1302 #define HDMI_3D_TX_PHY_PATTERNGEN 0x1b 1303 #define HDMI_3D_TX_PHY_SDCAP_MODE 0x1c 1304 #define HDMI_3D_TX_PHY_SCOPEMODE 0x1d 1305 #define HDMI_3D_TX_PHY_DIGTXMODE 0x1e 1306 #define HDMI_3D_TX_PHY_STR_STATUS 0x1f 1307 #define HDMI_3D_TX_PHY_SCOPECNT0 0x20 1308 #define HDMI_3D_TX_PHY_SCOPECNT1 0x21 1309 #define HDMI_3D_TX_PHY_SCOPECNT2 0x22 1310 #define HDMI_3D_TX_PHY_SCOPECNTCLK 0x23 1311 #define HDMI_3D_TX_PHY_SCOPESAMPLE 0x24 1312 #define HDMI_3D_TX_PHY_SCOPECNTMSB01 0x25 1313 #define HDMI_3D_TX_PHY_SCOPECNTMSB2CK 0x26 1314 1315 /* HDMI_3D_TX_PHY_CKCALCTRL values */ 1316 #define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE BIT(15) 1317 1318 /* HDMI_3D_TX_PHY_MSM_CTRL values */ 1319 #define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK BIT(13) 1320 #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL (0 << 1) 1321 #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF BIT(1) 1322 #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK (2 << 1) 1323 #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK (3 << 1) 1324 #define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL BIT(0) 1325 1326 /* HDMI_3D_TX_PHY_PTRPT_ENBL values */ 1327 #define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE BIT(15) 1328 #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2 BIT(8) 1329 #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1 BIT(7) 1330 #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0 BIT(6) 1331 #define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB BIT(5) 1332 #define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB BIT(4) 1333 #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB BIT(3) 1334 #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY BIT(2) 1335 #define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB BIT(1) 1336 #define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB BIT(0) 1337 1338 #define HDMI_VIDEO_DEFAULT_MODE 4 1339 1340 enum v4l2_ycbcr_encoding { 1341 /* 1342 * Mapping of V4L2_YCBCR_ENC_DEFAULT to actual encodings for the 1343 * various colorspaces: 1344 * 1345 * V4L2_COLORSPACE_SMPTE170M, V4L2_COLORSPACE_470_SYSTEM_M, 1346 * V4L2_COLORSPACE_470_SYSTEM_BG, V4L2_COLORSPACE_ADOBERGB and 1347 * V4L2_COLORSPACE_JPEG: V4L2_YCBCR_ENC_601 1348 * 1349 * V4L2_COLORSPACE_REC709 and V4L2_COLORSPACE_DCI_P3: V4L2_YCBCR_ENC_709 1350 * 1351 * V4L2_COLORSPACE_SRGB: V4L2_YCBCR_ENC_SYCC 1352 * 1353 * V4L2_COLORSPACE_BT2020: V4L2_YCBCR_ENC_BT2020 1354 * 1355 * V4L2_COLORSPACE_SMPTE240M: V4L2_YCBCR_ENC_SMPTE240M 1356 */ 1357 V4L2_YCBCR_ENC_DEFAULT = 0, 1358 1359 /* ITU-R 601 -- SDTV */ 1360 V4L2_YCBCR_ENC_601 = 1, 1361 1362 /* Rec. 709 -- HDTV */ 1363 V4L2_YCBCR_ENC_709 = 2, 1364 1365 /* ITU-R 601/EN 61966-2-4 Extended Gamut -- SDTV */ 1366 V4L2_YCBCR_ENC_XV601 = 3, 1367 1368 /* Rec. 709/EN 61966-2-4 Extended Gamut -- HDTV */ 1369 V4L2_YCBCR_ENC_XV709 = 4, 1370 1371 /* sYCC (Y'CbCr encoding of sRGB) */ 1372 V4L2_YCBCR_ENC_SYCC = 5, 1373 1374 /* BT.2020 Non-constant Luminance Y'CbCr */ 1375 V4L2_YCBCR_ENC_BT2020 = 6, 1376 1377 /* BT.2020 Constant Luminance Y'CbcCrc */ 1378 V4L2_YCBCR_ENC_BT2020_CONST_LUM = 7, 1379 1380 /* SMPTE 240M -- Obsolete HDTV */ 1381 V4L2_YCBCR_ENC_SMPTE240M = 8, 1382 }; 1383 1384 /* Color Space Conversion Mode */ 1385 enum { 1386 CSC_RGB_0_255_TO_RGB_16_235_8BIT, 1387 CSC_RGB_0_255_TO_RGB_16_235_10BIT, 1388 CSC_RGB_0_255_TO_ITU601_16_235_8BIT, 1389 CSC_RGB_0_255_TO_ITU601_16_235_10BIT, 1390 CSC_RGB_0_255_TO_ITU709_16_235_8BIT, 1391 CSC_RGB_0_255_TO_ITU709_16_235_10BIT, 1392 CSC_ITU601_16_235_TO_RGB_0_255_8BIT, 1393 CSC_ITU709_16_235_TO_RGB_0_255_8BIT, 1394 CSC_ITU601_16_235_TO_RGB_16_235_8BIT, 1395 CSC_ITU709_16_235_TO_RGB_16_235_8BIT 1396 }; 1397 1398 enum drm_connector_status { 1399 connector_status_disconnected = 0, 1400 connector_status_connected = 1, 1401 }; 1402 1403 enum { 1404 STANDARD_MODE = 0, 1405 FAST_MODE 1406 }; 1407 1408 void drm_rk_selete_output(struct hdmi_edid_data *edid_data, 1409 struct connector_state *conn_state, 1410 unsigned int *bus_format, 1411 struct overscan *overscan, 1412 enum dw_hdmi_devtype dev_type, 1413 bool output_bus_format_rgb); 1414 void inno_dw_hdmi_set_domain(void *grf, int status); 1415 void dw_hdmi_set_iomux(void *grf, void *gpio_base, struct gpio_desc *hpd_gpiod, 1416 int dev_type); 1417 1418 #endif /* _ROCKCHIP_HDMI_H_ */ 1419