1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip Vehicle driver 4 * 5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd. 6 */ 7 #ifndef __VEHICLE_CIF_H 8 #define __VEHICLE_CIF_H 9 10 #include "vehicle_cfg.h" 11 #include "vehicle_cif_regs.h" 12 #include "../../../media/platform/rockchip/cif/dev.h" 13 #include <linux/dma-mapping.h> 14 15 enum vehicle_rkcif_chip_id { 16 CHIP_RK3568_VEHICLE_CIF = 0x0, 17 CHIP_RK3588_VEHICLE_CIF, 18 CHIP_RK3562_VEHICLE_CIF, 19 }; 20 21 enum rkcif_csi_host_idx { 22 RKCIF_MIPI0_CSI2 = 0x0, 23 RKCIF_MIPI1_CSI2, 24 RKCIF_MIPI2_CSI2, 25 RKCIF_MIPI3_CSI2, 26 RKCIF_MIPI4_CSI2, 27 RKCIF_MIPI5_CSI2, 28 }; 29 30 struct vehicle_rkcif_dummy_buffer { 31 void *vaddr; 32 dma_addr_t dma_addr; 33 u32 size; 34 }; 35 36 struct rk_cif_clk { 37 /************clk************/ 38 struct clk *clks[RKCIF_MAX_BUS_CLK]; 39 struct clk *xvclk; 40 int clks_num; 41 /************reset************/ 42 struct reset_control *cif_rst[RKCIF_MAX_RESET]; 43 int rsts_num; 44 /* spinlock_t lock; */ 45 bool on; 46 }; 47 48 struct rk_cif_irqinfo { 49 unsigned int irq; 50 unsigned long cifirq_idx; 51 unsigned long cifirq_normal_idx; 52 unsigned long cifirq_abnormal_idx; 53 unsigned long dmairq_idx; 54 55 /* @csi_overflow_cnt: count of csi overflow irq 56 * @csi_bwidth_lack_cnt: count of csi bandwidth lack irq 57 * @dvp_bus_err_cnt: count of dvp bus err irq 58 * @dvp_overflow_cnt: count dvp overflow irq 59 * @dvp_line_err_cnt: count dvp line err irq 60 * @dvp_pix_err_cnt: count dvp pix err irq 61 * @all_frm_end_cnt: raw frame end count 62 * @all_err_cnt: all err count 63 * @ 64 */ 65 66 u64 csi_overflow_cnt; 67 u64 csi_bwidth_lack_cnt; 68 u64 dvp_bus_err_cnt; 69 u64 dvp_overflow_cnt; 70 u64 dvp_line_err_cnt; 71 u64 dvp_pix_err_cnt; 72 u64 all_frm_end_cnt; 73 u64 all_err_cnt; 74 u64 dvp_size_err_cnt; 75 u64 dvp_bwidth_lack_cnt; 76 u64 csi_size_err_cnt; 77 }; 78 79 #define RKCIF_MAX_CSI_CHANNEL 4 80 struct vehicle_csi_channel_info { 81 unsigned char id; 82 unsigned char enable; /* capture enable */ 83 unsigned char vc; 84 unsigned char data_type; 85 unsigned char crop_en; 86 unsigned char cmd_mode_en; 87 unsigned char fmt_val; 88 unsigned int width; 89 unsigned int height; 90 unsigned int virtual_width; 91 unsigned int crop_st_x; 92 unsigned int crop_st_y; 93 }; 94 95 struct vehicle_csi2_err_state_work { 96 struct workqueue_struct *err_print_wq; 97 struct work_struct work; 98 char err_str[CSI_ERRSTR_LEN]; 99 u32 err_val; 100 u32 err_num; 101 unsigned long err_stat; 102 }; 103 104 struct vehicle_cif { 105 struct device *dev; 106 struct device_node *phy_node; 107 struct rk_cif_clk clk; 108 struct vehicle_cfg cif_cfg; 109 char *base; /*cif base addr*/ 110 //unsigned long cru_base; 111 //unsigned long grf_base; 112 void __iomem *cru_base; /*cru base addr*/ 113 void __iomem *grf_base; /*grf base addr*/ 114 void __iomem *csi2_dphy_base; /*csi2_dphy base addr*/ 115 void __iomem *csi2_base; /*csi2 base addr*/ 116 struct delayed_work work; 117 118 bool is_enabled; 119 u32 frame_buf[MAX_BUF_NUM]; 120 u32 current_buf_index; 121 u32 last_buf_index; 122 u32 active[2]; 123 int irq; 124 int csi2_irq1; 125 int csi2_irq2; 126 int drop_frames; 127 struct rk_cif_irqinfo irqinfo; 128 const struct vehicle_cif_reg *cif_regs; 129 struct regmap *regmap_grf; 130 struct regmap *regmap_dphy_grf; 131 unsigned int frame_idx; 132 struct vehicle_rkcif_dummy_buffer dummy_buf; 133 struct csi2_dphy_hw *dphy_hw; 134 int num_channels; 135 int chip_id; 136 int inf_id; 137 unsigned int csi_host_idx; 138 struct vehicle_csi_channel_info channels[RKCIF_MAX_CSI_CHANNEL]; 139 spinlock_t vbq_lock; /* vfd lock */ 140 bool interlaced_enable; 141 unsigned int interlaced_offset; 142 unsigned int interlaced_counts; 143 unsigned long *interlaced_buffer; 144 atomic_t reset_status; 145 wait_queue_head_t wq_stopped; 146 bool stopping; 147 struct mutex stream_lock; 148 enum rkcif_state state; 149 struct vehicle_csi2_err_state_work err_state; 150 }; 151 152 int vehicle_cif_init_mclk(struct vehicle_cif *cif); 153 int vehicle_cif_init(struct vehicle_cif *cif); 154 int vehicle_cif_deinit(struct vehicle_cif *cif); 155 156 int vehicle_cif_reverse_open(struct vehicle_cfg *v_cfg); 157 158 int vehicle_cif_reverse_close(void); 159 int vehicle_wait_cif_reset_done(void); 160 161 /* CIF IRQ STAT*/ 162 #define DMA_FRAME_END (0x01 << 0) 163 #define LINE_END (0x01 << 1) 164 #define IFIFO_OF (0x01 << 4) 165 #define DFIFO_OF (0x01 << 5) 166 #define PRE_INF_FRAME_END (0x01 << 8) 167 #define PST_INF_FRAME_END (0x01 << 9) 168 169 enum rk_camera_signal_polarity { 170 RK_CAMERA_DEVICE_SIGNAL_HIGH_LEVEL = 1, 171 RK_CAMERA_DEVICE_SIGNAL_LOW_LEVEL = 0, 172 }; 173 174 enum rk_camera_device_type { 175 RK_CAMERA_DEVICE_BT601_8 = 0x10000011, 176 RK_CAMERA_DEVICE_BT601_10 = 0x10000012, 177 RK_CAMERA_DEVICE_BT601_12 = 0x10000014, 178 RK_CAMERA_DEVICE_BT601_16 = 0x10000018, 179 180 RK_CAMERA_DEVICE_BT656_8 = 0x10000021, 181 RK_CAMERA_DEVICE_BT656_10 = 0x10000022, 182 RK_CAMERA_DEVICE_BT656_12 = 0x10000024, 183 RK_CAMERA_DEVICE_BT656_16 = 0x10000028, 184 185 RK_CAMERA_DEVICE_CVBS_NTSC = 0x20000001, 186 RK_CAMERA_DEVICE_CVBS_PAL = 0x20000002 187 }; 188 189 #endif 190