1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * DesignWare MIPI DSI Host Controller v1.02 driver
4 *
5 * Copyright (c) 2016 Linaro Limited.
6 * Copyright (c) 2014-2016 Hisilicon Limited.
7 *
8 * Author:
9 * Xinliang Liu <z.liuxinliang@hisilicon.com>
10 * Xinliang Liu <xinliang.liu@linaro.org>
11 * Xinwei Kong <kong.kongxinwei@hisilicon.com>
12 * Da Lv <lvda3@hisilicon.com>
13 */
14
15 #include <linux/clk.h>
16 #include <linux/component.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_device.h>
24 #include <drm/drm_mipi_dsi.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_print.h>
27 #include <drm/drm_probe_helper.h>
28 #include <drm/drm_simple_kms_helper.h>
29
30 #include "../kirin_drm_dsi.h"
31 #include "../dw_dsi_reg.h"
32
33 #define MAX_TX_ESC_CLK 10
34
dsi_calc_phy_rate(u32 req_kHz,struct mipi_phy_params * phy)35 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
36 {
37 u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
38 u32 tmp_kHz = req_kHz;
39 u32 i = 0;
40 u32 q_pll = 1;
41 u32 m_pll = 0;
42 u32 n_pll = 0;
43 u32 r_pll = 1;
44 u32 m_n = 0;
45 u32 m_n_int = 0;
46 u32 f_kHz = 0;
47 u64 temp;
48
49 /*
50 * Find a rate >= req_kHz.
51 */
52 do {
53 f_kHz = tmp_kHz;
54
55 for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++)
56 if (f_kHz >= dphy_range_info[i].min_range_kHz &&
57 f_kHz <= dphy_range_info[i].max_range_kHz)
58 break;
59
60 if (i == ARRAY_SIZE(dphy_range_info)) {
61 DRM_ERROR("%dkHz out of range\n", f_kHz);
62 return 0;
63 }
64
65 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M;
66 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel;
67
68 if (phy->hstx_ckg_sel <= 7 &&
69 phy->hstx_ckg_sel >= 4)
70 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
71
72 temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
73 m_n_int = temp / (u64)1000000000;
74 m_n = (temp % (u64)1000000000) / (u64)100000000;
75
76 if (m_n_int % 2 == 0) {
77 if (m_n * 6 >= 50) {
78 n_pll = 2;
79 m_pll = (m_n_int + 1) * n_pll;
80 } else if (m_n * 6 >= 30) {
81 n_pll = 3;
82 m_pll = m_n_int * n_pll + 2;
83 } else {
84 n_pll = 1;
85 m_pll = m_n_int * n_pll;
86 }
87 } else {
88 if (m_n * 6 >= 50) {
89 n_pll = 1;
90 m_pll = (m_n_int + 1) * n_pll;
91 } else if (m_n * 6 >= 30) {
92 n_pll = 1;
93 m_pll = (m_n_int + 1) * n_pll;
94 } else if (m_n * 6 >= 10) {
95 n_pll = 3;
96 m_pll = m_n_int * n_pll + 1;
97 } else {
98 n_pll = 2;
99 m_pll = m_n_int * n_pll;
100 }
101 }
102
103 if (n_pll == 1) {
104 phy->pll_fbd_p = 0;
105 phy->pll_pre_div1p = 1;
106 } else {
107 phy->pll_fbd_p = n_pll;
108 phy->pll_pre_div1p = 0;
109 }
110
111 if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4)
112 r_pll = 0x10 >> (7 - phy->pll_fbd_2p);
113
114 if (m_pll == 2) {
115 phy->pll_pre_p = 0;
116 phy->pll_fbd_s = 0;
117 phy->pll_fbd_div1f = 0;
118 phy->pll_fbd_div5f = 1;
119 } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) {
120 phy->pll_pre_p = m_pll / (2 * r_pll);
121 phy->pll_fbd_s = 0;
122 phy->pll_fbd_div1f = 1;
123 phy->pll_fbd_div5f = 0;
124 } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) {
125 if (((m_pll / (2 * r_pll)) % 2) == 0) {
126 phy->pll_pre_p =
127 (m_pll / (2 * r_pll)) / 2 - 1;
128 phy->pll_fbd_s =
129 (m_pll / (2 * r_pll)) % 2 + 2;
130 } else {
131 phy->pll_pre_p =
132 (m_pll / (2 * r_pll)) / 2;
133 phy->pll_fbd_s =
134 (m_pll / (2 * r_pll)) % 2;
135 }
136 phy->pll_fbd_div1f = 0;
137 phy->pll_fbd_div5f = 0;
138 } else {
139 phy->pll_pre_p = 0;
140 phy->pll_fbd_s = 0;
141 phy->pll_fbd_div1f = 0;
142 phy->pll_fbd_div5f = 1;
143 }
144
145 f_kHz = (u64)1000000000 * (u64)m_pll /
146 ((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
147
148 if (f_kHz >= req_kHz)
149 break;
150
151 tmp_kHz += 10;
152
153 } while (true);
154
155 return f_kHz;
156 }
157
dsi_get_phy_params(u32 phy_req_kHz,struct mipi_phy_params * phy)158 static void dsi_get_phy_params(u32 phy_req_kHz,
159 struct mipi_phy_params *phy)
160 {
161 u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
162 u32 phy_rate_kHz;
163 u32 ui;
164
165 memset(phy, 0, sizeof(*phy));
166
167 phy_rate_kHz = dsi_calc_phy_rate(phy_req_kHz, phy);
168 if (!phy_rate_kHz)
169 return;
170
171 ui = 1000000 / phy_rate_kHz;
172
173 phy->clk_t_lpx = ROUND(50, 8 * ui);
174 phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
175
176 phy->clk_t_hs_zero = ROUND(262, 8 * ui);
177 phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
178 phy->clk_t_wakeup = ROUND(1000000, (ref_clk_ps / 1000) - 1);
179 if (phy->clk_t_wakeup > 0xff)
180 phy->clk_t_wakeup = 0xff;
181 phy->data_t_wakeup = phy->clk_t_wakeup;
182 phy->data_t_lpx = phy->clk_t_lpx;
183 phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
184 phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
185 phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
186 phy->data_t_ta_go = 3;
187 phy->data_t_ta_get = 4;
188
189 phy->pll_enbwt = 1;
190 phy->clklp2hs_time = ROUND(407, 8 * ui) + 12;
191 phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
192 phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
193 phy->hs2lp_time = phy->clkhs2lp_time;
194 phy->clk_to_data_delay = 1 + phy->clklp2hs_time;
195 phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
196 phy->clkhs2lp_time;
197
198 phy->lane_byte_clk_kHz = phy_rate_kHz / 8;
199 phy->clk_division =
200 DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK);
201 }
202
dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format)203 static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format)
204 {
205 u32 val;
206
207 /*
208 * TODO: only support RGB888 now, to support more
209 */
210 switch (format) {
211 case MIPI_DSI_FMT_RGB888:
212 val = DSI_24BITS_1;
213 break;
214 default:
215 val = DSI_24BITS_1;
216 break;
217 }
218
219 return val;
220 }
221
222 /*
223 * dsi phy reg write function
224 */
dsi_phy_tst_set(void __iomem * base,u32 reg,u32 val)225 static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val)
226 {
227 u32 reg_write = 0x10000 + reg;
228
229 /*
230 * latch reg first
231 */
232 writel(reg_write, base + PHY_TST_CTRL1);
233 writel(0x02, base + PHY_TST_CTRL0);
234 writel(0x00, base + PHY_TST_CTRL0);
235
236 /*
237 * then latch value
238 */
239 writel(val, base + PHY_TST_CTRL1);
240 writel(0x02, base + PHY_TST_CTRL0);
241 writel(0x00, base + PHY_TST_CTRL0);
242 }
243
dsi_set_phy_timer(void __iomem * base,struct mipi_phy_params * phy,u32 lanes)244 static void dsi_set_phy_timer(void __iomem *base,
245 struct mipi_phy_params *phy,
246 u32 lanes)
247 {
248 u32 val;
249
250 /*
251 * Set lane value and phy stop wait time.
252 */
253 val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8);
254 writel(val, base + PHY_IF_CFG);
255
256 /*
257 * Set phy clk division.
258 */
259 val = readl(base + CLKMGR_CFG) | phy->clk_division;
260 writel(val, base + CLKMGR_CFG);
261
262 /*
263 * Set lp and hs switching params.
264 */
265 dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time);
266 dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time);
267 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10),
268 phy->clkhs2lp_time);
269 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10),
270 phy->clklp2hs_time);
271 dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8),
272 phy->data_to_clk_delay);
273 dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8),
274 phy->clk_to_data_delay);
275 }
276
dsi_set_mipi_phy(void __iomem * base,struct mipi_phy_params * phy,u32 lanes)277 static void dsi_set_mipi_phy(void __iomem *base,
278 struct mipi_phy_params *phy,
279 u32 lanes)
280 {
281 u32 delay_count;
282 u32 val;
283 u32 i;
284
285 /* phy timer setting */
286 dsi_set_phy_timer(base, phy, lanes);
287
288 /*
289 * Reset to clean up phy tst params.
290 */
291 writel(0, base + PHY_RSTZ);
292 writel(0, base + PHY_TST_CTRL0);
293 writel(1, base + PHY_TST_CTRL0);
294 writel(0, base + PHY_TST_CTRL0);
295
296 /*
297 * Clock lane timing control setting: TLPX, THS-PREPARE,
298 * THS-ZERO, THS-TRAIL, TWAKEUP.
299 */
300 dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx);
301 dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare);
302 dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero);
303 dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial);
304 dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup);
305
306 /*
307 * Data lane timing control setting: TLPX, THS-PREPARE,
308 * THS-ZERO, THS-TRAIL, TTA-GO, TTA-GET, TWAKEUP.
309 */
310 for (i = 0; i < lanes; i++) {
311 dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx);
312 dsi_phy_tst_set(base, DATA_THS_PREPARE(i),
313 phy->data_t_hs_prepare);
314 dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero);
315 dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial);
316 dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go);
317 dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get);
318 dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup);
319 }
320
321 /*
322 * physical configuration: I, pll I, pll II, pll III,
323 * pll IV, pll V.
324 */
325 dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel);
326 val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) +
327 (phy->pll_fbd_2p << 1) + phy->pll_enbwt;
328 dsi_phy_tst_set(base, PHY_CFG_PLL_I, val);
329 dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p);
330 dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s);
331 val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p;
332 dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val);
333 val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) +
334 phy->pll_lpf_cs;
335 dsi_phy_tst_set(base, PHY_CFG_PLL_V, val);
336
337 writel(PHY_ENABLECLK, base + PHY_RSTZ);
338 udelay(1);
339 writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
340 udelay(1);
341 writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
342 usleep_range(1000, 1500);
343
344 /*
345 * wait for phy's clock ready
346 */
347 delay_count = 100;
348 while (delay_count) {
349 val = readl(base + PHY_STATUS);
350 if ((BIT(0) | BIT(2)) & val)
351 break;
352
353 udelay(1);
354 delay_count--;
355 }
356
357 if (!delay_count)
358 DRM_INFO("phylock and phystopstateclklane is not ready.\n");
359 }
360
dsi_set_mode_timing(void __iomem * base,u32 lane_byte_clk_kHz,struct drm_display_mode * mode,enum mipi_dsi_pixel_format format)361 static void dsi_set_mode_timing(void __iomem *base,
362 u32 lane_byte_clk_kHz,
363 struct drm_display_mode *mode,
364 enum mipi_dsi_pixel_format format)
365 {
366 u32 hfp, hbp, hsw, vfp, vbp, vsw;
367 u32 hline_time;
368 u32 hsa_time;
369 u32 hbp_time;
370 u32 pixel_clk_kHz;
371 int htot, vtot;
372 u32 val;
373 u64 tmp;
374
375 val = dsi_get_dpi_color_coding(format);
376 writel(val, base + DPI_COLOR_CODING);
377
378 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2;
379 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1;
380 writel(val, base + DPI_CFG_POL);
381
382 /*
383 * The DSI IP accepts vertical timing using lines as normal,
384 * but horizontal timing is a mixture of pixel-clocks for the
385 * active region and byte-lane clocks for the blanking-related
386 * timings. hfp is specified as the total hline_time in byte-
387 * lane clocks minus hsa, hbp and active.
388 */
389 pixel_clk_kHz = mode->clock;
390 htot = mode->htotal;
391 vtot = mode->vtotal;
392 hfp = mode->hsync_start - mode->hdisplay;
393 hbp = mode->htotal - mode->hsync_end;
394 hsw = mode->hsync_end - mode->hsync_start;
395 vfp = mode->vsync_start - mode->vdisplay;
396 vbp = mode->vtotal - mode->vsync_end;
397 vsw = mode->vsync_end - mode->vsync_start;
398 if (vsw > 15) {
399 DRM_DEBUG_DRIVER("vsw exceeded 15\n");
400 vsw = 15;
401 }
402
403 hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
404 hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
405 tmp = (u64)htot * (u64)lane_byte_clk_kHz;
406 hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
407
408 /* all specified in byte-lane clocks */
409 writel(hsa_time, base + VID_HSA_TIME);
410 writel(hbp_time, base + VID_HBP_TIME);
411 writel(hline_time, base + VID_HLINE_TIME);
412
413 writel(vsw, base + VID_VSA_LINES);
414 writel(vbp, base + VID_VBP_LINES);
415 writel(vfp, base + VID_VFP_LINES);
416 writel(mode->vdisplay, base + VID_VACTIVE_LINES);
417 writel(mode->hdisplay, base + VID_PKT_SIZE);
418
419 DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n",
420 htot, hfp, hbp, hsw);
421 DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n",
422 vtot, vfp, vbp, vsw);
423 DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n",
424 hsa_time, hbp_time, hline_time);
425 }
426
dsi_set_video_mode(void __iomem * base,unsigned long flags)427 static void dsi_set_video_mode(void __iomem *base, unsigned long flags)
428 {
429 u32 val;
430 u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
431 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
432 u32 non_burst_sync_pulse = MIPI_DSI_MODE_VIDEO |
433 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
434 u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO;
435
436 /*
437 * choose video mode type
438 */
439 if ((flags & mode_mask) == non_burst_sync_pulse)
440 val = DSI_NON_BURST_SYNC_PULSES;
441 else if ((flags & mode_mask) == non_burst_sync_event)
442 val = DSI_NON_BURST_SYNC_EVENTS;
443 else
444 val = DSI_BURST_SYNC_PULSES_1;
445 writel(val, base + VID_MODE_CFG);
446
447 writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL);
448 writel(DSI_VIDEO_MODE, base + MODE_CFG);
449 }
450
dsi_mipi_init(struct dw_dsi * dsi)451 static void dsi_mipi_init(struct dw_dsi *dsi)
452 {
453 struct dsi_hw_ctx *ctx = dsi->ctx;
454 struct mipi_phy_params *phy = &dsi->phy;
455 struct drm_display_mode *mode = &dsi->cur_mode;
456 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
457 void __iomem *base = ctx->base;
458 u32 dphy_req_kHz;
459
460 /*
461 * count phy params
462 */
463 dphy_req_kHz = mode->clock * bpp / dsi->lanes;
464 dsi_get_phy_params(dphy_req_kHz, phy);
465
466 /* reset Core */
467 writel(RESET, base + PWR_UP);
468
469 /* set dsi phy params */
470 dsi_set_mipi_phy(base, phy, dsi->lanes);
471
472 /* set dsi mode timing */
473 dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format);
474
475 /* set dsi video mode */
476 dsi_set_video_mode(base, dsi->mode_flags);
477
478 /* dsi wake up */
479 writel(POWERUP, base + PWR_UP);
480
481 DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n",
482 dsi->lanes, mode->clock, phy->lane_byte_clk_kHz);
483 }
484
dsi_encoder_enable_sub(struct drm_encoder * encoder)485 static void dsi_encoder_enable_sub(struct drm_encoder *encoder)
486 {
487 struct dw_dsi *dsi = encoder_to_dsi(encoder);
488 struct dsi_hw_ctx *ctx = dsi->ctx;
489 int ret;
490
491 if (dsi->enable)
492 return;
493
494 ret = clk_prepare_enable(ctx->pclk);
495 if (ret) {
496 DRM_ERROR("fail to enable pclk: %d\n", ret);
497 return;
498 }
499
500 dsi_mipi_init(dsi);
501 }
502
dsi_encoder_phy_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)503 static enum drm_mode_status dsi_encoder_phy_mode_valid(
504 struct drm_encoder *encoder,
505 const struct drm_display_mode *mode)
506 {
507 struct dw_dsi *dsi = encoder_to_dsi(encoder);
508 struct mipi_phy_params phy;
509 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
510 u32 req_kHz, act_kHz, lane_byte_clk_kHz;
511
512 /* Calculate the lane byte clk using the adjusted mode clk */
513 memset(&phy, 0, sizeof(phy));
514 req_kHz = mode->clock * bpp / dsi->lanes;
515 act_kHz = dsi_calc_phy_rate(req_kHz, &phy);
516 lane_byte_clk_kHz = act_kHz / 8;
517
518 DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...",
519 mode->hdisplay, mode->vdisplay, bpp,
520 drm_mode_vrefresh(mode), mode->clock);
521
522 /*
523 * Make sure the adjusted mode clock and the lane byte clk
524 * have a common denominator base frequency
525 */
526 if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) {
527 DRM_DEBUG_DRIVER("OK!\n");
528 return MODE_OK;
529 }
530
531 DRM_DEBUG_DRIVER("BAD!\n");
532 return MODE_BAD;
533 }
534
dsi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)535 static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder,
536 const struct drm_display_mode *mode)
537
538 {
539 const struct drm_crtc_helper_funcs *crtc_funcs = NULL;
540 struct drm_crtc *crtc = NULL;
541 struct drm_display_mode adj_mode;
542 enum drm_mode_status ret;
543
544 /*
545 * The crtc might adjust the mode, so go through the
546 * possible crtcs (technically just one) and call
547 * mode_fixup to figure out the adjusted mode before we
548 * validate it.
549 */
550 drm_for_each_crtc(crtc, encoder->dev) {
551 /*
552 * reset adj_mode to the mode value each time,
553 * so we don't adjust the mode twice
554 */
555 drm_mode_copy(&adj_mode, mode);
556
557 crtc_funcs = crtc->helper_private;
558 if (crtc_funcs && crtc_funcs->mode_fixup)
559 if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode))
560 return MODE_BAD;
561
562 ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode);
563 if (ret != MODE_OK)
564 return ret;
565 }
566 return MODE_OK;
567 }
568
dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * mdsi)569 static int dsi_host_attach(struct mipi_dsi_host *host,
570 struct mipi_dsi_device *mdsi)
571 {
572 struct dw_dsi *dsi = host_to_dsi(host);
573
574 if (mdsi->lanes < 1 || mdsi->lanes > 4) {
575 DRM_ERROR("dsi device params invalid\n");
576 return -EINVAL;
577 }
578
579 dsi->lanes = mdsi->lanes;
580 dsi->format = mdsi->format;
581 dsi->mode_flags = mdsi->mode_flags;
582
583 return 0;
584 }
585
dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * mdsi)586 static int dsi_host_detach(struct mipi_dsi_host *host,
587 struct mipi_dsi_device *mdsi)
588 {
589 /* do nothing */
590 return 0;
591 }
592
593 static const struct mipi_dsi_host_ops dsi_host_ops = {
594 .attach = dsi_host_attach,
595 .detach = dsi_host_detach,
596 };
597
dsi_host_init(struct device * dev,struct dw_dsi * dsi)598 static int dsi_host_init(struct device *dev, struct dw_dsi *dsi)
599 {
600 struct mipi_dsi_host *host = &dsi->host;
601 int ret;
602
603 host->dev = dev;
604 host->ops = &dsi_host_ops;
605 ret = mipi_dsi_host_register(host);
606 if (ret) {
607 DRM_ERROR("failed to register dsi host\n");
608 return ret;
609 }
610
611 return 0;
612 }
613
dsi_parse_dt(struct platform_device * pdev,struct dw_dsi * dsi)614 static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi)
615 {
616 struct dsi_hw_ctx *ctx = dsi->ctx;
617 struct device_node *np = pdev->dev.of_node;
618 struct resource *res;
619 int ret;
620
621 /*
622 * Get the endpoint node. In our case, dsi has one output port1
623 * to which the external HDMI bridge is connected.
624 */
625 ret = drm_of_find_panel_or_bridge(np, 1, 0, NULL, &dsi->bridge);
626 if (ret)
627 return ret;
628
629 ctx->pclk = devm_clk_get(&pdev->dev, "pclk");
630 if (IS_ERR(ctx->pclk)) {
631 DRM_ERROR("failed to get pclk clock\n");
632 return PTR_ERR(ctx->pclk);
633 }
634
635 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
636 ctx->base = devm_ioremap_resource(&pdev->dev, res);
637 if (IS_ERR(ctx->base)) {
638 DRM_ERROR("failed to remap dsi io region\n");
639 return PTR_ERR(ctx->base);
640 }
641
642 return 0;
643 }
644
645 const struct kirin_dsi_ops kirin_dsi_620 = {
646 .version = KIRIN620_DSI,
647 .parse_dt = dsi_parse_dt,
648 .host_init = dsi_host_init,
649 .encoder_enable = dsi_encoder_enable_sub,
650 .encoder_valid = dsi_encoder_mode_valid
651 };
652
653 MODULE_AUTHOR("Xinliang Liu <xinliang.liu@linaro.org>");
654 MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@hisilicon.com>");
655 MODULE_AUTHOR("Xinwei Kong <kong.kongxinwei@hisilicon.com>");
656 MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver");
657 MODULE_LICENSE("GPL v2");
658