1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 16 17 #ifndef __HALDMOUTSRC_H__ 18 #define __HALDMOUTSRC_H__ 19 20 /*============================================================*/ 21 /*include files*/ 22 /*============================================================*/ 23 /*PHYDM header*/ 24 #include "phydm_pre_define.h" 25 #include "phydm_dig.h" 26 #include "phydm_pathdiv.h" 27 #include "phydm_antdiv.h" 28 #include "phydm_soml.h" 29 #include "phydm_smt_ant.h" 30 #include "phydm_antdect.h" 31 #include "phydm_rainfo.h" 32 #include "phydm_dynamictxpower.h" 33 #include "phydm_cfotracking.h" 34 #include "phydm_acs.h" 35 #include "phydm_adaptivity.h" 36 #include "phydm_dfs.h" 37 #include "phydm_ccx.h" 38 #include "txbf/phydm_hal_txbf_api.h" 39 #include "phydm_adc_sampling.h" 40 #include "phydm_dynamic_rx_path.h" 41 #include "phydm_psd.h" 42 #include "phydm_primary_cca.h" 43 #include "phydm_cck_pd.h" 44 #include "phydm_rssi_monitor.h" 45 #include "phydm_auto_dbg.h" 46 #include "phydm_math_lib.h" 47 #include "phydm_noisemonitor.h" 48 #include "phydm_api.h" 49 #include "phydm_pow_train.h" 50 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 51 #include "phydm_beamforming.h" 52 #endif 53 54 /*HALRF header*/ 55 #include "halrf/halrf_iqk.h" 56 #include "halrf/halrf.h" 57 #include "halrf/halrf_powertracking.h" 58 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 59 #include "halrf/halphyrf_ap.h" 60 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) 61 #include "halrf/halphyrf_ce.h" 62 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 63 #include "halrf/halphyrf_win.h" 64 #endif 65 66 extern const u16 phy_rate_table[28]; 67 68 /*============================================================*/ 69 /*Definition */ 70 /*============================================================*/ 71 72 /* Traffic load decision */ 73 #define TRAFFIC_ULTRA_LOW 1 74 #define TRAFFIC_LOW 2 75 #define TRAFFIC_MID 3 76 #define TRAFFIC_HIGH 4 77 78 #define NONE 0 79 80 #define MAX_2(_x_, _y_) (((_x_)>(_y_))? (_x_) : (_y_)) 81 #define MIN_2(_x_, _y_) (((_x_)<(_y_))? (_x_) : (_y_)) 82 83 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 84 #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ 85 #else 86 #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ 87 #endif 88 89 /*============================================================*/ 90 /*structure and define*/ 91 /*============================================================*/ 92 93 #define dm_type_by_fw 0 94 #define dm_type_by_driver 1 95 96 struct phydm_phystatus_statistic { 97 98 /*[CCK]*/ 99 u32 rssi_cck_sum; 100 u32 rssi_cck_cnt; 101 /*[OFDM]*/ 102 u32 rssi_ofdm_sum; 103 u32 rssi_ofdm_cnt; 104 u32 evm_ofdm_sum; 105 u32 snr_ofdm_sum; 106 /*[1SS]*/ 107 u32 rssi_1ss_cnt; 108 u32 rssi_1ss_sum; 109 u32 evm_1ss_sum; 110 u32 snr_1ss_sum; 111 /*[2SS]*/ 112 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 113 u32 rssi_2ss_cnt; 114 u32 rssi_2ss_sum[2]; 115 u32 evm_2ss_sum[2]; 116 u32 snr_2ss_sum[2]; 117 #endif 118 /*[3SS]*/ 119 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 120 u32 rssi_3ss_cnt; 121 u32 rssi_3ss_sum[3]; 122 u32 evm_3ss_sum[3]; 123 u32 snr_3ss_sum[3]; 124 #endif 125 /*[4SS]*/ 126 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 127 u32 rssi_4ss_cnt; 128 u32 rssi_4ss_sum[4]; 129 u32 evm_4ss_sum[4]; 130 u32 snr_4ss_sum[4]; 131 #endif 132 }; 133 134 struct phydm_phystatus_avg { 135 136 /*[CCK]*/ 137 u8 rssi_cck_avg; 138 /*[OFDM]*/ 139 u8 rssi_ofdm_avg; 140 u8 evm_ofdm_avg; 141 u8 snr_ofdm_avg; 142 /*[1SS]*/ 143 u8 rssi_1ss_avg; 144 u8 evm_1ss_avg; 145 u8 snr_1ss_avg; 146 /*[2SS]*/ 147 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 148 u8 rssi_2ss_avg[2]; 149 u8 evm_2ss_avg[2]; 150 u8 snr_2ss_avg[2]; 151 #endif 152 /*[3SS]*/ 153 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 154 u8 rssi_3ss_avg[3]; 155 u8 evm_3ss_avg[3]; 156 u8 snr_3ss_avg[3]; 157 #endif 158 /*[4SS]*/ 159 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 160 u8 rssi_4ss_avg[4]; 161 u8 evm_4ss_avg[4]; 162 u8 snr_4ss_avg[4]; 163 #endif 164 }; 165 166 struct _odm_phy_dbg_info_ { 167 /*ODM Write,debug info*/ 168 s8 rx_snr_db[4]; 169 u32 num_qry_phy_status; 170 u32 num_qry_phy_status_cck; 171 u32 num_qry_phy_status_ofdm; 172 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 173 u32 num_qry_mu_pkt; 174 u32 num_qry_bf_pkt; 175 u32 num_qry_mu_vht_pkt[40]; 176 boolean is_ldpc_pkt; 177 boolean is_stbc_pkt; 178 u8 num_of_ppdu[4]; 179 u8 gid_num[4]; 180 #endif 181 u8 num_qry_beacon_pkt; 182 /* Others */ 183 s32 rx_evm[4]; 184 185 u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; 186 u16 num_qry_ht_pkt[HT_RATE_NUM]; 187 u8 ht_pkt_not_zero; 188 #if ODM_IC_11AC_SERIES_SUPPORT 189 u16 num_qry_vht_pkt[VHT_RATE_NUM]; 190 u8 vht_pkt_not_zero; 191 #endif 192 struct phydm_phystatus_statistic phystatus_statistic_info; 193 struct phydm_phystatus_avg phystatus_statistic_avg; 194 }; 195 196 enum odm_cmninfo_e { 197 /*Fixed value*/ 198 /*-----------HOOK BEFORE REG INIT-----------*/ 199 ODM_CMNINFO_PLATFORM = 0, 200 ODM_CMNINFO_ABILITY, 201 ODM_CMNINFO_INTERFACE, 202 ODM_CMNINFO_MP_TEST_CHIP, 203 ODM_CMNINFO_IC_TYPE, 204 ODM_CMNINFO_CUT_VER, 205 ODM_CMNINFO_FAB_VER, 206 ODM_CMNINFO_RF_TYPE, 207 ODM_CMNINFO_RFE_TYPE, 208 ODM_CMNINFO_DPK_EN, 209 ODM_CMNINFO_BOARD_TYPE, 210 ODM_CMNINFO_PACKAGE_TYPE, 211 ODM_CMNINFO_EXT_LNA, 212 ODM_CMNINFO_5G_EXT_LNA, 213 ODM_CMNINFO_EXT_PA, 214 ODM_CMNINFO_5G_EXT_PA, 215 ODM_CMNINFO_GPA, 216 ODM_CMNINFO_APA, 217 ODM_CMNINFO_GLNA, 218 ODM_CMNINFO_ALNA, 219 ODM_CMNINFO_EXT_TRSW, 220 ODM_CMNINFO_EXT_LNA_GAIN, 221 ODM_CMNINFO_PATCH_ID, 222 ODM_CMNINFO_BINHCT_TEST, 223 ODM_CMNINFO_BWIFI_TEST, 224 ODM_CMNINFO_SMART_CONCURRENT, 225 ODM_CMNINFO_CONFIG_BB_RF, 226 ODM_CMNINFO_DOMAIN_CODE_2G, 227 ODM_CMNINFO_DOMAIN_CODE_5G, 228 ODM_CMNINFO_IQKPAOFF, 229 ODM_CMNINFO_HUBUSBMODE, 230 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 231 ODM_CMNINFO_TX_TP, 232 ODM_CMNINFO_RX_TP, 233 ODM_CMNINFO_SOUNDING_SEQ, 234 ODM_CMNINFO_REGRFKFREEENABLE, 235 ODM_CMNINFO_RFKFREEENABLE, 236 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, 237 ODM_CMNINFO_EFUSE0X3D8, 238 ODM_CMNINFO_EFUSE0X3D7, 239 ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, 240 ODM_CMNINFO_ADVANCE_OTA, 241 ODM_CMNINFO_HP_HWID, 242 /*-----------HOOK BEFORE REG INIT-----------*/ 243 244 /*Dynamic value:*/ 245 246 /*--------- POINTER REFERENCE-----------*/ 247 ODM_CMNINFO_TX_UNI, 248 ODM_CMNINFO_RX_UNI, 249 ODM_CMNINFO_BAND, 250 ODM_CMNINFO_SEC_CHNL_OFFSET, 251 ODM_CMNINFO_SEC_MODE, 252 ODM_CMNINFO_BW, 253 ODM_CMNINFO_CHNL, 254 ODM_CMNINFO_FORCED_RATE, 255 ODM_CMNINFO_ANT_DIV, 256 ODM_CMNINFO_ADAPTIVITY, 257 ODM_CMNINFO_SCAN, 258 ODM_CMNINFO_POWER_SAVING, 259 ODM_CMNINFO_ONE_PATH_CCA, 260 ODM_CMNINFO_DRV_STOP, 261 ODM_CMNINFO_PNP_IN, 262 ODM_CMNINFO_INIT_ON, 263 ODM_CMNINFO_ANT_TEST, 264 ODM_CMNINFO_NET_CLOSED, 265 ODM_CMNINFO_P2P_LINK, 266 ODM_CMNINFO_FCS_MODE, 267 ODM_CMNINFO_IS1ANTENNA, 268 ODM_CMNINFO_RFDEFAULTPATH, 269 ODM_CMNINFO_DFS_MASTER_ENABLE, 270 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, 271 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, 272 ODM_CMNINFO_SOFT_AP_MODE, 273 ODM_CMNINFO_MP_MODE, 274 ODM_CMNINFO_INTERRUPT_MASK, 275 ODM_CMNINFO_BB_OPERATION_MODE, 276 /*--------- POINTER REFERENCE-----------*/ 277 278 /*------------CALL BY VALUE-------------*/ 279 ODM_CMNINFO_WIFI_DIRECT, 280 ODM_CMNINFO_WIFI_DISPLAY, 281 ODM_CMNINFO_LINK_IN_PROGRESS, 282 ODM_CMNINFO_LINK, 283 ODM_CMNINFO_CMW500LINK, 284 ODM_CMNINFO_STATION_STATE, 285 ODM_CMNINFO_RSSI_MIN, 286 ODM_CMNINFO_RSSI_MIN_BY_PATH, 287 ODM_CMNINFO_DBG_COMP, 288 ODM_CMNINFO_DBG_LEVEL, 289 ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ 290 ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ 291 ODM_CMNINFO_RF_ANTENNA_TYPE, 292 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 293 ODM_CMNINFO_BE_FIX_TX_ANT, 294 ODM_CMNINFO_BT_ENABLED, 295 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 296 ODM_CMNINFO_BT_HS_RSSI, 297 ODM_CMNINFO_BT_OPERATION, 298 ODM_CMNINFO_BT_LIMITED_DIG, 299 ODM_CMNINFO_AP_TOTAL_NUM, 300 ODM_CMNINFO_POWER_TRAINING, 301 ODM_CMNINFO_DFS_REGION_DOMAIN, 302 /*------------CALL BY VALUE-------------*/ 303 304 /*Dynamic ptr array hook itms.*/ 305 ODM_CMNINFO_STA_STATUS, 306 ODM_CMNINFO_MAX, 307 308 }; 309 310 enum phydm_rfe_bb_source_sel { 311 PAPE_2G = 0, 312 PAPE_5G = 1, 313 LNA0N_2G = 2, 314 LNAON_5G = 3, 315 TRSW = 4, 316 TRSW_B = 5, 317 GNT_BT = 6, 318 ZERO = 7, 319 ANTSEL_0 = 8, 320 ANTSEL_1 = 9, 321 ANTSEL_2 = 0xa, 322 ANTSEL_3 = 0xb, 323 ANTSEL_4 = 0xc, 324 ANTSEL_5 = 0xd, 325 ANTSEL_6 = 0xe, 326 ANTSEL_7 = 0xf 327 }; 328 329 enum phydm_info_query_e { 330 PHYDM_INFO_FA_OFDM, 331 PHYDM_INFO_FA_CCK, 332 PHYDM_INFO_FA_TOTAL, 333 PHYDM_INFO_CCA_OFDM, 334 PHYDM_INFO_CCA_CCK, 335 PHYDM_INFO_CCA_ALL, 336 PHYDM_INFO_CRC32_OK_VHT, 337 PHYDM_INFO_CRC32_OK_HT, 338 PHYDM_INFO_CRC32_OK_LEGACY, 339 PHYDM_INFO_CRC32_OK_CCK, 340 PHYDM_INFO_CRC32_ERROR_VHT, 341 PHYDM_INFO_CRC32_ERROR_HT, 342 PHYDM_INFO_CRC32_ERROR_LEGACY, 343 PHYDM_INFO_CRC32_ERROR_CCK, 344 PHYDM_INFO_EDCCA_FLAG, 345 PHYDM_INFO_OFDM_ENABLE, 346 PHYDM_INFO_CCK_ENABLE, 347 PHYDM_INFO_CRC32_OK_HT_AGG, 348 PHYDM_INFO_CRC32_ERROR_HT_AGG, 349 PHYDM_INFO_DBG_PORT_0, 350 PHYDM_INFO_CURR_IGI, 351 PHYDM_INFO_RSSI_MIN, 352 PHYDM_INFO_RSSI_MAX, 353 PHYDM_INFO_CLM_RATIO, 354 PHYDM_INFO_NHM_RATIO, 355 }; 356 357 enum phydm_api_e { 358 359 PHYDM_API_NBI = 1, 360 PHYDM_API_CSI_MASK, 361 362 }; 363 364 enum phydm_func_idx_e { /*F_XXX = PHYDM XXX function*/ 365 366 F00_DIG = 0, 367 F01_RA_MASK = 1, 368 F02_DYN_TXPWR = 2, 369 F03_FA_CNT = 3, 370 F04_RSSI_MNTR = 4, 371 F05_CCK_PD = 5, 372 F06_ANT_DIV = 6, 373 F07_SMT_ANT = 7, 374 F08_PWR_TRAIN = 8, 375 F09_RA = 9, 376 F10_PATH_DIV = 10, 377 F11_DFS = 11, 378 F12_DYN_ARFR = 12, 379 F13_ADPTVTY = 13, 380 F14_CFO_TRK = 14, 381 F15_ENV_MNTR = 15, 382 F16_PRI_CCA = 16, 383 F17_ADPTV_SOML = 17, 384 F18_LNA_SAT_CHK = 18, 385 /*BIT18*/ 386 /*BIT19*/ 387 F20_DYN_RX_PATH = 20 388 }; 389 390 /*=[PHYDM supportability]==========================================*/ 391 enum odm_ability_e { 392 393 ODM_BB_DIG = BIT(F00_DIG), 394 ODM_BB_RA_MASK = BIT(F01_RA_MASK), 395 ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), 396 ODM_BB_FA_CNT = BIT(F03_FA_CNT), 397 ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), 398 ODM_BB_CCK_PD = BIT(F05_CCK_PD), 399 ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), 400 ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), 401 ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), 402 ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), 403 ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), 404 ODM_BB_DFS = BIT(F11_DFS), 405 ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), 406 ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), 407 ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), 408 ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), 409 ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), 410 ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), 411 ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 412 /*BIT19*/ 413 ODM_BB_DYNAMIC_RX_PATH = BIT(F20_DYN_RX_PATH) 414 }; 415 416 /*=[PHYDM Debug Component]=====================================*/ 417 enum phydm_dbg_comp { 418 /*BB Driver Functions*/ 419 DBG_DIG = BIT(F00_DIG), 420 DBG_RA_MASK = BIT(F01_RA_MASK), 421 DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), 422 DBG_FA_CNT = BIT(F03_FA_CNT), 423 DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), 424 DBG_CCKPD = BIT(F05_CCK_PD), 425 DBG_ANT_DIV = BIT(F06_ANT_DIV), 426 DBG_SMT_ANT = BIT(F07_SMT_ANT), 427 DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), 428 DBG_RA = BIT(F09_RA), 429 DBG_PATH_DIV = BIT(F10_PATH_DIV), 430 DBG_DFS = BIT(F11_DFS), 431 DBG_DYN_ARFR = BIT(F12_DYN_ARFR), 432 DBG_ADPTVTY = BIT(F13_ADPTVTY), 433 DBG_CFO_TRK = BIT(F14_CFO_TRK), 434 DBG_ENV_MNTR = BIT(F15_ENV_MNTR), 435 DBG_PRI_CCA = BIT(F16_PRI_CCA), 436 DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), 437 DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 438 /*BIT19*/ 439 DBG_DYN_RX_PATH = BIT(F20_DYN_RX_PATH), 440 /*Neet to re-arrange*/ 441 DBG_TMP = BIT(21), 442 DBG_FW_TRACE = BIT(22), 443 DBG_TXBF = BIT(23), 444 DBG_COMMON_FLOW = BIT(24), 445 ODM_COMP_TX_PWR_TRACK = BIT(25), 446 ODM_COMP_CALIBRATION = BIT(26), 447 ODM_COMP_MP = BIT(27), 448 ODM_PHY_CONFIG = BIT(28), 449 ODM_COMP_INIT = BIT(29), 450 ODM_COMP_COMMON = BIT(30), 451 ODM_COMP_API = BIT(31) 452 }; 453 454 /*=========================================================*/ 455 456 /*ODM_CMNINFO_ONE_PATH_CCA*/ 457 enum odm_cca_path_e { 458 ODM_CCA_2R = 0, 459 ODM_CCA_1R_A = 1, 460 ODM_CCA_1R_B = 2, 461 }; 462 463 enum phy_reg_pg_type { 464 PHY_REG_PG_RELATIVE_VALUE = 0, 465 PHY_REG_PG_EXACT_VALUE = 1 466 }; 467 468 enum phydm_offload_ability { 469 PHYDM_PHY_PARAM_OFFLOAD = BIT(0), 470 PHYDM_RF_IQK_OFFLOAD = BIT(1), 471 }; 472 473 struct phydm_pause_lv { 474 s8 lv_dig; 475 s8 lv_cckpd; 476 s8 lv_antdiv; 477 s8 lv_adapt; 478 }; 479 480 struct phydm_func_poiner { 481 void (*pause_phydm_handler)(void *p_dm_void, u32 *val_buf, u8 val_len); 482 }; 483 484 struct pkt_process_info { 485 u8 phystatus_smp_mode_en; /*send phystatus every sampling time*/ 486 u8 pre_ppdu_cnt; 487 u8 lna_idx; 488 u8 vga_idx; 489 }; 490 491 #ifdef ODM_CONFIG_BT_COEXIST 492 struct phydm_bt_info { 493 boolean is_bt_enabled; /*BT is enabled*/ 494 boolean is_bt_connect_process; /*BT HS is under connection progress.*/ 495 u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/ 496 boolean is_bt_hs_operation; /*BT HS mode is under progress*/ 497 boolean is_bt_limited_dig; /*BT is busy.*/ 498 }; 499 #endif 500 501 struct phydm_iot_center { 502 boolean is_linked_cmw500; 503 u8 win_patch_id; /*Customer ID*/ 504 u32 phydm_patch_id; 505 506 }; 507 508 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 509 #if (RT_PLATFORM != PLATFORM_LINUX) 510 typedef 511 #endif 512 513 struct PHY_DM_STRUCT 514 #else/*for AP, CE Team*/ 515 struct PHY_DM_STRUCT 516 #endif 517 { 518 /*Add for different team use temporarily*/ 519 struct _ADAPTER *adapter; /*For CE/NIC team*/ 520 struct rtl8192cd_priv *priv; /*For AP team*/ 521 /*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/ 522 boolean odm_ready; 523 enum phy_reg_pg_type phy_reg_pg_value_type; 524 u8 phy_reg_pg_version; 525 u64 support_ability; /*PHYDM function Supportability*/ 526 u64 pause_ability; /*PHYDM function pause Supportability*/ 527 u64 debug_components; 528 u32 fw_debug_components; 529 u32 debug_level; 530 u32 num_qry_phy_status_all; /*CCK + OFDM*/ 531 u32 last_num_qry_phy_status_all; 532 u32 rx_pwdb_ave; 533 boolean is_init_hw_info_by_rfe; 534 535 /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 536 boolean is_cck_high_power; 537 u8 rf_path_rx_enable; 538 /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 539 540 /* COMMON INFORMATION */ 541 542 /*Init value*/ 543 /*-----------HOOK BEFORE REG INIT-----------*/ 544 545 u8 support_platform;/*PHYDM Platform info WIN/AP/CE = 1/2/3 */ 546 u8 normal_rx_path; 547 u8 support_interface;/*PHYDM PCIE/USB/SDIO = 1/2/3*/ 548 u32 support_ic_type; /*PHYDM supported IC*/ 549 u8 cut_version; /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ 550 u8 fab_version; /*Fab version TSMC/UMC = 0/1*/ 551 u8 rf_type; /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ 552 u8 rfe_type; 553 u8 board_type; 554 u8 package_type; 555 u16 type_glna; 556 u16 type_gpa; 557 u16 type_alna; 558 u16 type_apa; 559 u8 ext_lna; /*with 2G external LNA NO/Yes = 0/1*/ 560 u8 ext_lna_5g; /*with 5G external LNA NO/Yes = 0/1*/ 561 u8 ext_pa; /*with 2G external PNA NO/Yes = 0/1*/ 562 u8 ext_pa_5g; /*with 5G external PNA NO/Yes = 0/1*/ 563 u8 efuse0x3d7; /*with Efuse number*/ 564 u8 efuse0x3d8; 565 u8 ext_trsw; /*with external TRSW NO/Yes = 0/1*/ 566 u8 ext_lna_gain; /*gain of external lna*/ 567 boolean is_in_hct_test; 568 u8 wifi_test; 569 boolean is_dual_mac_smart_concurrent; 570 u32 bk_support_ability; /*SD4 only*/ 571 u8 with_extenal_ant_switch; 572 /*cck agc relative*/ 573 boolean cck_new_agc; 574 s8 cck_lna_gain_table[8]; 575 /*-------------------------------------*/ 576 u8 phydm_period; 577 u32 phydm_sys_up_time; 578 u8 num_rf_path; /*ex: 8821C=1, 8192E=2, 8814B=4*/ 579 u32 soft_ap_special_setting; 580 s8 s8_dummy; 581 u8 u8_dummy; 582 u16 u16_dummy; 583 u32 u32_dummy; 584 u8 rfe_hwsetting_band; 585 u8 p_advance_ota; 586 boolean hp_hw_id; 587 boolean BOOLEAN_temp; 588 boolean is_dfs_band; 589 u8 is_receiver_blocking_en; 590 u16 fw_offload_ability; 591 /*-----------HOOK BEFORE REG INIT-----------*/ 592 /*===========================================================*/ 593 /*====[ CALL BY Reference ]=========================================*/ 594 /*===========================================================*/ 595 596 u64 *p_num_tx_bytes_unicast; /*TX Unicast byte count*/ 597 u64 *p_num_rx_bytes_unicast; /*RX Unicast byte count*/ 598 u8 *p_band_type; /*Frequence band 2.4G/5G = 0/1*/ 599 u8 *p_sec_ch_offset; /*Secondary channel offset don't_care/below/above = 0/1/2*/ 600 u8 *p_security; /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/ 601 u8 *p_band_width; /*BW info 20M/40M/80M = 0/1/2*/ 602 u8 *p_channel; /*central channel number*/ 603 boolean *p_is_scan_in_process; /*Common info for status*/ 604 boolean *p_is_power_saving; 605 u8 *p_one_path_cca; /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path_e.*/ 606 u8 *p_antenna_test; 607 boolean *p_is_net_closed; 608 boolean *p_is_fcs_mode_enable; 609 /*--------- For 8723B IQK-------------------------------------*/ 610 boolean *p_is_1_antenna; 611 u8 *p_rf_default_path; /* 0:S1, 1:S0 */ 612 /*-----------------------------------------------------------*/ 613 614 u16 *p_forced_data_rate; 615 u8 *p_enable_antdiv; 616 u8 *p_enable_adaptivity; 617 u8 *hub_usb_mode; /*1: USB 2.0, 2: USB 3.0*/ 618 boolean *p_is_fw_dw_rsvd_page_in_progress; 619 u32 *p_current_tx_tp; 620 u32 *p_current_rx_tp; 621 u8 *p_sounding_seq; 622 u32 *p_soft_ap_mode; 623 u8 *p_mp_mode; 624 u32 *p_interrupt_mask; 625 u8 *p_bb_op_mode; 626 /*===========================================================*/ 627 /*====[ CALL BY VALUE ]===========================================*/ 628 /*===========================================================*/ 629 630 u8 disable_phydm_watchdog; 631 boolean is_link_in_process; 632 boolean is_wifi_direct; 633 boolean is_wifi_display; 634 boolean is_linked; 635 boolean bsta_state; 636 u8 rssi_min; 637 u8 pre_rssi_min; 638 u8 rssi_max; 639 u8 rssi_min_by_path; 640 boolean is_mp_chip; 641 boolean is_one_entry_only; 642 u32 one_entry_macid; 643 u32 one_entry_tp; 644 u32 pre_one_entry_tp; 645 u8 pre_number_linked_client; 646 u8 number_linked_client; 647 u8 pre_number_active_client; 648 u8 number_active_client; 649 boolean is_disable_phy_api; 650 u8 RSSI_A; 651 u8 RSSI_B; 652 u8 RSSI_C; 653 u8 RSSI_D; 654 u64 RSSI_TRSW; 655 u64 RSSI_TRSW_H; 656 u64 RSSI_TRSW_L; 657 u64 RSSI_TRSW_iso; 658 u8 tx_ant_status; 659 u8 rx_ant_status; 660 u8 cck_lna_idx; 661 u8 cck_vga_idx; 662 u8 curr_station_id; 663 u8 ofdm_agc_idx[4]; 664 u8 rx_rate; 665 u8 rate_ss; 666 u8 tx_rate; 667 u8 linked_interval; 668 u8 pre_channel; 669 u32 txagc_offset_value_a; 670 boolean is_txagc_offset_positive_a; 671 u32 txagc_offset_value_b; 672 boolean is_txagc_offset_positive_b; 673 /*[traffic]*/ 674 u8 traffic_load; 675 u8 pre_traffic_load; 676 u32 tx_tp; /*Mbps*/ 677 u32 rx_tp; /*Mbps*/ 678 u32 total_tp;/*Mbps*/ 679 u8 txrx_state_all; /*0: tx, 1:rx, 2:bi-direction*/ 680 u64 cur_tx_ok_cnt; 681 u64 cur_rx_ok_cnt; 682 u64 last_tx_ok_cnt; 683 u64 last_rx_ok_cnt; 684 u16 consecutive_idlel_time; /*unit: second*/ 685 /*---------------------------*/ 686 boolean is_bb_swing_offset_positive_a; 687 boolean is_bb_swing_offset_positive_b; 688 689 /*[DIG]*/ 690 boolean MPDIG_2G; /*off MPDIG*/ 691 u8 times_2g; /*for MP DIG*/ 692 693 /*[TDMA-DIG]*/ 694 u8 tdma_dig_timer_ms; 695 u8 tdma_dig_state_number; 696 u8 tdma_dig_low_upper_bond; 697 u8 fix_expire_to_zero; 698 boolean original_dig_restore; 699 /*---------------------------*/ 700 701 /*[AntDiv]*/ 702 u8 ant_div_type; 703 u8 antdiv_rssi; 704 u8 fat_comb_a; 705 u8 fat_comb_b; 706 u8 antdiv_intvl; 707 u8 ant_type; 708 u8 pre_ant_type; 709 u8 antdiv_period; 710 u8 evm_antdiv_period; 711 u8 antdiv_select; 712 u8 antdiv_train_num;/*training time for each antenna in EVM method*/ 713 u8 stop_antdiv_rssi_th; 714 u16 stop_antdiv_tp_diff_th; 715 u16 stop_antdiv_tp_th; 716 u8 antdiv_tp_period; 717 u16 tp_active_th; 718 u8 tp_active_occur; 719 u8 path_select; 720 u8 antdiv_evm_en; 721 u8 bdc_holdstate; 722 /*---------------------------*/ 723 724 u8 ndpa_period; 725 boolean h2c_rarpt_connect; 726 boolean cck_agc_report_type; 727 u8 print_agc; 728 u8 la_mode; 729 /*---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ 730 u8 current_rf_set_8821c; 731 u8 default_rf_set_8821c; 732 u8 current_ant_num_8821c; 733 u8 default_ant_num_8821c; 734 u8 rfe_type_21c; 735 /*-----------------------------------------------------------*/ 736 /*---For Adaptivtiy---------------------------------------------*/ 737 s8 TH_L2H_default; 738 s8 th_edcca_hl_diff_default; 739 s8 th_l2h_ini; 740 s8 th_edcca_hl_diff; 741 s8 th_l2h_ini_mode2; 742 s8 th_edcca_hl_diff_mode2; 743 boolean carrier_sense_enable; 744 boolean adaptivity_flag; /*Limit IGI upper bound for Adaptivity*/ 745 u8 dc_backoff; 746 boolean adaptivity_enable; 747 u8 ap_total_num; 748 boolean edcca_enable; 749 u8 odm_regulation_2_4g; 750 u8 odm_regulation_5g; 751 /*-----------------------------------------------------------*/ 752 753 u8 pre_dbg_priority; 754 u8 nbi_set_result; 755 u8 c2h_cmd_start; 756 u8 fw_debug_trace[60]; 757 u8 pre_c2h_seq; 758 boolean fw_buff_is_enpty; 759 u32 data_frame_num; 760 761 /*--- for noise detection ---------------------------------------*/ 762 boolean is_noisy_state; 763 boolean noisy_decision; /*b_noisy*/ 764 boolean pre_b_noisy; 765 u32 noisy_decision_smooth; 766 u8 lna_sat_chk_cnt; 767 u8 lna_sat_chk_duty_cycle; 768 u32 lna_sat_chk_period_ms; 769 boolean is_disable_lna_sat_chk; 770 boolean is_disable_gain_table_switch; 771 /*-----------------------------------------------------------*/ 772 773 boolean is_disable_dym_ecs; 774 boolean is_disable_dym_ant_weighting; 775 struct sta_info *p_odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];/*_ODM_STA_INFO, 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/ 776 struct cmn_sta_info *p_phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; 777 u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; 778 779 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 780 s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM]; 781 #endif 782 783 #if (RATE_ADAPTIVE_SUPPORT == 1) 784 u16 currmin_rpt_time; 785 struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; 786 /*Use mac_id as array index. STA mac_id=0, VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ 787 #endif 788 boolean ra_support88e; /*2012/02/14 MH Add to share 88E ra with other SW team.We need to colelct all support abilit to a proper area.*/ 789 boolean *p_is_driver_stopped; 790 boolean *p_is_driver_is_going_to_pnp_set_power_sleep; 791 boolean *pinit_adpt_in_progress; 792 boolean is_user_assign_level; 793 u8 RSSI_BT; /*come from BT*/ 794 795 /*---PSD Relative ---------------------------------------------*/ 796 boolean is_psd_in_process; 797 boolean is_psd_active; 798 /*-----------------------------------------------------------*/ 799 800 boolean bsomlenabled; /* for dynamic SoML control */ 801 boolean bhtstfdisabled; /* for dynamic HTSTF gain control */ 802 boolean disrxhpsoml; /* for dynamic RxHP control with SoML on/off */ 803 u32 n_iqk_cnt; 804 u32 n_iqk_ok_cnt; 805 u32 n_iqk_fail_cnt; 806 807 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 808 boolean config_bbrf; 809 #endif 810 boolean is_disable_power_training; 811 u8 dynamic_tx_high_power_lvl; 812 u8 last_dtp_lvl; 813 u32 tx_agc_ofdm_18_6; 814 u8 rx_pkt_type; 815 816 #ifdef CONFIG_PHYDM_DFS_MASTER 817 u8 dfs_region_domain; 818 u8 *dfs_master_enabled; 819 /*---phydm_radar_detect_with_dbg_parm start --------------------*/ 820 u8 radar_detect_dbg_parm_en; 821 u32 radar_detect_reg_918; 822 u32 radar_detect_reg_91c; 823 u32 radar_detect_reg_920; 824 u32 radar_detect_reg_924; 825 /*-----------------------------------------------------------*/ 826 #endif 827 828 /*=== PHYDM Timer ========================================== (start)*/ 829 830 struct timer_list mpt_dig_timer; /*MPT DIG timer*/ 831 struct timer_list path_div_switch_timer; 832 struct timer_list cck_path_diversity_timer; /*2011.09.27 add for path Diversity*/ 833 struct timer_list fast_ant_training_timer; 834 #ifdef ODM_EVM_ENHANCE_ANTDIV 835 struct timer_list evm_fast_ant_training_timer; 836 #endif 837 struct timer_list sbdcnt_timer; 838 839 840 /*=== PHYDM Workitem ======================================= (start)*/ 841 842 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 843 #if USE_WORKITEM 844 RT_WORK_ITEM path_div_switch_workitem; 845 RT_WORK_ITEM cck_path_diversity_workitem; 846 RT_WORK_ITEM fast_ant_training_workitem; 847 RT_WORK_ITEM ra_rpt_workitem; 848 RT_WORK_ITEM sbdcnt_workitem; 849 #endif 850 #endif 851 852 853 /*=== PHYDM Structure ======================================== (start)*/ 854 struct phydm_func_poiner phydm_func_handler; 855 struct phydm_iot_center iot_table; 856 857 #ifdef ODM_CONFIG_BT_COEXIST 858 struct phydm_bt_info bt_info_table; 859 #endif 860 861 struct pkt_process_info pkt_proc_struct; 862 struct phydm_adaptivity_struct adaptivity; 863 struct _DFS_STATISTICS dfs; 864 865 struct _ODM_NOISE_MONITOR_ noise_level; 866 867 struct _odm_phy_dbg_info_ phy_dbg_info; 868 869 #ifdef CONFIG_ADAPTIVE_SOML 870 struct adaptive_soml dm_soml_table; 871 #endif 872 873 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 874 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 875 struct _BF_DIV_COEX_ dm_bdc_table; 876 #endif 877 878 #if (defined(CONFIG_HL_SMART_ANTENNA)) 879 struct smt_ant_honbo dm_sat_table; 880 #endif 881 #endif 882 883 #if (defined(CONFIG_SMART_ANTENNA)) 884 struct smt_ant smtant_table; 885 #endif 886 887 struct phydm_fat_struct dm_fat_table; 888 struct phydm_dig_struct dm_dig_table; 889 struct phydm_lna_sat_info_struct dm_lna_sat_info; 890 891 #ifdef PHYDM_SUPPORT_CCKPD 892 struct phydm_cckpd_struct dm_cckpd_table; 893 #endif 894 895 #ifdef PHYDM_PRIMARY_CCA 896 struct phydm_pricca_struct dm_pri_cca; 897 #endif 898 899 struct _rate_adaptive_table_ dm_ra_table; 900 struct phydm_fa_struct false_alm_cnt; 901 #ifdef PHYDM_TDMA_DIG_SUPPORT 902 struct phydm_fa_acc_struct false_alm_cnt_acc; 903 #endif 904 struct _sw_antenna_switch_ dm_swat_table; 905 struct phydm_cfo_track_struct dm_cfo_track; 906 struct _ACS_ dm_acs; 907 struct _CCX_INFO dm_ccx_info; 908 struct _hal_rf_ rf_table; /*for HALRF function*/ 909 struct odm_rf_calibration_structure rf_calibrate_info; 910 struct odm_power_trim_data power_trim_data; 911 #if (RTL8822B_SUPPORT == 1) 912 struct drp_rtl8822b_struct phydm_rtl8822b; 913 #endif 914 915 #ifdef CONFIG_PSD_TOOL 916 struct _PHYDM_PSD_ dm_psd_table; 917 #endif 918 919 #if (PHYDM_LA_MODE_SUPPORT == 1) 920 struct _RT_ADCSMP adcsmp; 921 #endif 922 923 #ifdef CONFIG_DYNAMIC_RX_PATH 924 struct _DYNAMIC_RX_PATH_ dm_drp_table; 925 #endif 926 927 struct _IQK_INFORMATION IQK_info; 928 929 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 930 struct _path_div_parameter_define_ path_iqk; 931 #endif 932 933 #if (defined(CONFIG_PATH_DIVERSITY)) 934 struct _ODM_PATH_DIVERSITY_ dm_path_div; 935 #endif 936 937 #if (defined(CONFIG_ANT_DETECTION)) 938 struct _ANT_DETECTED_INFO ant_detected_info; /* Antenna detected information for RSSI tool*/ 939 #endif 940 941 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 942 #if (BEAMFORMING_SUPPORT == 1) 943 struct _RT_BEAMFORMING_INFO beamforming_info; 944 #endif 945 #endif 946 #ifdef PHYDM_AUTO_DEGBUG 947 struct phydm_auto_dbg_struc auto_dbg_table; 948 #endif 949 950 struct phydm_pause_lv pause_lv_table; 951 struct phydm_api_stuc api_table; 952 #ifdef PHYDM_POWER_TRAINING_SUPPORT 953 struct phydm_pow_train_stuc pow_train_table; 954 #endif 955 /*==========================================================*/ 956 957 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 958 959 #if (RT_PLATFORM != PLATFORM_LINUX) 960 }PHY_DM_STRUCT; /*DM_Dynamic_Mechanism_Structure*/ 961 #else 962 }; 963 #endif 964 965 #else /*for AP,CE Team*/ 966 }; 967 #endif 968 969 enum phydm_adv_ota { 970 PHYDM_PATHB_1RCCA = BIT(0), 971 PHYDM_HP_OTA_SETTING_A = BIT(1), 972 PHYDM_HP_OTA_SETTING_B = BIT(2), 973 PHYDM_ASUS_OTA_SETTING = BIT(3), 974 PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), 975 PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), 976 977 }; 978 979 enum phydm_bb_op_mode { 980 PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ 981 PHYDM_BALANCE_MODE = 1, /*Service more than one device*/ 982 }; 983 984 enum phydm_structure_type { 985 PHYDM_FALSEALMCNT, 986 PHYDM_CFOTRACK, 987 PHYDM_ADAPTIVITY, 988 PHYDM_DFS, 989 PHYDM_ROMINFO, 990 991 }; 992 993 enum odm_bb_config_type { 994 CONFIG_BB_PHY_REG, 995 CONFIG_BB_AGC_TAB, 996 CONFIG_BB_AGC_TAB_2G, 997 CONFIG_BB_AGC_TAB_5G, 998 CONFIG_BB_PHY_REG_PG, 999 CONFIG_BB_PHY_REG_MP, 1000 CONFIG_BB_AGC_TAB_DIFF, 1001 }; 1002 1003 enum odm_rf_config_type { 1004 CONFIG_RF_RADIO, 1005 CONFIG_RF_TXPWR_LMT, 1006 }; 1007 1008 enum odm_fw_config_type { 1009 CONFIG_FW_NIC, 1010 CONFIG_FW_NIC_2, 1011 CONFIG_FW_AP, 1012 CONFIG_FW_AP_2, 1013 CONFIG_FW_MP, 1014 CONFIG_FW_WOWLAN, 1015 CONFIG_FW_WOWLAN_2, 1016 CONFIG_FW_AP_WOWLAN, 1017 CONFIG_FW_BT, 1018 }; 1019 1020 /*status code*/ 1021 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1022 enum rt_status { 1023 RT_STATUS_SUCCESS, 1024 RT_STATUS_FAILURE, 1025 RT_STATUS_PENDING, 1026 RT_STATUS_RESOURCE, 1027 RT_STATUS_INVALID_CONTEXT, 1028 RT_STATUS_INVALID_PARAMETER, 1029 RT_STATUS_NOT_SUPPORT, 1030 RT_STATUS_OS_API_FAILED, 1031 }; 1032 #endif /*end of enum rt_status definition*/ 1033 1034 1035 /*===========================================================*/ 1036 /*AGC RX High Power mode*/ 1037 /*===========================================================*/ 1038 #define lna_low_gain_1 0x64 1039 #define lna_low_gain_2 0x5A 1040 #define lna_low_gain_3 0x58 1041 1042 /*Add for cmn sta info*/ 1043 1044 #define is_sta_active(p_sta) ((p_sta) && (p_sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) 1045 1046 void 1047 phydm_watchdog_lps( 1048 struct PHY_DM_STRUCT *p_dm 1049 ); 1050 1051 void 1052 phydm_watchdog_lps_32k( 1053 struct PHY_DM_STRUCT *p_dm 1054 ); 1055 1056 void 1057 phydm_txcurrentcalibration( 1058 struct PHY_DM_STRUCT *p_dm 1059 ); 1060 1061 void 1062 phydm_dm_early_init( 1063 struct PHY_DM_STRUCT *p_dm 1064 ); 1065 1066 void 1067 odm_dm_init( 1068 struct PHY_DM_STRUCT *p_dm 1069 ); 1070 1071 void 1072 odm_dm_reset( 1073 struct PHY_DM_STRUCT *p_dm 1074 ); 1075 1076 void 1077 phydm_fwoffload_ability_init( 1078 struct PHY_DM_STRUCT *p_dm, 1079 enum phydm_offload_ability offload_ability 1080 ); 1081 1082 void 1083 phydm_fwoffload_ability_clear( 1084 struct PHY_DM_STRUCT *p_dm, 1085 enum phydm_offload_ability offload_ability 1086 ); 1087 1088 1089 void 1090 phydm_support_ability_debug( 1091 void *p_dm_void, 1092 u32 *const dm_value, 1093 u32 *_used, 1094 char *output, 1095 u32 *_out_len 1096 ); 1097 1098 void 1099 phydm_pause_dm_watchdog( 1100 void *p_dm_void, 1101 enum phydm_pause_type pause_type 1102 ); 1103 1104 void 1105 phydm_watchdog( 1106 struct PHY_DM_STRUCT *p_dm 1107 ); 1108 1109 void 1110 phydm_watchdog_mp( 1111 struct PHY_DM_STRUCT *p_dm 1112 ); 1113 1114 u8 1115 phydm_pause_func( 1116 void *p_dm_void, 1117 enum phydm_func_idx_e pause_func, 1118 enum phydm_pause_type pause_type, 1119 enum phydm_pause_level pause_lv, 1120 u8 val_lehgth, 1121 u32 *val_buf 1122 1123 ); 1124 1125 void 1126 phydm_pause_func_console( 1127 void *p_dm_void, 1128 char input[][16], 1129 u32 *_used, 1130 char *output, 1131 u32 *_out_len, 1132 u32 input_num 1133 ); 1134 1135 void 1136 odm_cmn_info_init( 1137 struct PHY_DM_STRUCT *p_dm, 1138 enum odm_cmninfo_e cmn_info, 1139 u64 value 1140 ); 1141 1142 void 1143 odm_cmn_info_hook( 1144 struct PHY_DM_STRUCT *p_dm, 1145 enum odm_cmninfo_e cmn_info, 1146 void *p_value 1147 ); 1148 1149 void 1150 odm_cmn_info_update( 1151 struct PHY_DM_STRUCT *p_dm, 1152 u32 cmn_info, 1153 u64 value 1154 ); 1155 1156 u32 1157 phydm_cmn_info_query( 1158 struct PHY_DM_STRUCT *p_dm, 1159 enum phydm_info_query_e info_type 1160 ); 1161 1162 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 1163 void 1164 odm_init_all_threads( 1165 struct PHY_DM_STRUCT *p_dm 1166 ); 1167 1168 void 1169 odm_stop_all_threads( 1170 struct PHY_DM_STRUCT *p_dm 1171 ); 1172 #endif 1173 1174 void 1175 odm_init_all_timers( 1176 struct PHY_DM_STRUCT *p_dm 1177 ); 1178 1179 void 1180 odm_cancel_all_timers( 1181 struct PHY_DM_STRUCT *p_dm 1182 ); 1183 1184 void 1185 odm_release_all_timers( 1186 struct PHY_DM_STRUCT *p_dm 1187 ); 1188 1189 1190 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1191 void odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm); 1192 void odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm); 1193 1194 /*2012/01/12 MH Check afapter status. Temp fix BSOD.*/ 1195 1196 #define HAL_ADAPTER_STS_CHK(p_dm) do {\ 1197 if (p_dm->adapter == NULL) { \ 1198 \ 1199 return;\ 1200 } \ 1201 } while (0) 1202 1203 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ 1204 1205 void * 1206 phydm_get_structure( 1207 struct PHY_DM_STRUCT *p_dm, 1208 u8 structure_type 1209 ); 1210 1211 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE) 1212 /*===========================================================*/ 1213 /* The following is for compile only*/ 1214 /*===========================================================*/ 1215 1216 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) 1217 #define IS_HARDWARE_TYPE_8188E(_adapter) false 1218 #define IS_HARDWARE_TYPE_8188F(_adapter) false 1219 #define IS_HARDWARE_TYPE_8703B(_adapter) false 1220 #define IS_HARDWARE_TYPE_8723D(_adapter) false 1221 #define IS_HARDWARE_TYPE_8821C(_adapter) false 1222 #define IS_HARDWARE_TYPE_8812AU(_adapter) false 1223 #define IS_HARDWARE_TYPE_8814A(_adapter) false 1224 #define IS_HARDWARE_TYPE_8814AU(_adapter) false 1225 #define IS_HARDWARE_TYPE_8814AE(_adapter) false 1226 #define IS_HARDWARE_TYPE_8814AS(_adapter) false 1227 #define IS_HARDWARE_TYPE_8723BU(_adapter) false 1228 #define IS_HARDWARE_TYPE_8822BU(_adapter) false 1229 #define IS_HARDWARE_TYPE_8822BS(_adapter) false 1230 #define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \ 1231 (IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter)) 1232 #else 1233 #define IS_HARDWARE_TYPE_8723A(_adapter) false 1234 #endif 1235 #define IS_HARDWARE_TYPE_8723AE(_adapter) false 1236 #define IS_HARDWARE_TYPE_8192C(_adapter) false 1237 #define IS_HARDWARE_TYPE_8192D(_adapter) false 1238 #define RF_T_METER_92D 0x42 1239 1240 1241 #define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6) 1242 1243 #define REG_CONFIG_RAM64X16 0xb2c 1244 1245 1246 /* *********************************************************** */ 1247 #endif 1248 1249 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1250 void odm_dtc(struct PHY_DM_STRUCT *p_dm); 1251 #endif 1252 1253 void 1254 phydm_dc_cancellation( 1255 struct PHY_DM_STRUCT *p_dm 1256 ); 1257 1258 void 1259 phydm_receiver_blocking( 1260 void *p_dm_void 1261 ); 1262 #endif 1263