1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21 22 #ifndef __HALDMOUTSRC_H__ 23 #define __HALDMOUTSRC_H__ 24 25 //============================================================ 26 // include files 27 //============================================================ 28 #include "phydm_pre_define.h" 29 #include "phydm_dig.h" 30 #include "phydm_edcaturbocheck.h" 31 #include "phydm_pathdiv.h" 32 #include "phydm_antdiv.h" 33 #include "phydm_antdect.h" 34 #include "phydm_dynamicbbpowersaving.h" 35 #include "phydm_rainfo.h" 36 #include "phydm_dynamictxpower.h" 37 #include "phydm_cfotracking.h" 38 #include "phydm_acs.h" 39 #include "phydm_adaptivity.h" 40 41 42 #if (RTL8814A_SUPPORT == 1) 43 #include "rtl8814a/phydm_iqk_8814a.h" 44 #endif 45 46 47 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 48 #include "halphyrf_ap.h" 49 #include "phydm_powertracking_ap.h" 50 #endif 51 52 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 53 #include "phydm_noisemonitor.h" 54 #include "halphyrf_ce.h" 55 #include "phydm_powertracking_ce.h" 56 #endif 57 58 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 59 #include "phydm_beamforming.h" 60 #include "phydm_rxhp.h" 61 #include "halphyrf_win.h" 62 #include "phydm_powertracking_win.h" 63 #endif 64 65 //============================================================ 66 // Definition 67 //============================================================ 68 // 69 // 2011/09/22 MH Define all team supprt ability. 70 // 71 72 // 73 // 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. 74 // 75 //#define DM_ODM_SUPPORT_AP 0 76 //#define DM_ODM_SUPPORT_ADSL 0 77 //#define DM_ODM_SUPPORT_CE 0 78 //#define DM_ODM_SUPPORT_MP 1 79 80 // 81 // 2011/09/28 MH Define ODM SW team support flag. 82 // 83 84 //For SW AntDiv, PathDiv, 8192C AntDiv joint use 85 #define TP_MODE 0 86 #define RSSI_MODE 1 87 88 #define TRAFFIC_LOW 0 89 #define TRAFFIC_HIGH 1 90 #define TRAFFIC_UltraLOW 2 91 92 #define NONE 0 93 94 95 /*NBI API------------------------------------*/ 96 #define NBI_ENABLE 1 97 #define NBI_DISABLE 2 98 99 #define NBI_TABLE_SIZE_128 27 100 #define NBI_TABLE_SIZE_256 59 101 102 #define NUM_START_CH_80M 7 103 #define NUM_START_CH_40M 14 104 105 #define CH_OFFSET_40M 2 106 #define CH_OFFSET_80M 6 107 /*------------------------------------------------*/ 108 109 #define SET_SUCCESS 1 110 #define SET_ERROR 2 111 #define SET_NO_NEED 3 112 113 #define FFT_128_TYPE 1 114 #define FFT_256_TYPE 2 115 116 #define PHYDM_WATCH_DOG_PERIOD 2 117 118 //8723A High Power IGI Setting 119 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 120 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 121 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 122 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 123 124 125 //============================================================ 126 // structure and define 127 //============================================================ 128 129 // 130 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. 131 // We need to remove to other position??? 132 // 133 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) 134 typedef struct rtl8192cd_priv { 135 u1Byte temp; 136 137 }rtl8192cd_priv, *prtl8192cd_priv; 138 #endif 139 140 141 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) 142 typedef struct _ADAPTER{ 143 u1Byte temp; 144 #ifdef AP_BUILD_WORKAROUND 145 HAL_DATA_TYPE* temp2; 146 prtl8192cd_priv priv; 147 #endif 148 }ADAPTER, *PADAPTER; 149 #endif 150 151 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 152 153 typedef struct _WLAN_STA{ 154 u1Byte temp; 155 } WLAN_STA, *PRT_WLAN_STA; 156 157 #endif 158 159 typedef struct _Dynamic_Primary_CCA{ 160 u1Byte PriCCA_flag; 161 u1Byte intf_flag; 162 u1Byte intf_type; 163 u1Byte DupRTS_flag; 164 u1Byte Monitor_flag; 165 u1Byte CH_offset; 166 u1Byte MF_state; 167 }Pri_CCA_T, *pPri_CCA_T; 168 169 170 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 171 172 173 #ifdef ADSL_AP_BUILD_WORKAROUND 174 #define MAX_TOLERANCE 5 175 #define IQK_DELAY_TIME 1 //ms 176 #endif 177 #if 0//defined in 8192cd.h 178 // 179 // Indicate different AP vendor for IOT issue. 180 // 181 typedef enum _HT_IOT_PEER 182 { 183 HT_IOT_PEER_UNKNOWN = 0, 184 HT_IOT_PEER_REALTEK = 1, 185 HT_IOT_PEER_REALTEK_92SE = 2, 186 HT_IOT_PEER_BROADCOM = 3, 187 HT_IOT_PEER_RALINK = 4, 188 HT_IOT_PEER_ATHEROS = 5, 189 HT_IOT_PEER_CISCO = 6, 190 HT_IOT_PEER_MERU = 7, 191 HT_IOT_PEER_MARVELL = 8, 192 HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 193 HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP 194 HT_IOT_PEER_AIRGO = 11, 195 HT_IOT_PEER_INTEL = 12, 196 HT_IOT_PEER_RTK_APCLIENT = 13, 197 HT_IOT_PEER_REALTEK_81XX = 14, 198 HT_IOT_PEER_REALTEK_WOW = 15, 199 HT_IOT_PEER_MAX = 16 200 }HT_IOT_PEER_E, *PHTIOT_PEER_E; 201 #endif 202 #endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) 203 204 #define DM_Type_ByFW 0 205 #define DM_Type_ByDriver 1 206 207 // 208 // Declare for common info 209 // 210 211 #define IQK_THRESHOLD 8 212 #define DPK_THRESHOLD 4 213 214 215 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 216 __PACK typedef struct _ODM_Phy_Status_Info_ 217 { 218 u1Byte RxPWDBAll; 219 u1Byte SignalQuality; /* in 0-100 index. */ 220 u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ 221 s1Byte RxMIMOSignalQuality[4]; /* EVM */ 222 s1Byte RxSNR[4]; /* per-path's SNR */ 223 #if (RTL8822B_SUPPORT == 1) 224 u1Byte RxCount; /* RX path counter---*/ 225 #endif 226 u1Byte BandWidth; 227 228 } __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T; 229 230 typedef struct _ODM_Phy_Status_Info_Append_ 231 { 232 u1Byte MAC_CRC32; 233 234 }ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T; 235 236 #else 237 238 typedef struct _ODM_Phy_Status_Info_ 239 { 240 // 241 // Be care, if you want to add any element please insert between 242 // RxPWDBAll & SignalStrength. 243 // 244 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 245 u4Byte RxPWDBAll; 246 #else 247 u1Byte RxPWDBAll; 248 #endif 249 u1Byte SignalQuality; /* in 0-100 index. */ 250 s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ 251 u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ 252 u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ 253 s2Byte Cfo_short[4]; /* per-path's Cfo_short */ 254 s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ 255 s1Byte RxPower; /* in dBm Translate from PWdB */ 256 s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ 257 u1Byte BTRxRSSIPercentage; 258 u1Byte SignalStrength; /* in 0-100 index. */ 259 s1Byte RxPwr[4]; /* per-path's pwdb */ 260 s1Byte RxSNR[4]; /* per-path's SNR */ 261 #if (RTL8822B_SUPPORT == 1) 262 u1Byte RxCount:2; /* RX path counter---*/ 263 u1Byte BandWidth:2; 264 u1Byte rxsc:4; /* sub-channel---*/ 265 #else 266 u1Byte BandWidth; 267 #endif 268 u1Byte btCoexPwrAdjust; 269 #if (RTL8822B_SUPPORT == 1) 270 u1Byte channel; /* channel number---*/ 271 BOOLEAN bMuPacket; /* is MU packet or not---*/ 272 BOOLEAN bBeamformed; /* BF packet---*/ 273 #endif 274 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T; 275 #endif 276 277 typedef struct _ODM_Per_Pkt_Info_ 278 { 279 //u1Byte Rate; 280 u1Byte DataRate; 281 u1Byte StationID; 282 BOOLEAN bPacketMatchBSSID; 283 BOOLEAN bPacketToSelf; 284 BOOLEAN bPacketBeacon; 285 BOOLEAN bToSelf; 286 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; 287 288 289 typedef struct _ODM_Phy_Dbg_Info_ 290 { 291 //ODM Write,debug info 292 s1Byte RxSNRdB[4]; 293 u4Byte NumQryPhyStatus; 294 u4Byte NumQryPhyStatusCCK; 295 u4Byte NumQryPhyStatusOFDM; 296 #if (RTL8822B_SUPPORT == 1) 297 u4Byte NumQryMuPkt; 298 u4Byte NumQryBfPkt; 299 #endif 300 u1Byte NumQryBeaconPkt; 301 //Others 302 s4Byte RxEVM[4]; 303 304 }ODM_PHY_DBG_INFO_T; 305 306 307 typedef struct _ODM_Mac_Status_Info_ 308 { 309 u1Byte test; 310 311 }ODM_MAC_INFO; 312 313 // 314 // 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T 315 // Please declare below ODM relative info in your STA info structure. 316 // 317 #if 1 318 typedef struct _ODM_STA_INFO{ 319 // Driver Write 320 BOOLEAN bUsed; // record the sta status link or not? 321 //u1Byte WirelessMode; // 322 u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E 323 324 // ODM Write 325 //1 PHY_STATUS_INFO 326 u1Byte RSSI_Path[4]; // 327 u1Byte RSSI_Ave; 328 u1Byte RXEVM[4]; 329 u1Byte RXSNR[4]; 330 331 // ODM Write 332 //1 TX_INFO (may changed by IC) 333 //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. 334 #if 0 335 u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit 336 u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit 337 u1Byte ANTSEL_C; //only in Jagar: 4bit 338 u1Byte ANTSEL_D; //only in Jagar: 4bit 339 u1Byte TX_ANTL; //not in Jagar: 2bit 340 u1Byte TX_ANT_HT; //not in Jagar: 2bit 341 u1Byte TX_ANT_CCK; //not in Jagar: 2bit 342 u1Byte TXAGC_A; //not in Jagar: 4bit 343 u1Byte TXAGC_B; //not in Jagar: 4bit 344 u1Byte TXPWR_OFFSET; //only in Jagar: 3bit 345 u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK 346 #endif 347 348 // 349 // Please use compile flag to disabe the strcutrue for other IC except 88E. 350 // Move To lower layer. 351 // 352 // ODM Write Wilson will handle this part(said by Luke.Lee) 353 //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. 354 #if 0 355 //1 For 88E RA (don't redefine the naming) 356 u1Byte rate_id; 357 u1Byte rate_SGI; 358 u1Byte rssi_sta_ra; 359 u1Byte SGI_enable; 360 u1Byte Decision_rate; 361 u1Byte Pre_rate; 362 u1Byte Active; 363 364 // Driver write Wilson handle. 365 //1 TX_RPT (don't redefine the naming) 366 u2Byte RTY[4]; // ??? 367 u2Byte TOTAL; // ??? 368 u2Byte DROP; // ??? 369 // 370 // Please use compile flag to disabe the strcutrue for other IC except 88E. 371 // 372 #endif 373 374 }ODM_STA_INFO_T, *PODM_STA_INFO_T; 375 #endif 376 377 // 378 // 2011/10/20 MH Define Common info enum for all team. 379 // 380 typedef enum _ODM_Common_Info_Definition 381 { 382 //-------------REMOVED CASE-----------// 383 //ODM_CMNINFO_CCK_HP, 384 //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? 385 //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E 386 //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E 387 //-------------REMOVED CASE-----------// 388 389 // 390 // Fixed value: 391 // 392 393 //-----------HOOK BEFORE REG INIT-----------// 394 ODM_CMNINFO_PLATFORM = 0, 395 ODM_CMNINFO_ABILITY, // ODM_ABILITY_E 396 ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E 397 ODM_CMNINFO_MP_TEST_CHIP, 398 ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E 399 ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E 400 ODM_CMNINFO_FAB_VER, // ODM_FAB_E 401 ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? 402 ODM_CMNINFO_RFE_TYPE, 403 ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E 404 ODM_CMNINFO_PACKAGE_TYPE, 405 ODM_CMNINFO_EXT_LNA, // TRUE 406 ODM_CMNINFO_5G_EXT_LNA, 407 ODM_CMNINFO_EXT_PA, 408 ODM_CMNINFO_5G_EXT_PA, 409 ODM_CMNINFO_GPA, 410 ODM_CMNINFO_APA, 411 ODM_CMNINFO_GLNA, 412 ODM_CMNINFO_ALNA, 413 ODM_CMNINFO_EXT_TRSW, 414 ODM_CMNINFO_EXT_LNA_GAIN, 415 ODM_CMNINFO_PATCH_ID, //CUSTOMER ID 416 ODM_CMNINFO_BINHCT_TEST, 417 ODM_CMNINFO_BWIFI_TEST, 418 ODM_CMNINFO_SMART_CONCURRENT, 419 ODM_CMNINFO_CONFIG_BB_RF, 420 ODM_CMNINFO_DOMAIN_CODE_2G, 421 ODM_CMNINFO_DOMAIN_CODE_5G, 422 ODM_CMNINFO_IQKFWOFFLOAD, 423 //-----------HOOK BEFORE REG INIT-----------// 424 425 426 // 427 // Dynamic value: 428 // 429 //--------- POINTER REFERENCE-----------// 430 ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E 431 ODM_CMNINFO_TX_UNI, 432 ODM_CMNINFO_RX_UNI, 433 ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E 434 ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E 435 ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E 436 ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E 437 ODM_CMNINFO_BW, // ODM_BW_E 438 ODM_CMNINFO_CHNL, 439 ODM_CMNINFO_FORCED_RATE, 440 441 ODM_CMNINFO_DMSP_GET_VALUE, 442 ODM_CMNINFO_BUDDY_ADAPTOR, 443 ODM_CMNINFO_DMSP_IS_MASTER, 444 ODM_CMNINFO_SCAN, 445 ODM_CMNINFO_POWER_SAVING, 446 ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E 447 ODM_CMNINFO_DRV_STOP, 448 ODM_CMNINFO_PNP_IN, 449 ODM_CMNINFO_INIT_ON, 450 ODM_CMNINFO_ANT_TEST, 451 ODM_CMNINFO_NET_CLOSED, 452 //ODM_CMNINFO_RTSTA_AID, // For win driver only? 453 ODM_CMNINFO_FORCED_IGI_LB, 454 ODM_CMNINFO_P2P_LINK, 455 ODM_CMNINFO_FCS_MODE, 456 ODM_CMNINFO_IS1ANTENNA, 457 ODM_CMNINFO_RFDEFAULTPATH, 458 //--------- POINTER REFERENCE-----------// 459 460 //------------CALL BY VALUE-------------// 461 ODM_CMNINFO_WIFI_DIRECT, 462 ODM_CMNINFO_WIFI_DISPLAY, 463 ODM_CMNINFO_LINK_IN_PROGRESS, 464 ODM_CMNINFO_LINK, 465 ODM_CMNINFO_STATION_STATE, 466 ODM_CMNINFO_RSSI_MIN, 467 ODM_CMNINFO_DBG_COMP, // u8Byte 468 ODM_CMNINFO_DBG_LEVEL, // u4Byte 469 ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte 470 ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte 471 ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte 472 ODM_CMNINFO_BT_ENABLED, 473 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 474 ODM_CMNINFO_BT_HS_RSSI, 475 ODM_CMNINFO_BT_OPERATION, 476 ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not 477 ODM_CMNINFO_BT_DIG, 478 ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil 479 ODM_CMNINFO_BT_DISABLE_EDCA, 480 #if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 481 #ifdef UNIVERSAL_REPEATER 482 ODM_CMNINFO_VXD_LINK, 483 #endif 484 #endif 485 ODM_CMNINFO_AP_TOTAL_NUM, 486 //------------CALL BY VALUE-------------// 487 488 // 489 // Dynamic ptr array hook itms. 490 // 491 ODM_CMNINFO_STA_STATUS, 492 ODM_CMNINFO_PHY_STATUS, 493 ODM_CMNINFO_MAC_STATUS, 494 495 ODM_CMNINFO_MAX, 496 497 498 }ODM_CMNINFO_E; 499 500 // 501 // 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY 502 // 503 typedef enum _ODM_Support_Ability_Definition 504 { 505 // 506 // BB ODM section BIT 0-19 507 // 508 ODM_BB_DIG = BIT0, 509 ODM_BB_RA_MASK = BIT1, 510 ODM_BB_DYNAMIC_TXPWR = BIT2, 511 ODM_BB_FA_CNT = BIT3, 512 ODM_BB_RSSI_MONITOR = BIT4, 513 ODM_BB_CCK_PD = BIT5, 514 ODM_BB_ANT_DIV = BIT6, 515 ODM_BB_PWR_SAVE = BIT7, 516 ODM_BB_PWR_TRAIN = BIT8, 517 ODM_BB_RATE_ADAPTIVE = BIT9, 518 ODM_BB_PATH_DIV = BIT10, 519 ODM_BB_PSD = BIT11, 520 ODM_BB_RXHP = BIT12, 521 ODM_BB_ADAPTIVITY = BIT13, 522 ODM_BB_CFO_TRACKING = BIT14, 523 ODM_BB_NHM_CNT = BIT15, 524 ODM_BB_PRIMARY_CCA = BIT16, 525 ODM_BB_TXBF = BIT17, 526 527 // 528 // MAC DM section BIT 20-23 529 // 530 ODM_MAC_EDCA_TURBO = BIT20, 531 ODM_MAC_EARLY_MODE = BIT21, 532 533 // 534 // RF ODM section BIT 24-31 535 // 536 ODM_RF_TX_PWR_TRACK = BIT24, 537 ODM_RF_RX_GAIN_TRACK = BIT25, 538 ODM_RF_CALIBRATION = BIT26, 539 540 }ODM_ABILITY_E; 541 542 //Move some non-DM enum,define, struc. form phydm.h to phydm_types.h by Dino 543 544 // ODM_CMNINFO_ONE_PATH_CCA 545 typedef enum tag_CCA_Path 546 { 547 ODM_CCA_2R = 0, 548 ODM_CCA_1R_A = 1, 549 ODM_CCA_1R_B = 2, 550 }ODM_CCA_PATH_E; 551 552 //move RAInfo to Phydm_RaInfo.h 553 554 //Remove struct PATHDIV_PARA to odm_PathDiv.h 555 556 //Remove struct to odm_PowerTracking.h by YuChen 557 // 558 // ODM Dynamic common info value definition 559 // 560 //Move AntDiv form phydm.h to Phydm_AntDiv.h by Dino 561 562 //move PathDiv to Phydm_PathDiv.h 563 564 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ 565 PHY_REG_PG_RELATIVE_VALUE = 0, 566 PHY_REG_PG_EXACT_VALUE = 1 567 } PHY_REG_PG_TYPE; 568 569 // 570 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. 571 // 572 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) 573 #if (RT_PLATFORM != PLATFORM_LINUX) 574 typedef 575 #endif 576 577 struct DM_Out_Source_Dynamic_Mechanism_Structure 578 #else// for AP,ADSL,CE Team 579 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure 580 #endif 581 { 582 //RT_TIMER FastAntTrainingTimer; 583 // 584 // Add for different team use temporarily 585 // 586 PADAPTER Adapter; // For CE/NIC team 587 prtl8192cd_priv priv; // For AP/ADSL team 588 // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. 589 BOOLEAN odm_ready; 590 591 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) 592 rtl8192cd_priv fake_priv; 593 #endif 594 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) 595 // ADSL_AP_BUILD_WORKAROUND 596 ADAPTER fake_adapter; 597 #endif 598 599 PHY_REG_PG_TYPE PhyRegPgValueType; 600 u1Byte PhyRegPgVersion; 601 602 u8Byte DebugComponents; 603 u4Byte DebugLevel; 604 605 u4Byte NumQryPhyStatusAll; //CCK + OFDM 606 u4Byte LastNumQryPhyStatusAll; 607 u4Byte RxPWDBAve; 608 BOOLEAN MPDIG_2G; //off MPDIG 609 u1Byte Times_2G; 610 611 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// 612 BOOLEAN bCckHighPower; 613 u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE 614 u1Byte ControlChannel; 615 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// 616 617 //--------REMOVED COMMON INFO----------// 618 //u1Byte PseudoMacPhyMode; 619 //BOOLEAN *BTCoexist; 620 //BOOLEAN PseudoBtCoexist; 621 //u1Byte OPMode; 622 //BOOLEAN bAPMode; 623 //BOOLEAN bClientMode; 624 //BOOLEAN bAdHocMode; 625 //BOOLEAN bSlaveOfDMSP; 626 //--------REMOVED COMMON INFO----------// 627 628 629 //1 COMMON INFORMATION 630 631 // 632 // Init Value 633 // 634 //-----------HOOK BEFORE REG INIT-----------// 635 BOOLEAN NoisyDecision; 636 u4Byte NoisyDecision_Smooth; 637 // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 638 u1Byte SupportPlatform; 639 // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K 640 u4Byte SupportAbility; 641 // ODM PCIE/USB/SDIO = 1/2/3 642 u1Byte SupportInterface; 643 // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... 644 u4Byte SupportICType; 645 // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... 646 u1Byte CutVersion; 647 // Fab Version TSMC/UMC = 0/1 648 u1Byte FabVersion; 649 // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... 650 u1Byte RFType; 651 u1Byte RFEType; 652 // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... 653 u1Byte BoardType; 654 u1Byte PackageType; 655 u1Byte TypeGLNA; 656 u1Byte TypeGPA; 657 u1Byte TypeALNA; 658 u1Byte TypeAPA; 659 // with external LNA NO/Yes = 0/1 660 u1Byte ExtLNA; // 2G 661 u1Byte ExtLNA5G; //5G 662 // with external PA NO/Yes = 0/1 663 u1Byte ExtPA; // 2G 664 u1Byte ExtPA5G; //5G 665 // with external TRSW NO/Yes = 0/1 666 u1Byte ExtTRSW; 667 u1Byte ExtLNAGain; // 2G 668 u1Byte PatchID; //Customer ID 669 BOOLEAN bInHctTest; 670 BOOLEAN bWIFITest; 671 672 BOOLEAN bDualMacSmartConcurrent; 673 u4Byte BK_SupportAbility; 674 u1Byte AntDivType; 675 BOOLEAN ConfigBBRF; 676 u1Byte odm_Regulation2_4G; 677 u1Byte odm_Regulation5G; 678 u1Byte IQKFWOffload; 679 u8 is_nbi_enable; 680 //-----------HOOK BEFORE REG INIT-----------// 681 682 // 683 // Dynamic Value 684 // 685 //--------- POINTER REFERENCE-----------// 686 687 u1Byte u1Byte_temp; 688 BOOLEAN BOOLEAN_temp; 689 PADAPTER PADAPTER_temp; 690 691 // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 692 u1Byte *pMacPhyMode; 693 //TX Unicast byte count 694 u8Byte *pNumTxBytesUnicast; 695 //RX Unicast byte count 696 u8Byte *pNumRxBytesUnicast; 697 // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 698 u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E 699 // Frequence band 2.4G/5G = 0/1 700 u1Byte *pBandType; 701 // Secondary channel offset don't_care/below/above = 0/1/2 702 u1Byte *pSecChOffset; 703 // Security mode Open/WEP/AES/TKIP = 0/1/2/3 704 u1Byte *pSecurity; 705 // BW info 20M/40M/80M = 0/1/2 706 u1Byte *pBandWidth; 707 // Central channel location Ch1/Ch2/.... 708 u1Byte *pChannel; //central channel number 709 BOOLEAN DPK_Done; 710 // Common info for 92D DMSP 711 712 BOOLEAN *pbGetValueFromOtherMac; 713 PADAPTER *pBuddyAdapter; 714 BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave 715 // Common info for Status 716 BOOLEAN *pbScanInProcess; 717 BOOLEAN *pbPowerSaving; 718 // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. 719 u1Byte *pOnePathCCA; 720 //pMgntInfo->AntennaTest 721 u1Byte *pAntennaTest; 722 BOOLEAN *pbNet_closed; 723 //u1Byte *pAidMap; 724 u1Byte *pu1ForcedIgiLb; 725 BOOLEAN *pIsFcsModeEnable; 726 /*--------- For 8723B IQK-----------*/ 727 BOOLEAN *pIs1Antenna; 728 u1Byte *pRFDefaultPath; 729 // 0:S1, 1:S0 730 731 //--------- POINTER REFERENCE-----------// 732 pu2Byte pForcedDataRate; 733 //------------CALL BY VALUE-------------// 734 BOOLEAN bLinkInProcess; 735 BOOLEAN bWIFI_Direct; 736 BOOLEAN bWIFI_Display; 737 BOOLEAN bLinked; 738 BOOLEAN bsta_state; 739 #if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 740 #ifdef UNIVERSAL_REPEATER 741 BOOLEAN VXD_bLinked; 742 #endif 743 #endif // for repeater mode add by YuChen 2014.06.23 744 u1Byte RSSI_Min; 745 u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ 746 BOOLEAN bIsMPChip; 747 BOOLEAN bOneEntryOnly; 748 BOOLEAN mp_mode; 749 u4Byte OneEntry_MACID; 750 u1Byte pre_number_linked_client; 751 u1Byte number_linked_client; 752 u1Byte pre_number_active_client; 753 u1Byte number_active_client; 754 // Common info for BTDM 755 BOOLEAN bBtEnabled; // BT is enabled 756 BOOLEAN bBtConnectProcess; // BT HS is under connection progress. 757 u1Byte btHsRssi; // BT HS mode wifi rssi value. 758 BOOLEAN bBtHsOperation; // BT HS mode is under progress 759 u1Byte btHsDigVal; // use BT rssi to decide the DIG value 760 BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo 761 BOOLEAN bBtBusy; // BT is busy. 762 BOOLEAN bBtLimitedDig; // BT is busy. 763 //------------CALL BY VALUE-------------// 764 u1Byte RSSI_A; 765 u1Byte RSSI_B; 766 u1Byte RSSI_C; 767 u1Byte RSSI_D; 768 u8Byte RSSI_TRSW; 769 u8Byte RSSI_TRSW_H; 770 u8Byte RSSI_TRSW_L; 771 u8Byte RSSI_TRSW_iso; 772 u1Byte TRXAntStatus; 773 u1Byte cck_lna_idx; 774 u1Byte cck_vga_idx; 775 u1Byte ofdm_agc_idx[4]; 776 777 u1Byte RxRate; 778 BOOLEAN bNoisyState; 779 u1Byte TxRate; 780 u1Byte LinkedInterval; 781 u1Byte preChannel; 782 u4Byte TxagcOffsetValueA; 783 BOOLEAN IsTxagcOffsetPositiveA; 784 u4Byte TxagcOffsetValueB; 785 BOOLEAN IsTxagcOffsetPositiveB; 786 u8Byte lastTxOkCnt; 787 u8Byte lastRxOkCnt; 788 u4Byte BbSwingOffsetA; 789 BOOLEAN IsBbSwingOffsetPositiveA; 790 u4Byte BbSwingOffsetB; 791 BOOLEAN IsBbSwingOffsetPositiveB; 792 u1Byte antdiv_rssi; 793 u1Byte fat_comb_a; 794 u1Byte fat_comb_b; 795 u1Byte antdiv_intvl; 796 u1Byte AntType; 797 u1Byte pre_AntType; 798 u1Byte antdiv_period; 799 u1Byte antdiv_select; 800 u1Byte path_select; 801 u1Byte antdiv_evm_en; 802 u1Byte bdc_holdstate; 803 u1Byte NdpaPeriod; 804 BOOLEAN H2C_RARpt_connect; 805 BOOLEAN cck_agc_report_type; 806 807 u1Byte dm_dig_max_TH; 808 u1Byte dm_dig_min_TH; 809 u1Byte print_agc; 810 u1Byte consecutive_idlel_time; /*unit: second*/ 811 //For Adaptivtiy 812 u2Byte NHM_cnt_0; 813 u2Byte NHM_cnt_1; 814 s1Byte TH_L2H_ini; 815 s1Byte TH_EDCCA_HL_diff; 816 s1Byte TH_L2H_ini_mode2; 817 s1Byte TH_EDCCA_HL_diff_mode2; 818 BOOLEAN Carrier_Sense_enable; 819 u1Byte Adaptivity_IGI_upper; 820 BOOLEAN adaptivity_flag; 821 u1Byte DCbackoff; 822 BOOLEAN Adaptivity_enable; 823 u1Byte APTotalNum; 824 BOOLEAN EDCCA_enable; 825 ADAPTIVITY_STATISTICS Adaptivity; 826 //For Adaptivtiy 827 u1Byte LastUSBHub; 828 u1Byte TxBfDataRate; 829 830 u1Byte c2h_cmd_start; 831 u1Byte fw_debug_trace[60]; 832 u1Byte pre_c2h_seq; 833 BOOLEAN fw_buff_is_enpty; 834 u4Byte data_frame_num; 835 836 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 837 ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; 838 #endif 839 // 840 //2 Define STA info. 841 // _ODM_STA_INFO 842 // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? 843 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 844 u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */ 845 846 #if (RATE_ADAPTIVE_SUPPORT == 1) 847 u2Byte CurrminRptTime; 848 ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 849 #endif 850 // 851 // 2012/02/14 MH Add to share 88E ra with other SW team. 852 // We need to colelct all support abilit to a proper area. 853 // 854 BOOLEAN RaSupport88E; 855 856 // Define ........... 857 858 // Latest packet phy info (ODM write) 859 ODM_PHY_DBG_INFO_T PhyDbgInfo; 860 //PHY_INFO_88E PhyInfo; 861 862 // Latest packet phy info (ODM write) 863 ODM_MAC_INFO *pMacInfo; 864 //MAC_INFO_88E MacInfo; 865 866 // Different Team independt structure?? 867 868 // 869 //TX_RTP_CMN TX_retrpo; 870 //TX_RTP_88E TX_retrpo; 871 //TX_RTP_8195 TX_retrpo; 872 873 // 874 //ODM Structure 875 // 876 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) 877 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 878 BDC_T DM_BdcTable; 879 #endif 880 #endif 881 FAT_T DM_FatTable; 882 DIG_T DM_DigTable; 883 PS_T DM_PSTable; 884 Pri_CCA_T DM_PriCCA; 885 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 886 RXHP_T DM_RXHP_Table; 887 #endif 888 RA_T DM_RA_Table; 889 FALSE_ALARM_STATISTICS FalseAlmCnt; 890 FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 891 SWAT_T DM_SWAT_Table; 892 BOOLEAN RSSI_test; 893 CFO_TRACKING DM_CfoTrack; 894 ACS DM_ACS; 895 896 897 #if (RTL8814A_SUPPORT == 1) 898 IQK_INFO IQK_info; 899 #endif /* (RTL8814A_SUPPORT==1) */ 900 901 902 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 903 //Path Div Struct 904 PATHDIV_PARA pathIQK; 905 #endif 906 #if(defined(CONFIG_PATH_DIVERSITY)) 907 PATHDIV_T DM_PathDiv; 908 #endif 909 910 EDCA_T DM_EDCA_Table; 911 u4Byte WMMEDCA_BE; 912 913 // Copy from SD4 structure 914 // 915 // ================================================== 916 // 917 918 //common 919 //u1Byte DM_Type; 920 //u1Byte PSD_Report_RXHP[80]; // Add By Gary 921 //u1Byte PSD_func_flag; // Add By Gary 922 //for DIG 923 //u1Byte bDMInitialGainEnable; 924 //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. 925 //for Antenna diversity 926 //u8 AntDivCfg;// 0:OFF , 1:ON, 2:by efuse 927 //PSTA_INFO_T RSSI_target; 928 929 BOOLEAN *pbDriverStopped; 930 BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; 931 BOOLEAN *pinit_adpt_in_progress; 932 933 //PSD 934 BOOLEAN bUserAssignLevel; 935 RT_TIMER PSDTimer; 936 u1Byte RSSI_BT; //come from BT 937 BOOLEAN bPSDinProcess; 938 BOOLEAN bPSDactive; 939 BOOLEAN bDMInitialGainEnable; 940 941 //MPT DIG 942 RT_TIMER MPT_DIGTimer; 943 944 //for rate adaptive, in fact, 88c/92c fw will handle this 945 u1Byte bUseRAMask; 946 947 ODM_RATE_ADAPTIVE RateAdaptive; 948 //#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 949 #if(defined(CONFIG_ANT_DETECTION)) 950 ANT_DETECTED_INFO AntDetectedInfo; // Antenna detected information for RSSI tool 951 #endif 952 ODM_RF_CAL_T RFCalibrateInfo; 953 954 955 // 956 // Dynamic ATC switch 957 // 958 959 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 960 // 961 // Power Training 962 // 963 BOOLEAN bDisablePowerTraining; 964 u1Byte ForcePowerTrainingState; 965 BOOLEAN bChangeState; 966 u4Byte PT_score; 967 u8Byte OFDM_RX_Cnt; 968 u8Byte CCK_RX_Cnt; 969 #endif 970 971 // 972 // ODM system resource. 973 // 974 975 // ODM relative time. 976 RT_TIMER PathDivSwitchTimer; 977 //2011.09.27 add for Path Diversity 978 RT_TIMER CCKPathDiversityTimer; 979 RT_TIMER FastAntTrainingTimer; 980 #ifdef ODM_EVM_ENHANCE_ANTDIV 981 RT_TIMER EVM_FastAntTrainingTimer; 982 #endif 983 RT_TIMER sbdcnt_timer; 984 985 // ODM relative workitem. 986 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 987 #if USE_WORKITEM 988 RT_WORK_ITEM PathDivSwitchWorkitem; 989 RT_WORK_ITEM CCKPathDiversityWorkitem; 990 RT_WORK_ITEM FastAntTrainingWorkitem; 991 RT_WORK_ITEM MPT_DIGWorkitem; 992 RT_WORK_ITEM RaRptWorkitem; 993 RT_WORK_ITEM sbdcnt_workitem; 994 #endif 995 996 #if (BEAMFORMING_SUPPORT == 1) 997 RT_BEAMFORMING_INFO BeamformingInfo; 998 #endif 999 #endif 1000 1001 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) 1002 1003 #if (RT_PLATFORM != PLATFORM_LINUX) 1004 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure 1005 #else 1006 }; 1007 #endif 1008 1009 #else// for AP,ADSL,CE Team 1010 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure 1011 #endif 1012 1013 1014 typedef enum _PHYDM_STRUCTURE_TYPE{ 1015 PHYDM_FALSEALMCNT, 1016 PHYDM_CFOTRACK, 1017 PHYDM_ADAPTIVITY, 1018 PHYDM_ROMINFO, 1019 1020 }PHYDM_STRUCTURE_TYPE; 1021 1022 1023 1024 typedef enum _ODM_RF_CONTENT{ 1025 odm_radioa_txt = 0x1000, 1026 odm_radiob_txt = 0x1001, 1027 odm_radioc_txt = 0x1002, 1028 odm_radiod_txt = 0x1003 1029 } ODM_RF_CONTENT; 1030 1031 typedef enum _ODM_BB_Config_Type{ 1032 CONFIG_BB_PHY_REG, 1033 CONFIG_BB_AGC_TAB, 1034 CONFIG_BB_AGC_TAB_2G, 1035 CONFIG_BB_AGC_TAB_5G, 1036 CONFIG_BB_PHY_REG_PG, 1037 CONFIG_BB_PHY_REG_MP, 1038 CONFIG_BB_AGC_TAB_DIFF, 1039 } ODM_BB_Config_Type, *PODM_BB_Config_Type; 1040 1041 typedef enum _ODM_RF_Config_Type{ 1042 CONFIG_RF_RADIO, 1043 CONFIG_RF_TXPWR_LMT, 1044 } ODM_RF_Config_Type, *PODM_RF_Config_Type; 1045 1046 typedef enum _ODM_FW_Config_Type{ 1047 CONFIG_FW_NIC, 1048 CONFIG_FW_NIC_2, 1049 CONFIG_FW_AP, 1050 CONFIG_FW_AP_2, 1051 CONFIG_FW_MP, 1052 CONFIG_FW_WoWLAN, 1053 CONFIG_FW_WoWLAN_2, 1054 CONFIG_FW_AP_WoWLAN, 1055 CONFIG_FW_BT, 1056 } ODM_FW_Config_Type; 1057 1058 // Status code 1059 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1060 typedef enum _RT_STATUS{ 1061 RT_STATUS_SUCCESS, 1062 RT_STATUS_FAILURE, 1063 RT_STATUS_PENDING, 1064 RT_STATUS_RESOURCE, 1065 RT_STATUS_INVALID_CONTEXT, 1066 RT_STATUS_INVALID_PARAMETER, 1067 RT_STATUS_NOT_SUPPORT, 1068 RT_STATUS_OS_API_FAILED, 1069 }RT_STATUS,*PRT_STATUS; 1070 #endif // end of RT_STATUS definition 1071 1072 #ifdef REMOVE_PACK 1073 #pragma pack() 1074 #endif 1075 1076 //#include "odm_function.h" 1077 1078 //3=========================================================== 1079 //3 DIG 1080 //3=========================================================== 1081 1082 //Remove DIG by Yuchen 1083 1084 //3=========================================================== 1085 //3 AGC RX High Power Mode 1086 //3=========================================================== 1087 #define LNA_Low_Gain_1 0x64 1088 #define LNA_Low_Gain_2 0x5A 1089 #define LNA_Low_Gain_3 0x58 1090 1091 #define FA_RXHP_TH1 5000 1092 #define FA_RXHP_TH2 1500 1093 #define FA_RXHP_TH3 800 1094 #define FA_RXHP_TH4 600 1095 #define FA_RXHP_TH5 500 1096 1097 //3=========================================================== 1098 //3 EDCA 1099 //3=========================================================== 1100 1101 //3=========================================================== 1102 //3 Dynamic Tx Power 1103 //3=========================================================== 1104 //Dynamic Tx Power Control Threshold 1105 1106 //Remove By YuChen 1107 1108 //3=========================================================== 1109 //3 Tx Power Tracking 1110 //3=========================================================== 1111 1112 1113 1114 //3=========================================================== 1115 //3 Rate Adaptive 1116 //3=========================================================== 1117 //Remove to odm_RaInfo.h by RS_James 1118 1119 //3=========================================================== 1120 //3 BB Power Save 1121 //3=========================================================== 1122 1123 typedef enum tag_1R_CCA_Type_Definition 1124 { 1125 CCA_1R =0, 1126 CCA_2R = 1, 1127 CCA_MAX = 2, 1128 }DM_1R_CCA_E; 1129 1130 typedef enum tag_RF_Type_Definition 1131 { 1132 RF_Save =0, 1133 RF_Normal = 1, 1134 RF_MAX = 2, 1135 }DM_RF_E; 1136 1137 1138 // 1139 // Extern Global Variables. 1140 // 1141 //PowerTracking move to odm_powerTrakcing.h by YuChen 1142 // 1143 // check Sta pointer valid or not 1144 // 1145 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) 1146 #define IS_STA_VALID(pSta) (pSta && pSta->expire_to) 1147 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1148 #define IS_STA_VALID(pSta) (pSta && pSta->bUsed) 1149 #else 1150 #define IS_STA_VALID(pSta) (pSta) 1151 #endif 1152 1153 //Remove DIG by yuchen 1154 1155 //Remove BB power saving by Yuchen 1156 1157 //remove PT by yuchen 1158 1159 //ODM_RAStateCheck() Remove by RS_James 1160 1161 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL)) 1162 //============================================================ 1163 // function prototype 1164 //============================================================ 1165 //#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh 1166 //void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, 1167 // IN INT32 DM_Type, 1168 // IN INT32 DM_Value); 1169 1170 //Remove DIG by yuchen 1171 1172 1173 BOOLEAN 1174 ODM_CheckPowerStatus( 1175 IN PADAPTER Adapter 1176 ); 1177 1178 1179 //Remove ODM_RateAdaptiveStateApInit() by RS_James 1180 1181 //Remove Edca by YuChen 1182 1183 #endif 1184 1185 1186 1187 u4Byte odm_ConvertTo_dB(u4Byte Value); 1188 1189 u4Byte odm_ConvertTo_linear(u4Byte Value); 1190 1191 #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) 1192 1193 u4Byte 1194 GetPSDData( 1195 PDM_ODM_T pDM_Odm, 1196 unsigned int point, 1197 u1Byte initial_gain_psd); 1198 1199 #endif 1200 1201 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1202 VOID 1203 ODM_DMWatchdog_LPS( 1204 IN PDM_ODM_T pDM_Odm 1205 ); 1206 #endif 1207 1208 1209 s4Byte 1210 ODM_PWdB_Conversion( 1211 IN s4Byte X, 1212 IN u4Byte TotalBit, 1213 IN u4Byte DecimalBit 1214 ); 1215 1216 s4Byte 1217 ODM_SignConversion( 1218 IN s4Byte value, 1219 IN u4Byte TotalBit 1220 ); 1221 1222 VOID 1223 ODM_DMInit( 1224 IN PDM_ODM_T pDM_Odm 1225 ); 1226 1227 VOID 1228 ODM_DMReset( 1229 IN PDM_ODM_T pDM_Odm 1230 ); 1231 1232 VOID 1233 phydm_support_ablity_debug( 1234 IN PVOID pDM_VOID, 1235 IN u4Byte *const dm_value, 1236 IN u4Byte *_used, 1237 OUT char *output, 1238 IN u4Byte *_out_len 1239 ); 1240 1241 VOID 1242 ODM_DMWatchdog( 1243 IN PDM_ODM_T pDM_Odm // For common use in the future 1244 ); 1245 1246 VOID 1247 ODM_CmnInfoInit( 1248 IN PDM_ODM_T pDM_Odm, 1249 IN ODM_CMNINFO_E CmnInfo, 1250 IN u4Byte Value 1251 ); 1252 1253 VOID 1254 ODM_CmnInfoHook( 1255 IN PDM_ODM_T pDM_Odm, 1256 IN ODM_CMNINFO_E CmnInfo, 1257 IN PVOID pValue 1258 ); 1259 1260 VOID 1261 ODM_CmnInfoPtrArrayHook( 1262 IN PDM_ODM_T pDM_Odm, 1263 IN ODM_CMNINFO_E CmnInfo, 1264 IN u2Byte Index, 1265 IN PVOID pValue 1266 ); 1267 1268 VOID 1269 ODM_CmnInfoUpdate( 1270 IN PDM_ODM_T pDM_Odm, 1271 IN u4Byte CmnInfo, 1272 IN u8Byte Value 1273 ); 1274 1275 #if(DM_ODM_SUPPORT_TYPE==ODM_AP) 1276 VOID 1277 ODM_InitAllThreads( 1278 IN PDM_ODM_T pDM_Odm 1279 ); 1280 1281 VOID 1282 ODM_StopAllThreads( 1283 IN PDM_ODM_T pDM_Odm 1284 ); 1285 #endif 1286 1287 VOID 1288 ODM_InitAllTimers( 1289 IN PDM_ODM_T pDM_Odm 1290 ); 1291 1292 VOID 1293 ODM_CancelAllTimers( 1294 IN PDM_ODM_T pDM_Odm 1295 ); 1296 1297 VOID 1298 ODM_ReleaseAllTimers( 1299 IN PDM_ODM_T pDM_Odm 1300 ); 1301 1302 1303 1304 1305 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1306 VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); 1307 VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); 1308 1309 1310 1311 u8Byte 1312 PlatformDivision64( 1313 IN u8Byte x, 1314 IN u8Byte y 1315 ); 1316 1317 //==================================================== 1318 //3 PathDiV End 1319 //==================================================== 1320 1321 1322 #define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh 1323 //void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, 1324 // IN INT32 DM_Type, 1325 // IN INT32 DM_Value); 1326 // 1327 // PathDiveristy Remove by RS_James 1328 1329 typedef enum tag_DIG_Connect_Definition 1330 { 1331 DIG_STA_DISCONNECT = 0, 1332 DIG_STA_CONNECT = 1, 1333 DIG_STA_BEFORE_CONNECT = 2, 1334 DIG_MultiSTA_DISCONNECT = 3, 1335 DIG_MultiSTA_CONNECT = 4, 1336 DIG_CONNECT_MAX 1337 }DM_DIG_CONNECT_E; 1338 1339 1340 // 1341 // 2012/01/12 MH Check afapter status. Temp fix BSOD. 1342 // 1343 #define HAL_ADAPTER_STS_CHK(pDM_Odm)\ 1344 if (pDM_Odm->Adapter == NULL)\ 1345 {\ 1346 return;\ 1347 }\ 1348 1349 1350 // 1351 // For new definition in MP temporarily fro power tracking, 1352 // 1353 /* 1354 #define odm_TXPowerTrackingDirectCall(_Adapter) \ 1355 IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \ 1356 IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \ 1357 IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\ 1358 ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter) 1359 */ 1360 1361 1362 #endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1363 1364 VOID 1365 ODM_AsocEntry_Init( 1366 IN PDM_ODM_T pDM_Odm 1367 ); 1368 1369 //Remove ODM_DynamicARFBSelect() by RS_James 1370 1371 PVOID 1372 PhyDM_Get_Structure( 1373 IN PDM_ODM_T pDM_Odm, 1374 IN u1Byte Structure_Type 1375 ); 1376 1377 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE) 1378 /*===========================================================*/ 1379 /* The following is for compile only*/ 1380 /*===========================================================*/ 1381 1382 #define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE 1383 #define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE 1384 #define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE 1385 #define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE 1386 #define RF_T_METER_92D 0x42 1387 1388 1389 #define SET_TX_DESC_ANTSEL_A_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 0, 1, __Value) 1390 #define SET_TX_DESC_TX_ANTL_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 4, 2, __Value) 1391 #define SET_TX_DESC_TX_ANT_HT_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 6, 2, __Value) 1392 #define SET_TX_DESC_TX_ANT_CCK_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 2, 2, __Value) 1393 1394 #define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6) 1395 1396 #define RX_HAL_IS_CCK_RATE_92C(pDesc)\ 1397 (GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE1M ||\ 1398 GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE2M ||\ 1399 GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE5_5M ||\ 1400 GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE11M) 1401 1402 #define H2C_92C_PSD_RESULT 16 1403 1404 #define rConfig_ram64x16 0xb2c 1405 1406 #define TARGET_CHNL_NUM_2G_5G 59 1407 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1408 1409 VOID 1410 FillH2CCmd92C( 1411 IN PADAPTER Adapter, 1412 IN u1Byte ElementID, 1413 IN u4Byte CmdLen, 1414 IN pu1Byte pCmdBuffer 1415 ); 1416 VOID 1417 PHY_SetTxPowerLevel8192C( 1418 IN PADAPTER Adapter, 1419 IN u1Byte channel 1420 ); 1421 u1Byte GetRightChnlPlaceforIQK(u1Byte chnl); 1422 1423 #endif 1424 1425 //=========================================================== 1426 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1427 1428 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1429 void odm_dtc(PDM_ODM_T pDM_Odm); 1430 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ 1431 1432 1433 VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm ); 1434 1435 void 1436 phydm_receiver_blocking( 1437 IN PVOID pDM_VOID 1438 ); 1439 1440 #endif 1441 1442