Searched defs:irq_source (Results 1 – 7 of 7) sorted by relevance
84 enum dc_irq_source irq_source; member138 enum dc_irq_source irq_source; in remove_irq_handler() local208 static bool validate_irq_unregistration_params(enum dc_irq_source irq_source, in validate_irq_unregistration_params()255 enum dc_irq_source irq_source; in amdgpu_dm_irq_register_interrupt() local314 enum dc_irq_source irq_source, in amdgpu_dm_irq_unregister_interrupt()510 enum dc_irq_source irq_source) in amdgpu_dm_irq_schedule_work()566 enum dc_irq_source irq_source) in amdgpu_dm_irq_immediate_work()654 enum dc_irq_source irq_source; in dm_irq_state() local
1687 enum dc_irq_source irq_source; in dm_gpureset_toggle_interrupts() local4976 enum dc_irq_source irq_source; in dm_set_vupdate_irq() local4992 enum dc_irq_source irq_source; in dm_set_vblank() local
146 struct irq_source { struct147 uint32_t ivpr; /* IRQ vector/priority register */148 uint32_t idr; /* IRQ destination register */149 uint32_t destmask; /* bitmap of CPU destinations */150 int last_cpu;151 int output; /* IRQ level, e.g. ILR_INTTGT_INT */152 int pending; /* TRUE if IRQ is pending */153 enum irq_type type;154 bool level:1; /* level-triggered */155 bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
206 enum dc_irq_source irq_source; member
881 enum dc_irq_source irq_source; member
176 enum irq_source { enum184 int irq_source; member
390 struct amdgpu_irq_src irq_source; member