1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
3 */
4
5 #include <sys/queue.h>
6 #include <stdio.h>
7 #include <errno.h>
8 #include <stdint.h>
9 #include <stdarg.h>
10
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
15 #include <rte_log.h>
16 #include <rte_debug.h>
17 #include <rte_pci.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memory.h>
23 #include <rte_eal.h>
24 #include <rte_malloc.h>
25 #include <rte_dev.h>
26
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
30 #include "igb_regs.h"
31
32 /*
33 * Default values for port configuration
34 */
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
36
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
40
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
44
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
50
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
58
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
64
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
67
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
71
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
74
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static int eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static int eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
93 const uint64_t *ids,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
97 unsigned int size);
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names,
100 unsigned int limit);
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
125
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
127
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
132 uint16_t tpid_id);
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
134
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
141
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
144
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
153
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
158 static int igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
170 unsigned limit);
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
181
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
184 uint16_t reta_size);
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
187 uint16_t reta_size);
188
189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
196 struct rte_eth_ntuple_filter *ntuple_filter);
197 static int eth_igb_flow_ops_get(struct rte_eth_dev *dev,
198 const struct rte_flow_ops **ops);
199 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
200 static int eth_igb_get_regs(struct rte_eth_dev *dev,
201 struct rte_dev_reg_info *regs);
202 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
203 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
204 struct rte_dev_eeprom_info *eeprom);
205 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
206 struct rte_dev_eeprom_info *eeprom);
207 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
208 struct rte_eth_dev_module_info *modinfo);
209 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
210 struct rte_dev_eeprom_info *info);
211 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
212 struct rte_ether_addr *mc_addr_set,
213 uint32_t nb_mc_addr);
214 static int igb_timesync_enable(struct rte_eth_dev *dev);
215 static int igb_timesync_disable(struct rte_eth_dev *dev);
216 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
217 struct timespec *timestamp,
218 uint32_t flags);
219 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
220 struct timespec *timestamp);
221 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
222 static int igb_timesync_read_time(struct rte_eth_dev *dev,
223 struct timespec *timestamp);
224 static int igb_timesync_write_time(struct rte_eth_dev *dev,
225 const struct timespec *timestamp);
226 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
227 uint16_t queue_id);
228 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
229 uint16_t queue_id);
230 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
233 uint8_t index, uint8_t offset);
234 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
235 static void eth_igbvf_interrupt_handler(void *param);
236 static void igbvf_mbx_process(struct rte_eth_dev *dev);
237 static int igb_filter_restore(struct rte_eth_dev *dev);
238
239 /*
240 * Define VF Stats MACRO for Non "cleared on read" register
241 */
242 #define UPDATE_VF_STAT(reg, last, cur) \
243 { \
244 u32 latest = E1000_READ_REG(hw, reg); \
245 cur += (latest - last) & UINT_MAX; \
246 last = latest; \
247 }
248
249 #define IGB_FC_PAUSE_TIME 0x0680
250 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
251 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
252
253 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
254
255 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
256
257 /*
258 * The set of PCI devices this driver supports
259 */
260 static const struct rte_pci_id pci_id_igb_map[] = {
261 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
262 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
263 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
264 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
265 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
266 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
267 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
268 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
269
270 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
271 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
272 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
273
274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
275 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
280
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
302 { .vendor_id = 0, /* sentinel */ },
303 };
304
305 /*
306 * The set of PCI devices this driver supports (for 82576&I350 VF)
307 */
308 static const struct rte_pci_id pci_id_igbvf_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
313 { .vendor_id = 0, /* sentinel */ },
314 };
315
316 static const struct rte_eth_desc_lim rx_desc_lim = {
317 .nb_max = E1000_MAX_RING_DESC,
318 .nb_min = E1000_MIN_RING_DESC,
319 .nb_align = IGB_RXD_ALIGN,
320 };
321
322 static const struct rte_eth_desc_lim tx_desc_lim = {
323 .nb_max = E1000_MAX_RING_DESC,
324 .nb_min = E1000_MIN_RING_DESC,
325 .nb_align = IGB_RXD_ALIGN,
326 .nb_seg_max = IGB_TX_MAX_SEG,
327 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
328 };
329
330 static const struct eth_dev_ops eth_igb_ops = {
331 .dev_configure = eth_igb_configure,
332 .dev_start = eth_igb_start,
333 .dev_stop = eth_igb_stop,
334 .dev_set_link_up = eth_igb_dev_set_link_up,
335 .dev_set_link_down = eth_igb_dev_set_link_down,
336 .dev_close = eth_igb_close,
337 .dev_reset = eth_igb_reset,
338 .promiscuous_enable = eth_igb_promiscuous_enable,
339 .promiscuous_disable = eth_igb_promiscuous_disable,
340 .allmulticast_enable = eth_igb_allmulticast_enable,
341 .allmulticast_disable = eth_igb_allmulticast_disable,
342 .link_update = eth_igb_link_update,
343 .stats_get = eth_igb_stats_get,
344 .xstats_get = eth_igb_xstats_get,
345 .xstats_get_by_id = eth_igb_xstats_get_by_id,
346 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
347 .xstats_get_names = eth_igb_xstats_get_names,
348 .stats_reset = eth_igb_stats_reset,
349 .xstats_reset = eth_igb_xstats_reset,
350 .fw_version_get = eth_igb_fw_version_get,
351 .dev_infos_get = eth_igb_infos_get,
352 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
353 .mtu_set = eth_igb_mtu_set,
354 .vlan_filter_set = eth_igb_vlan_filter_set,
355 .vlan_tpid_set = eth_igb_vlan_tpid_set,
356 .vlan_offload_set = eth_igb_vlan_offload_set,
357 .rx_queue_setup = eth_igb_rx_queue_setup,
358 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
359 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
360 .rx_queue_release = eth_igb_rx_queue_release,
361 .tx_queue_setup = eth_igb_tx_queue_setup,
362 .tx_queue_release = eth_igb_tx_queue_release,
363 .tx_done_cleanup = eth_igb_tx_done_cleanup,
364 .dev_led_on = eth_igb_led_on,
365 .dev_led_off = eth_igb_led_off,
366 .flow_ctrl_get = eth_igb_flow_ctrl_get,
367 .flow_ctrl_set = eth_igb_flow_ctrl_set,
368 .mac_addr_add = eth_igb_rar_set,
369 .mac_addr_remove = eth_igb_rar_clear,
370 .mac_addr_set = eth_igb_default_mac_addr_set,
371 .reta_update = eth_igb_rss_reta_update,
372 .reta_query = eth_igb_rss_reta_query,
373 .rss_hash_update = eth_igb_rss_hash_update,
374 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
375 .flow_ops_get = eth_igb_flow_ops_get,
376 .set_mc_addr_list = eth_igb_set_mc_addr_list,
377 .rxq_info_get = igb_rxq_info_get,
378 .txq_info_get = igb_txq_info_get,
379 .timesync_enable = igb_timesync_enable,
380 .timesync_disable = igb_timesync_disable,
381 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
382 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
383 .get_reg = eth_igb_get_regs,
384 .get_eeprom_length = eth_igb_get_eeprom_length,
385 .get_eeprom = eth_igb_get_eeprom,
386 .set_eeprom = eth_igb_set_eeprom,
387 .get_module_info = eth_igb_get_module_info,
388 .get_module_eeprom = eth_igb_get_module_eeprom,
389 .timesync_adjust_time = igb_timesync_adjust_time,
390 .timesync_read_time = igb_timesync_read_time,
391 .timesync_write_time = igb_timesync_write_time,
392 };
393
394 /*
395 * dev_ops for virtual function, bare necessities for basic vf
396 * operation have been implemented
397 */
398 static const struct eth_dev_ops igbvf_eth_dev_ops = {
399 .dev_configure = igbvf_dev_configure,
400 .dev_start = igbvf_dev_start,
401 .dev_stop = igbvf_dev_stop,
402 .dev_close = igbvf_dev_close,
403 .promiscuous_enable = igbvf_promiscuous_enable,
404 .promiscuous_disable = igbvf_promiscuous_disable,
405 .allmulticast_enable = igbvf_allmulticast_enable,
406 .allmulticast_disable = igbvf_allmulticast_disable,
407 .link_update = eth_igb_link_update,
408 .stats_get = eth_igbvf_stats_get,
409 .xstats_get = eth_igbvf_xstats_get,
410 .xstats_get_names = eth_igbvf_xstats_get_names,
411 .stats_reset = eth_igbvf_stats_reset,
412 .xstats_reset = eth_igbvf_stats_reset,
413 .vlan_filter_set = igbvf_vlan_filter_set,
414 .dev_infos_get = eth_igbvf_infos_get,
415 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
416 .rx_queue_setup = eth_igb_rx_queue_setup,
417 .rx_queue_release = eth_igb_rx_queue_release,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .set_mc_addr_list = eth_igb_set_mc_addr_list,
422 .rxq_info_get = igb_rxq_info_get,
423 .txq_info_get = igb_txq_info_get,
424 .mac_addr_set = igbvf_default_mac_addr_set,
425 .get_reg = igbvf_get_regs,
426 };
427
428 /* store statistics names and its offset in stats structure */
429 struct rte_igb_xstats_name_off {
430 char name[RTE_ETH_XSTATS_NAME_SIZE];
431 unsigned offset;
432 };
433
434 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
435 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
436 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
437 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
438 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
439 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
440 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
441 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
442 ecol)},
443 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
444 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
445 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
446 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
447 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
448 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
449 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
450 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
451 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
452 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
453 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
454 fcruc)},
455 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
456 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
457 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
458 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
459 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
460 prc1023)},
461 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
462 prc1522)},
463 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
464 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
465 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
466 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
467 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
468 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
469 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
470 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
471 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
472 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
473 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
474 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
475 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
476 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
477 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
478 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
479 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
480 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
481 ptc1023)},
482 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
483 ptc1522)},
484 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
485 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
486 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
487 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
488 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
489 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
490 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
491
492 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
493 };
494
495 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
496 sizeof(rte_igb_stats_strings[0]))
497
498 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
499 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
500 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
501 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
502 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
503 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
504 };
505
506 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
507 sizeof(rte_igbvf_stats_strings[0]))
508
509
510 static inline void
igb_intr_enable(struct rte_eth_dev * dev)511 igb_intr_enable(struct rte_eth_dev *dev)
512 {
513 struct e1000_interrupt *intr =
514 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
518 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
519
520 if (rte_intr_allow_others(intr_handle) &&
521 dev->data->dev_conf.intr_conf.lsc != 0) {
522 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
523 }
524
525 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
526 E1000_WRITE_FLUSH(hw);
527 }
528
529 static void
igb_intr_disable(struct rte_eth_dev * dev)530 igb_intr_disable(struct rte_eth_dev *dev)
531 {
532 struct e1000_hw *hw =
533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
535 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
536
537 if (rte_intr_allow_others(intr_handle) &&
538 dev->data->dev_conf.intr_conf.lsc != 0) {
539 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
540 }
541
542 E1000_WRITE_REG(hw, E1000_IMC, ~0);
543 E1000_WRITE_FLUSH(hw);
544 }
545
546 static inline void
igbvf_intr_enable(struct rte_eth_dev * dev)547 igbvf_intr_enable(struct rte_eth_dev *dev)
548 {
549 struct e1000_hw *hw =
550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
551
552 /* only for mailbox */
553 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
554 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
555 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
556 E1000_WRITE_FLUSH(hw);
557 }
558
559 /* only for mailbox now. If RX/TX needed, should extend this function. */
560 static void
igbvf_set_ivar_map(struct e1000_hw * hw,uint8_t msix_vector)561 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
562 {
563 uint32_t tmp = 0;
564
565 /* mailbox */
566 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
567 tmp |= E1000_VTIVAR_VALID;
568 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
569 }
570
571 static void
eth_igbvf_configure_msix_intr(struct rte_eth_dev * dev)572 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
573 {
574 struct e1000_hw *hw =
575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
576
577 /* Configure VF other cause ivar */
578 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
579 }
580
581 static inline int32_t
igb_pf_reset_hw(struct e1000_hw * hw)582 igb_pf_reset_hw(struct e1000_hw *hw)
583 {
584 uint32_t ctrl_ext;
585 int32_t status;
586
587 status = e1000_reset_hw(hw);
588
589 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
590 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
591 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
592 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
593 E1000_WRITE_FLUSH(hw);
594
595 return status;
596 }
597
598 static void
igb_identify_hardware(struct rte_eth_dev * dev,struct rte_pci_device * pci_dev)599 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
600 {
601 struct e1000_hw *hw =
602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
603
604
605 hw->vendor_id = pci_dev->id.vendor_id;
606 hw->device_id = pci_dev->id.device_id;
607 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
608 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
609
610 e1000_set_mac_type(hw);
611
612 /* need to check if it is a vf device below */
613 }
614
615 static int
igb_reset_swfw_lock(struct e1000_hw * hw)616 igb_reset_swfw_lock(struct e1000_hw *hw)
617 {
618 int ret_val;
619
620 /*
621 * Do mac ops initialization manually here, since we will need
622 * some function pointers set by this call.
623 */
624 ret_val = e1000_init_mac_params(hw);
625 if (ret_val)
626 return ret_val;
627
628 /*
629 * SMBI lock should not fail in this early stage. If this is the case,
630 * it is due to an improper exit of the application.
631 * So force the release of the faulty lock.
632 */
633 if (e1000_get_hw_semaphore_generic(hw) < 0) {
634 PMD_DRV_LOG(DEBUG, "SMBI lock released");
635 }
636 e1000_put_hw_semaphore_generic(hw);
637
638 if (hw->mac.ops.acquire_swfw_sync != NULL) {
639 uint16_t mask;
640
641 /*
642 * Phy lock should not fail in this early stage. If this is the case,
643 * it is due to an improper exit of the application.
644 * So force the release of the faulty lock.
645 */
646 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
647 if (hw->bus.func > E1000_FUNC_1)
648 mask <<= 2;
649 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
650 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
651 hw->bus.func);
652 }
653 hw->mac.ops.release_swfw_sync(hw, mask);
654
655 /*
656 * This one is more tricky since it is common to all ports; but
657 * swfw_sync retries last long enough (1s) to be almost sure that if
658 * lock can not be taken it is due to an improper lock of the
659 * semaphore.
660 */
661 mask = E1000_SWFW_EEP_SM;
662 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
663 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
664 }
665 hw->mac.ops.release_swfw_sync(hw, mask);
666 }
667
668 return E1000_SUCCESS;
669 }
670
671 /* Remove all ntuple filters of the device */
igb_ntuple_filter_uninit(struct rte_eth_dev * eth_dev)672 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
673 {
674 struct e1000_filter_info *filter_info =
675 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
676 struct e1000_5tuple_filter *p_5tuple;
677 struct e1000_2tuple_filter *p_2tuple;
678
679 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
680 TAILQ_REMOVE(&filter_info->fivetuple_list,
681 p_5tuple, entries);
682 rte_free(p_5tuple);
683 }
684 filter_info->fivetuple_mask = 0;
685 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
686 TAILQ_REMOVE(&filter_info->twotuple_list,
687 p_2tuple, entries);
688 rte_free(p_2tuple);
689 }
690 filter_info->twotuple_mask = 0;
691
692 return 0;
693 }
694
695 /* Remove all flex filters of the device */
igb_flex_filter_uninit(struct rte_eth_dev * eth_dev)696 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
697 {
698 struct e1000_filter_info *filter_info =
699 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
700 struct e1000_flex_filter *p_flex;
701
702 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
703 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
704 rte_free(p_flex);
705 }
706 filter_info->flex_mask = 0;
707
708 return 0;
709 }
710
711 static int uio_cnt = 0;;
712 uint64_t base_hw_addr = 0;
713 static int rconfig_stmmac_uio(uint64_t hw_addr);
714 uint32_t igb_gbd_addr_b_p[4];
715 uint32_t igb_gbd_addr_r_p[4];
716 uint32_t igb_gbd_addr_t_p[4];
717 uint32_t igb_gbd_addr_x_p[4];
718
719 void *igb_gbd_addr_b_v[4];
720 void *igb_gbd_addr_t_v[4];
721 void *igb_gbd_addr_r_v[4];
722 void *igb_gbd_addr_x_v[4];
723
724 unsigned int igb_gbd_b_size[4];
725 unsigned int igb_gbd_r_size[4];
726 unsigned int igb_gbd_t_size[4];
727 unsigned int igb_gbd_x_size[4];
728 static int
eth_igb_dev_init(struct rte_eth_dev * eth_dev)729 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
730 {
731 int error = 0;
732 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
733 struct e1000_hw *hw =
734 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
735 struct e1000_vfta * shadow_vfta =
736 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
737 struct e1000_filter_info *filter_info =
738 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
739 struct e1000_adapter *adapter =
740 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
741
742 uint32_t ctrl_ext;
743 uint64_t index;
744
745 eth_dev->dev_ops = ð_igb_ops;
746 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
747 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
748 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
749 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
750 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
751 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
752
753 /* for secondary processes, we don't initialise any further as primary
754 * has already done this work. Only check we don't need a different
755 * RX function */
756 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
757 if (eth_dev->data->scattered_rx)
758 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
759 return 0;
760 }
761
762 rte_eth_copy_pci_info(eth_dev, pci_dev);
763
764 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
765 //hw->hw_addr= gbd_addr_b_v;
766
767 printf("eth_igb_dev_init\n");
768 if (rconfig_stmmac_uio((uint64_t)hw->hw_addr)) {
769 error = -EIO;
770 goto err_late;
771 }
772
773 index = ((uint64_t)hw->hw_addr - base_hw_addr) / 0x104000;
774 printf("addr1 %p:%p\n", pci_dev->mem_resource[0].addr, igb_gbd_addr_b_v[index]);
775 printf("addr2 0x%lx:0x%x\n", pci_dev->mem_resource[0].phys_addr, igb_gbd_addr_b_p[index]);
776
777 igb_identify_hardware(eth_dev, pci_dev);
778 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
779 error = -EIO;
780 goto err_late;
781 }
782
783 e1000_get_bus_info(hw);
784
785 /* Reset any pending lock */
786 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
787 error = -EIO;
788 goto err_late;
789 }
790
791 /* Finish initialization */
792 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
793 error = -EIO;
794 goto err_late;
795 }
796
797 hw->mac.autoneg = 1;
798 hw->phy.autoneg_wait_to_complete = 0;
799 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
800
801 /* Copper options */
802 if (hw->phy.media_type == e1000_media_type_copper) {
803 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
804 hw->phy.disable_polarity_correction = 0;
805 hw->phy.ms_type = e1000_ms_hw_default;
806 }
807
808 /*
809 * Start from a known state, this is important in reading the nvm
810 * and mac from that.
811 */
812 igb_pf_reset_hw(hw);
813
814 /* Make sure we have a good EEPROM before we read from it */
815 if (e1000_validate_nvm_checksum(hw) < 0) {
816 /*
817 * Some PCI-E parts fail the first check due to
818 * the link being in sleep state, call it again,
819 * if it fails a second time its a real issue.
820 */
821 if (e1000_validate_nvm_checksum(hw) < 0) {
822 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
823 error = -EIO;
824 goto err_late;
825 }
826 }
827
828 /* Read the permanent MAC address out of the EEPROM */
829 if (e1000_read_mac_addr(hw) != 0) {
830 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
831 error = -EIO;
832 goto err_late;
833 }
834
835 /* Allocate memory for storing MAC addresses */
836 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
837 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
838 if (eth_dev->data->mac_addrs == NULL) {
839 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
840 "store MAC addresses",
841 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
842 error = -ENOMEM;
843 goto err_late;
844 }
845
846 /* Copy the permanent MAC address */
847 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
848 ð_dev->data->mac_addrs[0]);
849
850 /* initialize the vfta */
851 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
852
853 /* Now initialize the hardware */
854 if (igb_hardware_init(hw) != 0) {
855 PMD_INIT_LOG(ERR, "Hardware initialization failed");
856 rte_free(eth_dev->data->mac_addrs);
857 eth_dev->data->mac_addrs = NULL;
858 error = -ENODEV;
859 goto err_late;
860 }
861 hw->mac.get_link_status = 1;
862 adapter->stopped = 0;
863
864 /* Indicate SOL/IDER usage */
865 if (e1000_check_reset_block(hw) < 0) {
866 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
867 "SOL/IDER session");
868 }
869
870 /* initialize PF if max_vfs not zero */
871 igb_pf_host_init(eth_dev);
872
873 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
874 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
875 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
876 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
877 E1000_WRITE_FLUSH(hw);
878
879 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
880 eth_dev->data->port_id, pci_dev->id.vendor_id,
881 pci_dev->id.device_id);
882
883 rte_intr_callback_register(pci_dev->intr_handle,
884 eth_igb_interrupt_handler,
885 (void *)eth_dev);
886
887 /* enable uio/vfio intr/eventfd mapping */
888 rte_intr_enable(pci_dev->intr_handle);
889
890 /* enable support intr */
891 igb_intr_enable(eth_dev);
892
893 eth_igb_dev_set_link_down(eth_dev);
894
895 /* initialize filter info */
896 memset(filter_info, 0,
897 sizeof(struct e1000_filter_info));
898
899 TAILQ_INIT(&filter_info->flex_list);
900 TAILQ_INIT(&filter_info->twotuple_list);
901 TAILQ_INIT(&filter_info->fivetuple_list);
902
903 TAILQ_INIT(&igb_filter_ntuple_list);
904 TAILQ_INIT(&igb_filter_ethertype_list);
905 TAILQ_INIT(&igb_filter_syn_list);
906 TAILQ_INIT(&igb_filter_flex_list);
907 TAILQ_INIT(&igb_filter_rss_list);
908 TAILQ_INIT(&igb_flow_list);
909
910 return 0;
911
912 err_late:
913 igb_hw_control_release(hw);
914
915 return error;
916 }
917
918 static int
eth_igb_dev_uninit(struct rte_eth_dev * eth_dev)919 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
920 {
921 PMD_INIT_FUNC_TRACE();
922
923 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
924 return 0;
925
926 eth_igb_close(eth_dev);
927
928 return 0;
929 }
930 #include <sys/mman.h>
931 #include <fcntl.h>
932
933 #define STMMAC_UIO_MAX_DEVICE_FILE_NAME_LENGTH 30
934 #define STMMAC_UIO_MAX_ATTR_FILE_NAME 100
935 #define STMMAC_UIO_DEVICE_SYS_ATTR_PATH "/sys/class/uio"
936 #define STMMAC_UIO_DEVICE_SYS_MAP_ATTR "maps/map"
937 #define STMMAC_UIO_DEVICE_FILE_NAME "/dev/uio"
938 #define STMMAC_UIO_REG_MAP_ID 0
939 #define STMMAC_UIO_RX_BD_MAP_ID 1
940 #define STMMAC_UIO_TX_BD_MAP_ID 2
941 #define STMMAC_UIO_RX_BD1_MAP_ID 3
942 #define STMMAC_UIO_TX_BD1_MAP_ID 4
943
944 struct uio_job {
945 uint32_t fec_id;
946 int uio_fd;
947 void *bd_start_addr;
948 void *register_base_addr;
949 int map_size;
950 uint64_t map_addr;
951 int uio_minor_number;
952 };
953 static struct uio_job guio_job;
954
955 /*
956 * @brief Reads first line from a file.
957 * Composes file name as: root/subdir/filename
958 *
959 * @param [in] root Root path
960 * @param [in] subdir Subdirectory name
961 * @param [in] filename File name
962 * @param [out] line The first line read from file.
963 *
964 * @retval 0 for success
965 * @retval other value for error
966 */
967 static int
file_read_first_line(const char root[],const char subdir[],const char filename[],char * line)968 file_read_first_line(const char root[], const char subdir[],
969 const char filename[], char *line)
970 {
971 char absolute_file_name[STMMAC_UIO_MAX_ATTR_FILE_NAME];
972 int fd = 0, ret = 0;
973
974 /*compose the file name: root/subdir/filename */
975 memset(absolute_file_name, 0, sizeof(absolute_file_name));
976 snprintf(absolute_file_name, STMMAC_UIO_MAX_ATTR_FILE_NAME,
977 "%s/%s/%s", root, subdir, filename);
978
979 fd = open(absolute_file_name, O_RDONLY);
980 if (fd <= 0)
981 printf("Error opening file %s\n", absolute_file_name);
982
983 /* read UIO device name from first line in file */
984 ret = read(fd, line, STMMAC_UIO_MAX_DEVICE_FILE_NAME_LENGTH);
985 if (ret <= 0) {
986 printf("Error reading file %s\n", absolute_file_name);
987 return ret;
988 }
989 close(fd);
990
991 /* NULL-ify string */
992 line[ret] = '\0';
993
994 return 0;
995 }
996
997 /*
998 * @brief Maps rx-tx bd range assigned for a bd ring.
999 *
1000 * @param [in] uio_device_fd UIO device file descriptor
1001 * @param [in] uio_device_id UIO device id
1002 * @param [in] uio_map_id UIO allows maximum 5 different mapping for
1003 each device. Maps start with id 0.
1004 * @param [out] map_size Map size.
1005 * @param [out] map_addr Map physical address
1006 *
1007 * @retval NULL if failed to map registers
1008 * @retval Virtual address for mapped register address range
1009 */
1010 static void *
guio_map_mem(int uio_device_fd,int uio_device_id,int uio_map_id,int * map_size,uint64_t * map_addr)1011 guio_map_mem(int uio_device_fd, int uio_device_id,
1012 int uio_map_id, int *map_size, uint64_t *map_addr)
1013 {
1014 void *mapped_address = NULL;
1015 unsigned int uio_map_size = 0;
1016 unsigned int uio_map_p_addr = 0;
1017 char uio_sys_root[100];
1018 char uio_sys_map_subdir[100];
1019 char uio_map_size_str[30 + 1];
1020 char uio_map_p_addr_str[32];
1021 int ret = 0;
1022
1023 /* compose the file name: root/subdir/filename */
1024 memset(uio_sys_root, 0, sizeof(uio_sys_root));
1025 memset(uio_sys_map_subdir, 0, sizeof(uio_sys_map_subdir));
1026 memset(uio_map_size_str, 0, sizeof(uio_map_size_str));
1027 memset(uio_map_p_addr_str, 0, sizeof(uio_map_p_addr_str));
1028
1029 /* Compose string: /sys/class/uio/uioX */
1030 snprintf(uio_sys_root, sizeof(uio_sys_root), "%s/%s%d",
1031 "/sys/class/uio", "uio", uio_device_id);
1032 /* Compose string: maps/mapY */
1033 snprintf(uio_sys_map_subdir, sizeof(uio_sys_map_subdir), "%s%d",
1034 "maps/map", uio_map_id);
1035
1036 printf("US_UIO: uio_map_mem uio_sys_root: %s, uio_sys_map_subdir: %s, uio_map_size_str: %s\n",
1037 uio_sys_root, uio_sys_map_subdir, uio_map_size_str);
1038
1039 /* Read first (and only) line from file
1040 * /sys/class/uio/uioX/maps/mapY/size
1041 */
1042 ret = file_read_first_line(uio_sys_root, uio_sys_map_subdir,
1043 "size", uio_map_size_str);
1044 if (ret < 0) {
1045 printf("file_read_first_line() failed\n");
1046 return NULL;
1047 }
1048 ret = file_read_first_line(uio_sys_root, uio_sys_map_subdir,
1049 "addr", uio_map_p_addr_str);
1050 if (ret < 0) {
1051 printf("file_read_first_line() failed\n");
1052 return NULL;
1053 }
1054
1055 /* Read mapping size and physical address expressed in hexa(base 16) */
1056 uio_map_size = strtol(uio_map_size_str, NULL, 16);
1057 uio_map_p_addr = strtol(uio_map_p_addr_str, NULL, 16);
1058 printf("size: 0x%x, addr: 0x%x\n", uio_map_size, uio_map_p_addr);
1059
1060 /* Map the BD memory in user space */
1061 mapped_address = mmap(NULL, uio_map_size,
1062 PROT_READ | PROT_WRITE,
1063 MAP_SHARED, uio_device_fd, (uio_map_id * 4096));
1064
1065 if (mapped_address == MAP_FAILED) {
1066 printf("Failed to map! errno = %d uio job fd = %d,"
1067 "uio device id = %d, uio map id = %d\n", errno,
1068 uio_device_fd, uio_device_id, uio_map_id);
1069 return NULL;
1070 }
1071
1072 /* Save the map size to use it later on for munmap-ing */
1073 *map_size = uio_map_size;
1074 *map_addr = uio_map_p_addr;
1075
1076 printf("UIO dev[%d] mapped region [id =%d] size 0x%x map_addr_p: 0x%lx, at %p\n",
1077 uio_device_id, uio_map_id, uio_map_size, *map_addr, mapped_address);
1078
1079 printf("UIO dev[%d] mapped region [id =%d] size 0x%x at phy 0x%lx\n",
1080 uio_device_id, uio_map_id, uio_map_size, rte_mem_virt2phy(mapped_address));
1081
1082 return mapped_address;
1083 }
1084
1085 static int
rconfig_stmmac_uio(uint64_t hw_addr)1086 rconfig_stmmac_uio(uint64_t hw_addr)
1087 {
1088 char uio_device_file_name[32];
1089 uint64_t addr;
1090 int index;
1091
1092 printf("rconfig_stmmac_uio\n");
1093
1094 if (base_hw_addr == 0) {
1095 base_hw_addr = hw_addr;
1096 addr = hw_addr;
1097 } else {
1098 addr = hw_addr;
1099 }
1100
1101 index = (addr - base_hw_addr) / 0x104000;
1102 printf("index: %d, hw_addr: 0x%lx, base_hw_addr: 0x%lx\n", index, addr, base_hw_addr);
1103 if ((index < 0) && (index > 3))
1104 return -1;
1105
1106 snprintf(uio_device_file_name, sizeof(uio_device_file_name), "/dev/uio%d",
1107 uio_cnt);
1108
1109 /* Open device file */
1110 guio_job.uio_fd = open(uio_device_file_name, O_RDWR);
1111 if (guio_job.uio_fd < 0) {
1112 printf("Unable to open STMMAC_UIO file\n");
1113 return -1;
1114 }
1115
1116 igb_gbd_addr_b_v[index] = guio_map_mem(guio_job.uio_fd,
1117 uio_cnt, 0,
1118 &guio_job.map_size, &guio_job.map_addr);
1119 if (igb_gbd_addr_b_v[index] == NULL)
1120 return -ENOMEM;
1121 igb_gbd_addr_b_p[index] = (uint32_t)guio_job.map_addr;
1122 igb_gbd_b_size[index] = guio_job.map_size;
1123
1124 igb_gbd_addr_r_v[index] = guio_map_mem(guio_job.uio_fd,
1125 uio_cnt, 2,
1126 &guio_job.map_size, &guio_job.map_addr);
1127 if (igb_gbd_addr_r_v[index] == NULL)
1128 return -ENOMEM;
1129 igb_gbd_addr_r_p[index] = (uint32_t)guio_job.map_addr;
1130 igb_gbd_r_size[index] = guio_job.map_size;
1131
1132 igb_gbd_addr_t_v[index] = guio_map_mem(guio_job.uio_fd,
1133 uio_cnt, 3,
1134 &guio_job.map_size, &guio_job.map_addr);
1135 if (igb_gbd_addr_t_v[index] == NULL)
1136 return -ENOMEM;
1137 igb_gbd_addr_t_p[index] = (uint32_t)guio_job.map_addr;
1138 igb_gbd_t_size[index] = guio_job.map_size;
1139
1140 igb_gbd_addr_x_v[index] = guio_map_mem(guio_job.uio_fd,
1141 uio_cnt, 4,
1142 &guio_job.map_size, &guio_job.map_addr);
1143 if (igb_gbd_addr_x_v[index] == NULL)
1144 return -ENOMEM;
1145 igb_gbd_addr_x_p[index] = (uint32_t)guio_job.map_addr;
1146 igb_gbd_x_size[index] = guio_job.map_size;
1147
1148 uio_cnt++;
1149
1150 return 0;
1151 }
1152
1153 /*
1154 * Virtual Function device init
1155 */
1156 static int
eth_igbvf_dev_init(struct rte_eth_dev * eth_dev)1157 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1158 {
1159 struct rte_pci_device *pci_dev;
1160 struct rte_intr_handle *intr_handle;
1161 struct e1000_adapter *adapter =
1162 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1163 struct e1000_hw *hw =
1164 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1165 int diag;
1166 struct rte_ether_addr *perm_addr =
1167 (struct rte_ether_addr *)hw->mac.perm_addr;
1168
1169 PMD_INIT_FUNC_TRACE();
1170
1171 eth_dev->dev_ops = &igbvf_eth_dev_ops;
1172 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
1173 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
1174 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
1175 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
1176 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
1177
1178 /* for secondary processes, we don't initialise any further as primary
1179 * has already done this work. Only check we don't need a different
1180 * RX function */
1181 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1182 if (eth_dev->data->scattered_rx)
1183 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1184 return 0;
1185 }
1186
1187 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1188 rte_eth_copy_pci_info(eth_dev, pci_dev);
1189
1190 hw->device_id = pci_dev->id.device_id;
1191 hw->vendor_id = pci_dev->id.vendor_id;
1192 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1193 adapter->stopped = 0;
1194
1195 /* Initialize the shared code (base driver) */
1196 diag = e1000_setup_init_funcs(hw, TRUE);
1197 if (diag != 0) {
1198 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1199 diag);
1200 return -EIO;
1201 }
1202
1203 /* init_mailbox_params */
1204 hw->mbx.ops.init_params(hw);
1205
1206 /* Disable the interrupts for VF */
1207 igbvf_intr_disable(hw);
1208
1209 diag = hw->mac.ops.reset_hw(hw);
1210
1211 /* Allocate memory for storing MAC addresses */
1212 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
1213 hw->mac.rar_entry_count, 0);
1214 if (eth_dev->data->mac_addrs == NULL) {
1215 PMD_INIT_LOG(ERR,
1216 "Failed to allocate %d bytes needed to store MAC "
1217 "addresses",
1218 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1219 return -ENOMEM;
1220 }
1221
1222 /* Generate a random MAC address, if none was assigned by PF. */
1223 if (rte_is_zero_ether_addr(perm_addr)) {
1224 rte_eth_random_addr(perm_addr->addr_bytes);
1225 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1226 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1227 RTE_ETHER_ADDR_PRT_FMT,
1228 RTE_ETHER_ADDR_BYTES(perm_addr));
1229 }
1230
1231 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1232 if (diag) {
1233 rte_free(eth_dev->data->mac_addrs);
1234 eth_dev->data->mac_addrs = NULL;
1235 return diag;
1236 }
1237 /* Copy the permanent MAC address */
1238 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1239 ð_dev->data->mac_addrs[0]);
1240
1241 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1242 "mac.type=%s",
1243 eth_dev->data->port_id, pci_dev->id.vendor_id,
1244 pci_dev->id.device_id, "igb_mac_82576_vf");
1245
1246 intr_handle = pci_dev->intr_handle;
1247 rte_intr_callback_register(intr_handle,
1248 eth_igbvf_interrupt_handler, eth_dev);
1249
1250 return 0;
1251 }
1252
1253 static int
eth_igbvf_dev_uninit(struct rte_eth_dev * eth_dev)1254 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1255 {
1256 PMD_INIT_FUNC_TRACE();
1257
1258 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1259 return 0;
1260
1261 igbvf_dev_close(eth_dev);
1262
1263 return 0;
1264 }
1265
eth_igb_pci_probe(struct rte_pci_driver * pci_drv __rte_unused,struct rte_pci_device * pci_dev)1266 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1267 struct rte_pci_device *pci_dev)
1268 {
1269 return rte_eth_dev_pci_generic_probe(pci_dev,
1270 sizeof(struct e1000_adapter), eth_igb_dev_init);
1271 }
1272
eth_igb_pci_remove(struct rte_pci_device * pci_dev)1273 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1274 {
1275 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1276 }
1277
1278 static struct rte_pci_driver rte_igb_pmd = {
1279 .id_table = pci_id_igb_map,
1280 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1281 .probe = eth_igb_pci_probe,
1282 .remove = eth_igb_pci_remove,
1283 };
1284
1285
eth_igbvf_pci_probe(struct rte_pci_driver * pci_drv __rte_unused,struct rte_pci_device * pci_dev)1286 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1287 struct rte_pci_device *pci_dev)
1288 {
1289 return rte_eth_dev_pci_generic_probe(pci_dev,
1290 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1291 }
1292
eth_igbvf_pci_remove(struct rte_pci_device * pci_dev)1293 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1294 {
1295 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1296 }
1297
1298 /*
1299 * virtual function driver struct
1300 */
1301 static struct rte_pci_driver rte_igbvf_pmd = {
1302 .id_table = pci_id_igbvf_map,
1303 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1304 .probe = eth_igbvf_pci_probe,
1305 .remove = eth_igbvf_pci_remove,
1306 };
1307
1308 static void
igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev * dev)1309 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1310 {
1311 struct e1000_hw *hw =
1312 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1314 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1315 rctl |= E1000_RCTL_VFE;
1316 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1317 }
1318
1319 static int
igb_check_mq_mode(struct rte_eth_dev * dev)1320 igb_check_mq_mode(struct rte_eth_dev *dev)
1321 {
1322 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1323 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1324 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1325 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1326
1327 if ((rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) ||
1328 tx_mq_mode == RTE_ETH_MQ_TX_DCB ||
1329 tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) {
1330 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1331 return -EINVAL;
1332 }
1333 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1334 /* Check multi-queue mode.
1335 * To no break software we accept RTE_ETH_MQ_RX_NONE as this might
1336 * be used to turn off VLAN filter.
1337 */
1338
1339 if (rx_mq_mode == RTE_ETH_MQ_RX_NONE ||
1340 rx_mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) {
1341 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_ONLY;
1342 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1343 } else {
1344 /* Only support one queue on VFs.
1345 * RSS together with SRIOV is not supported.
1346 */
1347 PMD_INIT_LOG(ERR, "SRIOV is active,"
1348 " wrong mq_mode rx %d.",
1349 rx_mq_mode);
1350 return -EINVAL;
1351 }
1352 /* TX mode is not used here, so mode might be ignored.*/
1353 if (tx_mq_mode != RTE_ETH_MQ_TX_VMDQ_ONLY) {
1354 /* SRIOV only works in VMDq enable mode */
1355 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1356 " TX mode %d is not supported. "
1357 " Driver will behave as %d mode.",
1358 tx_mq_mode, RTE_ETH_MQ_TX_VMDQ_ONLY);
1359 }
1360
1361 /* check valid queue number */
1362 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1363 PMD_INIT_LOG(ERR, "SRIOV is active,"
1364 " only support one queue on VFs.");
1365 return -EINVAL;
1366 }
1367 } else {
1368 /* To no break software that set invalid mode, only display
1369 * warning if invalid mode is used.
1370 */
1371 if (rx_mq_mode != RTE_ETH_MQ_RX_NONE &&
1372 rx_mq_mode != RTE_ETH_MQ_RX_VMDQ_ONLY &&
1373 rx_mq_mode != RTE_ETH_MQ_RX_RSS) {
1374 /* RSS together with VMDq not supported*/
1375 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1376 rx_mq_mode);
1377 return -EINVAL;
1378 }
1379
1380 if (tx_mq_mode != RTE_ETH_MQ_TX_NONE &&
1381 tx_mq_mode != RTE_ETH_MQ_TX_VMDQ_ONLY) {
1382 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1383 " Due to txmode is meaningless in this"
1384 " driver, just ignore.",
1385 tx_mq_mode);
1386 }
1387 }
1388 return 0;
1389 }
1390
1391 static int
eth_igb_configure(struct rte_eth_dev * dev)1392 eth_igb_configure(struct rte_eth_dev *dev)
1393 {
1394 struct e1000_interrupt *intr =
1395 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1396 int ret;
1397
1398 PMD_INIT_FUNC_TRACE();
1399
1400 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1401 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1402
1403 /* multipe queue mode checking */
1404 ret = igb_check_mq_mode(dev);
1405 if (ret != 0) {
1406 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1407 ret);
1408 return ret;
1409 }
1410
1411 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1412 PMD_INIT_FUNC_TRACE();
1413
1414 return 0;
1415 }
1416
1417 static void
eth_igb_rxtx_control(struct rte_eth_dev * dev,bool enable)1418 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1419 bool enable)
1420 {
1421 struct e1000_hw *hw =
1422 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1423 uint32_t tctl, rctl;
1424
1425 tctl = E1000_READ_REG(hw, E1000_TCTL);
1426 rctl = E1000_READ_REG(hw, E1000_RCTL);
1427
1428 if (enable) {
1429 /* enable Tx/Rx */
1430 tctl |= E1000_TCTL_EN;
1431 rctl |= E1000_RCTL_EN;
1432 } else {
1433 /* disable Tx/Rx */
1434 tctl &= ~E1000_TCTL_EN;
1435 rctl &= ~E1000_RCTL_EN;
1436 }
1437 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1438 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1439 E1000_WRITE_FLUSH(hw);
1440 }
1441
1442 static int
eth_igb_start(struct rte_eth_dev * dev)1443 eth_igb_start(struct rte_eth_dev *dev)
1444 {
1445 struct e1000_hw *hw =
1446 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1447 struct e1000_adapter *adapter =
1448 E1000_DEV_PRIVATE(dev->data->dev_private);
1449 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1450 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1451 int ret, mask;
1452 uint32_t intr_vector = 0;
1453 uint32_t ctrl_ext;
1454 uint32_t *speeds;
1455 int num_speeds;
1456 bool autoneg;
1457
1458 PMD_INIT_FUNC_TRACE();
1459
1460 /* disable uio/vfio intr/eventfd mapping */
1461 rte_intr_disable(intr_handle);
1462
1463 /* Power up the phy. Needed to make the link go Up */
1464 eth_igb_dev_set_link_up(dev);
1465
1466 /*
1467 * Packet Buffer Allocation (PBA)
1468 * Writing PBA sets the receive portion of the buffer
1469 * the remainder is used for the transmit buffer.
1470 */
1471 if (hw->mac.type == e1000_82575) {
1472 uint32_t pba;
1473
1474 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1475 E1000_WRITE_REG(hw, E1000_PBA, pba);
1476 }
1477
1478 /* Put the address into the Receive Address Array */
1479 e1000_rar_set(hw, hw->mac.addr, 0);
1480
1481 /* Initialize the hardware */
1482 if (igb_hardware_init(hw)) {
1483 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1484 return -EIO;
1485 }
1486 adapter->stopped = 0;
1487
1488 E1000_WRITE_REG(hw, E1000_VET,
1489 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1490
1491 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1492 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1493 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1494 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1495 E1000_WRITE_FLUSH(hw);
1496
1497 /* configure PF module if SRIOV enabled */
1498 igb_pf_host_configure(dev);
1499
1500 /* check and configure queue intr-vector mapping */
1501 if ((rte_intr_cap_multiple(intr_handle) ||
1502 !RTE_ETH_DEV_SRIOV(dev).active) &&
1503 dev->data->dev_conf.intr_conf.rxq != 0) {
1504 intr_vector = dev->data->nb_rx_queues;
1505 if (rte_intr_efd_enable(intr_handle, intr_vector))
1506 return -1;
1507 }
1508
1509 /* Allocate the vector list */
1510 if (rte_intr_dp_is_en(intr_handle)) {
1511 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
1512 dev->data->nb_rx_queues)) {
1513 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1514 " intr_vec", dev->data->nb_rx_queues);
1515 return -ENOMEM;
1516 }
1517 }
1518
1519 /* confiugre msix for rx interrupt */
1520 eth_igb_configure_msix_intr(dev);
1521
1522 /* Configure for OS presence */
1523 igb_init_manageability(hw);
1524
1525 eth_igb_tx_init(dev);
1526
1527 /* This can fail when allocating mbufs for descriptor rings */
1528 ret = eth_igb_rx_init(dev);
1529 if (ret) {
1530 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1531 igb_dev_clear_queues(dev);
1532 return ret;
1533 }
1534
1535 e1000_clear_hw_cntrs_base_generic(hw);
1536
1537 /*
1538 * VLAN Offload Settings
1539 */
1540 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
1541 RTE_ETH_VLAN_EXTEND_MASK;
1542 ret = eth_igb_vlan_offload_set(dev, mask);
1543 if (ret) {
1544 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1545 igb_dev_clear_queues(dev);
1546 return ret;
1547 }
1548
1549 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) {
1550 /* Enable VLAN filter since VMDq always use VLAN filter */
1551 igb_vmdq_vlan_hw_filter_enable(dev);
1552 }
1553
1554 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1555 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1556 (hw->mac.type == e1000_i211)) {
1557 /* Configure EITR with the maximum possible value (0xFFFF) */
1558 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1559 }
1560
1561 /* Setup link speed and duplex */
1562 speeds = &dev->data->dev_conf.link_speeds;
1563 if (*speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
1564 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1565 hw->mac.autoneg = 1;
1566 } else {
1567 num_speeds = 0;
1568 autoneg = (*speeds & RTE_ETH_LINK_SPEED_FIXED) == 0;
1569
1570 /* Reset */
1571 hw->phy.autoneg_advertised = 0;
1572
1573 if (*speeds & ~(RTE_ETH_LINK_SPEED_10M_HD | RTE_ETH_LINK_SPEED_10M |
1574 RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M |
1575 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_FIXED)) {
1576 num_speeds = -1;
1577 goto error_invalid_config;
1578 }
1579 if (*speeds & RTE_ETH_LINK_SPEED_10M_HD) {
1580 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1581 num_speeds++;
1582 }
1583 if (*speeds & RTE_ETH_LINK_SPEED_10M) {
1584 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1585 num_speeds++;
1586 }
1587 if (*speeds & RTE_ETH_LINK_SPEED_100M_HD) {
1588 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1589 num_speeds++;
1590 }
1591 if (*speeds & RTE_ETH_LINK_SPEED_100M) {
1592 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1593 num_speeds++;
1594 }
1595 if (*speeds & RTE_ETH_LINK_SPEED_1G) {
1596 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1597 num_speeds++;
1598 }
1599 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1600 goto error_invalid_config;
1601
1602 /* Set/reset the mac.autoneg based on the link speed,
1603 * fixed or not
1604 */
1605 if (!autoneg) {
1606 hw->mac.autoneg = 0;
1607 hw->mac.forced_speed_duplex =
1608 hw->phy.autoneg_advertised;
1609 } else {
1610 hw->mac.autoneg = 1;
1611 }
1612 }
1613
1614 e1000_setup_link(hw);
1615
1616 if (rte_intr_allow_others(intr_handle)) {
1617 /* check if lsc interrupt is enabled */
1618 if (dev->data->dev_conf.intr_conf.lsc != 0)
1619 eth_igb_lsc_interrupt_setup(dev, TRUE);
1620 else
1621 eth_igb_lsc_interrupt_setup(dev, FALSE);
1622 } else {
1623 rte_intr_callback_unregister(intr_handle,
1624 eth_igb_interrupt_handler,
1625 (void *)dev);
1626 if (dev->data->dev_conf.intr_conf.lsc != 0)
1627 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1628 " no intr multiplex");
1629 }
1630
1631 /* check if rxq interrupt is enabled */
1632 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1633 rte_intr_dp_is_en(intr_handle))
1634 eth_igb_rxq_interrupt_setup(dev);
1635
1636 /* enable uio/vfio intr/eventfd mapping */
1637 rte_intr_enable(intr_handle);
1638
1639 /* resume enabled intr since hw reset */
1640 igb_intr_enable(dev);
1641
1642 /* restore all types filter */
1643 igb_filter_restore(dev);
1644
1645 eth_igb_rxtx_control(dev, true);
1646 eth_igb_link_update(dev, 0);
1647
1648 PMD_INIT_LOG(DEBUG, "<<");
1649
1650 return 0;
1651
1652 error_invalid_config:
1653 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1654 dev->data->dev_conf.link_speeds, dev->data->port_id);
1655 igb_dev_clear_queues(dev);
1656 return -EINVAL;
1657 }
1658
1659 /*********************************************************************
1660 *
1661 * This routine disables all traffic on the adapter by issuing a
1662 * global reset on the MAC.
1663 *
1664 **********************************************************************/
1665 static int
eth_igb_stop(struct rte_eth_dev * dev)1666 eth_igb_stop(struct rte_eth_dev *dev)
1667 {
1668 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1670 struct rte_eth_link link;
1671 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1672 struct e1000_adapter *adapter =
1673 E1000_DEV_PRIVATE(dev->data->dev_private);
1674
1675 if (adapter->stopped)
1676 return 0;
1677
1678 eth_igb_rxtx_control(dev, false);
1679
1680 igb_intr_disable(dev);
1681
1682 /* disable intr eventfd mapping */
1683 rte_intr_disable(intr_handle);
1684
1685 igb_pf_reset_hw(hw);
1686 E1000_WRITE_REG(hw, E1000_WUC, 0);
1687
1688 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1689 if (hw->mac.type >= e1000_82580 &&
1690 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1691 uint32_t phpm_reg;
1692
1693 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1694 phpm_reg |= E1000_82580_PM_GO_LINKD;
1695 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1696 }
1697
1698 /* Power down the phy. Needed to make the link go Down */
1699 eth_igb_dev_set_link_down(dev);
1700
1701 igb_dev_clear_queues(dev);
1702
1703 /* clear the recorded link status */
1704 memset(&link, 0, sizeof(link));
1705 rte_eth_linkstatus_set(dev, &link);
1706
1707 if (!rte_intr_allow_others(intr_handle))
1708 /* resume to the default handler */
1709 rte_intr_callback_register(intr_handle,
1710 eth_igb_interrupt_handler,
1711 (void *)dev);
1712
1713 /* Clean datapath event and queue/vec mapping */
1714 rte_intr_efd_disable(intr_handle);
1715 rte_intr_vec_list_free(intr_handle);
1716
1717 adapter->stopped = true;
1718 dev->data->dev_started = 0;
1719
1720 return 0;
1721 }
1722
1723 static int
eth_igb_dev_set_link_up(struct rte_eth_dev * dev)1724 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1725 {
1726 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727
1728 if (hw->phy.media_type == e1000_media_type_copper)
1729 e1000_power_up_phy(hw);
1730 else
1731 e1000_power_up_fiber_serdes_link(hw);
1732
1733 return 0;
1734 }
1735
1736 static int
eth_igb_dev_set_link_down(struct rte_eth_dev * dev)1737 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1738 {
1739 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740
1741 if (hw->phy.media_type == e1000_media_type_copper)
1742 e1000_power_down_phy(hw);
1743 else
1744 e1000_shutdown_fiber_serdes_link(hw);
1745
1746 return 0;
1747 }
1748
1749 static int
eth_igb_close(struct rte_eth_dev * dev)1750 eth_igb_close(struct rte_eth_dev *dev)
1751 {
1752 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1753 struct rte_eth_link link;
1754 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1755 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1756 struct e1000_filter_info *filter_info =
1757 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1758 int ret;
1759
1760 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1761 return 0;
1762
1763 ret = eth_igb_stop(dev);
1764
1765 e1000_phy_hw_reset(hw);
1766 igb_release_manageability(hw);
1767 igb_hw_control_release(hw);
1768
1769 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1770 if (hw->mac.type >= e1000_82580 &&
1771 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1772 uint32_t phpm_reg;
1773
1774 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1775 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1776 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1777 }
1778
1779 igb_dev_free_queues(dev);
1780
1781 /* Cleanup vector list */
1782 rte_intr_vec_list_free(intr_handle);
1783
1784 memset(&link, 0, sizeof(link));
1785 rte_eth_linkstatus_set(dev, &link);
1786
1787 /* Reset any pending lock */
1788 igb_reset_swfw_lock(hw);
1789
1790 /* uninitialize PF if max_vfs not zero */
1791 igb_pf_host_uninit(dev);
1792
1793 rte_intr_callback_unregister(intr_handle,
1794 eth_igb_interrupt_handler, dev);
1795
1796 /* clear the SYN filter info */
1797 filter_info->syn_info = 0;
1798
1799 /* clear the ethertype filters info */
1800 filter_info->ethertype_mask = 0;
1801 memset(filter_info->ethertype_filters, 0,
1802 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1803
1804 /* clear the rss filter info */
1805 memset(&filter_info->rss_info, 0,
1806 sizeof(struct igb_rte_flow_rss_conf));
1807
1808 /* remove all ntuple filters of the device */
1809 igb_ntuple_filter_uninit(dev);
1810
1811 /* remove all flex filters of the device */
1812 igb_flex_filter_uninit(dev);
1813
1814 /* clear all the filters list */
1815 igb_filterlist_flush(dev);
1816
1817 return ret;
1818 }
1819
1820 /*
1821 * Reset PF device.
1822 */
1823 static int
eth_igb_reset(struct rte_eth_dev * dev)1824 eth_igb_reset(struct rte_eth_dev *dev)
1825 {
1826 int ret;
1827
1828 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1829 * its VF to make them align with it. The detailed notification
1830 * mechanism is PMD specific and is currently not implemented.
1831 * To avoid unexpected behavior in VF, currently reset of PF with
1832 * SR-IOV activation is not supported. It might be supported later.
1833 */
1834 if (dev->data->sriov.active)
1835 return -ENOTSUP;
1836
1837 ret = eth_igb_dev_uninit(dev);
1838 if (ret)
1839 return ret;
1840
1841 ret = eth_igb_dev_init(dev);
1842
1843 return ret;
1844 }
1845
1846
1847 static int
igb_get_rx_buffer_size(struct e1000_hw * hw)1848 igb_get_rx_buffer_size(struct e1000_hw *hw)
1849 {
1850 uint32_t rx_buf_size;
1851 if (hw->mac.type == e1000_82576) {
1852 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1853 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1854 /* PBS needs to be translated according to a lookup table */
1855 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1856 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1857 rx_buf_size = (rx_buf_size << 10);
1858 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1859 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1860 } else {
1861 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1862 }
1863
1864 return rx_buf_size;
1865 }
1866
1867 /*********************************************************************
1868 *
1869 * Initialize the hardware
1870 *
1871 **********************************************************************/
1872 static int
igb_hardware_init(struct e1000_hw * hw)1873 igb_hardware_init(struct e1000_hw *hw)
1874 {
1875 uint32_t rx_buf_size;
1876 int diag;
1877
1878 /* Let the firmware know the OS is in control */
1879 igb_hw_control_acquire(hw);
1880
1881 /*
1882 * These parameters control the automatic generation (Tx) and
1883 * response (Rx) to Ethernet PAUSE frames.
1884 * - High water mark should allow for at least two standard size (1518)
1885 * frames to be received after sending an XOFF.
1886 * - Low water mark works best when it is very near the high water mark.
1887 * This allows the receiver to restart by sending XON when it has
1888 * drained a bit. Here we use an arbitrary value of 1500 which will
1889 * restart after one full frame is pulled from the buffer. There
1890 * could be several smaller frames in the buffer and if so they will
1891 * not trigger the XON until their total number reduces the buffer
1892 * by 1500.
1893 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1894 */
1895 rx_buf_size = igb_get_rx_buffer_size(hw);
1896
1897 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1898 hw->fc.low_water = hw->fc.high_water - 1500;
1899 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1900 hw->fc.send_xon = 1;
1901
1902 /* Set Flow control, use the tunable location if sane */
1903 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1904 hw->fc.requested_mode = igb_fc_setting;
1905 else
1906 hw->fc.requested_mode = e1000_fc_none;
1907
1908 /* Issue a global reset */
1909 igb_pf_reset_hw(hw);
1910 E1000_WRITE_REG(hw, E1000_WUC, 0);
1911
1912 diag = e1000_init_hw(hw);
1913 if (diag < 0)
1914 return diag;
1915
1916 E1000_WRITE_REG(hw, E1000_VET,
1917 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1918 e1000_get_phy_info(hw);
1919 e1000_check_for_link(hw);
1920
1921 return 0;
1922 }
1923
1924 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1925 static void
igb_read_stats_registers(struct e1000_hw * hw,struct e1000_hw_stats * stats)1926 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1927 {
1928 int pause_frames;
1929
1930 uint64_t old_gprc = stats->gprc;
1931 uint64_t old_gptc = stats->gptc;
1932 uint64_t old_tpr = stats->tpr;
1933 uint64_t old_tpt = stats->tpt;
1934 uint64_t old_rpthc = stats->rpthc;
1935 uint64_t old_hgptc = stats->hgptc;
1936
1937 if(hw->phy.media_type == e1000_media_type_copper ||
1938 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1939 stats->symerrs +=
1940 E1000_READ_REG(hw,E1000_SYMERRS);
1941 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1942 }
1943
1944 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1945 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1946 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1947 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1948
1949 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1950 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1951 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1952 stats->dc += E1000_READ_REG(hw, E1000_DC);
1953 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1954 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1955 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1956 /*
1957 ** For watchdog management we need to know if we have been
1958 ** paused during the last interval, so capture that here.
1959 */
1960 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1961 stats->xoffrxc += pause_frames;
1962 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1963 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1964 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1965 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1966 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1967 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1968 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1969 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1970 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1971 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1972 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1973 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1974
1975 /* For the 64-bit byte counters the low dword must be read first. */
1976 /* Both registers clear on the read of the high dword */
1977
1978 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1979 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1980 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1981 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1982 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1983 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1984 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1985
1986 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1987 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1988 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1989 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1990 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1991
1992 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1993 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1994
1995 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1996 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1997 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1998 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1999 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
2000 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
2001
2002 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2003 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2004 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2005 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2006 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2007 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2008 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2009 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2010
2011 /* Interrupt Counts */
2012
2013 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2014 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2015 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2016 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2017 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2018 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2019 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2020 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2021 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2022
2023 /* Host to Card Statistics */
2024
2025 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2026 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2027 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2028 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2029 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2030 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2031 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2032 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
2033 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
2034 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
2035 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
2036 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
2037 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
2038 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2039 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2040 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2041
2042 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2043 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2044 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2045 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2046 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2047 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2048 }
2049
2050 static int
eth_igb_stats_get(struct rte_eth_dev * dev,struct rte_eth_stats * rte_stats)2051 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2052 {
2053 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054 struct e1000_hw_stats *stats =
2055 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2056
2057 igb_read_stats_registers(hw, stats);
2058
2059 if (rte_stats == NULL)
2060 return -EINVAL;
2061
2062 /* Rx Errors */
2063 rte_stats->imissed = stats->mpc;
2064 rte_stats->ierrors = stats->crcerrs + stats->rlec +
2065 stats->rxerrc + stats->algnerrc + stats->cexterr;
2066
2067 /* Tx Errors */
2068 rte_stats->oerrors = stats->ecol + stats->latecol;
2069
2070 rte_stats->ipackets = stats->gprc;
2071 rte_stats->opackets = stats->gptc;
2072 rte_stats->ibytes = stats->gorc;
2073 rte_stats->obytes = stats->gotc;
2074 return 0;
2075 }
2076
2077 static int
eth_igb_stats_reset(struct rte_eth_dev * dev)2078 eth_igb_stats_reset(struct rte_eth_dev *dev)
2079 {
2080 struct e1000_hw_stats *hw_stats =
2081 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2082
2083 /* HW registers are cleared on read */
2084 eth_igb_stats_get(dev, NULL);
2085
2086 /* Reset software totals */
2087 memset(hw_stats, 0, sizeof(*hw_stats));
2088
2089 return 0;
2090 }
2091
2092 static int
eth_igb_xstats_reset(struct rte_eth_dev * dev)2093 eth_igb_xstats_reset(struct rte_eth_dev *dev)
2094 {
2095 struct e1000_hw_stats *stats =
2096 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2097
2098 /* HW registers are cleared on read */
2099 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
2100
2101 /* Reset software totals */
2102 memset(stats, 0, sizeof(*stats));
2103
2104 return 0;
2105 }
2106
eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev * dev,struct rte_eth_xstat_name * xstats_names,__rte_unused unsigned int size)2107 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2108 struct rte_eth_xstat_name *xstats_names,
2109 __rte_unused unsigned int size)
2110 {
2111 unsigned i;
2112
2113 if (xstats_names == NULL)
2114 return IGB_NB_XSTATS;
2115
2116 /* Note: limit checked in rte_eth_xstats_names() */
2117
2118 for (i = 0; i < IGB_NB_XSTATS; i++) {
2119 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
2120 sizeof(xstats_names[i].name));
2121 }
2122
2123 return IGB_NB_XSTATS;
2124 }
2125
eth_igb_xstats_get_names_by_id(struct rte_eth_dev * dev,const uint64_t * ids,struct rte_eth_xstat_name * xstats_names,unsigned int limit)2126 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
2127 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names,
2128 unsigned int limit)
2129 {
2130 unsigned int i;
2131
2132 if (!ids) {
2133 if (xstats_names == NULL)
2134 return IGB_NB_XSTATS;
2135
2136 for (i = 0; i < IGB_NB_XSTATS; i++)
2137 strlcpy(xstats_names[i].name,
2138 rte_igb_stats_strings[i].name,
2139 sizeof(xstats_names[i].name));
2140
2141 return IGB_NB_XSTATS;
2142
2143 } else {
2144 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
2145
2146 eth_igb_xstats_get_names_by_id(dev, NULL, xstats_names_copy,
2147 IGB_NB_XSTATS);
2148
2149 for (i = 0; i < limit; i++) {
2150 if (ids[i] >= IGB_NB_XSTATS) {
2151 PMD_INIT_LOG(ERR, "id value isn't valid");
2152 return -1;
2153 }
2154 strcpy(xstats_names[i].name,
2155 xstats_names_copy[ids[i]].name);
2156 }
2157 return limit;
2158 }
2159 }
2160
2161 static int
eth_igb_xstats_get(struct rte_eth_dev * dev,struct rte_eth_xstat * xstats,unsigned n)2162 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2163 unsigned n)
2164 {
2165 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2166 struct e1000_hw_stats *hw_stats =
2167 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2168 unsigned i;
2169
2170 if (n < IGB_NB_XSTATS)
2171 return IGB_NB_XSTATS;
2172
2173 igb_read_stats_registers(hw, hw_stats);
2174
2175 /* If this is a reset xstats is NULL, and we have cleared the
2176 * registers by reading them.
2177 */
2178 if (!xstats)
2179 return 0;
2180
2181 /* Extended stats */
2182 for (i = 0; i < IGB_NB_XSTATS; i++) {
2183 xstats[i].id = i;
2184 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2185 rte_igb_stats_strings[i].offset);
2186 }
2187
2188 return IGB_NB_XSTATS;
2189 }
2190
2191 static int
eth_igb_xstats_get_by_id(struct rte_eth_dev * dev,const uint64_t * ids,uint64_t * values,unsigned int n)2192 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2193 uint64_t *values, unsigned int n)
2194 {
2195 unsigned int i;
2196
2197 if (!ids) {
2198 struct e1000_hw *hw =
2199 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200 struct e1000_hw_stats *hw_stats =
2201 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2202
2203 if (n < IGB_NB_XSTATS)
2204 return IGB_NB_XSTATS;
2205
2206 igb_read_stats_registers(hw, hw_stats);
2207
2208 /* If this is a reset xstats is NULL, and we have cleared the
2209 * registers by reading them.
2210 */
2211 if (!values)
2212 return 0;
2213
2214 /* Extended stats */
2215 for (i = 0; i < IGB_NB_XSTATS; i++)
2216 values[i] = *(uint64_t *)(((char *)hw_stats) +
2217 rte_igb_stats_strings[i].offset);
2218
2219 return IGB_NB_XSTATS;
2220
2221 } else {
2222 uint64_t values_copy[IGB_NB_XSTATS];
2223
2224 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2225 IGB_NB_XSTATS);
2226
2227 for (i = 0; i < n; i++) {
2228 if (ids[i] >= IGB_NB_XSTATS) {
2229 PMD_INIT_LOG(ERR, "id value isn't valid");
2230 return -1;
2231 }
2232 values[i] = values_copy[ids[i]];
2233 }
2234 return n;
2235 }
2236 }
2237
2238 static void
igbvf_read_stats_registers(struct e1000_hw * hw,struct e1000_vf_stats * hw_stats)2239 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2240 {
2241 /* Good Rx packets, include VF loopback */
2242 UPDATE_VF_STAT(E1000_VFGPRC,
2243 hw_stats->last_gprc, hw_stats->gprc);
2244
2245 /* Good Rx octets, include VF loopback */
2246 UPDATE_VF_STAT(E1000_VFGORC,
2247 hw_stats->last_gorc, hw_stats->gorc);
2248
2249 /* Good Tx packets, include VF loopback */
2250 UPDATE_VF_STAT(E1000_VFGPTC,
2251 hw_stats->last_gptc, hw_stats->gptc);
2252
2253 /* Good Tx octets, include VF loopback */
2254 UPDATE_VF_STAT(E1000_VFGOTC,
2255 hw_stats->last_gotc, hw_stats->gotc);
2256
2257 /* Rx Multicst packets */
2258 UPDATE_VF_STAT(E1000_VFMPRC,
2259 hw_stats->last_mprc, hw_stats->mprc);
2260
2261 /* Good Rx loopback packets */
2262 UPDATE_VF_STAT(E1000_VFGPRLBC,
2263 hw_stats->last_gprlbc, hw_stats->gprlbc);
2264
2265 /* Good Rx loopback octets */
2266 UPDATE_VF_STAT(E1000_VFGORLBC,
2267 hw_stats->last_gorlbc, hw_stats->gorlbc);
2268
2269 /* Good Tx loopback packets */
2270 UPDATE_VF_STAT(E1000_VFGPTLBC,
2271 hw_stats->last_gptlbc, hw_stats->gptlbc);
2272
2273 /* Good Tx loopback octets */
2274 UPDATE_VF_STAT(E1000_VFGOTLBC,
2275 hw_stats->last_gotlbc, hw_stats->gotlbc);
2276 }
2277
eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev * dev,struct rte_eth_xstat_name * xstats_names,__rte_unused unsigned limit)2278 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2279 struct rte_eth_xstat_name *xstats_names,
2280 __rte_unused unsigned limit)
2281 {
2282 unsigned i;
2283
2284 if (xstats_names != NULL)
2285 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2286 strlcpy(xstats_names[i].name,
2287 rte_igbvf_stats_strings[i].name,
2288 sizeof(xstats_names[i].name));
2289 }
2290 return IGBVF_NB_XSTATS;
2291 }
2292
2293 static int
eth_igbvf_xstats_get(struct rte_eth_dev * dev,struct rte_eth_xstat * xstats,unsigned n)2294 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2295 unsigned n)
2296 {
2297 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2299 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2300 unsigned i;
2301
2302 if (n < IGBVF_NB_XSTATS)
2303 return IGBVF_NB_XSTATS;
2304
2305 igbvf_read_stats_registers(hw, hw_stats);
2306
2307 if (!xstats)
2308 return 0;
2309
2310 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2311 xstats[i].id = i;
2312 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2313 rte_igbvf_stats_strings[i].offset);
2314 }
2315
2316 return IGBVF_NB_XSTATS;
2317 }
2318
2319 static int
eth_igbvf_stats_get(struct rte_eth_dev * dev,struct rte_eth_stats * rte_stats)2320 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2321 {
2322 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2324 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2325
2326 igbvf_read_stats_registers(hw, hw_stats);
2327
2328 if (rte_stats == NULL)
2329 return -EINVAL;
2330
2331 rte_stats->ipackets = hw_stats->gprc;
2332 rte_stats->ibytes = hw_stats->gorc;
2333 rte_stats->opackets = hw_stats->gptc;
2334 rte_stats->obytes = hw_stats->gotc;
2335 return 0;
2336 }
2337
2338 static int
eth_igbvf_stats_reset(struct rte_eth_dev * dev)2339 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2340 {
2341 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2342 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2343
2344 /* Sync HW register to the last stats */
2345 eth_igbvf_stats_get(dev, NULL);
2346
2347 /* reset HW current stats*/
2348 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2349 offsetof(struct e1000_vf_stats, gprc));
2350
2351 return 0;
2352 }
2353
2354 static int
eth_igb_fw_version_get(struct rte_eth_dev * dev,char * fw_version,size_t fw_size)2355 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2356 size_t fw_size)
2357 {
2358 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359 struct e1000_fw_version fw;
2360 int ret;
2361
2362 e1000_get_fw_version(hw, &fw);
2363
2364 switch (hw->mac.type) {
2365 case e1000_i210:
2366 case e1000_i211:
2367 if (!(e1000_get_flash_presence_i210(hw))) {
2368 ret = snprintf(fw_version, fw_size,
2369 "%2d.%2d-%d",
2370 fw.invm_major, fw.invm_minor,
2371 fw.invm_img_type);
2372 break;
2373 }
2374 /* fall through */
2375 default:
2376 /* if option rom is valid, display its version too */
2377 if (fw.or_valid) {
2378 ret = snprintf(fw_version, fw_size,
2379 "%d.%d, 0x%08x, %d.%d.%d",
2380 fw.eep_major, fw.eep_minor, fw.etrack_id,
2381 fw.or_major, fw.or_build, fw.or_patch);
2382 /* no option rom */
2383 } else {
2384 if (fw.etrack_id != 0X0000) {
2385 ret = snprintf(fw_version, fw_size,
2386 "%d.%d, 0x%08x",
2387 fw.eep_major, fw.eep_minor,
2388 fw.etrack_id);
2389 } else {
2390 ret = snprintf(fw_version, fw_size,
2391 "%d.%d.%d",
2392 fw.eep_major, fw.eep_minor,
2393 fw.eep_build);
2394 }
2395 }
2396 break;
2397 }
2398 if (ret < 0)
2399 return -EINVAL;
2400
2401 ret += 1; /* add the size of '\0' */
2402 if (fw_size < (size_t)ret)
2403 return ret;
2404 else
2405 return 0;
2406 }
2407
2408 static int
eth_igb_infos_get(struct rte_eth_dev * dev,struct rte_eth_dev_info * dev_info)2409 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2410 {
2411 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412
2413 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2414 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2415 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2416 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2417 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2418 dev_info->rx_queue_offload_capa;
2419 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2420 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2421 dev_info->tx_queue_offload_capa;
2422 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
2423
2424 switch (hw->mac.type) {
2425 case e1000_82575:
2426 dev_info->max_rx_queues = 4;
2427 dev_info->max_tx_queues = 4;
2428 dev_info->max_vmdq_pools = 0;
2429 break;
2430
2431 case e1000_82576:
2432 dev_info->max_rx_queues = 16;
2433 dev_info->max_tx_queues = 16;
2434 dev_info->max_vmdq_pools = RTE_ETH_8_POOLS;
2435 dev_info->vmdq_queue_num = 16;
2436 break;
2437
2438 case e1000_82580:
2439 dev_info->max_rx_queues = 8;
2440 dev_info->max_tx_queues = 8;
2441 dev_info->max_vmdq_pools = RTE_ETH_8_POOLS;
2442 dev_info->vmdq_queue_num = 8;
2443 break;
2444
2445 case e1000_i350:
2446 dev_info->max_rx_queues = 8;
2447 dev_info->max_tx_queues = 8;
2448 dev_info->max_vmdq_pools = RTE_ETH_8_POOLS;
2449 dev_info->vmdq_queue_num = 8;
2450 break;
2451
2452 case e1000_i354:
2453 dev_info->max_rx_queues = 8;
2454 dev_info->max_tx_queues = 8;
2455 break;
2456
2457 case e1000_i210:
2458 dev_info->max_rx_queues = 4;
2459 dev_info->max_tx_queues = 4;
2460 dev_info->max_vmdq_pools = 0;
2461 break;
2462
2463 case e1000_i211:
2464 dev_info->max_rx_queues = 2;
2465 dev_info->max_tx_queues = 2;
2466 dev_info->max_vmdq_pools = 0;
2467 break;
2468
2469 default:
2470 /* Should not happen */
2471 return -EINVAL;
2472 }
2473 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2474 dev_info->reta_size = RTE_ETH_RSS_RETA_SIZE_128;
2475 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2476
2477 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2478 .rx_thresh = {
2479 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2480 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2481 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2482 },
2483 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2484 .rx_drop_en = 0,
2485 .offloads = 0,
2486 };
2487
2488 dev_info->default_txconf = (struct rte_eth_txconf) {
2489 .tx_thresh = {
2490 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2491 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2492 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2493 },
2494 .offloads = 0,
2495 };
2496
2497 dev_info->rx_desc_lim = rx_desc_lim;
2498 dev_info->tx_desc_lim = tx_desc_lim;
2499
2500 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD | RTE_ETH_LINK_SPEED_10M |
2501 RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M |
2502 RTE_ETH_LINK_SPEED_1G;
2503
2504 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2505 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2506
2507 return 0;
2508 }
2509
2510 static const uint32_t *
eth_igb_supported_ptypes_get(struct rte_eth_dev * dev)2511 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2512 {
2513 static const uint32_t ptypes[] = {
2514 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2515 RTE_PTYPE_L2_ETHER,
2516 RTE_PTYPE_L3_IPV4,
2517 RTE_PTYPE_L3_IPV4_EXT,
2518 RTE_PTYPE_L3_IPV6,
2519 RTE_PTYPE_L3_IPV6_EXT,
2520 RTE_PTYPE_L4_TCP,
2521 RTE_PTYPE_L4_UDP,
2522 RTE_PTYPE_L4_SCTP,
2523 RTE_PTYPE_TUNNEL_IP,
2524 RTE_PTYPE_INNER_L3_IPV6,
2525 RTE_PTYPE_INNER_L3_IPV6_EXT,
2526 RTE_PTYPE_INNER_L4_TCP,
2527 RTE_PTYPE_INNER_L4_UDP,
2528 RTE_PTYPE_UNKNOWN
2529 };
2530
2531 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2532 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2533 return ptypes;
2534 return NULL;
2535 }
2536
2537 static int
eth_igbvf_infos_get(struct rte_eth_dev * dev,struct rte_eth_dev_info * dev_info)2538 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2539 {
2540 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541
2542 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2543 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2544 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2545 dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
2546 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
2547 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
2548 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
2549 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
2550 RTE_ETH_TX_OFFLOAD_TCP_TSO;
2551 switch (hw->mac.type) {
2552 case e1000_vfadapt:
2553 dev_info->max_rx_queues = 2;
2554 dev_info->max_tx_queues = 2;
2555 break;
2556 case e1000_vfadapt_i350:
2557 dev_info->max_rx_queues = 1;
2558 dev_info->max_tx_queues = 1;
2559 break;
2560 default:
2561 /* Should not happen */
2562 return -EINVAL;
2563 }
2564
2565 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2566 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2567 dev_info->rx_queue_offload_capa;
2568 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2569 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2570 dev_info->tx_queue_offload_capa;
2571
2572 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2573 .rx_thresh = {
2574 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2575 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2576 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2577 },
2578 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2579 .rx_drop_en = 0,
2580 .offloads = 0,
2581 };
2582
2583 dev_info->default_txconf = (struct rte_eth_txconf) {
2584 .tx_thresh = {
2585 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2586 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2587 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2588 },
2589 .offloads = 0,
2590 };
2591
2592 dev_info->rx_desc_lim = rx_desc_lim;
2593 dev_info->tx_desc_lim = tx_desc_lim;
2594
2595 return 0;
2596 }
2597
2598 /* return 0 means link status changed, -1 means not changed */
2599 static int
eth_igb_link_update(struct rte_eth_dev * dev,int wait_to_complete)2600 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2601 {
2602 struct e1000_hw *hw =
2603 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604 struct rte_eth_link link;
2605 int link_check, count;
2606
2607 link_check = 0;
2608 hw->mac.get_link_status = 1;
2609
2610 /* possible wait-to-complete in up to 9 seconds */
2611 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2612 /* Read the real link status */
2613 switch (hw->phy.media_type) {
2614 case e1000_media_type_copper:
2615 /* Do the work to read phy */
2616 e1000_check_for_link(hw);
2617 link_check = !hw->mac.get_link_status;
2618 break;
2619
2620 case e1000_media_type_fiber:
2621 e1000_check_for_link(hw);
2622 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2623 E1000_STATUS_LU);
2624 break;
2625
2626 case e1000_media_type_internal_serdes:
2627 e1000_check_for_link(hw);
2628 link_check = hw->mac.serdes_has_link;
2629 break;
2630
2631 /* VF device is type_unknown */
2632 case e1000_media_type_unknown:
2633 eth_igbvf_link_update(hw);
2634 link_check = !hw->mac.get_link_status;
2635 break;
2636
2637 default:
2638 break;
2639 }
2640 if (link_check || wait_to_complete == 0)
2641 break;
2642 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2643 }
2644 memset(&link, 0, sizeof(link));
2645
2646 /* Now we check if a transition has happened */
2647 if (link_check) {
2648 uint16_t duplex, speed;
2649 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2650 link.link_duplex = (duplex == FULL_DUPLEX) ?
2651 RTE_ETH_LINK_FULL_DUPLEX :
2652 RTE_ETH_LINK_HALF_DUPLEX;
2653 link.link_speed = speed;
2654 link.link_status = RTE_ETH_LINK_UP;
2655 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2656 RTE_ETH_LINK_SPEED_FIXED);
2657 } else if (!link_check) {
2658 link.link_speed = 0;
2659 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
2660 link.link_status = RTE_ETH_LINK_DOWN;
2661 link.link_autoneg = RTE_ETH_LINK_FIXED;
2662 }
2663
2664 return rte_eth_linkstatus_set(dev, &link);
2665 }
2666
2667 /*
2668 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2669 * For ASF and Pass Through versions of f/w this means
2670 * that the driver is loaded.
2671 */
2672 static void
igb_hw_control_acquire(struct e1000_hw * hw)2673 igb_hw_control_acquire(struct e1000_hw *hw)
2674 {
2675 uint32_t ctrl_ext;
2676
2677 /* Let firmware know the driver has taken over */
2678 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2679 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2680 }
2681
2682 /*
2683 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2684 * For ASF and Pass Through versions of f/w this means that the
2685 * driver is no longer loaded.
2686 */
2687 static void
igb_hw_control_release(struct e1000_hw * hw)2688 igb_hw_control_release(struct e1000_hw *hw)
2689 {
2690 uint32_t ctrl_ext;
2691
2692 /* Let firmware taken over control of h/w */
2693 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2694 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2695 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2696 }
2697
2698 /*
2699 * Bit of a misnomer, what this really means is
2700 * to enable OS management of the system... aka
2701 * to disable special hardware management features.
2702 */
2703 static void
igb_init_manageability(struct e1000_hw * hw)2704 igb_init_manageability(struct e1000_hw *hw)
2705 {
2706 if (e1000_enable_mng_pass_thru(hw)) {
2707 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2708 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2709
2710 /* disable hardware interception of ARP */
2711 manc &= ~(E1000_MANC_ARP_EN);
2712
2713 /* enable receiving management packets to the host */
2714 manc |= E1000_MANC_EN_MNG2HOST;
2715 manc2h |= 1 << 5; /* Mng Port 623 */
2716 manc2h |= 1 << 6; /* Mng Port 664 */
2717 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2718 E1000_WRITE_REG(hw, E1000_MANC, manc);
2719 }
2720 }
2721
2722 static void
igb_release_manageability(struct e1000_hw * hw)2723 igb_release_manageability(struct e1000_hw *hw)
2724 {
2725 if (e1000_enable_mng_pass_thru(hw)) {
2726 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2727
2728 manc |= E1000_MANC_ARP_EN;
2729 manc &= ~E1000_MANC_EN_MNG2HOST;
2730
2731 E1000_WRITE_REG(hw, E1000_MANC, manc);
2732 }
2733 }
2734
2735 static int
eth_igb_promiscuous_enable(struct rte_eth_dev * dev)2736 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2737 {
2738 struct e1000_hw *hw =
2739 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2740 uint32_t rctl;
2741
2742 rctl = E1000_READ_REG(hw, E1000_RCTL);
2743 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2744 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2745
2746 return 0;
2747 }
2748
2749 static int
eth_igb_promiscuous_disable(struct rte_eth_dev * dev)2750 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2751 {
2752 struct e1000_hw *hw =
2753 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2754 uint32_t rctl;
2755
2756 rctl = E1000_READ_REG(hw, E1000_RCTL);
2757 rctl &= (~E1000_RCTL_UPE);
2758 if (dev->data->all_multicast == 1)
2759 rctl |= E1000_RCTL_MPE;
2760 else
2761 rctl &= (~E1000_RCTL_MPE);
2762 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2763
2764 return 0;
2765 }
2766
2767 static int
eth_igb_allmulticast_enable(struct rte_eth_dev * dev)2768 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2769 {
2770 struct e1000_hw *hw =
2771 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772 uint32_t rctl;
2773
2774 rctl = E1000_READ_REG(hw, E1000_RCTL);
2775 rctl |= E1000_RCTL_MPE;
2776 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2777
2778 return 0;
2779 }
2780
2781 static int
eth_igb_allmulticast_disable(struct rte_eth_dev * dev)2782 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2783 {
2784 struct e1000_hw *hw =
2785 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786 uint32_t rctl;
2787
2788 if (dev->data->promiscuous == 1)
2789 return 0; /* must remain in all_multicast mode */
2790 rctl = E1000_READ_REG(hw, E1000_RCTL);
2791 rctl &= (~E1000_RCTL_MPE);
2792 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2793
2794 return 0;
2795 }
2796
2797 static int
eth_igb_vlan_filter_set(struct rte_eth_dev * dev,uint16_t vlan_id,int on)2798 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2799 {
2800 struct e1000_hw *hw =
2801 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802 struct e1000_vfta * shadow_vfta =
2803 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2804 uint32_t vfta;
2805 uint32_t vid_idx;
2806 uint32_t vid_bit;
2807
2808 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2809 E1000_VFTA_ENTRY_MASK);
2810 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2811 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2812 if (on)
2813 vfta |= vid_bit;
2814 else
2815 vfta &= ~vid_bit;
2816 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2817
2818 /* update local VFTA copy */
2819 shadow_vfta->vfta[vid_idx] = vfta;
2820
2821 return 0;
2822 }
2823
2824 static int
eth_igb_vlan_tpid_set(struct rte_eth_dev * dev,enum rte_vlan_type vlan_type,uint16_t tpid)2825 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2826 enum rte_vlan_type vlan_type,
2827 uint16_t tpid)
2828 {
2829 struct e1000_hw *hw =
2830 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831 uint32_t reg, qinq;
2832
2833 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2834 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2835
2836 /* only outer TPID of double VLAN can be configured*/
2837 if (qinq && vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
2838 reg = E1000_READ_REG(hw, E1000_VET);
2839 reg = (reg & (~E1000_VET_VET_EXT)) |
2840 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2841 E1000_WRITE_REG(hw, E1000_VET, reg);
2842
2843 return 0;
2844 }
2845
2846 /* all other TPID values are read-only*/
2847 PMD_DRV_LOG(ERR, "Not supported");
2848
2849 return -ENOTSUP;
2850 }
2851
2852 static void
igb_vlan_hw_filter_disable(struct rte_eth_dev * dev)2853 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2854 {
2855 struct e1000_hw *hw =
2856 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857 uint32_t reg;
2858
2859 /* Filter Table Disable */
2860 reg = E1000_READ_REG(hw, E1000_RCTL);
2861 reg &= ~E1000_RCTL_CFIEN;
2862 reg &= ~E1000_RCTL_VFE;
2863 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2864 }
2865
2866 static void
igb_vlan_hw_filter_enable(struct rte_eth_dev * dev)2867 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2868 {
2869 struct e1000_hw *hw =
2870 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871 struct e1000_vfta * shadow_vfta =
2872 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2873 uint32_t reg;
2874 int i;
2875
2876 /* Filter Table Enable, CFI not used for packet acceptance */
2877 reg = E1000_READ_REG(hw, E1000_RCTL);
2878 reg &= ~E1000_RCTL_CFIEN;
2879 reg |= E1000_RCTL_VFE;
2880 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2881
2882 /* restore VFTA table */
2883 for (i = 0; i < IGB_VFTA_SIZE; i++)
2884 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2885 }
2886
2887 static void
igb_vlan_hw_strip_disable(struct rte_eth_dev * dev)2888 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2889 {
2890 struct e1000_hw *hw =
2891 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2892 uint32_t reg;
2893
2894 /* VLAN Mode Disable */
2895 reg = E1000_READ_REG(hw, E1000_CTRL);
2896 reg &= ~E1000_CTRL_VME;
2897 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2898 }
2899
2900 static void
igb_vlan_hw_strip_enable(struct rte_eth_dev * dev)2901 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2902 {
2903 struct e1000_hw *hw =
2904 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2905 uint32_t reg;
2906
2907 /* VLAN Mode Enable */
2908 reg = E1000_READ_REG(hw, E1000_CTRL);
2909 reg |= E1000_CTRL_VME;
2910 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2911 }
2912
2913 static void
igb_vlan_hw_extend_disable(struct rte_eth_dev * dev)2914 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2915 {
2916 struct e1000_hw *hw =
2917 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2918 uint32_t reg;
2919
2920 /* CTRL_EXT: Extended VLAN */
2921 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2922 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2923 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2924
2925 /* Update maximum packet length */
2926 E1000_WRITE_REG(hw, E1000_RLPML, dev->data->mtu + E1000_ETH_OVERHEAD);
2927 }
2928
2929 static void
igb_vlan_hw_extend_enable(struct rte_eth_dev * dev)2930 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2931 {
2932 struct e1000_hw *hw =
2933 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934 uint32_t reg;
2935
2936 /* CTRL_EXT: Extended VLAN */
2937 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2938 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2939 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2940
2941 /* Update maximum packet length */
2942 E1000_WRITE_REG(hw, E1000_RLPML,
2943 dev->data->mtu + E1000_ETH_OVERHEAD + VLAN_TAG_SIZE);
2944 }
2945
2946 static int
eth_igb_vlan_offload_set(struct rte_eth_dev * dev,int mask)2947 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2948 {
2949 struct rte_eth_rxmode *rxmode;
2950
2951 rxmode = &dev->data->dev_conf.rxmode;
2952 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2953 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
2954 igb_vlan_hw_strip_enable(dev);
2955 else
2956 igb_vlan_hw_strip_disable(dev);
2957 }
2958
2959 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2960 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
2961 igb_vlan_hw_filter_enable(dev);
2962 else
2963 igb_vlan_hw_filter_disable(dev);
2964 }
2965
2966 if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2967 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2968 igb_vlan_hw_extend_enable(dev);
2969 else
2970 igb_vlan_hw_extend_disable(dev);
2971 }
2972
2973 return 0;
2974 }
2975
2976
2977 /**
2978 * It enables the interrupt mask and then enable the interrupt.
2979 *
2980 * @param dev
2981 * Pointer to struct rte_eth_dev.
2982 * @param on
2983 * Enable or Disable
2984 *
2985 * @return
2986 * - On success, zero.
2987 * - On failure, a negative value.
2988 */
2989 static int
eth_igb_lsc_interrupt_setup(struct rte_eth_dev * dev,uint8_t on)2990 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2991 {
2992 struct e1000_interrupt *intr =
2993 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2994
2995 if (on)
2996 intr->mask |= E1000_ICR_LSC;
2997 else
2998 intr->mask &= ~E1000_ICR_LSC;
2999
3000 return 0;
3001 }
3002
3003 /* It clears the interrupt causes and enables the interrupt.
3004 * It will be called once only during nic initialized.
3005 *
3006 * @param dev
3007 * Pointer to struct rte_eth_dev.
3008 *
3009 * @return
3010 * - On success, zero.
3011 * - On failure, a negative value.
3012 */
eth_igb_rxq_interrupt_setup(struct rte_eth_dev * dev)3013 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
3014 {
3015 uint32_t mask, regval;
3016 int ret;
3017 struct e1000_hw *hw =
3018 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3020 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3021 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
3022 struct rte_eth_dev_info dev_info;
3023
3024 memset(&dev_info, 0, sizeof(dev_info));
3025 ret = eth_igb_infos_get(dev, &dev_info);
3026 if (ret != 0)
3027 return ret;
3028
3029 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
3030 regval = E1000_READ_REG(hw, E1000_EIMS);
3031 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
3032
3033 return 0;
3034 }
3035
3036 /*
3037 * It reads ICR and gets interrupt causes, check it and set a bit flag
3038 * to update link status.
3039 *
3040 * @param dev
3041 * Pointer to struct rte_eth_dev.
3042 *
3043 * @return
3044 * - On success, zero.
3045 * - On failure, a negative value.
3046 */
3047 static int
eth_igb_interrupt_get_status(struct rte_eth_dev * dev)3048 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
3049 {
3050 uint32_t icr;
3051 struct e1000_hw *hw =
3052 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3053 struct e1000_interrupt *intr =
3054 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3055
3056 igb_intr_disable(dev);
3057
3058 /* read-on-clear nic registers here */
3059 icr = E1000_READ_REG(hw, E1000_ICR);
3060
3061 intr->flags = 0;
3062 if (icr & E1000_ICR_LSC) {
3063 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
3064 }
3065
3066 if (icr & E1000_ICR_VMMB)
3067 intr->flags |= E1000_FLAG_MAILBOX;
3068
3069 return 0;
3070 }
3071
3072 /*
3073 * It executes link_update after knowing an interrupt is prsent.
3074 *
3075 * @param dev
3076 * Pointer to struct rte_eth_dev.
3077 *
3078 * @return
3079 * - On success, zero.
3080 * - On failure, a negative value.
3081 */
3082 static int
eth_igb_interrupt_action(struct rte_eth_dev * dev,struct rte_intr_handle * intr_handle)3083 eth_igb_interrupt_action(struct rte_eth_dev *dev,
3084 struct rte_intr_handle *intr_handle)
3085 {
3086 struct e1000_hw *hw =
3087 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3088 struct e1000_interrupt *intr =
3089 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3090 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3091 struct rte_eth_link link;
3092 int ret;
3093
3094 if (intr->flags & E1000_FLAG_MAILBOX) {
3095 igb_pf_mbx_process(dev);
3096 intr->flags &= ~E1000_FLAG_MAILBOX;
3097 }
3098
3099 igb_intr_enable(dev);
3100 rte_intr_ack(intr_handle);
3101
3102 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
3103 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
3104
3105 /* set get_link_status to check register later */
3106 hw->mac.get_link_status = 1;
3107 ret = eth_igb_link_update(dev, 0);
3108
3109 /* check if link has changed */
3110 if (ret < 0)
3111 return 0;
3112
3113 rte_eth_linkstatus_get(dev, &link);
3114 if (link.link_status) {
3115 PMD_INIT_LOG(INFO,
3116 " Port %d: Link Up - speed %u Mbps - %s",
3117 dev->data->port_id,
3118 (unsigned)link.link_speed,
3119 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?
3120 "full-duplex" : "half-duplex");
3121 } else {
3122 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3123 dev->data->port_id);
3124 }
3125
3126 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3127 pci_dev->addr.domain,
3128 pci_dev->addr.bus,
3129 pci_dev->addr.devid,
3130 pci_dev->addr.function);
3131 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3132 }
3133
3134 return 0;
3135 }
3136
3137 /**
3138 * Interrupt handler which shall be registered at first.
3139 *
3140 * @param handle
3141 * Pointer to interrupt handle.
3142 * @param param
3143 * The address of parameter (struct rte_eth_dev *) regsitered before.
3144 *
3145 * @return
3146 * void
3147 */
3148 static void
eth_igb_interrupt_handler(void * param)3149 eth_igb_interrupt_handler(void *param)
3150 {
3151 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3152
3153 eth_igb_interrupt_get_status(dev);
3154 eth_igb_interrupt_action(dev, dev->intr_handle);
3155 }
3156
3157 static int
eth_igbvf_interrupt_get_status(struct rte_eth_dev * dev)3158 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
3159 {
3160 uint32_t eicr;
3161 struct e1000_hw *hw =
3162 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163 struct e1000_interrupt *intr =
3164 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3165
3166 igbvf_intr_disable(hw);
3167
3168 /* read-on-clear nic registers here */
3169 eicr = E1000_READ_REG(hw, E1000_EICR);
3170 intr->flags = 0;
3171
3172 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
3173 intr->flags |= E1000_FLAG_MAILBOX;
3174
3175 return 0;
3176 }
3177
igbvf_mbx_process(struct rte_eth_dev * dev)3178 void igbvf_mbx_process(struct rte_eth_dev *dev)
3179 {
3180 struct e1000_hw *hw =
3181 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3182 struct e1000_mbx_info *mbx = &hw->mbx;
3183 u32 in_msg = 0;
3184
3185 /* peek the message first */
3186 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
3187
3188 /* PF reset VF event */
3189 if (in_msg == E1000_PF_CONTROL_MSG) {
3190 /* dummy mbx read to ack pf */
3191 if (mbx->ops.read(hw, &in_msg, 1, 0))
3192 return;
3193 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
3194 NULL);
3195 }
3196 }
3197
3198 static int
eth_igbvf_interrupt_action(struct rte_eth_dev * dev,struct rte_intr_handle * intr_handle)3199 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
3200 {
3201 struct e1000_interrupt *intr =
3202 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3203
3204 if (intr->flags & E1000_FLAG_MAILBOX) {
3205 igbvf_mbx_process(dev);
3206 intr->flags &= ~E1000_FLAG_MAILBOX;
3207 }
3208
3209 igbvf_intr_enable(dev);
3210 rte_intr_ack(intr_handle);
3211
3212 return 0;
3213 }
3214
3215 static void
eth_igbvf_interrupt_handler(void * param)3216 eth_igbvf_interrupt_handler(void *param)
3217 {
3218 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3219
3220 eth_igbvf_interrupt_get_status(dev);
3221 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3222 }
3223
3224 static int
eth_igb_led_on(struct rte_eth_dev * dev)3225 eth_igb_led_on(struct rte_eth_dev *dev)
3226 {
3227 struct e1000_hw *hw;
3228
3229 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3230 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3231 }
3232
3233 static int
eth_igb_led_off(struct rte_eth_dev * dev)3234 eth_igb_led_off(struct rte_eth_dev *dev)
3235 {
3236 struct e1000_hw *hw;
3237
3238 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3239 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3240 }
3241
3242 static int
eth_igb_flow_ctrl_get(struct rte_eth_dev * dev,struct rte_eth_fc_conf * fc_conf)3243 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3244 {
3245 struct e1000_hw *hw;
3246 uint32_t ctrl;
3247 int tx_pause;
3248 int rx_pause;
3249
3250 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251 fc_conf->pause_time = hw->fc.pause_time;
3252 fc_conf->high_water = hw->fc.high_water;
3253 fc_conf->low_water = hw->fc.low_water;
3254 fc_conf->send_xon = hw->fc.send_xon;
3255 fc_conf->autoneg = hw->mac.autoneg;
3256
3257 /*
3258 * Return rx_pause and tx_pause status according to actual setting of
3259 * the TFCE and RFCE bits in the CTRL register.
3260 */
3261 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3262 if (ctrl & E1000_CTRL_TFCE)
3263 tx_pause = 1;
3264 else
3265 tx_pause = 0;
3266
3267 if (ctrl & E1000_CTRL_RFCE)
3268 rx_pause = 1;
3269 else
3270 rx_pause = 0;
3271
3272 if (rx_pause && tx_pause)
3273 fc_conf->mode = RTE_ETH_FC_FULL;
3274 else if (rx_pause)
3275 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
3276 else if (tx_pause)
3277 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
3278 else
3279 fc_conf->mode = RTE_ETH_FC_NONE;
3280
3281 return 0;
3282 }
3283
3284 static int
eth_igb_flow_ctrl_set(struct rte_eth_dev * dev,struct rte_eth_fc_conf * fc_conf)3285 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3286 {
3287 struct e1000_hw *hw;
3288 int err;
3289 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3290 e1000_fc_none,
3291 e1000_fc_rx_pause,
3292 e1000_fc_tx_pause,
3293 e1000_fc_full
3294 };
3295 uint32_t rx_buf_size;
3296 uint32_t max_high_water;
3297 uint32_t rctl;
3298 uint32_t ctrl;
3299
3300 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301 if (fc_conf->autoneg != hw->mac.autoneg)
3302 return -ENOTSUP;
3303 rx_buf_size = igb_get_rx_buffer_size(hw);
3304 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3305
3306 /* At least reserve one Ethernet frame for watermark */
3307 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3308 if ((fc_conf->high_water > max_high_water) ||
3309 (fc_conf->high_water < fc_conf->low_water)) {
3310 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3311 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3312 return -EINVAL;
3313 }
3314
3315 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3316 hw->fc.pause_time = fc_conf->pause_time;
3317 hw->fc.high_water = fc_conf->high_water;
3318 hw->fc.low_water = fc_conf->low_water;
3319 hw->fc.send_xon = fc_conf->send_xon;
3320
3321 err = e1000_setup_link_generic(hw);
3322 if (err == E1000_SUCCESS) {
3323
3324 /* check if we want to forward MAC frames - driver doesn't have native
3325 * capability to do that, so we'll write the registers ourselves */
3326
3327 rctl = E1000_READ_REG(hw, E1000_RCTL);
3328
3329 /* set or clear MFLCN.PMCF bit depending on configuration */
3330 if (fc_conf->mac_ctrl_frame_fwd != 0)
3331 rctl |= E1000_RCTL_PMCF;
3332 else
3333 rctl &= ~E1000_RCTL_PMCF;
3334
3335 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3336
3337 /*
3338 * check if we want to change flow control mode - driver doesn't have native
3339 * capability to do that, so we'll write the registers ourselves
3340 */
3341 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3342
3343 /*
3344 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending
3345 * on configuration
3346 */
3347 switch (fc_conf->mode) {
3348 case RTE_ETH_FC_NONE:
3349 ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
3350 break;
3351 case RTE_ETH_FC_RX_PAUSE:
3352 ctrl |= E1000_CTRL_RFCE;
3353 ctrl &= ~E1000_CTRL_TFCE;
3354 break;
3355 case RTE_ETH_FC_TX_PAUSE:
3356 ctrl |= E1000_CTRL_TFCE;
3357 ctrl &= ~E1000_CTRL_RFCE;
3358 break;
3359 case RTE_ETH_FC_FULL:
3360 ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
3361 break;
3362 default:
3363 PMD_INIT_LOG(ERR, "invalid flow control mode");
3364 return -EINVAL;
3365 }
3366
3367 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3368
3369 E1000_WRITE_FLUSH(hw);
3370
3371 return 0;
3372 }
3373
3374 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3375 return -EIO;
3376 }
3377
3378 #define E1000_RAH_POOLSEL_SHIFT (18)
3379 static int
eth_igb_rar_set(struct rte_eth_dev * dev,struct rte_ether_addr * mac_addr,uint32_t index,uint32_t pool)3380 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3381 uint32_t index, uint32_t pool)
3382 {
3383 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384 uint32_t rah;
3385
3386 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3387 rah = E1000_READ_REG(hw, E1000_RAH(index));
3388 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3389 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3390 return 0;
3391 }
3392
3393 static void
eth_igb_rar_clear(struct rte_eth_dev * dev,uint32_t index)3394 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3395 {
3396 uint8_t addr[RTE_ETHER_ADDR_LEN];
3397 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398
3399 memset(addr, 0, sizeof(addr));
3400
3401 e1000_rar_set(hw, addr, index);
3402 }
3403
3404 static int
eth_igb_default_mac_addr_set(struct rte_eth_dev * dev,struct rte_ether_addr * addr)3405 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3406 struct rte_ether_addr *addr)
3407 {
3408 eth_igb_rar_clear(dev, 0);
3409 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3410
3411 return 0;
3412 }
3413 /*
3414 * Virtual Function operations
3415 */
3416 static void
igbvf_intr_disable(struct e1000_hw * hw)3417 igbvf_intr_disable(struct e1000_hw *hw)
3418 {
3419 PMD_INIT_FUNC_TRACE();
3420
3421 /* Clear interrupt mask to stop from interrupts being generated */
3422 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3423
3424 E1000_WRITE_FLUSH(hw);
3425 }
3426
3427 static void
igbvf_stop_adapter(struct rte_eth_dev * dev)3428 igbvf_stop_adapter(struct rte_eth_dev *dev)
3429 {
3430 u32 reg_val;
3431 u16 i;
3432 struct rte_eth_dev_info dev_info;
3433 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434 int ret;
3435
3436 memset(&dev_info, 0, sizeof(dev_info));
3437 ret = eth_igbvf_infos_get(dev, &dev_info);
3438 if (ret != 0)
3439 return;
3440
3441 /* Clear interrupt mask to stop from interrupts being generated */
3442 igbvf_intr_disable(hw);
3443
3444 /* Clear any pending interrupts, flush previous writes */
3445 E1000_READ_REG(hw, E1000_EICR);
3446
3447 /* Disable the transmit unit. Each queue must be disabled. */
3448 for (i = 0; i < dev_info.max_tx_queues; i++)
3449 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3450
3451 /* Disable the receive unit by stopping each queue */
3452 for (i = 0; i < dev_info.max_rx_queues; i++) {
3453 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3454 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3455 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3456 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3457 ;
3458 }
3459
3460 /* flush all queues disables */
3461 E1000_WRITE_FLUSH(hw);
3462 msec_delay(2);
3463 }
3464
eth_igbvf_link_update(struct e1000_hw * hw)3465 static int eth_igbvf_link_update(struct e1000_hw *hw)
3466 {
3467 struct e1000_mbx_info *mbx = &hw->mbx;
3468 struct e1000_mac_info *mac = &hw->mac;
3469 int ret_val = E1000_SUCCESS;
3470
3471 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3472
3473 /*
3474 * We only want to run this if there has been a rst asserted.
3475 * in this case that could mean a link change, device reset,
3476 * or a virtual function reset
3477 */
3478
3479 /* If we were hit with a reset or timeout drop the link */
3480 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3481 mac->get_link_status = TRUE;
3482
3483 if (!mac->get_link_status)
3484 goto out;
3485
3486 /* if link status is down no point in checking to see if pf is up */
3487 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3488 goto out;
3489
3490 /* if we passed all the tests above then the link is up and we no
3491 * longer need to check for link */
3492 mac->get_link_status = FALSE;
3493
3494 out:
3495 return ret_val;
3496 }
3497
3498
3499 static int
igbvf_dev_configure(struct rte_eth_dev * dev)3500 igbvf_dev_configure(struct rte_eth_dev *dev)
3501 {
3502 struct rte_eth_conf* conf = &dev->data->dev_conf;
3503
3504 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3505 dev->data->port_id);
3506
3507 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
3508 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
3509
3510 /*
3511 * VF has no ability to enable/disable HW CRC
3512 * Keep the persistent behavior the same as Host PF
3513 */
3514 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3515 if (conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) {
3516 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3517 conf->rxmode.offloads &= ~RTE_ETH_RX_OFFLOAD_KEEP_CRC;
3518 }
3519 #else
3520 if (!(conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)) {
3521 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3522 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC;
3523 }
3524 #endif
3525
3526 return 0;
3527 }
3528
3529 static int
igbvf_dev_start(struct rte_eth_dev * dev)3530 igbvf_dev_start(struct rte_eth_dev *dev)
3531 {
3532 struct e1000_hw *hw =
3533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3534 struct e1000_adapter *adapter =
3535 E1000_DEV_PRIVATE(dev->data->dev_private);
3536 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3537 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3538 int ret;
3539 uint32_t intr_vector = 0;
3540
3541 PMD_INIT_FUNC_TRACE();
3542
3543 hw->mac.ops.reset_hw(hw);
3544 adapter->stopped = 0;
3545
3546 /* Set all vfta */
3547 igbvf_set_vfta_all(dev,1);
3548
3549 eth_igbvf_tx_init(dev);
3550
3551 /* This can fail when allocating mbufs for descriptor rings */
3552 ret = eth_igbvf_rx_init(dev);
3553 if (ret) {
3554 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3555 igb_dev_clear_queues(dev);
3556 return ret;
3557 }
3558
3559 /* check and configure queue intr-vector mapping */
3560 if (rte_intr_cap_multiple(intr_handle) &&
3561 dev->data->dev_conf.intr_conf.rxq) {
3562 intr_vector = dev->data->nb_rx_queues;
3563 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3564 if (ret)
3565 return ret;
3566 }
3567
3568 /* Allocate the vector list */
3569 if (rte_intr_dp_is_en(intr_handle)) {
3570 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3571 dev->data->nb_rx_queues)) {
3572 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3573 " intr_vec", dev->data->nb_rx_queues);
3574 return -ENOMEM;
3575 }
3576 }
3577
3578 eth_igbvf_configure_msix_intr(dev);
3579
3580 /* enable uio/vfio intr/eventfd mapping */
3581 rte_intr_enable(intr_handle);
3582
3583 /* resume enabled intr since hw reset */
3584 igbvf_intr_enable(dev);
3585
3586 return 0;
3587 }
3588
3589 static int
igbvf_dev_stop(struct rte_eth_dev * dev)3590 igbvf_dev_stop(struct rte_eth_dev *dev)
3591 {
3592 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3593 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3594 struct e1000_adapter *adapter =
3595 E1000_DEV_PRIVATE(dev->data->dev_private);
3596
3597 if (adapter->stopped)
3598 return 0;
3599
3600 PMD_INIT_FUNC_TRACE();
3601
3602 igbvf_stop_adapter(dev);
3603
3604 /*
3605 * Clear what we set, but we still keep shadow_vfta to
3606 * restore after device starts
3607 */
3608 igbvf_set_vfta_all(dev,0);
3609
3610 igb_dev_clear_queues(dev);
3611
3612 /* disable intr eventfd mapping */
3613 rte_intr_disable(intr_handle);
3614
3615 /* Clean datapath event and queue/vec mapping */
3616 rte_intr_efd_disable(intr_handle);
3617
3618 /* Clean vector list */
3619 rte_intr_vec_list_free(intr_handle);
3620
3621 adapter->stopped = true;
3622 dev->data->dev_started = 0;
3623
3624 return 0;
3625 }
3626
3627 static int
igbvf_dev_close(struct rte_eth_dev * dev)3628 igbvf_dev_close(struct rte_eth_dev *dev)
3629 {
3630 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3631 struct rte_ether_addr addr;
3632 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3633 int ret;
3634
3635 PMD_INIT_FUNC_TRACE();
3636
3637 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3638 return 0;
3639
3640 e1000_reset_hw(hw);
3641
3642 ret = igbvf_dev_stop(dev);
3643 if (ret != 0)
3644 return ret;
3645
3646 igb_dev_free_queues(dev);
3647
3648 /**
3649 * reprogram the RAR with a zero mac address,
3650 * to ensure that the VF traffic goes to the PF
3651 * after stop, close and detach of the VF.
3652 **/
3653
3654 memset(&addr, 0, sizeof(addr));
3655 igbvf_default_mac_addr_set(dev, &addr);
3656
3657 rte_intr_callback_unregister(pci_dev->intr_handle,
3658 eth_igbvf_interrupt_handler,
3659 (void *)dev);
3660
3661 return 0;
3662 }
3663
3664 static int
igbvf_promiscuous_enable(struct rte_eth_dev * dev)3665 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3666 {
3667 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668
3669 /* Set both unicast and multicast promisc */
3670 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3671
3672 return 0;
3673 }
3674
3675 static int
igbvf_promiscuous_disable(struct rte_eth_dev * dev)3676 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3677 {
3678 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679
3680 /* If in allmulticast mode leave multicast promisc */
3681 if (dev->data->all_multicast == 1)
3682 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3683 else
3684 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3685
3686 return 0;
3687 }
3688
3689 static int
igbvf_allmulticast_enable(struct rte_eth_dev * dev)3690 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3691 {
3692 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3693
3694 /* In promiscuous mode multicast promisc already set */
3695 if (dev->data->promiscuous == 0)
3696 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3697
3698 return 0;
3699 }
3700
3701 static int
igbvf_allmulticast_disable(struct rte_eth_dev * dev)3702 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3703 {
3704 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705
3706 /* In promiscuous mode leave multicast promisc enabled */
3707 if (dev->data->promiscuous == 0)
3708 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3709
3710 return 0;
3711 }
3712
igbvf_set_vfta(struct e1000_hw * hw,uint16_t vid,bool on)3713 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3714 {
3715 struct e1000_mbx_info *mbx = &hw->mbx;
3716 uint32_t msgbuf[2];
3717 s32 err;
3718
3719 /* After set vlan, vlan strip will also be enabled in igb driver*/
3720 msgbuf[0] = E1000_VF_SET_VLAN;
3721 msgbuf[1] = vid;
3722 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3723 if (on)
3724 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3725
3726 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3727 if (err)
3728 goto mbx_err;
3729
3730 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3731 if (err)
3732 goto mbx_err;
3733
3734 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3735 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3736 err = -EINVAL;
3737
3738 mbx_err:
3739 return err;
3740 }
3741
igbvf_set_vfta_all(struct rte_eth_dev * dev,bool on)3742 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3743 {
3744 struct e1000_hw *hw =
3745 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3746 struct e1000_vfta * shadow_vfta =
3747 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3748 int i = 0, j = 0, vfta = 0, mask = 1;
3749
3750 for (i = 0; i < IGB_VFTA_SIZE; i++){
3751 vfta = shadow_vfta->vfta[i];
3752 if(vfta){
3753 mask = 1;
3754 for (j = 0; j < 32; j++){
3755 if(vfta & mask)
3756 igbvf_set_vfta(hw,
3757 (uint16_t)((i<<5)+j), on);
3758 mask<<=1;
3759 }
3760 }
3761 }
3762
3763 }
3764
3765 static int
igbvf_vlan_filter_set(struct rte_eth_dev * dev,uint16_t vlan_id,int on)3766 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3767 {
3768 struct e1000_hw *hw =
3769 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3770 struct e1000_vfta * shadow_vfta =
3771 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3772 uint32_t vid_idx = 0;
3773 uint32_t vid_bit = 0;
3774 int ret = 0;
3775
3776 PMD_INIT_FUNC_TRACE();
3777
3778 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3779 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3780 if(ret){
3781 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3782 return ret;
3783 }
3784 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3785 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3786
3787 /*Save what we set and retore it after device reset*/
3788 if (on)
3789 shadow_vfta->vfta[vid_idx] |= vid_bit;
3790 else
3791 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3792
3793 return 0;
3794 }
3795
3796 static int
igbvf_default_mac_addr_set(struct rte_eth_dev * dev,struct rte_ether_addr * addr)3797 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3798 {
3799 struct e1000_hw *hw =
3800 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801
3802 /* index is not used by rar_set() */
3803 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3804 return 0;
3805 }
3806
3807
3808 static int
eth_igb_rss_reta_update(struct rte_eth_dev * dev,struct rte_eth_rss_reta_entry64 * reta_conf,uint16_t reta_size)3809 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3810 struct rte_eth_rss_reta_entry64 *reta_conf,
3811 uint16_t reta_size)
3812 {
3813 uint8_t i, j, mask;
3814 uint32_t reta, r;
3815 uint16_t idx, shift;
3816 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3817
3818 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) {
3819 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3820 "(%d) doesn't match the number hardware can supported "
3821 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128);
3822 return -EINVAL;
3823 }
3824
3825 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3826 idx = i / RTE_ETH_RETA_GROUP_SIZE;
3827 shift = i % RTE_ETH_RETA_GROUP_SIZE;
3828 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3829 IGB_4_BIT_MASK);
3830 if (!mask)
3831 continue;
3832 if (mask == IGB_4_BIT_MASK)
3833 r = 0;
3834 else
3835 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3836 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3837 if (mask & (0x1 << j))
3838 reta |= reta_conf[idx].reta[shift + j] <<
3839 (CHAR_BIT * j);
3840 else
3841 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3842 }
3843 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3844 }
3845
3846 return 0;
3847 }
3848
3849 static int
eth_igb_rss_reta_query(struct rte_eth_dev * dev,struct rte_eth_rss_reta_entry64 * reta_conf,uint16_t reta_size)3850 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3851 struct rte_eth_rss_reta_entry64 *reta_conf,
3852 uint16_t reta_size)
3853 {
3854 uint8_t i, j, mask;
3855 uint32_t reta;
3856 uint16_t idx, shift;
3857 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3858
3859 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) {
3860 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3861 "(%d) doesn't match the number hardware can supported "
3862 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128);
3863 return -EINVAL;
3864 }
3865
3866 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3867 idx = i / RTE_ETH_RETA_GROUP_SIZE;
3868 shift = i % RTE_ETH_RETA_GROUP_SIZE;
3869 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3870 IGB_4_BIT_MASK);
3871 if (!mask)
3872 continue;
3873 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3874 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3875 if (mask & (0x1 << j))
3876 reta_conf[idx].reta[shift + j] =
3877 ((reta >> (CHAR_BIT * j)) &
3878 IGB_8_BIT_MASK);
3879 }
3880 }
3881
3882 return 0;
3883 }
3884
3885 int
eth_igb_syn_filter_set(struct rte_eth_dev * dev,struct rte_eth_syn_filter * filter,bool add)3886 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3887 struct rte_eth_syn_filter *filter,
3888 bool add)
3889 {
3890 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3891 struct e1000_filter_info *filter_info =
3892 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3893 uint32_t synqf, rfctl;
3894
3895 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3896 return -EINVAL;
3897
3898 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3899
3900 if (add) {
3901 if (synqf & E1000_SYN_FILTER_ENABLE)
3902 return -EINVAL;
3903
3904 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3905 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3906
3907 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3908 if (filter->hig_pri)
3909 rfctl |= E1000_RFCTL_SYNQFP;
3910 else
3911 rfctl &= ~E1000_RFCTL_SYNQFP;
3912
3913 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3914 } else {
3915 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3916 return -ENOENT;
3917 synqf = 0;
3918 }
3919
3920 filter_info->syn_info = synqf;
3921 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3922 E1000_WRITE_FLUSH(hw);
3923 return 0;
3924 }
3925
3926 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3927 static inline int
ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter * filter,struct e1000_2tuple_filter_info * filter_info)3928 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3929 struct e1000_2tuple_filter_info *filter_info)
3930 {
3931 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3932 return -EINVAL;
3933 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3934 return -EINVAL; /* filter index is out of range. */
3935 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3936 return -EINVAL; /* flags is invalid. */
3937
3938 switch (filter->dst_port_mask) {
3939 case UINT16_MAX:
3940 filter_info->dst_port_mask = 0;
3941 filter_info->dst_port = filter->dst_port;
3942 break;
3943 case 0:
3944 filter_info->dst_port_mask = 1;
3945 break;
3946 default:
3947 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3948 return -EINVAL;
3949 }
3950
3951 switch (filter->proto_mask) {
3952 case UINT8_MAX:
3953 filter_info->proto_mask = 0;
3954 filter_info->proto = filter->proto;
3955 break;
3956 case 0:
3957 filter_info->proto_mask = 1;
3958 break;
3959 default:
3960 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3961 return -EINVAL;
3962 }
3963
3964 filter_info->priority = (uint8_t)filter->priority;
3965 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3966 filter_info->tcp_flags = filter->tcp_flags;
3967 else
3968 filter_info->tcp_flags = 0;
3969
3970 return 0;
3971 }
3972
3973 static inline struct e1000_2tuple_filter *
igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list * filter_list,struct e1000_2tuple_filter_info * key)3974 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3975 struct e1000_2tuple_filter_info *key)
3976 {
3977 struct e1000_2tuple_filter *it;
3978
3979 TAILQ_FOREACH(it, filter_list, entries) {
3980 if (memcmp(key, &it->filter_info,
3981 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3982 return it;
3983 }
3984 }
3985 return NULL;
3986 }
3987
3988 /* inject a igb 2tuple filter to HW */
3989 static inline void
igb_inject_2uple_filter(struct rte_eth_dev * dev,struct e1000_2tuple_filter * filter)3990 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3991 struct e1000_2tuple_filter *filter)
3992 {
3993 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3995 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3996 int i;
3997
3998 i = filter->index;
3999 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4000 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4001 imir |= E1000_IMIR_PORT_BP;
4002 else
4003 imir &= ~E1000_IMIR_PORT_BP;
4004
4005 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4006
4007 ttqf |= E1000_TTQF_QUEUE_ENABLE;
4008 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
4009 ttqf |= (uint32_t)(filter->filter_info.proto &
4010 E1000_TTQF_PROTOCOL_MASK);
4011 if (filter->filter_info.proto_mask == 0)
4012 ttqf &= ~E1000_TTQF_MASK_ENABLE;
4013
4014 /* tcp flags bits setting. */
4015 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4016 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4017 imir_ext |= E1000_IMIREXT_CTRL_URG;
4018 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4019 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4020 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4021 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4022 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4023 imir_ext |= E1000_IMIREXT_CTRL_RST;
4024 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4025 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4026 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4027 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4028 } else {
4029 imir_ext |= E1000_IMIREXT_CTRL_BP;
4030 }
4031 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4032 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
4033 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4034 }
4035
4036 /*
4037 * igb_add_2tuple_filter - add a 2tuple filter
4038 *
4039 * @param
4040 * dev: Pointer to struct rte_eth_dev.
4041 * ntuple_filter: ponter to the filter that will be added.
4042 *
4043 * @return
4044 * - On success, zero.
4045 * - On failure, a negative value.
4046 */
4047 static int
igb_add_2tuple_filter(struct rte_eth_dev * dev,struct rte_eth_ntuple_filter * ntuple_filter)4048 igb_add_2tuple_filter(struct rte_eth_dev *dev,
4049 struct rte_eth_ntuple_filter *ntuple_filter)
4050 {
4051 struct e1000_filter_info *filter_info =
4052 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4053 struct e1000_2tuple_filter *filter;
4054 int i, ret;
4055
4056 filter = rte_zmalloc("e1000_2tuple_filter",
4057 sizeof(struct e1000_2tuple_filter), 0);
4058 if (filter == NULL)
4059 return -ENOMEM;
4060
4061 ret = ntuple_filter_to_2tuple(ntuple_filter,
4062 &filter->filter_info);
4063 if (ret < 0) {
4064 rte_free(filter);
4065 return ret;
4066 }
4067 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
4068 &filter->filter_info) != NULL) {
4069 PMD_DRV_LOG(ERR, "filter exists.");
4070 rte_free(filter);
4071 return -EEXIST;
4072 }
4073 filter->queue = ntuple_filter->queue;
4074
4075 /*
4076 * look for an unused 2tuple filter index,
4077 * and insert the filter to list.
4078 */
4079 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
4080 if (!(filter_info->twotuple_mask & (1 << i))) {
4081 filter_info->twotuple_mask |= 1 << i;
4082 filter->index = i;
4083 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
4084 filter,
4085 entries);
4086 break;
4087 }
4088 }
4089 if (i >= E1000_MAX_TTQF_FILTERS) {
4090 PMD_DRV_LOG(ERR, "2tuple filters are full.");
4091 rte_free(filter);
4092 return -ENOSYS;
4093 }
4094
4095 igb_inject_2uple_filter(dev, filter);
4096 return 0;
4097 }
4098
4099 int
igb_delete_2tuple_filter(struct rte_eth_dev * dev,struct e1000_2tuple_filter * filter)4100 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
4101 struct e1000_2tuple_filter *filter)
4102 {
4103 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104 struct e1000_filter_info *filter_info =
4105 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4106
4107 filter_info->twotuple_mask &= ~(1 << filter->index);
4108 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
4109 rte_free(filter);
4110
4111 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
4112 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4113 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4114 return 0;
4115 }
4116
4117 /*
4118 * igb_remove_2tuple_filter - remove a 2tuple filter
4119 *
4120 * @param
4121 * dev: Pointer to struct rte_eth_dev.
4122 * ntuple_filter: ponter to the filter that will be removed.
4123 *
4124 * @return
4125 * - On success, zero.
4126 * - On failure, a negative value.
4127 */
4128 static int
igb_remove_2tuple_filter(struct rte_eth_dev * dev,struct rte_eth_ntuple_filter * ntuple_filter)4129 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
4130 struct rte_eth_ntuple_filter *ntuple_filter)
4131 {
4132 struct e1000_filter_info *filter_info =
4133 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4134 struct e1000_2tuple_filter_info filter_2tuple;
4135 struct e1000_2tuple_filter *filter;
4136 int ret;
4137
4138 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
4139 ret = ntuple_filter_to_2tuple(ntuple_filter,
4140 &filter_2tuple);
4141 if (ret < 0)
4142 return ret;
4143
4144 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
4145 &filter_2tuple);
4146 if (filter == NULL) {
4147 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4148 return -ENOENT;
4149 }
4150
4151 igb_delete_2tuple_filter(dev, filter);
4152
4153 return 0;
4154 }
4155
4156 /* inject a igb flex filter to HW */
4157 static inline void
igb_inject_flex_filter(struct rte_eth_dev * dev,struct e1000_flex_filter * filter)4158 igb_inject_flex_filter(struct rte_eth_dev *dev,
4159 struct e1000_flex_filter *filter)
4160 {
4161 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4162 uint32_t wufc, queueing;
4163 uint32_t reg_off;
4164 uint8_t i, j = 0;
4165
4166 wufc = E1000_READ_REG(hw, E1000_WUFC);
4167 if (filter->index < E1000_MAX_FHFT)
4168 reg_off = E1000_FHFT(filter->index);
4169 else
4170 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4171
4172 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
4173 (E1000_WUFC_FLX0 << filter->index));
4174 queueing = filter->filter_info.len |
4175 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
4176 (filter->filter_info.priority <<
4177 E1000_FHFT_QUEUEING_PRIO_SHIFT);
4178 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
4179 queueing);
4180
4181 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
4182 E1000_WRITE_REG(hw, reg_off,
4183 filter->filter_info.dwords[j]);
4184 reg_off += sizeof(uint32_t);
4185 E1000_WRITE_REG(hw, reg_off,
4186 filter->filter_info.dwords[++j]);
4187 reg_off += sizeof(uint32_t);
4188 E1000_WRITE_REG(hw, reg_off,
4189 (uint32_t)filter->filter_info.mask[i]);
4190 reg_off += sizeof(uint32_t) * 2;
4191 ++j;
4192 }
4193 }
4194
4195 static inline struct e1000_flex_filter *
eth_igb_flex_filter_lookup(struct e1000_flex_filter_list * filter_list,struct e1000_flex_filter_info * key)4196 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4197 struct e1000_flex_filter_info *key)
4198 {
4199 struct e1000_flex_filter *it;
4200
4201 TAILQ_FOREACH(it, filter_list, entries) {
4202 if (memcmp(key, &it->filter_info,
4203 sizeof(struct e1000_flex_filter_info)) == 0)
4204 return it;
4205 }
4206
4207 return NULL;
4208 }
4209
4210 /* remove a flex byte filter
4211 * @param
4212 * dev: Pointer to struct rte_eth_dev.
4213 * filter: the pointer of the filter will be removed.
4214 */
4215 void
igb_remove_flex_filter(struct rte_eth_dev * dev,struct e1000_flex_filter * filter)4216 igb_remove_flex_filter(struct rte_eth_dev *dev,
4217 struct e1000_flex_filter *filter)
4218 {
4219 struct e1000_filter_info *filter_info =
4220 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4221 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222 uint32_t wufc, i;
4223 uint32_t reg_off;
4224
4225 wufc = E1000_READ_REG(hw, E1000_WUFC);
4226 if (filter->index < E1000_MAX_FHFT)
4227 reg_off = E1000_FHFT(filter->index);
4228 else
4229 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4230
4231 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4232 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4233
4234 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4235 (~(E1000_WUFC_FLX0 << filter->index)));
4236
4237 filter_info->flex_mask &= ~(1 << filter->index);
4238 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4239 rte_free(filter);
4240 }
4241
4242 int
eth_igb_add_del_flex_filter(struct rte_eth_dev * dev,struct igb_flex_filter * filter,bool add)4243 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4244 struct igb_flex_filter *filter,
4245 bool add)
4246 {
4247 struct e1000_filter_info *filter_info =
4248 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4249 struct e1000_flex_filter *flex_filter, *it;
4250 uint32_t mask;
4251 uint8_t shift, i;
4252
4253 flex_filter = rte_zmalloc("e1000_flex_filter",
4254 sizeof(struct e1000_flex_filter), 0);
4255 if (flex_filter == NULL)
4256 return -ENOMEM;
4257
4258 flex_filter->filter_info.len = filter->len;
4259 flex_filter->filter_info.priority = filter->priority;
4260 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4261 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4262 mask = 0;
4263 /* reverse bits in flex filter's mask*/
4264 for (shift = 0; shift < CHAR_BIT; shift++) {
4265 if (filter->mask[i] & (0x01 << shift))
4266 mask |= (0x80 >> shift);
4267 }
4268 flex_filter->filter_info.mask[i] = mask;
4269 }
4270
4271 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4272 &flex_filter->filter_info);
4273 if (it == NULL && !add) {
4274 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4275 rte_free(flex_filter);
4276 return -ENOENT;
4277 }
4278 if (it != NULL && add) {
4279 PMD_DRV_LOG(ERR, "filter exists.");
4280 rte_free(flex_filter);
4281 return -EEXIST;
4282 }
4283
4284 if (add) {
4285 flex_filter->queue = filter->queue;
4286 /*
4287 * look for an unused flex filter index
4288 * and insert the filter into the list.
4289 */
4290 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4291 if (!(filter_info->flex_mask & (1 << i))) {
4292 filter_info->flex_mask |= 1 << i;
4293 flex_filter->index = i;
4294 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4295 flex_filter,
4296 entries);
4297 break;
4298 }
4299 }
4300 if (i >= E1000_MAX_FLEX_FILTERS) {
4301 PMD_DRV_LOG(ERR, "flex filters are full.");
4302 rte_free(flex_filter);
4303 return -ENOSYS;
4304 }
4305
4306 igb_inject_flex_filter(dev, flex_filter);
4307
4308 } else {
4309 igb_remove_flex_filter(dev, it);
4310 rte_free(flex_filter);
4311 }
4312
4313 return 0;
4314 }
4315
4316 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4317 static inline int
ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter * filter,struct e1000_5tuple_filter_info * filter_info)4318 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4319 struct e1000_5tuple_filter_info *filter_info)
4320 {
4321 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4322 return -EINVAL;
4323 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4324 return -EINVAL; /* filter index is out of range. */
4325 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4326 return -EINVAL; /* flags is invalid. */
4327
4328 switch (filter->dst_ip_mask) {
4329 case UINT32_MAX:
4330 filter_info->dst_ip_mask = 0;
4331 filter_info->dst_ip = filter->dst_ip;
4332 break;
4333 case 0:
4334 filter_info->dst_ip_mask = 1;
4335 break;
4336 default:
4337 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4338 return -EINVAL;
4339 }
4340
4341 switch (filter->src_ip_mask) {
4342 case UINT32_MAX:
4343 filter_info->src_ip_mask = 0;
4344 filter_info->src_ip = filter->src_ip;
4345 break;
4346 case 0:
4347 filter_info->src_ip_mask = 1;
4348 break;
4349 default:
4350 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4351 return -EINVAL;
4352 }
4353
4354 switch (filter->dst_port_mask) {
4355 case UINT16_MAX:
4356 filter_info->dst_port_mask = 0;
4357 filter_info->dst_port = filter->dst_port;
4358 break;
4359 case 0:
4360 filter_info->dst_port_mask = 1;
4361 break;
4362 default:
4363 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4364 return -EINVAL;
4365 }
4366
4367 switch (filter->src_port_mask) {
4368 case UINT16_MAX:
4369 filter_info->src_port_mask = 0;
4370 filter_info->src_port = filter->src_port;
4371 break;
4372 case 0:
4373 filter_info->src_port_mask = 1;
4374 break;
4375 default:
4376 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4377 return -EINVAL;
4378 }
4379
4380 switch (filter->proto_mask) {
4381 case UINT8_MAX:
4382 filter_info->proto_mask = 0;
4383 filter_info->proto = filter->proto;
4384 break;
4385 case 0:
4386 filter_info->proto_mask = 1;
4387 break;
4388 default:
4389 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4390 return -EINVAL;
4391 }
4392
4393 filter_info->priority = (uint8_t)filter->priority;
4394 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4395 filter_info->tcp_flags = filter->tcp_flags;
4396 else
4397 filter_info->tcp_flags = 0;
4398
4399 return 0;
4400 }
4401
4402 static inline struct e1000_5tuple_filter *
igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list * filter_list,struct e1000_5tuple_filter_info * key)4403 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4404 struct e1000_5tuple_filter_info *key)
4405 {
4406 struct e1000_5tuple_filter *it;
4407
4408 TAILQ_FOREACH(it, filter_list, entries) {
4409 if (memcmp(key, &it->filter_info,
4410 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4411 return it;
4412 }
4413 }
4414 return NULL;
4415 }
4416
4417 /* inject a igb 5-tuple filter to HW */
4418 static inline void
igb_inject_5tuple_filter_82576(struct rte_eth_dev * dev,struct e1000_5tuple_filter * filter)4419 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4420 struct e1000_5tuple_filter *filter)
4421 {
4422 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4423 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4424 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4425 uint8_t i;
4426
4427 i = filter->index;
4428 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4429 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4430 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4431 if (filter->filter_info.dst_ip_mask == 0)
4432 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4433 if (filter->filter_info.src_port_mask == 0)
4434 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4435 if (filter->filter_info.proto_mask == 0)
4436 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4437 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4438 E1000_FTQF_QUEUE_MASK;
4439 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4440 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4441 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4442 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4443
4444 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4445 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4446
4447 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4448 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4449 imir |= E1000_IMIR_PORT_BP;
4450 else
4451 imir &= ~E1000_IMIR_PORT_BP;
4452 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4453
4454 /* tcp flags bits setting. */
4455 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4456 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4457 imir_ext |= E1000_IMIREXT_CTRL_URG;
4458 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4459 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4460 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4461 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4462 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4463 imir_ext |= E1000_IMIREXT_CTRL_RST;
4464 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4465 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4466 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4467 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4468 } else {
4469 imir_ext |= E1000_IMIREXT_CTRL_BP;
4470 }
4471 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4472 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4473 }
4474
4475 /*
4476 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4477 *
4478 * @param
4479 * dev: Pointer to struct rte_eth_dev.
4480 * ntuple_filter: ponter to the filter that will be added.
4481 *
4482 * @return
4483 * - On success, zero.
4484 * - On failure, a negative value.
4485 */
4486 static int
igb_add_5tuple_filter_82576(struct rte_eth_dev * dev,struct rte_eth_ntuple_filter * ntuple_filter)4487 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4488 struct rte_eth_ntuple_filter *ntuple_filter)
4489 {
4490 struct e1000_filter_info *filter_info =
4491 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4492 struct e1000_5tuple_filter *filter;
4493 uint8_t i;
4494 int ret;
4495
4496 filter = rte_zmalloc("e1000_5tuple_filter",
4497 sizeof(struct e1000_5tuple_filter), 0);
4498 if (filter == NULL)
4499 return -ENOMEM;
4500
4501 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4502 &filter->filter_info);
4503 if (ret < 0) {
4504 rte_free(filter);
4505 return ret;
4506 }
4507
4508 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4509 &filter->filter_info) != NULL) {
4510 PMD_DRV_LOG(ERR, "filter exists.");
4511 rte_free(filter);
4512 return -EEXIST;
4513 }
4514 filter->queue = ntuple_filter->queue;
4515
4516 /*
4517 * look for an unused 5tuple filter index,
4518 * and insert the filter to list.
4519 */
4520 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4521 if (!(filter_info->fivetuple_mask & (1 << i))) {
4522 filter_info->fivetuple_mask |= 1 << i;
4523 filter->index = i;
4524 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4525 filter,
4526 entries);
4527 break;
4528 }
4529 }
4530 if (i >= E1000_MAX_FTQF_FILTERS) {
4531 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4532 rte_free(filter);
4533 return -ENOSYS;
4534 }
4535
4536 igb_inject_5tuple_filter_82576(dev, filter);
4537 return 0;
4538 }
4539
4540 int
igb_delete_5tuple_filter_82576(struct rte_eth_dev * dev,struct e1000_5tuple_filter * filter)4541 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4542 struct e1000_5tuple_filter *filter)
4543 {
4544 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4545 struct e1000_filter_info *filter_info =
4546 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4547
4548 filter_info->fivetuple_mask &= ~(1 << filter->index);
4549 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4550 rte_free(filter);
4551
4552 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4553 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4554 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4555 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4556 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4557 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4558 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4559 return 0;
4560 }
4561
4562 /*
4563 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4564 *
4565 * @param
4566 * dev: Pointer to struct rte_eth_dev.
4567 * ntuple_filter: ponter to the filter that will be removed.
4568 *
4569 * @return
4570 * - On success, zero.
4571 * - On failure, a negative value.
4572 */
4573 static int
igb_remove_5tuple_filter_82576(struct rte_eth_dev * dev,struct rte_eth_ntuple_filter * ntuple_filter)4574 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4575 struct rte_eth_ntuple_filter *ntuple_filter)
4576 {
4577 struct e1000_filter_info *filter_info =
4578 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4579 struct e1000_5tuple_filter_info filter_5tuple;
4580 struct e1000_5tuple_filter *filter;
4581 int ret;
4582
4583 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4584 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4585 &filter_5tuple);
4586 if (ret < 0)
4587 return ret;
4588
4589 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4590 &filter_5tuple);
4591 if (filter == NULL) {
4592 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4593 return -ENOENT;
4594 }
4595
4596 igb_delete_5tuple_filter_82576(dev, filter);
4597
4598 return 0;
4599 }
4600
4601 static int
eth_igb_mtu_set(struct rte_eth_dev * dev,uint16_t mtu)4602 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4603 {
4604 uint32_t rctl;
4605 struct e1000_hw *hw;
4606 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4607
4608 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4609
4610 #ifdef RTE_LIBRTE_82571_SUPPORT
4611 /* XXX: not bigger than max_rx_pktlen */
4612 if (hw->mac.type == e1000_82571)
4613 return -ENOTSUP;
4614 #endif
4615 /*
4616 * If device is started, refuse mtu that requires the support of
4617 * scattered packets when this feature has not been enabled before.
4618 */
4619 if (dev->data->dev_started && !dev->data->scattered_rx &&
4620 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
4621 PMD_INIT_LOG(ERR, "Stop port first.");
4622 return -EINVAL;
4623 }
4624
4625 rctl = E1000_READ_REG(hw, E1000_RCTL);
4626
4627 /* switch to jumbo mode if needed */
4628 if (mtu > RTE_ETHER_MTU)
4629 rctl |= E1000_RCTL_LPE;
4630 else
4631 rctl &= ~E1000_RCTL_LPE;
4632 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4633
4634 E1000_WRITE_REG(hw, E1000_RLPML, frame_size);
4635
4636 return 0;
4637 }
4638
4639 /*
4640 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4641 *
4642 * @param
4643 * dev: Pointer to struct rte_eth_dev.
4644 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4645 * add: if true, add filter, if false, remove filter
4646 *
4647 * @return
4648 * - On success, zero.
4649 * - On failure, a negative value.
4650 */
4651 int
igb_add_del_ntuple_filter(struct rte_eth_dev * dev,struct rte_eth_ntuple_filter * ntuple_filter,bool add)4652 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4653 struct rte_eth_ntuple_filter *ntuple_filter,
4654 bool add)
4655 {
4656 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4657 int ret;
4658
4659 switch (ntuple_filter->flags) {
4660 case RTE_5TUPLE_FLAGS:
4661 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4662 if (hw->mac.type != e1000_82576)
4663 return -ENOTSUP;
4664 if (add)
4665 ret = igb_add_5tuple_filter_82576(dev,
4666 ntuple_filter);
4667 else
4668 ret = igb_remove_5tuple_filter_82576(dev,
4669 ntuple_filter);
4670 break;
4671 case RTE_2TUPLE_FLAGS:
4672 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4673 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4674 hw->mac.type != e1000_i210 &&
4675 hw->mac.type != e1000_i211)
4676 return -ENOTSUP;
4677 if (add)
4678 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4679 else
4680 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4681 break;
4682 default:
4683 ret = -EINVAL;
4684 break;
4685 }
4686
4687 return ret;
4688 }
4689
4690 static inline int
igb_ethertype_filter_lookup(struct e1000_filter_info * filter_info,uint16_t ethertype)4691 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4692 uint16_t ethertype)
4693 {
4694 int i;
4695
4696 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4697 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4698 (filter_info->ethertype_mask & (1 << i)))
4699 return i;
4700 }
4701 return -1;
4702 }
4703
4704 static inline int
igb_ethertype_filter_insert(struct e1000_filter_info * filter_info,uint16_t ethertype,uint32_t etqf)4705 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4706 uint16_t ethertype, uint32_t etqf)
4707 {
4708 int i;
4709
4710 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4711 if (!(filter_info->ethertype_mask & (1 << i))) {
4712 filter_info->ethertype_mask |= 1 << i;
4713 filter_info->ethertype_filters[i].ethertype = ethertype;
4714 filter_info->ethertype_filters[i].etqf = etqf;
4715 return i;
4716 }
4717 }
4718 return -1;
4719 }
4720
4721 int
igb_ethertype_filter_remove(struct e1000_filter_info * filter_info,uint8_t idx)4722 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4723 uint8_t idx)
4724 {
4725 if (idx >= E1000_MAX_ETQF_FILTERS)
4726 return -1;
4727 filter_info->ethertype_mask &= ~(1 << idx);
4728 filter_info->ethertype_filters[idx].ethertype = 0;
4729 filter_info->ethertype_filters[idx].etqf = 0;
4730 return idx;
4731 }
4732
4733
4734 int
igb_add_del_ethertype_filter(struct rte_eth_dev * dev,struct rte_eth_ethertype_filter * filter,bool add)4735 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4736 struct rte_eth_ethertype_filter *filter,
4737 bool add)
4738 {
4739 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4740 struct e1000_filter_info *filter_info =
4741 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4742 uint32_t etqf = 0;
4743 int ret;
4744
4745 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4746 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4747 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4748 " ethertype filter.", filter->ether_type);
4749 return -EINVAL;
4750 }
4751
4752 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4753 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4754 return -EINVAL;
4755 }
4756 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4757 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4758 return -EINVAL;
4759 }
4760
4761 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4762 if (ret >= 0 && add) {
4763 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4764 filter->ether_type);
4765 return -EEXIST;
4766 }
4767 if (ret < 0 && !add) {
4768 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4769 filter->ether_type);
4770 return -ENOENT;
4771 }
4772
4773 if (add) {
4774 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4775 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4776 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4777 ret = igb_ethertype_filter_insert(filter_info,
4778 filter->ether_type, etqf);
4779 if (ret < 0) {
4780 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4781 return -ENOSYS;
4782 }
4783 } else {
4784 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4785 if (ret < 0)
4786 return -ENOSYS;
4787 }
4788 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4789 E1000_WRITE_FLUSH(hw);
4790
4791 return 0;
4792 }
4793
4794 static int
eth_igb_flow_ops_get(struct rte_eth_dev * dev __rte_unused,const struct rte_flow_ops ** ops)4795 eth_igb_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
4796 const struct rte_flow_ops **ops)
4797 {
4798 *ops = &igb_flow_ops;
4799 return 0;
4800 }
4801
4802 static int
eth_igb_set_mc_addr_list(struct rte_eth_dev * dev,struct rte_ether_addr * mc_addr_set,uint32_t nb_mc_addr)4803 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4804 struct rte_ether_addr *mc_addr_set,
4805 uint32_t nb_mc_addr)
4806 {
4807 struct e1000_hw *hw;
4808
4809 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4810 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4811 return 0;
4812 }
4813
4814 static uint64_t
igb_read_systime_cyclecounter(struct rte_eth_dev * dev)4815 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4816 {
4817 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818 uint64_t systime_cycles;
4819
4820 switch (hw->mac.type) {
4821 case e1000_i210:
4822 case e1000_i211:
4823 /*
4824 * Need to read System Time Residue Register to be able
4825 * to read the other two registers.
4826 */
4827 E1000_READ_REG(hw, E1000_SYSTIMR);
4828 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4829 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4830 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4831 * NSEC_PER_SEC;
4832 break;
4833 case e1000_82580:
4834 case e1000_i350:
4835 case e1000_i354:
4836 /*
4837 * Need to read System Time Residue Register to be able
4838 * to read the other two registers.
4839 */
4840 E1000_READ_REG(hw, E1000_SYSTIMR);
4841 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4842 /* Only the 8 LSB are valid. */
4843 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4844 & 0xff) << 32;
4845 break;
4846 default:
4847 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4848 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4849 << 32;
4850 break;
4851 }
4852
4853 return systime_cycles;
4854 }
4855
4856 static uint64_t
igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev * dev)4857 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4858 {
4859 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860 uint64_t rx_tstamp_cycles;
4861
4862 switch (hw->mac.type) {
4863 case e1000_i210:
4864 case e1000_i211:
4865 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4866 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4867 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4868 * NSEC_PER_SEC;
4869 break;
4870 case e1000_82580:
4871 case e1000_i350:
4872 case e1000_i354:
4873 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4874 /* Only the 8 LSB are valid. */
4875 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4876 & 0xff) << 32;
4877 break;
4878 default:
4879 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4880 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4881 << 32;
4882 break;
4883 }
4884
4885 return rx_tstamp_cycles;
4886 }
4887
4888 static uint64_t
igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev * dev)4889 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4890 {
4891 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4892 uint64_t tx_tstamp_cycles;
4893
4894 switch (hw->mac.type) {
4895 case e1000_i210:
4896 case e1000_i211:
4897 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4898 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4899 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4900 * NSEC_PER_SEC;
4901 break;
4902 case e1000_82580:
4903 case e1000_i350:
4904 case e1000_i354:
4905 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4906 /* Only the 8 LSB are valid. */
4907 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4908 & 0xff) << 32;
4909 break;
4910 default:
4911 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4912 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4913 << 32;
4914 break;
4915 }
4916
4917 return tx_tstamp_cycles;
4918 }
4919
4920 static void
igb_start_timecounters(struct rte_eth_dev * dev)4921 igb_start_timecounters(struct rte_eth_dev *dev)
4922 {
4923 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4924 struct e1000_adapter *adapter = dev->data->dev_private;
4925 uint32_t incval = 1;
4926 uint32_t shift = 0;
4927 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4928
4929 switch (hw->mac.type) {
4930 case e1000_82580:
4931 case e1000_i350:
4932 case e1000_i354:
4933 /* 32 LSB bits + 8 MSB bits = 40 bits */
4934 mask = (1ULL << 40) - 1;
4935 /* fall-through */
4936 case e1000_i210:
4937 case e1000_i211:
4938 /*
4939 * Start incrementing the register
4940 * used to timestamp PTP packets.
4941 */
4942 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4943 break;
4944 case e1000_82576:
4945 incval = E1000_INCVALUE_82576;
4946 shift = IGB_82576_TSYNC_SHIFT;
4947 E1000_WRITE_REG(hw, E1000_TIMINCA,
4948 E1000_INCPERIOD_82576 | incval);
4949 break;
4950 default:
4951 /* Not supported */
4952 return;
4953 }
4954
4955 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4956 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4957 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4958
4959 adapter->systime_tc.cc_mask = mask;
4960 adapter->systime_tc.cc_shift = shift;
4961 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4962
4963 adapter->rx_tstamp_tc.cc_mask = mask;
4964 adapter->rx_tstamp_tc.cc_shift = shift;
4965 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4966
4967 adapter->tx_tstamp_tc.cc_mask = mask;
4968 adapter->tx_tstamp_tc.cc_shift = shift;
4969 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4970 }
4971
4972 static int
igb_timesync_adjust_time(struct rte_eth_dev * dev,int64_t delta)4973 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4974 {
4975 struct e1000_adapter *adapter = dev->data->dev_private;
4976
4977 adapter->systime_tc.nsec += delta;
4978 adapter->rx_tstamp_tc.nsec += delta;
4979 adapter->tx_tstamp_tc.nsec += delta;
4980
4981 return 0;
4982 }
4983
4984 static int
igb_timesync_write_time(struct rte_eth_dev * dev,const struct timespec * ts)4985 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4986 {
4987 uint64_t ns;
4988 struct e1000_adapter *adapter = dev->data->dev_private;
4989
4990 ns = rte_timespec_to_ns(ts);
4991
4992 /* Set the timecounters to a new value. */
4993 adapter->systime_tc.nsec = ns;
4994 adapter->rx_tstamp_tc.nsec = ns;
4995 adapter->tx_tstamp_tc.nsec = ns;
4996
4997 return 0;
4998 }
4999
5000 static int
igb_timesync_read_time(struct rte_eth_dev * dev,struct timespec * ts)5001 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5002 {
5003 uint64_t ns, systime_cycles;
5004 struct e1000_adapter *adapter = dev->data->dev_private;
5005
5006 systime_cycles = igb_read_systime_cyclecounter(dev);
5007 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5008 *ts = rte_ns_to_timespec(ns);
5009
5010 return 0;
5011 }
5012
5013 static int
igb_timesync_enable(struct rte_eth_dev * dev)5014 igb_timesync_enable(struct rte_eth_dev *dev)
5015 {
5016 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5017 uint32_t tsync_ctl;
5018 uint32_t tsauxc;
5019
5020 /* Stop the timesync system time. */
5021 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5022 /* Reset the timesync system time value. */
5023 switch (hw->mac.type) {
5024 case e1000_82580:
5025 case e1000_i350:
5026 case e1000_i354:
5027 case e1000_i210:
5028 case e1000_i211:
5029 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5030 /* fall-through */
5031 case e1000_82576:
5032 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5033 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5034 break;
5035 default:
5036 /* Not supported. */
5037 return -ENOTSUP;
5038 }
5039
5040 /* Enable system time for it isn't on by default. */
5041 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5042 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5043 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5044
5045 igb_start_timecounters(dev);
5046
5047 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5048 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5049 (RTE_ETHER_TYPE_1588 |
5050 E1000_ETQF_FILTER_ENABLE |
5051 E1000_ETQF_1588));
5052
5053 /* Enable timestamping of received PTP packets. */
5054 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5055 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5056 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5057
5058 /* Enable Timestamping of transmitted PTP packets. */
5059 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5060 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5061 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5062
5063 return 0;
5064 }
5065
5066 static int
igb_timesync_disable(struct rte_eth_dev * dev)5067 igb_timesync_disable(struct rte_eth_dev *dev)
5068 {
5069 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070 uint32_t tsync_ctl;
5071
5072 /* Disable timestamping of transmitted PTP packets. */
5073 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5074 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5075 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5076
5077 /* Disable timestamping of received PTP packets. */
5078 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5079 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5080 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5081
5082 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5083 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5084
5085 /* Stop incrementating the System Time registers. */
5086 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5087
5088 return 0;
5089 }
5090
5091 static int
igb_timesync_read_rx_timestamp(struct rte_eth_dev * dev,struct timespec * timestamp,uint32_t flags __rte_unused)5092 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5093 struct timespec *timestamp,
5094 uint32_t flags __rte_unused)
5095 {
5096 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5097 struct e1000_adapter *adapter = dev->data->dev_private;
5098 uint32_t tsync_rxctl;
5099 uint64_t rx_tstamp_cycles;
5100 uint64_t ns;
5101
5102 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5103 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5104 return -EINVAL;
5105
5106 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5107 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5108 *timestamp = rte_ns_to_timespec(ns);
5109
5110 return 0;
5111 }
5112
5113 static int
igb_timesync_read_tx_timestamp(struct rte_eth_dev * dev,struct timespec * timestamp)5114 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5115 struct timespec *timestamp)
5116 {
5117 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5118 struct e1000_adapter *adapter = dev->data->dev_private;
5119 uint32_t tsync_txctl;
5120 uint64_t tx_tstamp_cycles;
5121 uint64_t ns;
5122
5123 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5124 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5125 return -EINVAL;
5126
5127 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5128 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5129 *timestamp = rte_ns_to_timespec(ns);
5130
5131 return 0;
5132 }
5133
5134 static int
eth_igb_get_reg_length(struct rte_eth_dev * dev __rte_unused)5135 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5136 {
5137 int count = 0;
5138 int g_ind = 0;
5139 const struct reg_info *reg_group;
5140
5141 while ((reg_group = igb_regs[g_ind++]))
5142 count += igb_reg_group_count(reg_group);
5143
5144 return count;
5145 }
5146
5147 static int
igbvf_get_reg_length(struct rte_eth_dev * dev __rte_unused)5148 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5149 {
5150 int count = 0;
5151 int g_ind = 0;
5152 const struct reg_info *reg_group;
5153
5154 while ((reg_group = igbvf_regs[g_ind++]))
5155 count += igb_reg_group_count(reg_group);
5156
5157 return count;
5158 }
5159
5160 static int
eth_igb_get_regs(struct rte_eth_dev * dev,struct rte_dev_reg_info * regs)5161 eth_igb_get_regs(struct rte_eth_dev *dev,
5162 struct rte_dev_reg_info *regs)
5163 {
5164 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5165 uint32_t *data = regs->data;
5166 int g_ind = 0;
5167 int count = 0;
5168 const struct reg_info *reg_group;
5169
5170 if (data == NULL) {
5171 regs->length = eth_igb_get_reg_length(dev);
5172 regs->width = sizeof(uint32_t);
5173 return 0;
5174 }
5175
5176 /* Support only full register dump */
5177 if ((regs->length == 0) ||
5178 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5179 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5180 hw->device_id;
5181 while ((reg_group = igb_regs[g_ind++]))
5182 count += igb_read_regs_group(dev, &data[count],
5183 reg_group);
5184 return 0;
5185 }
5186
5187 return -ENOTSUP;
5188 }
5189
5190 static int
igbvf_get_regs(struct rte_eth_dev * dev,struct rte_dev_reg_info * regs)5191 igbvf_get_regs(struct rte_eth_dev *dev,
5192 struct rte_dev_reg_info *regs)
5193 {
5194 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5195 uint32_t *data = regs->data;
5196 int g_ind = 0;
5197 int count = 0;
5198 const struct reg_info *reg_group;
5199
5200 if (data == NULL) {
5201 regs->length = igbvf_get_reg_length(dev);
5202 regs->width = sizeof(uint32_t);
5203 return 0;
5204 }
5205
5206 /* Support only full register dump */
5207 if ((regs->length == 0) ||
5208 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5209 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5210 hw->device_id;
5211 while ((reg_group = igbvf_regs[g_ind++]))
5212 count += igb_read_regs_group(dev, &data[count],
5213 reg_group);
5214 return 0;
5215 }
5216
5217 return -ENOTSUP;
5218 }
5219
5220 static int
eth_igb_get_eeprom_length(struct rte_eth_dev * dev)5221 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5222 {
5223 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5224
5225 /* Return unit is byte count */
5226 return hw->nvm.word_size * 2;
5227 }
5228
5229 static int
eth_igb_get_eeprom(struct rte_eth_dev * dev,struct rte_dev_eeprom_info * in_eeprom)5230 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5231 struct rte_dev_eeprom_info *in_eeprom)
5232 {
5233 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5234 struct e1000_nvm_info *nvm = &hw->nvm;
5235 uint16_t *data = in_eeprom->data;
5236 int first, length;
5237
5238 first = in_eeprom->offset >> 1;
5239 length = in_eeprom->length >> 1;
5240 if ((first >= hw->nvm.word_size) ||
5241 ((first + length) >= hw->nvm.word_size))
5242 return -EINVAL;
5243
5244 in_eeprom->magic = hw->vendor_id |
5245 ((uint32_t)hw->device_id << 16);
5246
5247 if ((nvm->ops.read) == NULL)
5248 return -ENOTSUP;
5249
5250 return nvm->ops.read(hw, first, length, data);
5251 }
5252
5253 static int
eth_igb_set_eeprom(struct rte_eth_dev * dev,struct rte_dev_eeprom_info * in_eeprom)5254 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5255 struct rte_dev_eeprom_info *in_eeprom)
5256 {
5257 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5258 struct e1000_nvm_info *nvm = &hw->nvm;
5259 uint16_t *data = in_eeprom->data;
5260 int first, length;
5261
5262 first = in_eeprom->offset >> 1;
5263 length = in_eeprom->length >> 1;
5264 if ((first >= hw->nvm.word_size) ||
5265 ((first + length) >= hw->nvm.word_size))
5266 return -EINVAL;
5267
5268 in_eeprom->magic = (uint32_t)hw->vendor_id |
5269 ((uint32_t)hw->device_id << 16);
5270
5271 if ((nvm->ops.write) == NULL)
5272 return -ENOTSUP;
5273 return nvm->ops.write(hw, first, length, data);
5274 }
5275
5276 static int
eth_igb_get_module_info(struct rte_eth_dev * dev,struct rte_eth_dev_module_info * modinfo)5277 eth_igb_get_module_info(struct rte_eth_dev *dev,
5278 struct rte_eth_dev_module_info *modinfo)
5279 {
5280 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5281
5282 uint32_t status = 0;
5283 uint16_t sff8472_rev, addr_mode;
5284 bool page_swap = false;
5285
5286 if (hw->phy.media_type == e1000_media_type_copper ||
5287 hw->phy.media_type == e1000_media_type_unknown)
5288 return -EOPNOTSUPP;
5289
5290 /* Check whether we support SFF-8472 or not */
5291 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5292 if (status)
5293 return -EIO;
5294
5295 /* addressing mode is not supported */
5296 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5297 if (status)
5298 return -EIO;
5299
5300 /* addressing mode is not supported */
5301 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5302 PMD_DRV_LOG(ERR,
5303 "Address change required to access page 0xA2, "
5304 "but not supported. Please report the module "
5305 "type to the driver maintainers.\n");
5306 page_swap = true;
5307 }
5308
5309 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5310 /* We have an SFP, but it does not support SFF-8472 */
5311 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5312 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5313 } else {
5314 /* We have an SFP which supports a revision of SFF-8472 */
5315 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5316 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5317 }
5318
5319 return 0;
5320 }
5321
5322 static int
eth_igb_get_module_eeprom(struct rte_eth_dev * dev,struct rte_dev_eeprom_info * info)5323 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5324 struct rte_dev_eeprom_info *info)
5325 {
5326 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5327
5328 uint32_t status = 0;
5329 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5330 u16 first_word, last_word;
5331 int i = 0;
5332
5333 first_word = info->offset >> 1;
5334 last_word = (info->offset + info->length - 1) >> 1;
5335
5336 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5337 for (i = 0; i < last_word - first_word + 1; i++) {
5338 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5339 &dataword[i]);
5340 if (status) {
5341 /* Error occurred while reading module */
5342 return -EIO;
5343 }
5344
5345 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5346 }
5347
5348 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5349
5350 return 0;
5351 }
5352
5353 static int
eth_igb_rx_queue_intr_disable(struct rte_eth_dev * dev,uint16_t queue_id)5354 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5355 {
5356 struct e1000_hw *hw =
5357 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5358 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5359 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5360 uint32_t vec = E1000_MISC_VEC_ID;
5361
5362 if (rte_intr_allow_others(intr_handle))
5363 vec = E1000_RX_VEC_START;
5364
5365 uint32_t mask = 1 << (queue_id + vec);
5366
5367 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5368 E1000_WRITE_FLUSH(hw);
5369
5370 return 0;
5371 }
5372
5373 static int
eth_igb_rx_queue_intr_enable(struct rte_eth_dev * dev,uint16_t queue_id)5374 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5375 {
5376 struct e1000_hw *hw =
5377 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5378 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5379 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5380 uint32_t vec = E1000_MISC_VEC_ID;
5381
5382 if (rte_intr_allow_others(intr_handle))
5383 vec = E1000_RX_VEC_START;
5384
5385 uint32_t mask = 1 << (queue_id + vec);
5386 uint32_t regval;
5387
5388 regval = E1000_READ_REG(hw, E1000_EIMS);
5389 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5390 E1000_WRITE_FLUSH(hw);
5391
5392 rte_intr_ack(intr_handle);
5393
5394 return 0;
5395 }
5396
5397 static void
eth_igb_write_ivar(struct e1000_hw * hw,uint8_t msix_vector,uint8_t index,uint8_t offset)5398 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5399 uint8_t index, uint8_t offset)
5400 {
5401 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5402
5403 /* clear bits */
5404 val &= ~((uint32_t)0xFF << offset);
5405
5406 /* write vector and valid bit */
5407 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5408
5409 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5410 }
5411
5412 static void
eth_igb_assign_msix_vector(struct e1000_hw * hw,int8_t direction,uint8_t queue,uint8_t msix_vector)5413 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5414 uint8_t queue, uint8_t msix_vector)
5415 {
5416 uint32_t tmp = 0;
5417
5418 if (hw->mac.type == e1000_82575) {
5419 if (direction == 0)
5420 tmp = E1000_EICR_RX_QUEUE0 << queue;
5421 else if (direction == 1)
5422 tmp = E1000_EICR_TX_QUEUE0 << queue;
5423 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5424 } else if (hw->mac.type == e1000_82576) {
5425 if ((direction == 0) || (direction == 1))
5426 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5427 ((queue & 0x8) << 1) +
5428 8 * direction);
5429 } else if ((hw->mac.type == e1000_82580) ||
5430 (hw->mac.type == e1000_i350) ||
5431 (hw->mac.type == e1000_i354) ||
5432 (hw->mac.type == e1000_i210) ||
5433 (hw->mac.type == e1000_i211)) {
5434 if ((direction == 0) || (direction == 1))
5435 eth_igb_write_ivar(hw, msix_vector,
5436 queue >> 1,
5437 ((queue & 0x1) << 4) +
5438 8 * direction);
5439 }
5440 }
5441
5442 /* Sets up the hardware to generate MSI-X interrupts properly
5443 * @hw
5444 * board private structure
5445 */
5446 static void
eth_igb_configure_msix_intr(struct rte_eth_dev * dev)5447 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5448 {
5449 int queue_id, nb_efd;
5450 uint32_t tmpval, regval, intr_mask;
5451 struct e1000_hw *hw =
5452 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5453 uint32_t vec = E1000_MISC_VEC_ID;
5454 uint32_t base = E1000_MISC_VEC_ID;
5455 uint32_t misc_shift = 0;
5456 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5457 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5458
5459 /* won't configure msix register if no mapping is done
5460 * between intr vector and event fd
5461 */
5462 if (!rte_intr_dp_is_en(intr_handle))
5463 return;
5464
5465 if (rte_intr_allow_others(intr_handle)) {
5466 vec = base = E1000_RX_VEC_START;
5467 misc_shift = 1;
5468 }
5469
5470 /* set interrupt vector for other causes */
5471 if (hw->mac.type == e1000_82575) {
5472 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5473 /* enable MSI-X PBA support */
5474 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5475
5476 /* Auto-Mask interrupts upon ICR read */
5477 tmpval |= E1000_CTRL_EXT_EIAME;
5478 tmpval |= E1000_CTRL_EXT_IRCA;
5479
5480 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5481
5482 /* enable msix_other interrupt */
5483 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5484 regval = E1000_READ_REG(hw, E1000_EIAC);
5485 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5486 regval = E1000_READ_REG(hw, E1000_EIAM);
5487 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5488 } else if ((hw->mac.type == e1000_82576) ||
5489 (hw->mac.type == e1000_82580) ||
5490 (hw->mac.type == e1000_i350) ||
5491 (hw->mac.type == e1000_i354) ||
5492 (hw->mac.type == e1000_i210) ||
5493 (hw->mac.type == e1000_i211)) {
5494 /* turn on MSI-X capability first */
5495 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5496 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5497 E1000_GPIE_NSICR);
5498 nb_efd = rte_intr_nb_efd_get(intr_handle);
5499 if (nb_efd < 0)
5500 return;
5501
5502 intr_mask = RTE_LEN2MASK(nb_efd, uint32_t) << misc_shift;
5503
5504 if (dev->data->dev_conf.intr_conf.lsc != 0)
5505 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5506
5507 regval = E1000_READ_REG(hw, E1000_EIAC);
5508 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5509
5510 /* enable msix_other interrupt */
5511 regval = E1000_READ_REG(hw, E1000_EIMS);
5512 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5513 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5514 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5515 }
5516
5517 /* use EIAM to auto-mask when MSI-X interrupt
5518 * is asserted, this saves a register write for every interrupt
5519 */
5520 nb_efd = rte_intr_nb_efd_get(intr_handle);
5521 if (nb_efd < 0)
5522 return;
5523
5524 intr_mask = RTE_LEN2MASK(nb_efd, uint32_t) << misc_shift;
5525
5526 if (dev->data->dev_conf.intr_conf.lsc != 0)
5527 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5528
5529 regval = E1000_READ_REG(hw, E1000_EIAM);
5530 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5531
5532 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5533 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5534 rte_intr_vec_list_index_set(intr_handle, queue_id, vec);
5535 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
5536 vec++;
5537 }
5538
5539 E1000_WRITE_FLUSH(hw);
5540 }
5541
5542 /* restore n-tuple filter */
5543 static inline void
igb_ntuple_filter_restore(struct rte_eth_dev * dev)5544 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5545 {
5546 struct e1000_filter_info *filter_info =
5547 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5548 struct e1000_5tuple_filter *p_5tuple;
5549 struct e1000_2tuple_filter *p_2tuple;
5550
5551 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5552 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5553 }
5554
5555 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5556 igb_inject_2uple_filter(dev, p_2tuple);
5557 }
5558 }
5559
5560 /* restore SYN filter */
5561 static inline void
igb_syn_filter_restore(struct rte_eth_dev * dev)5562 igb_syn_filter_restore(struct rte_eth_dev *dev)
5563 {
5564 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5565 struct e1000_filter_info *filter_info =
5566 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5567 uint32_t synqf;
5568
5569 synqf = filter_info->syn_info;
5570
5571 if (synqf & E1000_SYN_FILTER_ENABLE) {
5572 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5573 E1000_WRITE_FLUSH(hw);
5574 }
5575 }
5576
5577 /* restore ethernet type filter */
5578 static inline void
igb_ethertype_filter_restore(struct rte_eth_dev * dev)5579 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5580 {
5581 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5582 struct e1000_filter_info *filter_info =
5583 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5584 int i;
5585
5586 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5587 if (filter_info->ethertype_mask & (1 << i)) {
5588 E1000_WRITE_REG(hw, E1000_ETQF(i),
5589 filter_info->ethertype_filters[i].etqf);
5590 E1000_WRITE_FLUSH(hw);
5591 }
5592 }
5593 }
5594
5595 /* restore flex byte filter */
5596 static inline void
igb_flex_filter_restore(struct rte_eth_dev * dev)5597 igb_flex_filter_restore(struct rte_eth_dev *dev)
5598 {
5599 struct e1000_filter_info *filter_info =
5600 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5601 struct e1000_flex_filter *flex_filter;
5602
5603 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5604 igb_inject_flex_filter(dev, flex_filter);
5605 }
5606 }
5607
5608 /* restore rss filter */
5609 static inline void
igb_rss_filter_restore(struct rte_eth_dev * dev)5610 igb_rss_filter_restore(struct rte_eth_dev *dev)
5611 {
5612 struct e1000_filter_info *filter_info =
5613 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5614
5615 if (filter_info->rss_info.conf.queue_num)
5616 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5617 }
5618
5619 /* restore all types filter */
5620 static int
igb_filter_restore(struct rte_eth_dev * dev)5621 igb_filter_restore(struct rte_eth_dev *dev)
5622 {
5623 igb_ntuple_filter_restore(dev);
5624 igb_ethertype_filter_restore(dev);
5625 igb_syn_filter_restore(dev);
5626 igb_flex_filter_restore(dev);
5627 igb_rss_filter_restore(dev);
5628
5629 return 0;
5630 }
5631
5632 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5633 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5634 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5635 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5636 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5637 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5638