1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
28 #if RT_PLATFORM == PLATFORM_MACOSX
29 #include "phydm_precomp.h"
30 #else
31 #include "../phydm_precomp.h"
32 #endif
33 #else
34 #include "../../phydm_precomp.h"
35 #endif
36
37 #if (RTL8822C_SUPPORT == 1)
38
_halrf_txgapk_backup_bb_registers_8822c(void * dm_void,u32 * reg,u32 * reg_backup,u32 reg_num)39 void _halrf_txgapk_backup_bb_registers_8822c(
40 void *dm_void,
41 u32 *reg,
42 u32 *reg_backup,
43 u32 reg_num)
44 {
45 struct dm_struct *dm = (struct dm_struct *)dm_void;
46 u32 i;
47
48 for (i = 0; i < reg_num; i++) {
49 reg_backup[i] = odm_get_bb_reg(dm, reg[i], MASKDWORD);
50
51 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TXGAPK] Backup BB 0x%x = 0x%x\n",
52 reg[i], reg_backup[i]);
53 }
54 }
55
_halrf_txgapk_reload_bb_registers_8822c(void * dm_void,u32 * reg,u32 * reg_backup,u32 reg_num)56 void _halrf_txgapk_reload_bb_registers_8822c(
57 void *dm_void,
58 u32 *reg,
59 u32 *reg_backup,
60 u32 reg_num)
61
62 {
63 struct dm_struct *dm = (struct dm_struct *)dm_void;
64 u32 i;
65
66 for (i = 0; i < reg_num; i++) {
67 odm_set_bb_reg(dm, reg[i], MASKDWORD, reg_backup[i]);
68 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TXGAPK] Reload BB 0x%x = 0x%x\n",
69 reg[i], reg_backup[i]);
70 }
71 }
72
_halrf_txgapk_tx_pause_8822c(struct dm_struct * dm)73 void _halrf_txgapk_tx_pause_8822c(
74 struct dm_struct *dm)
75 {
76 u8 reg_rf0_a, reg_rf0_b;
77 u16 count = 0;
78
79 odm_write_1byte(dm, R_0x522, 0xff);
80 odm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x2); /*hw tx stop*/
81
82 reg_rf0_a = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xF0000);
83 reg_rf0_b = (u8)odm_get_rf_reg(dm, RF_PATH_B, RF_0x00, 0xF0000);
84
85 while (((reg_rf0_a == 2) || (reg_rf0_b == 2)) && count < 2500) {
86 reg_rf0_a = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xF0000);
87 reg_rf0_b = (u8)odm_get_rf_reg(dm, RF_PATH_B, RF_0x00, 0xF0000);
88 ODM_delay_us(2);
89 count++;
90 }
91
92 RF_DBG(dm, DBG_RF_DPK, "[TXGAPK] Tx pause!!\n");
93 }
94
_halrf_txgapk_bb_dpk_8822c(void * dm_void,u8 path)95 void _halrf_txgapk_bb_dpk_8822c(
96 void *dm_void, u8 path)
97 {
98 struct dm_struct *dm = (struct dm_struct *)dm_void;
99
100 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
101
102 odm_set_bb_reg(dm, R_0x1e24, 0x00020000, 0x1);
103 odm_set_bb_reg(dm, R_0x1cd0, 0x10000000, 0x1);
104 odm_set_bb_reg(dm, R_0x1cd0, 0x20000000, 0x1);
105 odm_set_bb_reg(dm, R_0x1cd0, 0x40000000, 0x1);
106 odm_set_bb_reg(dm, R_0x1cd0, 0x80000000, 0x0);
107 /*odm_set_bb_reg(dm, R_0x1c68, 0x0f000000, 0xf);*/
108 odm_set_bb_reg(dm, R_0x1d58, 0x00000ff8, 0x1ff);
109
110 if (path == RF_PATH_A) {
111 odm_set_bb_reg(dm, R_0x1864, 0x80000000, 0x1);
112 odm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);
113 odm_set_bb_reg(dm, R_0x186c, 0x00000080, 0x1);
114 odm_set_bb_reg(dm, R_0x180c, 0x00000003, 0x0);
115 } else if (path == RF_PATH_B) {
116 odm_set_bb_reg(dm, R_0x4164, 0x80000000, 0x1);
117 odm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);
118 odm_set_bb_reg(dm, R_0x416c, 0x00000080, 0x1);
119 odm_set_bb_reg(dm, R_0x410c, 0x00000003, 0x0);
120 }
121
122 odm_set_bb_reg(dm, R_0x1a00, 0x00000003, 0x2);
123 }
124
_halrf_txgapk_afe_dpk_8822c(void * dm_void,u8 path)125 void _halrf_txgapk_afe_dpk_8822c(
126 void *dm_void, u8 path)
127 {
128 struct dm_struct *dm = (struct dm_struct *)dm_void;
129
130 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
131
132 if (path == RF_PATH_A) {
133 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffffffff);
134 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700f0001);
135 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700f0001);
136 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0001);
137 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0001);
138 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0001);
139 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0001);
140 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705f0001);
141 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0001);
142 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707f0001);
143 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708f0001);
144 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709f0001);
145 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70af0001);
146 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bf0001);
147 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cf0001);
148 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70df0001);
149 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ef0001);
150 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ff0001);
151 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ff0001);
152 } else if (path == RF_PATH_B) {
153 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffffffff);
154 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700f0001);
155 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700f0001);
156 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0001);
157 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0001);
158 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0001);
159 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0001);
160 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705f0001);
161 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0001);
162 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707f0001);
163 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708f0001);
164 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709f0001);
165 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70af0001);
166 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bf0001);
167 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cf0001);
168 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70df0001);
169 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ef0001);
170 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ff0001);
171 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ff0001);
172 }
173 }
174
_halrf_txgapk_afe_dpk_restore_8822c(void * dm_void,u8 path)175 void _halrf_txgapk_afe_dpk_restore_8822c(
176 void *dm_void, u8 path)
177 {
178 struct dm_struct *dm = (struct dm_struct *)dm_void;
179
180 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
181
182 if (path == RF_PATH_A) {
183 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffa1005e);
184 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);
185 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70144041);
186 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70244041);
187 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70344041);
188 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70444041);
189 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);
190 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70644041);
191 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);
192 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);
193 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);
194 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);
195 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);
196 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);
197 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);
198 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);
199 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);
200 } else if (path == RF_PATH_B) {
201 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffa1005e);
202 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);
203 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70144041);
204 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70244041);
205 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70344041);
206 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70444041);
207 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);
208 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70644041);
209 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);
210 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);
211 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);
212 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);
213 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);
214 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);
215 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);
216 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);
217 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);
218 }
219 }
220
_halrf_txgapk_bb_dpk_restore_8822c(void * dm_void,u8 path)221 void _halrf_txgapk_bb_dpk_restore_8822c(
222 void *dm_void, u8 path)
223 {
224 struct dm_struct *dm = (struct dm_struct *)dm_void;
225
226 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
227
228 odm_set_rf_reg(dm, path, RF_0xde, 0x10000, 0x0);
229 odm_set_rf_reg(dm, path, RF_0x9e, 0x00020, 0x0);
230 odm_set_rf_reg(dm, path, RF_0x9e, 0x00400, 0x0);
231 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, 0x0);
232 odm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x0);
233 odm_set_bb_reg(dm, R_0x1bb8, 0x00100000, 0x0);
234 odm_set_bb_reg(dm, R_0x1bcc, 0xff, 0x00);
235 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, 0x1);
236 odm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x0);
237 odm_set_bb_reg(dm, R_0x1bb8, 0x00100000, 0x0);
238 odm_set_bb_reg(dm, R_0x1bcc, 0xff, 0x00);
239 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, 0x0);
240 #if 0
241 odm_set_bb_reg(dm, R_0x1d0c, 0x00010000, 0x1);
242 odm_set_bb_reg(dm, R_0x1d0c, 0x00010000, 0x0);
243 odm_set_bb_reg(dm, R_0x1d0c, 0x00010000, 0x1);
244 #endif
245 /*odm_set_bb_reg(dm, R_0x1c68, 0x0f000000, 0x0);*/
246 odm_set_bb_reg(dm, R_0x1d58, 0x00000ff8, 0x0);
247
248 if (path == RF_PATH_A) {
249 odm_set_bb_reg(dm, R_0x1864, 0x80000000, 0x0);
250 odm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x0);
251 odm_set_bb_reg(dm, R_0x186c, 0x00000080, 0x0);
252 odm_set_bb_reg(dm, R_0x180c, 0x00000003, 0x3);
253 } else if (path == RF_PATH_B) {
254 odm_set_bb_reg(dm, R_0x4164, 0x80000000, 0x0);
255 odm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x0);
256 odm_set_bb_reg(dm, R_0x416c, 0x00000080, 0x0);
257 odm_set_bb_reg(dm, R_0x410c, 0x00000003, 0x3);
258 }
259
260 odm_set_bb_reg(dm, R_0x1a00, 0x00000003, 0x0);
261 odm_set_bb_reg(dm, R_0x1b20, 0x07000000, 0x5);
262
263 }
264
_halrf_txgapk_write_gain_bb_table_8822c(void * dm_void)265 void _halrf_txgapk_write_gain_bb_table_8822c(
266 void *dm_void)
267 {
268 #if 0
269 struct dm_struct *dm = (struct dm_struct *)dm_void;
270 struct _hal_rf_ *rf = &dm->rf_table;
271 struct _halrf_txgapk_info *txgapk = &rf->halrf_txgapk_info;
272 u8 channel = *dm->channel, i;
273 u32 tmp_3f;
274
275 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s channel=%d\n",
276 __func__, channel);
277
278 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, 0x0);
279
280 if (channel >= 1 && channel <= 14)
281 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x0);
282 else if (channel >= 36 && channel <= 64)
283 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x2);
284 else if (channel >= 100 && channel <= 144)
285 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x3);
286 else if (channel >= 149 && channel <= 177)
287 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x4);
288
289 odm_set_bb_reg(dm, R_0x1b9c, 0x000000ff, 0x88);
290
291 for (i = 0; i < 11; i++) {
292 tmp_3f = txgapk->txgapk_rf3f_bp[0][i][RF_PATH_A] & 0xfff;
293 odm_set_bb_reg(dm, R_0x1b98, 0x00000fff, tmp_3f);
294 odm_set_bb_reg(dm, R_0x1b98, 0x000f0000, i);
295 odm_set_bb_reg(dm, R_0x1b98, 0x00008000, 0x1);
296 odm_set_bb_reg(dm, R_0x1b98, 0x00008000, 0x0);
297
298 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] Set 0x1b98[11:0]=0x%03X 0x%x\n",
299 tmp_3f, i);
300 }
301 #else
302 struct dm_struct *dm = (struct dm_struct *)dm_void;
303 struct _hal_rf_ *rf = &dm->rf_table;
304 struct _halrf_txgapk_info *txgapk = &rf->halrf_txgapk_info;
305 u8 channel = *dm->channel, i;
306 u8 path_idx, gain_idx, band_idx, check_txgain;
307 u32 tmp_3f = 0;
308
309 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s channel=%d\n",
310 __func__, channel);
311
312 for (band_idx = 0; band_idx < 5; band_idx++) {
313 for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8822C; path_idx++) {
314 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, path_idx);
315
316 //if (band_idx == 0 || band_idx == 1) /*2G*/
317 if (band_idx == 1)
318 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x0);
319 else if (band_idx == 2) /*5GL*/
320 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x2);
321 else if (band_idx == 3) /*5GM*/
322 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x3);
323 else if (band_idx == 4) /*5GH*/
324 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x4);
325
326 odm_set_bb_reg(dm, R_0x1b9c, 0x000000ff, 0x88);
327
328 check_txgain = 0;
329 for (gain_idx = 0; gain_idx < 11; gain_idx++) {
330
331 if (((txgapk->txgapk_rf3f_bp[band_idx][gain_idx][path_idx] & 0xf00) >> 8) >= 0xc &&
332 ((txgapk->txgapk_rf3f_bp[band_idx][gain_idx][path_idx] & 0xf0) >> 4) >= 0xe) {
333 if (check_txgain == 0) {
334 tmp_3f = txgapk->txgapk_rf3f_bp[band_idx][gain_idx][path_idx];
335 check_txgain = 1;
336 }
337 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n",
338 txgapk->txgapk_rf3f_bp[band_idx][gain_idx][path_idx]);
339 } else
340 tmp_3f = txgapk->txgapk_rf3f_bp[band_idx][gain_idx][path_idx] & 0xfff;
341
342 odm_set_bb_reg(dm, R_0x1b98, 0x00000fff, tmp_3f);
343 odm_set_bb_reg(dm, R_0x1b98, 0x000f0000, gain_idx);
344 odm_set_bb_reg(dm, R_0x1b98, 0x00008000, 0x1);
345 odm_set_bb_reg(dm, R_0x1b98, 0x00008000, 0x0);
346
347 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] Write Gain 0x1b98 Band=%d 0x1b98[11:0]=0x%03X path=%d\n",
348 band_idx, tmp_3f, path_idx);
349 }
350 }
351 }
352 #endif
353 }
354
_halrf_txgapk_calculate_offset_8822c(void * dm_void,u8 path)355 void _halrf_txgapk_calculate_offset_8822c(
356 void *dm_void, u8 path)
357 {
358 struct dm_struct *dm = (struct dm_struct *)dm_void;
359 struct _hal_rf_ *rf = &dm->rf_table;
360 struct _halrf_txgapk_info *txgapk = &rf->halrf_txgapk_info;
361
362 u8 i;
363 u8 channel = *dm->channel;
364
365 u32 set_pi[MAX_PATH_NUM_8822C] = {R_0x1c, R_0xec};
366 u32 set_1b00_cfg1[MAX_PATH_NUM_8822C] = {0x00000d18, 0x00000d2a};
367 u32 set_1b00_cfg2[MAX_PATH_NUM_8822C] = {0x00000d19, 0x00000d2b};
368 u32 path_setting[2] = {R_0x1800, R_0x4100};
369
370 u32 bb_reg[5] = {R_0x820, R_0x1e2c, R_0x1e28, R_0x1800, R_0x4100};
371 u32 bb_reg_backup[5] = {0};
372 u32 backup_num = 5;
373
374 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s channel=%d\n",
375 __func__, channel);
376
377 _halrf_txgapk_backup_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
378
379 if (channel >= 1 && channel <= 14) { /*2G*/
380 odm_set_bb_reg(dm, R_0x1bb8, 0x00100000, 0x0);
381 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, path);
382 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x3f);
383 odm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x0);
384 odm_set_rf_reg(dm, path, RF_0xde, 0x10000, 0x1);
385 odm_set_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK, 0x5000f);
386 odm_set_rf_reg(dm, path, RF_0x55, 0x0001c, 0x0);
387 odm_set_rf_reg(dm, path, RF_0x87, 0x40000, 0x1);
388 odm_set_rf_reg(dm, path, RF_0x00, 0x003e0, 0x0f);
389 odm_set_rf_reg(dm, path, RF_0xde, 0x00004, 0x1);
390 odm_set_rf_reg(dm, path, RF_0x1a, 0x07000, 0x1);
391 odm_set_rf_reg(dm, path, RF_0x1a, 0x00c00, 0x0);
392 odm_set_rf_reg(dm, path, RF_0x8f, 0x00002, 0x1);
393
394 odm_set_bb_reg(dm, R_0x1b10, 0xff, 0x00);
395 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x0);
396
397 odm_set_bb_reg(dm, R_0x820, 0x00000003, path + 1);
398 odm_set_bb_reg(dm, R_0x1e2c, MASKDWORD, 0xe4e40000);
399 odm_set_bb_reg(dm, R_0x1e28, 0x0000000f, 0x3);
400 odm_set_bb_reg(dm, path_setting[path], 0x000fffff, 0x33312);
401 odm_set_bb_reg(dm, path_setting[path], 0x80000000, 0x1);
402
403 odm_set_bb_reg(dm, set_pi[path], 0xc0000000, 0x0);
404 odm_set_rf_reg(dm, path, RF_0xdf, 0x00010, 0x1);
405 odm_set_rf_reg(dm, path, RF_0x58, 0xfff00, 0x820);
406 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, path);
407
408 odm_set_bb_reg(dm, R_0x1b10, 0x000000ff, 0x0);
409
410 odm_set_bb_reg(dm, R_0x1b2c, 0xff, 0x018);
411 ODM_delay_us(1000);
412 odm_set_bb_reg(dm, R_0x1bcc, 0xff, 0x2d);
413 ODM_delay_us(1000);
414
415 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, set_1b00_cfg1[path]);
416 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, set_1b00_cfg2[path]);
417
418 for (i = 0; i < 100; i++) {
419 ODM_delay_us(1000);
420 RF_DBG(dm, DBG_RF_TXGAPK, "================= delay %dms\n", i + 1);
421 if (odm_get_bb_reg(dm, R_0x2d9c, 0x000000ff) == 0x55)
422 break;
423 }
424
425 odm_set_bb_reg(dm, set_pi[path], 0xc0000000, 0x2);
426 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, path);
427 odm_set_bb_reg(dm, R_0x1bd4, 0x00200000, 0x1);
428 odm_set_bb_reg(dm, R_0x1bd4, 0x001f0000, 0x12);
429 odm_set_bb_reg(dm, R_0x1b9c, 0x00000f00, 0x3);
430
431 txgapk->offset[0][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x0000000f);
432 txgapk->offset[1][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x000000f0);
433 txgapk->offset[2][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x00000f00);
434 txgapk->offset[3][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x0000f000);
435 txgapk->offset[4][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x000f0000);
436 txgapk->offset[5][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x00f00000);
437 txgapk->offset[6][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x0f000000);
438 txgapk->offset[7][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0xf0000000);
439 odm_set_bb_reg(dm, R_0x1b9c, 0x00000f00, 0x4);
440 txgapk->offset[8][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x0000000f);
441 txgapk->offset[9][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x000000f0);
442
443 for (i = 0; i < 10; i++) {
444 if (txgapk->offset[i][path] & BIT(3))
445 txgapk->offset[i][path] = txgapk->offset[i][path] | 0xf0;
446 }
447
448 for (i = 0; i < 10; i++)
449 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] offset %d %d path=%d\n",
450 txgapk->offset[i][path], i, path);
451
452 RF_DBG(dm, DBG_RF_TXGAPK, "========================================\n");
453 } else { /*5G*/
454 odm_set_bb_reg(dm, R_0x1bb8, 0x00100000, 0x0);
455 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, path);
456 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x3f);
457 odm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x0);
458 odm_set_rf_reg(dm, path, RF_0xde, 0x10000, 0x1);
459 odm_set_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK, 0x50011);
460 odm_set_rf_reg(dm, path, RF_0x63, 0x0c000, 0x3);
461 odm_set_rf_reg(dm, path, RF_0x63, 0x0001c, 0x3);
462 odm_set_rf_reg(dm, path, RF_0x63, 0x03000, 0x1);
463 odm_set_rf_reg(dm, path, RF_0x8a, 0x00018, 0x2);
464 odm_set_rf_reg(dm, path, RF_0x00, 0x003e0, 0x12);
465 odm_set_rf_reg(dm, path, RF_0xde, 0x00004, 0x1);
466 odm_set_rf_reg(dm, path, RF_0x1a, 0x00c00, 0x0);
467 odm_set_rf_reg(dm, path, RF_0x8f, 0x00002, 0x1);
468 odm_set_rf_reg(dm, path, RF_0x0, 0xf0000, 0x5);
469
470 odm_set_bb_reg(dm, R_0x1b10, 0xff, 0x0);
471
472 if (channel >= 36 && channel <= 64)
473 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x2);
474 else if (channel >= 100 && channel <= 144)
475 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x3);
476 else if (channel >= 149 && channel <= 177)
477 odm_set_bb_reg(dm, R_0x1b98, 0x00007000, 0x4);
478
479 odm_set_bb_reg(dm, R_0x820, 0x00000003, path + 1);
480 odm_set_bb_reg(dm, R_0x1e2c, MASKDWORD, 0xe4e40000);
481 odm_set_bb_reg(dm, R_0x1e28, 0x0000000f, 0x3);
482 odm_set_bb_reg(dm, path_setting[path], 0x000fffff, 0x33312);
483 odm_set_bb_reg(dm, path_setting[path], 0x80000000, 0x1);
484
485 odm_set_bb_reg(dm, set_pi[path], 0xc0000000, 0x0);
486 odm_set_rf_reg(dm, path, RF_0xdf, 0x00010, 0x1);
487 odm_set_rf_reg(dm, path, RF_0x58, 0xfff00, 0x820);
488 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, path);
489
490 odm_set_bb_reg(dm, R_0x1b10, 0x000000ff, 0x0);
491
492 odm_set_bb_reg(dm, R_0x1b2c, 0xff, 0x018);
493 ODM_delay_us(1000);
494 odm_set_bb_reg(dm, R_0x1bcc, 0xff, 0x36);
495 ODM_delay_us(1000);
496
497 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, set_1b00_cfg1[path]);
498 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, set_1b00_cfg2[path]);
499
500 for (i = 0; i < 100; i++) {
501 ODM_delay_us(1000);
502 RF_DBG(dm, DBG_RF_TXGAPK, "================= delay %dms\n", i + 1);
503 if (odm_get_bb_reg(dm, R_0x2d9c, 0x000000ff) == 0x55)
504 break;
505 }
506
507 odm_set_bb_reg(dm, set_pi[path], 0xc0000000, 0x2);
508 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, path);
509 odm_set_bb_reg(dm, R_0x1bd4, 0x00200000, 0x1);
510 odm_set_bb_reg(dm, R_0x1bd4, 0x001f0000, 0x12);
511 odm_set_bb_reg(dm, R_0x1b9c, 0x00000f00, 0x3);
512
513 txgapk->offset[0][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x0000000f);
514 txgapk->offset[1][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x000000f0);
515 txgapk->offset[2][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x00000f00);
516 txgapk->offset[3][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x0000f000);
517 txgapk->offset[4][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x000f0000);
518 txgapk->offset[5][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x00f00000);
519 txgapk->offset[6][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x0f000000);
520 txgapk->offset[7][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0xf0000000);
521 odm_set_bb_reg(dm, R_0x1b9c, 0x00000f00, 0x4);
522 txgapk->offset[8][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x0000000f);
523 txgapk->offset[9][path] = (s8)odm_get_bb_reg(dm, R_0x1bfc, 0x000000f0);
524
525 for (i = 0; i < 10; i++) {
526 if (txgapk->offset[i][path] & BIT(3))
527 txgapk->offset[i][path] = txgapk->offset[i][path] | 0xf0;
528 }
529
530 for (i = 0; i < 10; i++)
531 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] offset %d %d path=%d\n",
532 txgapk->offset[i][path], i, path);
533
534 RF_DBG(dm, DBG_RF_TXGAPK, "========================================\n");
535 }
536 _halrf_txgapk_reload_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
537 }
538
_halrf_txgapk_rf_restore_8822c(void * dm_void,u8 path)539 void _halrf_txgapk_rf_restore_8822c(
540 void *dm_void, u8 path)
541 {
542 struct dm_struct *dm = (struct dm_struct *)dm_void;
543 u8 i;
544 u32 tmp[10] = {0};
545
546 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
547
548 if (path == RF_PATH_A) {
549 odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, 0xf0000, 0x3);
550 odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x00004, 0x0);
551 odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, 0x00002, 0x0);
552 } else if (path == RF_PATH_B) {
553 odm_set_rf_reg(dm, RF_PATH_B, RF_0x00, 0xf0000, 0x3);
554 odm_set_rf_reg(dm, RF_PATH_B, RF_0xde, 0x00004, 0x0);
555 odm_set_rf_reg(dm, RF_PATH_B, RF_0x8f, 0x00002, 0x0);
556 }
557 }
558
_halrf_txgapk_calculat_tx_gain_8822c(void * dm_void,u32 original_tx_gain,s8 offset)559 u32 _halrf_txgapk_calculat_tx_gain_8822c(
560 void *dm_void, u32 original_tx_gain, s8 offset)
561 {
562 struct dm_struct *dm = (struct dm_struct *)dm_void;
563 struct _hal_rf_ *rf = &dm->rf_table;
564 struct _halrf_txgapk_info *txgapk = &rf->halrf_txgapk_info;
565 u32 modify_tx_gain = original_tx_gain;
566
567 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
568
569 if (((original_tx_gain & 0xf00) >> 8) >= 0xc && ((original_tx_gain & 0xf0) >> 4) >= 0xe) {
570 modify_tx_gain = original_tx_gain;
571 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] original_tx_gain=0x%03X(>=0xCEX) offset=%d modify_tx_gain=0x%03X\n",
572 original_tx_gain, offset, modify_tx_gain);
573 return modify_tx_gain;
574 }
575
576 if (offset < 0) {
577 if ((offset % 2) == 0)
578 modify_tx_gain = modify_tx_gain + (offset / 2);
579 else {
580 modify_tx_gain = modify_tx_gain + 0x1000 + (offset / 2) - 1;
581 }
582 } else {
583 if ((offset % 2) == 0)
584 modify_tx_gain = modify_tx_gain + (offset / 2);
585 else {
586 modify_tx_gain = modify_tx_gain + 0x1000 + (offset / 2);
587 }
588 }
589
590 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] original_tx_gain=0x%X offset=%d modify_tx_gain=0x%X\n",
591 original_tx_gain, offset, modify_tx_gain);
592
593 return modify_tx_gain;
594 }
595
_halrf_txgapk_write_tx_gain_8822c(void * dm_void)596 void _halrf_txgapk_write_tx_gain_8822c(
597 void *dm_void)
598 {
599 struct dm_struct *dm = (struct dm_struct *)dm_void;
600 struct _hal_rf_ *rf = &dm->rf_table;
601 struct _halrf_txgapk_info *txgapk = &rf->halrf_txgapk_info;
602
603 u32 i, j, tmp = 0x20, tmp1 = 0x60, tmp_3f;
604 s8 offset_tmp[11] = {0};
605 u8 channel = *dm->channel, path_idx, band_idx = 1;
606
607 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
608
609 if (channel >= 1 && channel <= 14) {
610 tmp = 0x20; /*2G OFDM*/
611 tmp1 = 0x60; /*2G CCK*/
612 band_idx = 1;
613 } else if (channel >= 36 && channel <= 64) {
614 tmp = 0x200; /*5G L*/
615 tmp1 = 0x0;
616 band_idx = 2;
617 } else if (channel >= 100 && channel <= 144) {
618 tmp = 0x280; /*5G M*/
619 tmp1 = 0x0;
620 band_idx = 3;
621 } else if (channel >= 149 && channel <= 177) {
622 tmp = 0x300; /*5G H*/
623 tmp1 = 0x0;
624 band_idx = 4;
625 }
626
627 for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8822C; path_idx++) {
628 for (i = 0; i <= 10; i++) {
629 offset_tmp[i] = 0;
630 for (j = i; j <= 10; j++) {
631 if ((((txgapk->txgapk_rf3f_bp[band_idx][j][path_idx] & 0xf00) >> 8) >= 0xc) &&
632 (((txgapk->txgapk_rf3f_bp[band_idx][j][path_idx] & 0xf0) >> 4) >= 0xe))
633 continue;
634
635 offset_tmp[i] = offset_tmp[i] + txgapk->offset[j][path_idx];
636 txgapk->fianl_offset[i][path_idx] = offset_tmp[i];
637 }
638
639 if ((((txgapk->txgapk_rf3f_bp[band_idx][i][path_idx] & 0xf00) >> 8) >= 0xc) &&
640 (((txgapk->txgapk_rf3f_bp[band_idx][i][path_idx] & 0xf0) >> 4) >= 0xe))
641 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n",
642 txgapk->txgapk_rf3f_bp[band_idx][i][path_idx]);
643 else
644 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] offset %d %d\n", offset_tmp[i], i);
645 }
646
647 odm_set_rf_reg(dm, path_idx, 0xee, 0xfffff, 0x10000);
648
649 j = 0;
650 for (i = tmp; i <= (tmp + 10); i++) {
651 odm_set_rf_reg(dm, path_idx, RF_0x33, 0xfffff, i);
652
653 tmp_3f = _halrf_txgapk_calculat_tx_gain_8822c(dm,
654 txgapk->txgapk_rf3f_bp[band_idx][j][path_idx], offset_tmp[j]);
655 tmp_3f = tmp_3f & 0x01fff;
656 odm_set_rf_reg(dm, path_idx, RF_0x3f, 0x01fff, tmp_3f);
657
658 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n",
659 i, tmp_3f);
660 j++;
661 }
662
663 #if 0
664 if (tmp1 == 0x60) {
665 j = 0;
666 for (i = tmp1; i <= (tmp1 + 10); i++) {
667 odm_set_rf_reg(dm, path_idx, RF_0x33, 0xfffff, i);
668
669 tmp_3f = _halrf_txgapk_calculat_tx_gain_8822c(dm,
670 txgapk->txgapk_rf3f_bp[band_idx][j][path_idx], offset_tmp[j]);
671 tmp_3f = tmp_3f & 0x01fff;
672 odm_set_rf_reg(dm, path_idx, RF_0x3f, 0x01fff, tmp_3f);
673
674 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n",
675 i, tmp_3f);
676 j++;
677 }
678 }
679 #endif
680 odm_set_rf_reg(dm, path_idx, 0xee, 0xfffff, 0x0);
681 }
682 }
683
_halrf_txgapk_disable_power_trim_8822c(void * dm_void)684 void _halrf_txgapk_disable_power_trim_8822c(
685 void *dm_void)
686 {
687 struct dm_struct *dm = (struct dm_struct *)dm_void;
688 u8 path_idx;
689
690 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
691
692 for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8822C; path_idx++) {
693 odm_set_rf_reg(dm, path_idx, RF_0xde, BIT(9), 0x1);
694 odm_set_rf_reg(dm, path_idx, RF_0x55, 0x000fc000, 0x0);
695 }
696
697 }
698
_halrf_txgapk_enable_power_trim_8822c(void * dm_void)699 void _halrf_txgapk_enable_power_trim_8822c(
700 void *dm_void)
701 {
702 struct dm_struct *dm = (struct dm_struct *)dm_void;
703 u8 path_idx;
704
705 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
706
707 for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8822C; path_idx++)
708 odm_set_rf_reg(dm, path_idx, RF_0xde, BIT(9), 0x0);
709 }
710
halrf_txgapk_save_all_tx_gain_table_8822c(void * dm_void)711 void halrf_txgapk_save_all_tx_gain_table_8822c(
712 void *dm_void)
713 {
714 struct dm_struct *dm = (struct dm_struct *)dm_void;
715 struct _hal_rf_ *rf = &dm->rf_table;
716 struct _halrf_txgapk_info *txgapk = &rf->halrf_txgapk_info;
717 u32 three_wire[2] = {R_0x180c, R_0x410c}, rf18;
718 u8 ch_num[5] = {1, 1, 36, 100, 149};
719 u8 band_num[5] = {0x0, 0x0, 0x1, 0x3, 0x5};
720 u8 cck[5] = {0x1, 0x0, 0x0, 0x0, 0x0};
721 u8 path_idx, band_idx, gain_idx, rf0_idx;
722
723 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
724
725 if (txgapk->read_txgain == 1) {
726 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] Already Read txgapk->read_txgain return!!!\n");
727 _halrf_txgapk_write_gain_bb_table_8822c(dm);
728 return;
729 }
730
731 for (band_idx = 0; band_idx < 5; band_idx++) {
732 for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8822C; path_idx++) {
733 rf18 = odm_get_rf_reg(dm, path_idx, RF_0x18, 0xfffff);
734
735 odm_set_bb_reg(dm, three_wire[path_idx], 0x00000003, 0x0);
736
737 odm_set_rf_reg(dm, path_idx, RF_0x18, 0x000ff, ch_num[band_idx]);
738 odm_set_rf_reg(dm, path_idx, RF_0x18, 0x70000, band_num[band_idx]);
739 odm_set_rf_reg(dm, path_idx, RF_0x1a, 0x00001, cck[band_idx]);
740 odm_set_rf_reg(dm, path_idx, RF_0x1a, 0x10000, cck[band_idx]);
741
742 gain_idx = 0;
743 for (rf0_idx = 1; rf0_idx < 32; rf0_idx = rf0_idx + 3) {
744 odm_set_rf_reg(dm, path_idx, 0x0, 0x000ff, rf0_idx);
745 txgapk->txgapk_rf3f_bp[band_idx][gain_idx][path_idx] = odm_get_rf_reg(dm, path_idx, 0x5f, 0xfffff);
746
747 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] 0x5f=0x%03X band_idx=%d path=%d\n",
748 txgapk->txgapk_rf3f_bp[band_idx][gain_idx][path_idx], band_idx, path_idx);
749 gain_idx++;
750 }
751
752 odm_set_rf_reg(dm, path_idx, RF_0x18, 0xfffff, rf18);
753 odm_set_bb_reg(dm, three_wire[path_idx], 0x00000003, 0x3);
754 }
755 }
756
757 _halrf_txgapk_write_gain_bb_table_8822c(dm);
758
759 txgapk->read_txgain = 1;
760 }
761
halrf_txgapk_reload_tx_gain_8822c(void * dm_void)762 void halrf_txgapk_reload_tx_gain_8822c(
763 void *dm_void)
764 {
765 struct dm_struct *dm = (struct dm_struct *)dm_void;
766 struct _hal_rf_ *rf = &dm->rf_table;
767 struct _halrf_txgapk_info *txgapk = &rf->halrf_txgapk_info;
768
769 u32 i, j, tmp, tmp1;
770 u8 path_idx, band_idx;
771
772 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
773
774 for (band_idx = 1; band_idx <= 4; band_idx++) {
775 if (band_idx == 1) {
776 tmp = 0x20; /*2G OFDM*/
777 tmp1 = 0x60; /*2G CCK*/
778 } else if (band_idx == 2) {
779 tmp = 0x200; /*5G L*/
780 tmp1 = 0x0;
781 } else if (band_idx == 3) {
782 tmp = 0x280; /*5G M*/
783 tmp1 = 0x0;
784 } else if (band_idx == 4) {
785 tmp = 0x300; /*5G H*/
786 tmp1 = 0x0;
787 }
788
789 for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8822C; path_idx++) {
790 odm_set_rf_reg(dm, path_idx, 0xee, 0xfffff, 0x10000);
791
792 j = 0;
793 for (i = tmp; i <= (tmp + 10); i++) {
794 odm_set_rf_reg(dm, path_idx, RF_0x33, 0xfffff, i);
795
796 odm_set_rf_reg(dm, path_idx, RF_0x3f, 0xfff,
797 txgapk->txgapk_rf3f_bp[band_idx][j][path_idx]);
798
799 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] 0x33=0x%05X 0x3f=0x%03X\n",
800 i, txgapk->txgapk_rf3f_bp[band_idx][j][path_idx]);
801 j++;
802 }
803
804 #if 0
805 if (tmp1 == 0x60) {
806 j = 0;
807 for (i = tmp1; i <= (tmp1 + 10); i++) {
808 odm_set_rf_reg(dm, path_idx, RF_0x33, 0xfffff, i);
809
810 odm_set_rf_reg(dm, path_idx, RF_0x3f, 0xfff,
811 txgapk->txgapk_rf3f_bp[band_idx][j][path_idx]);
812
813 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n",
814 i, txgapk->txgapk_rf3f_bp[band_idx][j][path_idx]);
815 j++;
816 }
817 }
818 #endif
819 odm_set_rf_reg(dm, path_idx, 0xee, 0xfffff, 0x0);
820 }
821 }
822 }
823
halrf_txgapk_8822c(void * dm_void)824 void halrf_txgapk_8822c(
825 void *dm_void)
826 {
827 struct dm_struct *dm = (struct dm_struct *)dm_void;
828 struct _hal_rf_ *rf = &dm->rf_table;
829 struct _halrf_txgapk_info *txgapk = &rf->halrf_txgapk_info;
830 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
831 u8 path_idx;
832 u32 bb_reg_backup[2];
833 u32 bb_reg[2] = {R_0x520, R_0x1e70};
834
835 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] ======>%s\n", __func__);
836
837 if (txgapk->read_txgain == 0) {
838 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] txgapk->read_txgain == 0 return!!!\n");
839 return;
840 }
841
842 if (*dm->mp_mode == 1) {
843 if (cali_info->txpowertrack_control == 2 ||
844 cali_info->txpowertrack_control == 3 ||
845 cali_info->txpowertrack_control == 4 ||
846 cali_info->txpowertrack_control == 5) {
847 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] MP Mode in TSSI mode. return!!!\n");
848 return;
849 }
850 } else {
851 if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {
852 RF_DBG(dm, DBG_RF_TXGAPK, "[TXGAPK] Normal Mode in TSSI mode. return!!!\n");
853 return;
854 }
855 }
856
857 rf->is_tssi_in_progress = 1;
858
859 /*_halrf_txgapk_disable_power_trim_8822c(dm);*/
860
861 _halrf_txgapk_backup_bb_registers_8822c(dm, bb_reg, bb_reg_backup, 2);
862
863 _halrf_txgapk_tx_pause_8822c(dm);
864
865 for (path_idx = 0; path_idx < MAX_PATH_NUM_8822C; path_idx++) {
866 _halrf_txgapk_bb_dpk_8822c(dm, path_idx);
867 _halrf_txgapk_afe_dpk_8822c(dm, path_idx);
868 _halrf_txgapk_calculate_offset_8822c(dm, path_idx);
869 _halrf_txgapk_rf_restore_8822c(dm, path_idx);
870 _halrf_txgapk_afe_dpk_restore_8822c(dm, path_idx);
871 _halrf_txgapk_bb_dpk_restore_8822c(dm, path_idx);
872 }
873
874 _halrf_txgapk_write_tx_gain_8822c(dm);
875
876 _halrf_txgapk_reload_bb_registers_8822c(dm, bb_reg, bb_reg_backup, 2);
877
878 /*_halrf_txgapk_enable_power_trim_8822c(dm);*/
879
880 rf->is_tssi_in_progress = 0;
881 }
882
883
884 #endif
885