1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
28 #if RT_PLATFORM == PLATFORM_MACOSX
29 #include "phydm_precomp.h"
30 #else
31 #include "../phydm_precomp.h"
32 #endif
33 #else
34 #include "../../phydm_precomp.h"
35 #endif
36
37 #if (RTL8822C_SUPPORT == 1)
38
_backup_bb_registers_8822c(void * dm_void,u32 * reg,u32 * reg_backup,u32 reg_num)39 void _backup_bb_registers_8822c(
40 void *dm_void,
41 u32 *reg,
42 u32 *reg_backup,
43 u32 reg_num)
44 {
45 struct dm_struct *dm = (struct dm_struct *)dm_void;
46 u32 i;
47
48 for (i = 0; i < reg_num; i++) {
49 reg_backup[i] = odm_get_bb_reg(dm, reg[i], MASKDWORD);
50
51 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n",
52 reg[i], reg_backup[i]);
53 }
54 }
55
_reload_bb_registers_8822c(void * dm_void,u32 * reg,u32 * reg_backup,u32 reg_num)56 void _reload_bb_registers_8822c(
57 void *dm_void,
58 u32 *reg,
59 u32 *reg_backup,
60 u32 reg_num)
61
62 {
63 struct dm_struct *dm = (struct dm_struct *)dm_void;
64 u32 i;
65
66 for (i = 0; i < reg_num; i++) {
67 odm_set_bb_reg(dm, reg[i], MASKDWORD, reg_backup[i]);
68 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n",
69 reg[i], reg_backup[i]);
70 }
71 }
72
73
74
_halrf_driver_rate_to_tssi_rate_8822c(void * dm_void,u8 rate)75 u8 _halrf_driver_rate_to_tssi_rate_8822c(
76 void *dm_void, u8 rate)
77 {
78 u8 tssi_rate = 0;
79
80 struct dm_struct *dm = (struct dm_struct *)dm_void;
81
82 if (rate == MGN_1M)
83 tssi_rate = 0;
84 else if (rate == MGN_2M)
85 tssi_rate = 1;
86 else if (rate == MGN_5_5M)
87 tssi_rate = 2;
88 else if (rate == MGN_11M)
89 tssi_rate = 3;
90 else if (rate == MGN_6M)
91 tssi_rate = 4;
92 else if (rate == MGN_9M)
93 tssi_rate = 5;
94 else if (rate == MGN_12M)
95 tssi_rate = 6;
96 else if (rate == MGN_18M)
97 tssi_rate = 7;
98 else if (rate == MGN_24M)
99 tssi_rate = 8;
100 else if (rate == MGN_36M)
101 tssi_rate = 9;
102 else if (rate == MGN_48M)
103 tssi_rate = 10;
104 else if (rate == MGN_54M)
105 tssi_rate = 11;
106 else if (rate >= MGN_MCS0 && rate <= MGN_VHT4SS_MCS9)
107 tssi_rate = rate - MGN_MCS0 + 12;
108 else
109 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
110 "===>%s not exit tx rate\n", __func__);
111
112 return tssi_rate;
113 }
114
_halrf_tssi_rate_to_driver_rate_8822c(void * dm_void,u8 rate)115 u8 _halrf_tssi_rate_to_driver_rate_8822c(
116 void *dm_void, u8 rate)
117 {
118 u8 driver_rate = 0;
119
120 struct dm_struct *dm = (struct dm_struct *)dm_void;
121
122 if (rate == 0)
123 driver_rate = MGN_1M;
124 else if (rate == 1)
125 driver_rate = MGN_2M;
126 else if (rate == 2)
127 driver_rate = MGN_5_5M;
128 else if (rate == 3)
129 driver_rate = MGN_11M;
130 else if (rate == 4)
131 driver_rate = MGN_6M;
132 else if (rate == 5)
133 driver_rate = MGN_9M;
134 else if (rate == 6)
135 driver_rate = MGN_12M;
136 else if (rate == 7)
137 driver_rate = MGN_18M;
138 else if (rate == 8)
139 driver_rate = MGN_24M;
140 else if (rate == 9)
141 driver_rate = MGN_36M;
142 else if (rate == 10)
143 driver_rate = MGN_48M;
144 else if (rate == 11)
145 driver_rate = MGN_54M;
146 else if (rate >= 12 && rate <= 83)
147 driver_rate = rate + MGN_MCS0 - 12;
148 else
149 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
150 "===>%s not exit tx rate\n", __func__);
151
152 return driver_rate;
153 }
154
_halrf_calculate_txagc_codeword_8822c(void * dm_void,u16 * tssi_value,s16 * txagc_value)155 void _halrf_calculate_txagc_codeword_8822c(
156 void *dm_void, u16 *tssi_value, s16 *txagc_value)
157 {
158 #if 0
159 struct dm_struct *dm = (struct dm_struct *)dm_void;
160 struct _hal_rf_ *rf = &dm->rf_table;
161 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
162
163 u32 i, mcs7 = 19;
164
165 for (i = 0; i < TSSI_CODE_NUM; i++) {
166 txagc_value[i] =
167 ((tssi_value[i] - tssi->tssi_codeword[mcs7]) / TSSI_TXAGC_DIFF) & 0x7f;
168
169 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
170 "===>%s txagc_value[%d](0x%x) = ((tssi_value[%d](%d) - tssi_value[mcs7](%d)) / %d) & 0x7f\n",
171 __func__, i, txagc_value[i], i, tssi_value[i], tssi_value[mcs7], TSSI_TXAGC_DIFF);
172 }
173 #endif
174 }
175
_halrf_get_efuse_tssi_offset_8822c(void * dm_void,u8 path)176 u32 _halrf_get_efuse_tssi_offset_8822c(
177 void *dm_void, u8 path)
178 {
179 struct dm_struct *dm = (struct dm_struct *)dm_void;
180 struct _hal_rf_ *rf = &dm->rf_table;
181 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
182 u8 channel = *dm->channel;
183 u32 offset = 0;
184 u32 offset_index = 0;
185 /*u8 bandwidth = *dm->band_width;*/
186
187 if (channel >= 1 && channel <= 2)
188 offset_index = 6;
189 else if (channel >= 3 && channel <= 5)
190 offset_index = 7;
191 else if (channel >= 6 && channel <= 8)
192 offset_index = 8;
193 else if (channel >= 9 && channel <= 11)
194 offset_index = 9;
195 else if (channel >= 12 && channel <= 14)
196 offset_index = 10;
197 else if (channel >= 36 && channel <= 40)
198 offset_index = 11;
199 else if (channel >= 42 && channel <= 48)
200 offset_index = 12;
201 else if (channel >= 50 && channel <= 58)
202 offset_index = 13;
203 else if (channel >= 60 && channel <= 64)
204 offset_index = 14;
205 else if (channel >= 100 && channel <= 104)
206 offset_index = 15;
207 else if (channel >= 106 && channel <= 112)
208 offset_index = 16;
209 else if (channel >= 114 && channel <= 120)
210 offset_index = 17;
211 else if (channel >= 122 && channel <= 128)
212 offset_index = 18;
213 else if (channel >= 130 && channel <= 136)
214 offset_index = 19;
215 else if (channel >= 138 && channel <= 144)
216 offset_index = 20;
217 else if (channel >= 149 && channel <= 153)
218 offset_index = 21;
219 else if (channel >= 155 && channel <= 161)
220 offset_index = 22;
221 else if (channel >= 163 && channel <= 169)
222 offset_index = 23;
223 else if (channel >= 171 && channel <= 177)
224 offset_index = 24;
225
226 offset = (u32)tssi->tssi_efuse[path][offset_index];
227
228 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
229 "=====>%s channel=%d offset_index(Chn Group)=%d offset=%d\n",
230 __func__, channel, offset_index, offset);
231
232 return offset;
233 }
234
_halrf_get_kfree_tssi_offset_8822c(void * dm_void)235 s8 _halrf_get_kfree_tssi_offset_8822c(
236 void *dm_void)
237 {
238 struct dm_struct *dm = (struct dm_struct *)dm_void;
239 struct _hal_rf_ *rf = &dm->rf_table;
240 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
241 u8 channel = *dm->channel;
242 s8 offset = 0;
243 u32 offset_index = 0;
244
245 if (channel >= 1 && channel <= 14)
246 offset_index = 0;
247 else if (channel >= 36 && channel <= 64)
248 offset_index = 1;
249 else if (channel >= 100 && channel <= 144)
250 offset_index = 2;
251 else if (channel >= 149 && channel <= 177)
252 offset_index = 3;
253
254 return offset = tssi->tssi_kfree_efuse[0][offset_index];
255 }
256
_halrf_calculate_set_thermal_codeword_8822c(void * dm_void)257 void _halrf_calculate_set_thermal_codeword_8822c(
258 void *dm_void)
259 {
260 struct dm_struct *dm = (struct dm_struct *)dm_void;
261 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
262 struct _hal_rf_ *rf = &dm->rf_table;
263 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
264
265 u8 channel = *dm->channel, i, thermal;
266 s8 j;
267 u8 rate = phydm_get_tx_rate(dm);
268 u32 thermal_offset_tmp = 0, thermal_offset_index = 0x10, thermal_tmp = 0xff, tmp;
269 s8 thermal_offset[64] = {0};
270 u8 thermal_up_a[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_a[DELTA_SWINGIDX_SIZE] = {0};
271 u8 thermal_up_b[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_b[DELTA_SWINGIDX_SIZE] = {0};
272
273 tssi->thermal[RF_PATH_A] = 0xff;
274 tssi->thermal[RF_PATH_B] = 0xff;
275
276 if (cali_info->txpowertrack_control == 4) {
277 tmp = thermal_offset_index;
278 i = 0;
279 while (i < 64) {
280 thermal_offset_tmp = 0;
281 for (j = 0; j < 23; j = j + 6)
282 thermal_offset_tmp = thermal_offset_tmp | ((thermal_offset[i++] & 0x3f) << j);
283
284 thermal_offset_tmp = thermal_offset_tmp | ((tmp++ & 0xff) << 24);
285
286 odm_set_bb_reg(dm, 0x18f4, MASKDWORD, thermal_offset_tmp);
287 odm_set_bb_reg(dm, 0x41f4, MASKDWORD, thermal_offset_tmp);
288
289 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
290 "===>%s write addr:0x%x value=0x%08x\n",
291 __func__, 0x18f4, thermal_offset_tmp);
292
293 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
294 "===>%s write addr:0x%x value=0x%08x\n",
295 __func__, 0x41f4, thermal_offset_tmp);
296 }
297
298 odm_set_bb_reg(dm, R_0x1c20, 0x000fc000, 0x0);
299 odm_set_bb_reg(dm, R_0x1c20, 0x03f00000, 0x0);
300
301 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
302 "======>%s TSSI Calibration Mode Set Thermal Table == 0 return!!!\n", __func__);
303 return;
304 }
305
306 if (rate == ODM_MGN_1M || rate == ODM_MGN_2M || rate == ODM_MGN_5_5M || rate == ODM_MGN_11M) {
307 odm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_2g_cck_a_p, sizeof(thermal_up_a));
308 odm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_2g_cck_a_n, sizeof(thermal_down_a));
309 odm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_2g_cck_b_p, sizeof(thermal_up_b));
310 odm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_2g_cck_b_n, sizeof(thermal_down_b));
311 } else if (channel >= 1 && channel <= 14) {
312 odm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_2ga_p, sizeof(thermal_up_a));
313 odm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_2ga_n, sizeof(thermal_down_a));
314 odm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_2gb_p, sizeof(thermal_up_b));
315 odm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_2gb_n, sizeof(thermal_down_b));
316 } else if (channel >= 36 && channel <= 64) {
317 odm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_5ga_p[0], sizeof(thermal_up_a));
318 odm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_5ga_n[0], sizeof(thermal_down_a));
319 odm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_5gb_p[0], sizeof(thermal_up_b));
320 odm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_5gb_n[0], sizeof(thermal_down_b));
321 } else if (channel >= 100 && channel <= 144) {
322 odm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_5ga_p[1], sizeof(thermal_up_a));
323 odm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_5ga_n[1], sizeof(thermal_down_a));
324 odm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_5gb_p[1], sizeof(thermal_up_b));
325 odm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_5gb_n[1], sizeof(thermal_down_b));
326 } else if (channel >= 149 && channel <= 177) {
327 odm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_5ga_p[2], sizeof(thermal_up_a));
328 odm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_5ga_n[2], sizeof(thermal_down_a));
329 odm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_5gb_p[2], sizeof(thermal_up_b));
330 odm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_5gb_n[2], sizeof(thermal_down_b));
331 }
332
333 /*path s0*/
334 odm_efuse_logical_map_read(dm, 1, 0xd0, &thermal_tmp);
335
336 thermal = (u8)thermal_tmp;
337
338 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
339 "======>%s channel=%d thermal_pahtA=0x%x cali_info->txpowertrack_control=%d\n",
340 __func__, channel, thermal, cali_info->txpowertrack_control);
341
342 if (thermal == 0xff) {
343 tmp = thermal_offset_index;
344 i = 0;
345 while (i < 64) {
346 thermal_offset_tmp = 0;
347 for (j = 0; j < 23; j = j + 6)
348 thermal_offset_tmp = thermal_offset_tmp | ((thermal_offset[i++] & 0x3f) << j);
349
350 thermal_offset_tmp = thermal_offset_tmp | ((tmp++ & 0xff) << 24);
351
352 odm_set_bb_reg(dm, 0x18f4, MASKDWORD, thermal_offset_tmp);
353
354 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
355 "===>%s write addr:0x%x value=0x%08x\n",
356 __func__, 0x18f4, thermal_offset_tmp);
357 }
358
359 odm_set_bb_reg(dm, R_0x1c20, 0x000fc000, 0x0);
360
361 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
362 "======>%s thermal A=0x%x!!!\n", __func__, thermal);
363 }
364
365 tssi->thermal[RF_PATH_A] = thermal;
366
367 if (thermal != 0xff) {
368 odm_set_bb_reg(dm, R_0x1c20, 0x000fc000, (thermal & 0x3f));
369
370 i = 0;
371 for (j = thermal; j >= 0; j--) {
372 if (i < DELTA_SWINGIDX_SIZE)
373 thermal_offset[j] = thermal_down_a[i++];
374 else
375 thermal_offset[j] = thermal_down_a[DELTA_SWINGIDX_SIZE - 1];
376 }
377
378 i = 0;
379 for (j = thermal; j < 64; j++) {
380 if (i < DELTA_SWINGIDX_SIZE)
381 thermal_offset[j] = -1 * thermal_up_a[i++];
382 else
383 thermal_offset[j] = -1 * thermal_up_a[DELTA_SWINGIDX_SIZE - 1];
384 }
385
386 for (i = 0; i < 64; i = i + 4) {
387 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
388 "======>%s thermal_offset[%.2d]=%.2x %.2x %.2x %.2x\n",
389 __func__, i, thermal_offset[i] & 0xff, thermal_offset[i + 1] & 0xff,
390 thermal_offset[i + 2] & 0xff, thermal_offset[i + 3] & 0xff);
391 }
392
393 tmp = thermal_offset_index;
394 i = 0;
395 while (i < 64) {
396 thermal_offset_tmp = 0;
397 for (j = 0; j < 23; j = j + 6)
398 thermal_offset_tmp = thermal_offset_tmp | ((thermal_offset[i++] & 0x3f) << j);
399
400 thermal_offset_tmp = thermal_offset_tmp | ((tmp++ & 0xff) << 24);
401
402 odm_set_bb_reg(dm, 0x18f4, MASKDWORD, thermal_offset_tmp);
403
404 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
405 "======>%s write addr:0x%x value=0x%08x\n",
406 __func__, 0x18f4, thermal_offset_tmp);
407 }
408 } else
409 odm_set_bb_reg(dm, R_0x1c20, 0x000fc000, 0x0);
410
411
412 /*path s1*/
413 odm_memory_set(dm, thermal_offset, 0, sizeof(thermal_offset));
414 odm_efuse_logical_map_read(dm, 1, 0xd1, &thermal_tmp);
415
416 thermal = (u8)thermal_tmp;
417
418 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
419 "======>%s channel=%d thermal pahtB=0x%x cali_info->txpowertrack_control=%d\n",
420 __func__, channel, thermal, cali_info->txpowertrack_control);
421
422 if (thermal == 0xff) {
423 tmp = thermal_offset_index;
424 i = 0;
425 while (i < 64) {
426 thermal_offset_tmp = 0;
427 for (j = 0; j < 23; j = j + 6)
428 thermal_offset_tmp = thermal_offset_tmp | ((thermal_offset[i++] & 0x3f) << j);
429
430 thermal_offset_tmp = thermal_offset_tmp | ((tmp++ & 0xff) << 24);
431
432 odm_set_bb_reg(dm, 0x41f4, MASKDWORD, thermal_offset_tmp);
433
434 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
435 "===>%s write addr:0x%x value=0x%08x\n",
436 __func__, 0x41f4, thermal_offset_tmp);
437 }
438
439 odm_set_bb_reg(dm, R_0x1c20, 0x03f00000, 0x0);
440
441 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
442 "======>%s thermal=0x%x return!!!\n", __func__, thermal);
443 }
444
445 tssi->thermal[RF_PATH_B] = thermal;
446
447 if (thermal != 0xff) {
448 odm_set_bb_reg(dm, R_0x1c20, 0x03f00000, (thermal & 0x3f));
449
450 i = 0;
451 for (j = thermal; j >= 0; j--) {
452 if (i < DELTA_SWINGIDX_SIZE)
453 thermal_offset[j] = thermal_down_b[i++];
454 else
455 thermal_offset[j] = thermal_down_b[DELTA_SWINGIDX_SIZE - 1];
456 }
457
458 i = 0;
459 for (j = thermal; j < 64; j++) {
460 if (i < DELTA_SWINGIDX_SIZE)
461 thermal_offset[j] = -1 * thermal_up_b[i++];
462 else
463 thermal_offset[j] = -1 * thermal_up_b[DELTA_SWINGIDX_SIZE - 1];
464 }
465
466 for (i = 0; i < 64; i = i + 4) {
467 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
468 "======>%s thermal_offset[%.2d]=%.2x %.2x %.2x %.2x\n",
469 __func__, i, thermal_offset[i] & 0xff, thermal_offset[i + 1] & 0xff,
470 thermal_offset[i + 2] & 0xff, thermal_offset[i + 3] & 0xff);
471 }
472
473 tmp = thermal_offset_index;
474 i = 0;
475 while (i < 64) {
476 thermal_offset_tmp = 0;
477 for (j = 0; j < 23; j = j + 6)
478 thermal_offset_tmp = thermal_offset_tmp | ((thermal_offset[i++] & 0x3f) << j);
479
480 thermal_offset_tmp = thermal_offset_tmp | ((tmp++ & 0xff) << 24);
481
482 odm_set_bb_reg(dm, 0x41f4, MASKDWORD, thermal_offset_tmp);
483
484 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
485 "======>%s write addr:0x%x value=0x%08x\n",
486 __func__, 0x41f4, thermal_offset_tmp);
487 }
488 } else
489 odm_set_bb_reg(dm, R_0x1c20, 0x03f00000, 0x0);
490 }
491
_halrf_set_txagc_codeword_8822c(void * dm_void,s16 * tssi_value)492 void _halrf_set_txagc_codeword_8822c(
493 void *dm_void, s16 *tssi_value)
494 {
495 #if 0
496 struct dm_struct *dm = (struct dm_struct *)dm_void;
497 u32 i, j, k = 0, tssi_value_tmp;
498
499 /*power by rate table (tssi codeword)*/
500 for (i = 0x3a00; i <= R_0x3a50; i = i + 4) {
501 tssi_value_tmp = 0;
502
503 for (j = 0; j < 31; j = j + 8)
504 tssi_value_tmp = tssi_value_tmp | ((tssi_value[k++] & 0x7f) << j);
505
506 odm_set_bb_reg(dm, i, MASKDWORD, tssi_value_tmp);
507
508 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
509 "===>%s write addr:0x%x value=0x%08x\n",
510 __func__, i, tssi_value_tmp);
511 }
512 #endif
513 }
514
_halrf_set_efuse_kfree_offset_8822c(void * dm_void)515 void _halrf_set_efuse_kfree_offset_8822c(
516 void *dm_void)
517 {
518 #if 0
519 struct dm_struct *dm = (struct dm_struct *)dm_void;
520 struct _hal_rf_ *rf = &dm->rf_table;
521 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
522
523 s32 offset = 0;
524
525 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
526 "===>%s\n", __func__);
527
528 /*path s0*/
529 /*2G CCK*/
530 offset = (_halrf_get_efuse_tssi_offset_8822c(dm, 3) +
531 _halrf_get_kfree_tssi_offset_8822c(dm)) & 0xff;
532 odm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, (u32)offset);
533
534 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
535 "===>%s write addr:0x%x value=0x%08x\n",
536 __func__, R_0x18e8, offset);
537
538 /*2G & 5G OFDM*/
539 offset = (_halrf_get_efuse_tssi_offset_8822c(dm, 19) +
540 _halrf_get_kfree_tssi_offset_8822c(dm)) & 0xff;
541 odm_set_bb_reg(dm, R_0x18a8, 0xff000000, (u32)offset);
542
543 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
544 "===>%s write addr:0x%x value=0x%08x\n",
545 __func__, R_0x18a8, offset);
546
547 /*path s1*/
548 /*2G CCK*/
549 offset = (_halrf_get_efuse_tssi_offset_8822c(dm, 3) +
550 _halrf_get_kfree_tssi_offset_8822c(dm)) & 0xff;
551 odm_set_bb_reg(dm, R_0x1ef0, 0x0001fe00, (u32)offset);
552
553 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
554 "===>%s write addr:0x%x value=0x%08x\n",
555 __func__, R_0x1ef0, offset);
556
557 /*2G & 5G OFDM*/
558 offset = (_halrf_get_efuse_tssi_offset_8822c(dm, 19) +
559 _halrf_get_kfree_tssi_offset_8822c(dm)) & 0xff;
560 odm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, (u32)offset);
561
562 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
563 "===>%s write addr:0x%x value=0x%08x\n",
564 __func__, R_0x1eec, offset);
565 #endif
566 }
567
_halrf_tssi_init_8822c(void * dm_void)568 void _halrf_tssi_init_8822c(
569 void *dm_void)
570 {
571 struct dm_struct *dm = (struct dm_struct *)dm_void;
572 struct _hal_rf_ *rf = &dm->rf_table;
573 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
574
575 _halrf_calculate_set_thermal_codeword_8822c(dm);
576 halrf_calculate_tssi_codeword_8822c(dm);
577 /*_halrf_calculate_txagc_codeword_8822c(dm, tssi->tssi_codeword, tssi->txagc_codeword);*/
578 /*_halrf_set_txagc_codeword_8822c(dm, tssi->txagc_codeword);*/
579 halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);
580 /*_halrf_set_efuse_kfree_offset_8822c(dm);*/
581 }
582
_halrf_tssi_8822c(void * dm_void)583 void _halrf_tssi_8822c(
584 void *dm_void)
585 {
586 struct dm_struct *dm = (struct dm_struct *)dm_void;
587 struct _hal_rf_ *rf = &dm->rf_table;
588 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
589 u8 channel = *dm->channel;
590
591 /*path s0*/
592 if (channel >= 1 && channel <= 14) {
593 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
594 /*odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4);*/
595 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);
596 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0044);
597 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0044);
598 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0044);
599 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0044);
600 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);
601 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0044);
602 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);
603 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);
604 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);
605 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);
606 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);
607 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);
608 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);
609 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);
610 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);
611 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
612 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
613 odm_set_bb_reg(dm, R_0x1c24, 0x07f80000, 0x20);
614 odm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x2);
615 odm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x0);
616 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
617 odm_set_bb_reg(dm, R_0x18e8, 0x00000001, 0x0);
618 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
619 odm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);
620 odm_set_bb_reg(dm, R_0x18ec, 0x80000000, 0x1);
621 odm_set_bb_reg(dm, R_0x1880, 0x80000000, 0x1);
622 odm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x1266);
623 odm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);
624 odm_set_bb_reg(dm, R_0x1880, 0x7fc00000, 0x000);
625 /*odm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);*/
626 /*odm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, 0x00);*/
627 odm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x110);
628 odm_set_rf_reg(dm, RF_PATH_A, RF_0x7f, 0x00002, 0x1);
629 odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);
630 odm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x0000c, 0x3);
631 odm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x000c0, 0x0);
632 odm_set_rf_reg(dm, RF_PATH_A, RF_0x6e, 0x001e0, 0x0);
633 odm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);
634 odm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x1);
635 odm_set_bb_reg(dm, R_0x1800, 0x80000000, 0x1);
636 odm_set_bb_reg(dm, R_0x1804, 0x80000000, 0x1);
637 odm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);
638 odm_set_bb_reg(dm, R_0x1800, 0x40000000, 0x0);
639 odm_set_bb_reg(dm, R_0x1804, 0x40000000, 0x0);
640 odm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x0);
641 odm_set_bb_reg(dm, R_0x18ec, 0x40000000, 0x0);
642 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
643 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
644 odm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);
645 } else {
646 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
647 /*odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x2);*/
648 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);
649 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0042);
650 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0042);
651 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0042);
652 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0042);
653 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);
654 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0042);
655 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);
656 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);
657 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);
658 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);
659 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);
660 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);
661 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);
662 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);
663 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);
664 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
665 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
666 odm_set_bb_reg(dm, R_0x1c24, 0x07f80000, 0x20);
667 odm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x2);
668 odm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x0);
669 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
670 odm_set_bb_reg(dm, R_0x18e8, 0x00000001, 0x0);
671 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
672 odm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);
673 odm_set_bb_reg(dm, R_0x1880, 0x80000000, 0x1);
674 odm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x1266);
675 odm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);
676 /*odm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);*/
677 odm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x110);
678 odm_set_rf_reg(dm, RF_PATH_A, RF_0x7f, 0x00100, 0x1);
679 odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);
680 odm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x00003, 0x3);
681 odm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x00030, 0x2);
682 odm_set_rf_reg(dm, RF_PATH_A, RF_0x6f, 0x001e0, 0x0);
683 odm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);
684 odm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x1);
685 odm_set_bb_reg(dm, R_0x1800, 0x80000000, 0x1);
686 odm_set_bb_reg(dm, R_0x1804, 0x80000000, 0x1);
687 odm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);
688 odm_set_bb_reg(dm, R_0x1800, 0x40000000, 0x0);
689 odm_set_bb_reg(dm, R_0x1804, 0x40000000, 0x0);
690 odm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x0);
691 odm_set_bb_reg(dm, R_0x18ec, 0x40000000, 0x0);
692 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
693 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
694 odm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);
695 }
696
697 /*path s1*/
698 if (channel >= 1 && channel <= 14) {
699 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
700 /*odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4);*/
701 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);
702 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0044);
703 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0044);
704 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0044);
705 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0044);
706 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);
707 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0044);
708 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);
709 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);
710 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);
711 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);
712 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);
713 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);
714 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);
715 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);
716 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);
717 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
718 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
719 odm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);
720 odm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x2);
721 odm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x0);
722 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
723 odm_set_bb_reg(dm, R_0x41e8, 0x00000001, 0x0);
724 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
725 odm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);
726 odm_set_bb_reg(dm, R_0x41ec, 0x80000000, 0x1);
727 odm_set_bb_reg(dm, R_0x4180, 0x80000000, 0x1);
728 odm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x1266);
729 odm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);
730 odm_set_bb_reg(dm, R_0x4180, 0x7fc00000, 0x000);
731 /*odm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);*/
732 /*odm_set_bb_reg(dm, R_0x41e8, 0x01fe0000, 0x00);*/
733 odm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x110);
734 odm_set_rf_reg(dm, RF_PATH_B, RF_0x7f, 0x00002, 0x1);
735 odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, 0x03000, 0x3);
736 odm_set_rf_reg(dm, RF_PATH_B, RF_0x67, 0x0000c, 0x3);
737 odm_set_rf_reg(dm, RF_PATH_B, RF_0x67, 0x000c0, 0x0);
738 odm_set_rf_reg(dm, RF_PATH_B, RF_0x6e, 0x001e0, 0x0);
739 odm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);
740 odm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x1);
741 odm_set_bb_reg(dm, R_0x4100, 0x80000000, 0x1);
742 odm_set_bb_reg(dm, R_0x4104, 0x80000000, 0x1);
743 odm_set_bb_reg(dm, R_0x4100, 0x40000000, 0x0);
744 odm_set_bb_reg(dm, R_0x4104, 0x40000000, 0x0);
745 odm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x0);
746 odm_set_bb_reg(dm, R_0x41ec, 0x40000000, 0x0);
747 odm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);
748 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x1);
749 /*odm_set_bb_reg(dm, R_0x1c20, 0x03f00000, 0x26);*/
750 } else {
751 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
752 /*odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x2);*/
753 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);
754 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0042);
755 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0042);
756 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0042);
757 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0042);
758 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);
759 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0042);
760 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);
761 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);
762 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);
763 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);
764 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);
765 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);
766 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);
767 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);
768 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);
769 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
770 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
771 odm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);
772 odm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x2);
773 odm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x0);
774 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
775 odm_set_bb_reg(dm, R_0x41e8, 0x00000001, 0x0);
776 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
777 odm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);
778 odm_set_bb_reg(dm, R_0x4180, 0x80000000, 0x1);
779 odm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x1266);
780 odm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);
781 /*odm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);*/
782 odm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x110);
783 odm_set_rf_reg(dm, RF_PATH_B, RF_0x7f, 0x00100, 0x1);
784 odm_set_rf_reg(dm, RF_PATH_B, RF_0x65, 0x03000, 0x3);
785 odm_set_rf_reg(dm, RF_PATH_B, RF_0x67, 0x00003, 0x3);
786 odm_set_rf_reg(dm, RF_PATH_B, RF_0x67, 0x00030, 0x2);
787 odm_set_rf_reg(dm, RF_PATH_B, RF_0x6f, 0x001e0, 0x0);
788 odm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);
789 odm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x1);
790 odm_set_bb_reg(dm, R_0x4100, 0x80000000, 0x1);
791 odm_set_bb_reg(dm, R_0x4104, 0x80000000, 0x1);
792 odm_set_bb_reg(dm, R_0x4100, 0x40000000, 0x0);
793 odm_set_bb_reg(dm, R_0x4104, 0x40000000, 0x0);
794 odm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x0);
795 odm_set_bb_reg(dm, R_0x41ec, 0x40000000, 0x0);
796 odm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);
797 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x1);
798 /*odm_set_bb_reg(dm, R_0x1c20, 0x03f00000, 0x26);*/
799 }
800 }
801
_halrf_thermal_init_8822c(void * dm_void)802 void _halrf_thermal_init_8822c(
803 void *dm_void)
804 {
805 #if 0
806 struct dm_struct *dm = (struct dm_struct *)dm_void;
807 struct _hal_rf_ *rf = &dm->rf_table;
808 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
809
810 _halrf_calculate_set_thermal_codeword_8822c(dm);
811 /*halrf_calculate_tssi_codeword_8822c(dm);*/
812 /*_halrf_calculate_txagc_codeword_8822c(dm, tssi->tssi_codeword, tssi->txagc_codeword);*/
813 /*_halrf_set_txagc_codeword_8822c(dm, tssi->txagc_codeword);*/
814 /*halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);*/
815 /*_halrf_set_efuse_kfree_offset_8822c(dm);*/
816 #endif
817 }
818
halrf_calculate_tssi_codeword_8822c(void * dm_void)819 void halrf_calculate_tssi_codeword_8822c(
820 void *dm_void)
821 {
822 struct dm_struct *dm = (struct dm_struct *)dm_void;
823 struct _hal_rf_ *rf = &dm->rf_table;
824 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
825
826 u8 i, rate;
827 u8 channel = *dm->channel, bandwidth = *dm->band_width;
828 u32 big_a, small_a, slope, db_temp;
829 s32 samll_b = 64;
830 /*u32 big_a_reg[2] = {0x18a8, 0x1eec};*/
831 /*u32 big_a_bit_mask[2] = {0x7ffc, 0x1fff};*/
832
833 big_a = odm_get_bb_reg(dm, 0x18a8, 0x7ffc);
834
835 if (big_a == 0) {
836 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
837 "======>%s big_a = %d rf_path=%d return !!!\n",
838 __func__, big_a, RF_PATH_A);
839 return;
840 }
841
842 big_a = (big_a * 100) / 128; /* 100 * big_a */
843 small_a = 434295 / big_a; /* 1000 * small_a */
844 slope = 1000000 / small_a; /* 1000 * slope */
845
846 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
847 "======>%s 0x18a8[14:2] = 0x%x(%d) 100*big_a(%d) = 0x18a8[14:2] / 128 path=%d\n",
848 __func__, odm_get_bb_reg(dm, 0x18a8, 0x7ffc),
849 odm_get_bb_reg(dm, 0x18a8, 0x7ffc), big_a, RF_PATH_A);
850
851 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
852 "1000 * small_a(%d) = 434295 / big_a(%d) 1000*slope(%d) = 1000000/small_a path=%d\n",
853 small_a, big_a, slope, RF_PATH_A);
854
855 for (i = 0; i < TSSI_CODE_NUM; i++) {
856 rate = _halrf_tssi_rate_to_driver_rate_8822c(dm, i);
857 db_temp = (u32)phydm_get_tx_power_dbm(dm, RF_PATH_A, rate, bandwidth, channel);
858
859 db_temp = db_temp * slope;
860 db_temp = db_temp / 1000 + samll_b;
861
862 if (db_temp > 0xff)
863 db_temp = 0xff;
864 else if ((s32)db_temp < 0)
865 db_temp = 0x0;
866
867 tssi->tssi_codeword[i] = (u16)(db_temp);
868
869 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "phydm_get_tx_power_dbm = %d, rate=0x%x(%d) bandwidth=%d channel=%d rf_path=%d\n",
870 phydm_get_tx_power_dbm(dm, RF_PATH_A, rate, bandwidth, channel),
871 rate, rate, bandwidth, channel, RF_PATH_A);
872
873 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "tssi_codeword[%d] = 0x%x(%d)\n",
874 i, tssi->tssi_codeword[i], tssi->tssi_codeword[i]);
875 }
876
877 }
878
halrf_set_tssi_codeword_8822c(void * dm_void,u16 * tssi_value)879 void halrf_set_tssi_codeword_8822c(
880 void *dm_void, u16 *tssi_value)
881 {
882 struct dm_struct *dm = (struct dm_struct *)dm_void;
883 u32 i, j, k = 0, tssi_value_tmp;
884
885 /*power by rate table (tssi codeword)*/
886 for (i = 0x3a54; i <= 0x3aa4; i = i + 4) {
887 tssi_value_tmp = 0;
888
889 for (j = 0; j < 31; j = j + 8)
890 tssi_value_tmp = tssi_value_tmp | ((tssi_value[k++] & 0xff) << j);
891
892 odm_set_bb_reg(dm, i, MASKDWORD, tssi_value_tmp);
893
894 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
895 "===>%s write addr:0x%x value=0x%08x\n",
896 __func__, i, tssi_value_tmp);
897 }
898 }
899
halrf_tssi_dck_8822c(void * dm_void)900 void halrf_tssi_dck_8822c(
901 void *dm_void)
902 {
903 struct dm_struct *dm = (struct dm_struct *)dm_void;
904 struct _hal_rf_ *rf = &dm->rf_table;
905 u8 channel = *dm->channel, i, j, k;
906
907 u32 reg = 0, dck_check;
908 s32 reg_tmp = 0;
909 u32 bb_reg[8] = {R_0x1800, R_0x4100, R_0x820, R_0x1e2c, R_0x1d08,
910 R_0x1c3c, R_0x2dbc, R_0x1e70};
911 u32 bb_reg_backup[8] = {0};
912 u32 backup_num = 8;
913
914 u32 tssi_setting[2] = {R_0x1830, R_0x4130};
915 u32 dc_offset[2] = {R_0x189c, R_0x419c};
916 u32 path_setting[2] = {R_0x1800, R_0x4100};
917 u32 tssi_counter[2] = {R_0x18a4, R_0x41a4};
918 u32 tssi_enalbe[2] = {R_0x180c, R_0x410c};
919 u32 debug_port[2] = {0x930, 0xb30};
920
921 u32 addr_d[2] = {0x18a8, 0x1eec};
922 u32 addr_d_bitmask[2] = {0xff000000, 0x3fc00000};
923 u32 addr_cck_d[2] = {R_0x18e8, R_0x1ef0};
924 u32 addr_cck_d_bitmask[2] = {0x01fe0000, 0x0001fe00};
925
926 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] ======>%s channel=%d\n",
927 __func__, channel);
928
929 /*odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);*/
930 rf->is_tssi_in_progress = 1;
931
932 _backup_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
933
934 for (i = 0; i < MAX_PATH_NUM_8822C; i++) {
935 odm_set_bb_reg(dm, addr_cck_d[i], addr_cck_d_bitmask[i], 0x0);
936 odm_set_bb_reg(dm, addr_d[i], addr_d_bitmask[i], 0x0);
937 }
938
939 halrf_disable_tssi_8822c(dm);
940
941 for (i = 0; i < 2 ; i++){
942 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
943 "[TSSI] ============== Path - %d ==============\n", i);
944
945 if (channel >= 1 && channel <= 14) {
946 for (k = 0; k < 3; k++) {
947 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
948
949 odm_set_bb_reg(dm, R_0x1d58, 0x00000008, 0x1);
950 odm_set_bb_reg(dm, R_0x1d58, 0x00000ff0, 0xff);
951 odm_set_bb_reg(dm, R_0x1a00, 0x00000003, 0x2);
952
953 /*odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4);*/
954 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x700b8041);
955 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x701f0044);
956 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x702f0044);
957 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x703f0044);
958 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x704f0044);
959 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x705b8041);
960 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x706f0044);
961 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x707b8041);
962 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x708b8041);
963 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x709b8041);
964 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70ab8041);
965 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70bb8041);
966 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70cb8041);
967 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70db8041);
968 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70eb8041);
969 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70fb8041);
970
971 odm_set_bb_reg(dm, tssi_counter[i], 0xe0000000, 0x0);
972 ODM_delay_us(200);
973
974 odm_set_rf_reg(dm, i, RF_0x7f, 0x00002, 0x1);
975 odm_set_rf_reg(dm, i, RF_0x65, 0x03000, 0x3);
976 odm_set_rf_reg(dm, i, RF_0x67, 0x0000c, 0x3);
977 odm_set_rf_reg(dm, i, RF_0x67, 0x000c0, 0x0);
978 odm_set_rf_reg(dm, i, RF_0x6e, 0x001e0, 0x0);
979
980 odm_set_bb_reg(dm, tssi_enalbe[i], 0x08000000, 0x1);
981 odm_set_bb_reg(dm, tssi_enalbe[i], 0x40000000, 0x1);
982 odm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x1);
983 odm_set_bb_reg(dm, R_0x1ca4, 0x00000001, 0x1);
984 //ODM_delay_us(100);
985 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, i);
986 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x3f);
987 odm_set_rf_reg(dm, i, RF_0xde, 0x10000, 0x1);
988 odm_set_rf_reg(dm, i, RF_0x56, 0x000ff, 0x0);
989
990 btc_set_gnt_wl_bt_8822c(dm, true);
991
992 odm_set_bb_reg(dm, dc_offset[i], 0x0003ff00, 0xc00);
993 odm_set_bb_reg(dm, R_0x820, 0x00000003, i + 1);
994 odm_set_bb_reg(dm, R_0x1e2c, MASKDWORD, 0xe4e40000);
995 odm_set_bb_reg(dm, R_0x1e28, 0x0000000f, 0x3);
996 odm_set_bb_reg(dm, path_setting[i], 0x000fffff, 0x33312);
997 odm_set_bb_reg(dm, path_setting[i], 0x80000000, 0x1);
998
999 odm_set_bb_reg(dm, R_0x1e70, 0x00000004, 0x1);
1000 //ODM_delay_us(100);
1001 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x1);
1002 //ODM_delay_us(100);
1003
1004 /*odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x930);*/
1005 phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, debug_port[i]);
1006 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x0);
1007 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x1);
1008 /*reg = odm_get_bb_reg(dm, R_0x2dbc, 0x000003ff);*/
1009 reg = phydm_get_bb_dbg_port_val(dm) & 0x000003ff;
1010 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x2dbc[9:0]=0x%x\n", reg);
1011 phydm_release_bb_dbg_port(dm);
1012
1013 reg_tmp = reg;
1014 reg = 1024 - (((reg_tmp - 512) * 4) & 0x000003ff) + 0;
1015 odm_set_bb_reg(dm, dc_offset[i], 0x0003ff00, (reg & 0x03ff));
1016
1017 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x%x[17:8]=0x%x reg=0x%x\n",
1018 dc_offset[i], odm_get_bb_reg(dm, dc_offset[i], 0x0003ff00), reg);
1019
1020 for (j = 0; j < 3; j++) {
1021 /*odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x930);*/
1022 phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, debug_port[i]);
1023 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x0);
1024 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x1);
1025 /*dck_check = odm_get_bb_reg(dm, R_0x2dbc, 0x000003ff);*/
1026 dck_check = phydm_get_bb_dbg_port_val(dm) & 0x000003ff;
1027 phydm_release_bb_dbg_port(dm);
1028
1029 if (dck_check < 0x1ff) {
1030 if (reg >= 0x3fb)
1031 reg = 0x3ff;
1032 else
1033 reg = reg + 4;
1034 odm_set_bb_reg(dm, dc_offset[i], 0x0003ff00, reg);
1035 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x2dbc[23:12]=0x%x < 0x1ff Set 0x%x retry=%d\n",
1036 dck_check, reg, j);
1037 } else if (dck_check > 0x202) {
1038 if (reg <= 4)
1039 reg = 0;
1040 else
1041 reg = reg - 4;
1042 odm_set_bb_reg(dm, dc_offset[i], 0x0003ff00, reg);
1043 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x2dbc[23:12]=0x%x > 0x202 Set 0x%x retry=%d\n",
1044 dck_check, reg, j);
1045 } else {
1046 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x2dbc[23:12]=0x%x OK!!! retry=%d\n",
1047 dck_check, j);
1048 k = 3;
1049 break;
1050 }
1051 }
1052
1053 btc_set_gnt_wl_bt_8822c(dm, false);
1054 }
1055 #if 1
1056 odm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x2);
1057 odm_set_rf_reg(dm, i, RF_0xde, 0x10000, 0x0);
1058 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x0);
1059 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, i);
1060 odm_set_bb_reg(dm, R_0x1ca4, 0x00000001, 0x0);
1061 odm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x0);
1062
1063 odm_set_rf_reg(dm, i, RF_0x7f, 0x00002, 0x0);
1064 ODM_delay_us(100);
1065 odm_set_bb_reg(dm, tssi_enalbe[i], 0x08000000, 0x0);
1066 odm_set_bb_reg(dm, tssi_enalbe[i], 0x40000000, 0x0);
1067 ODM_delay_us(100);
1068 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x0);
1069 ODM_delay_us(100);
1070
1071 #else
1072 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, i);
1073 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x00);
1074 odm_set_bb_reg(dm, R_0x1ca4, 0x00000001, 0x0);
1075 odm_set_rf_reg(dm, i, RF_0x7f, 0x00002, 0x0);
1076 odm_set_bb_reg(dm, tssi_enalbe[i], 0x08000000, 0x0);
1077 odm_set_bb_reg(dm, tssi_enalbe[i], 0x40000000, 0x0);
1078 odm_set_bb_reg(dm, R_0x1e70, 0x00000004, 0x0);
1079 odm_set_rf_reg(dm, i, RF_0xde, 0x10000, 0x0);
1080 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x0);
1081 odm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x0);
1082 #endif
1083 odm_set_bb_reg(dm, R_0x1d58, 0x00000008, 0x0);
1084 odm_set_bb_reg(dm, R_0x1d58, 0x00000ff0, 0x0);
1085 odm_set_bb_reg(dm, R_0x1a00, 0x00000003, 0x0);
1086
1087 } else {
1088 for (k = 0; k < 3; k++) {
1089 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
1090 /*odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x2);*/
1091
1092 odm_set_bb_reg(dm, R_0x1d58, 0x00000008, 0x1);
1093 odm_set_bb_reg(dm, R_0x1d58, 0x00000ff0, 0xff);
1094 odm_set_bb_reg(dm, R_0x1a00, 0x00000003, 0x2);
1095
1096 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x700b8041);
1097 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x701f0042);
1098 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x702f0042);
1099 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x703f0042);
1100 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x704f0042);
1101 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x705b8041);
1102 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x706f0042);
1103 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x707b8041);
1104 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x708b8041);
1105 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x709b8041);
1106 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70ab8041);
1107 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70bb8041);
1108 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70cb8041);
1109 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70db8041);
1110 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70eb8041);
1111 odm_set_bb_reg(dm, tssi_setting[i], MASKDWORD, 0x70fb8041);
1112
1113
1114 odm_set_bb_reg(dm, dc_offset[i], 0x0003ff00, 0x0);
1115 odm_set_bb_reg(dm, R_0x820, 0x00000003, i + 1);
1116 odm_set_bb_reg(dm, R_0x1e2c, MASKDWORD, 0xe4e40000);
1117 odm_set_bb_reg(dm, R_0x1e28, 0x0000000f, 0x3);
1118 odm_set_bb_reg(dm, path_setting[i], 0x000fffff, 0x33312);
1119 odm_set_bb_reg(dm, path_setting[i], 0x80000000, 0x1);
1120 odm_set_bb_reg(dm, tssi_counter[i], 0xe0000000, 0x0);
1121 ODM_delay_us(200);
1122 odm_set_rf_reg(dm, i, RF_0x7f, 0x100, 0x1);
1123 odm_set_rf_reg(dm, i, RF_0x65, 0x03000, 0x3);
1124 odm_set_rf_reg(dm, i, RF_0x67, 0x00003, 0x3);
1125 odm_set_rf_reg(dm, i, RF_0x67, 0x00030, 0x2);
1126 odm_set_rf_reg(dm, i, RF_0x6f, 0x001e0, 0x0);
1127
1128 odm_set_bb_reg(dm, tssi_enalbe[i], 0x08000000, 0x1);
1129 odm_set_bb_reg(dm, tssi_enalbe[i], 0x40000000, 0x1);
1130 odm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x1);
1131 odm_set_bb_reg(dm, R_0x1ca4, 0x00000001, 0x1);
1132 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, i);
1133 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x3f);
1134 odm_set_rf_reg(dm, i, RF_0xde, 0x10000, 0x1);
1135 odm_set_rf_reg(dm, i, RF_0x56, 0x000ff, 0x0);
1136
1137 /*Set OFDM Packet Type*/
1138 odm_set_bb_reg(dm, R_0x900, 0x00000004, 0x1);
1139 odm_set_bb_reg(dm, R_0x900, 0x30000000, 0x2);
1140 odm_set_bb_reg(dm, R_0x908, 0x00ffffff, 0x21b6b);
1141 odm_set_bb_reg(dm, R_0x90c, 0x00ffffff, 0x800006);
1142 odm_set_bb_reg(dm, R_0x910, 0x00ffffff, 0x13600);
1143 odm_set_bb_reg(dm, R_0x914, 0x1fffffff, 0x6000fa);
1144 odm_set_bb_reg(dm, R_0x938, 0x0000ffff, 0x4b0f);
1145 odm_set_bb_reg(dm, R_0x940, MASKDWORD, 0x4ee33e41);
1146 odm_set_bb_reg(dm, R_0xa58, 0x003f8000, 0x2c);
1147
1148 odm_set_bb_reg(dm, R_0x1e70, 0x00000004, 0x1);
1149 //ODM_delay_us(100);
1150 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x1);
1151 //ODM_delay_us(100);
1152
1153 /*odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x930);*/
1154 phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, debug_port[i]);
1155 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x0);
1156 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x1);
1157 /*reg = odm_get_bb_reg(dm, R_0x2dbc, 0x000003ff);*/
1158 reg = phydm_get_bb_dbg_port_val(dm) & 0x000003ff;
1159 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x2dbc[9:0]=0x%x\n", reg);
1160 phydm_release_bb_dbg_port(dm);
1161
1162 reg_tmp = reg;
1163 reg = 1024 - (((reg_tmp - 512) * 4) & 0x000003ff) + 5;
1164 odm_set_bb_reg(dm, dc_offset[i], 0x0003ff00, (reg & 0x03ff));
1165
1166 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x%x[17:8]=0x%x reg=0x%x\n",
1167 dc_offset[i], odm_get_bb_reg(dm, dc_offset[i], 0x0003ff00), reg);
1168
1169 for (j = 0; j < 3; j++) {
1170 /*odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x930);*/
1171 phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, debug_port[i]);
1172 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x0);
1173 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x1);
1174 /*dck_check = odm_get_bb_reg(dm, R_0x2dbc, 0x000003ff);*/
1175 dck_check = phydm_get_bb_dbg_port_val(dm) & 0x000003ff;
1176 phydm_release_bb_dbg_port(dm);
1177
1178 if (dck_check < 0x1ff) {
1179 if (reg >= 0x3fb)
1180 reg = 0x3ff;
1181 else
1182 reg = reg + 4;
1183 odm_set_bb_reg(dm, dc_offset[i], 0x0003ff00, reg);
1184 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x2dbc[23:12]=0x%x < 0x1ff Set 0x%x retry=%d\n",
1185 dck_check, reg, j);
1186 } else if (dck_check > 0x202) {
1187 if (reg <= 4)
1188 reg = 0;
1189 else
1190 reg = reg - 4;
1191 odm_set_bb_reg(dm, dc_offset[i], 0x0003ff00, reg);
1192 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x2dbc[23:12]=0x%x > 0x202 Set 0x%x retry=%d\n",
1193 dck_check, reg, j);
1194 } else {
1195 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] 0x2dbc[23:12]=0x%x OK!!! retry=%d\n",
1196 dck_check, j);
1197 k = 3;
1198 break;
1199 }
1200 }
1201 }
1202
1203 #if 1
1204 odm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x2);
1205 odm_set_rf_reg(dm, i, RF_0xde, 0x10000, 0x0);
1206 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x0);
1207 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, i);
1208 odm_set_bb_reg(dm, R_0x1ca4, 0x00000001, 0x0);
1209 odm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x0);
1210
1211 odm_set_rf_reg(dm, i, RF_0x7f, 0x100, 0x0);
1212 ODM_delay_us(100);
1213 odm_set_bb_reg(dm, tssi_enalbe[i], 0x08000000, 0x0);
1214 odm_set_bb_reg(dm, tssi_enalbe[i], 0x40000000, 0x0);
1215 ODM_delay_us(100);
1216 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x0);
1217 ODM_delay_us(100);
1218 #else
1219 odm_set_bb_reg(dm, R_0x1b00, 0x00000006, i);
1220 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x00);
1221 odm_set_bb_reg(dm, R_0x1ca4, 0x00000001, 0x0);
1222 odm_set_rf_reg(dm, i, RF_0x7f, 0x100, 0x0);
1223 odm_set_bb_reg(dm, tssi_enalbe[i], 0x08000000, 0x0);
1224 odm_set_bb_reg(dm, tssi_enalbe[i], 0x40000000, 0x0);
1225 odm_set_bb_reg(dm, R_0x1e70, 0x00000004, 0x0);
1226 odm_set_rf_reg(dm, i, RF_0xde, 0x10000, 0x0);
1227 odm_set_bb_reg(dm, tssi_counter[i], 0x10000000, 0x0);
1228 odm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x0);
1229 #endif
1230 odm_set_bb_reg(dm, R_0x1d58, 0x00000008, 0x0);
1231 odm_set_bb_reg(dm, R_0x1d58, 0x00000ff0, 0x0);
1232 odm_set_bb_reg(dm, R_0x1a00, 0x00000003, 0x0);
1233
1234
1235 }
1236 }
1237
1238 _reload_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
1239 rf->is_tssi_in_progress = 0;
1240 /*odm_release_spin_lock(dm, RT_IQK_SPINLOCK);*/
1241
1242 }
1243
halrf_tssi_get_efuse_8822c(void * dm_void)1244 void halrf_tssi_get_efuse_8822c(
1245 void *dm_void)
1246 {
1247 struct dm_struct *dm = (struct dm_struct *)dm_void;
1248 struct _hal_rf_ *rf = &dm->rf_table;
1249 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
1250
1251 u8 pg_tssi = 0xff, i, j;
1252 u32 pg_tssi_tmp = 0xff;
1253
1254 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1255 "===>%s\n", __func__);
1256
1257 /*path s0*/
1258 j = 0;
1259 for (i = 0x10; i <= 0x1a; i++) {
1260 odm_efuse_logical_map_read(dm, 1, i, &pg_tssi_tmp);
1261 tssi->tssi_efuse[0][j] = (s8)pg_tssi_tmp;
1262 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1263 "tssi->tssi_efuse[%d][%d]=%d\n", 0, j, tssi->tssi_efuse[0][j]);
1264 j++;
1265 }
1266
1267 for (i = 0x22; i <= 0x2f; i++) {
1268 odm_efuse_logical_map_read(dm, 1, i, &pg_tssi_tmp);
1269 tssi->tssi_efuse[0][j] = (s8)pg_tssi_tmp;
1270 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1271 "tssi->tssi_efuse[%d][%d]=%d\n", 0, j, tssi->tssi_efuse[0][j]);
1272 j++;
1273 }
1274
1275 /*path s1*/
1276 j = 0;
1277 for (i = 0x3a; i <= 0x44; i++) {
1278 odm_efuse_logical_map_read(dm, 1, i, &pg_tssi_tmp);
1279 tssi->tssi_efuse[1][j] = (s8)pg_tssi_tmp;
1280 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1281 "tssi->tssi_efuse[%d][%d]=%d\n", 1, j, tssi->tssi_efuse[1][j]);
1282 j++;
1283 }
1284
1285 for (i = 0x4c; i <= 0x59; i++) {
1286 odm_efuse_logical_map_read(dm, 1, i, &pg_tssi_tmp);
1287 tssi->tssi_efuse[1][j] = (s8)pg_tssi_tmp;
1288 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1289 "tssi->tssi_efuse[%d][%d]=%d\n", 1, j, tssi->tssi_efuse[1][j]);
1290 j++;
1291 }
1292 }
1293
halrf_tssi_get_de_8822c(void * dm_void,u8 path)1294 u32 halrf_tssi_get_de_8822c(
1295 void *dm_void, u8 path)
1296 {
1297 struct dm_struct *dm = (struct dm_struct *)dm_void;
1298 struct _hal_rf_ *rf = &dm->rf_table;
1299
1300 u32 i;
1301
1302 u32 tssi_offest_de = 0;
1303 /*halrf_do_tssi_8822c(dm);*/
1304 rf->is_tssi_in_progress = 1;
1305
1306 _halrf_tssi_8822c(dm);
1307
1308 if (path == RF_PATH_A) {
1309 odm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);
1310 odm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x1);
1311 odm_set_bb_reg(dm, R_0x1c64, 0x00007f00, 0x00);
1312 odm_set_bb_reg(dm, R_0x1c64, 0x003f8000, 0x00);
1313 odm_set_bb_reg(dm, R_0x1c64, 0x1fc00000, 0x00);
1314 odm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x2);
1315 odm_set_bb_reg(dm, R_0x1c24, 0x07f80000, 0x20);
1316 odm_set_bb_reg(dm, R_0x1c64, 0x00007f00, 0x00);
1317 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
1318 odm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);
1319 odm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x0);
1320 odm_set_bb_reg(dm, R_0x1860, 0x00000800, 0x0);
1321 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
1322 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1323 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);
1324
1325 for (i = 0; odm_get_bb_reg(dm, R_0x28a4, 0x10000) == 0; i++) {
1326 ODM_delay_ms(1);
1327 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1328 "TSSI finish bit != 1 retry=%d s0 0x%x\n", i,
1329 odm_get_bb_reg(dm, R_0x28a4, MASKDWORD));
1330 if (i >= 36) {
1331 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1332 "TSSI finish bit i > 36ms, return s0\n");
1333 rf->is_tssi_in_progress = 0;
1334 break;
1335 }
1336 }
1337
1338 tssi_offest_de = odm_get_bb_reg(dm, R_0x28a4, 0x1ff);
1339 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1340 "======>%s path=%d tssi_offest_de_org=0x%x\n",
1341 __func__, path, tssi_offest_de);
1342 } else if (path == RF_PATH_B) {
1343 odm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);
1344 odm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x1);
1345 odm_set_bb_reg(dm, R_0x1c64, 0x00007f00, 0x00);
1346 odm_set_bb_reg(dm, R_0x1c64, 0x003f8000, 0x00);
1347 odm_set_bb_reg(dm, R_0x1c64, 0x1fc00000, 0x00);
1348 odm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);
1349 odm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x2);
1350 odm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);
1351 odm_set_bb_reg(dm, R_0x1c64, 0x00007f00, 0x00);
1352 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
1353 odm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x0);
1354 odm_set_bb_reg(dm, R_0x4160, 0x00000800, 0x0);
1355 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
1356 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1357 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);
1358
1359 for (i = 0; odm_get_bb_reg(dm, R_0x45a4, 0x10000) == 0; i++) {
1360 ODM_delay_ms(1);
1361 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1362 "TSSI finish bit != 1 retry=%d s1 0x%x\n", i,
1363 odm_get_bb_reg(dm, R_0x45a4, MASKDWORD));
1364 if (i >= 36) {
1365 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1366 "TSSI finish bit i > 36ms, return s1\n");
1367 rf->is_tssi_in_progress = 0;
1368 break;
1369 }
1370 }
1371
1372 tssi_offest_de = odm_get_bb_reg(dm, R_0x45a4, 0x1ff);
1373 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1374 "======>%s path=%d tssi_offest_de_org=0x%x\n",
1375 __func__, path, tssi_offest_de);
1376 } else {
1377 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1378 "======>%s path=%d is not exist!!!\n", __func__, path);
1379 }
1380
1381 if (tssi_offest_de & BIT(8))
1382 tssi_offest_de = (tssi_offest_de & 0xff) | BIT(7);
1383
1384 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1385 "======>%s path=%d tssi_offest_de_change=0x%x\n", __func__, path, tssi_offest_de);
1386 rf->is_tssi_in_progress = 0;
1387
1388 return tssi_offest_de;
1389 }
1390
1391
halrf_tssi_get_kfree_efuse_8822c(void * dm_void)1392 void halrf_tssi_get_kfree_efuse_8822c(
1393 void *dm_void)
1394 {
1395 #if 0
1396 struct dm_struct *dm = (struct dm_struct *)dm_void;
1397 struct _hal_rf_ *rf = &dm->rf_table;
1398 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
1399
1400 u8 pg_tssi = 0xff, i, j;
1401
1402 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1403 "===>%s\n", __func__);
1404
1405 /*path s0*/
1406 j = 0;
1407 odm_efuse_one_byte_read(dm, 0x1c0, &pg_tssi, false);
1408 if (((pg_tssi & BIT(7)) >> 7) == 0) {
1409 if ((pg_tssi & BIT(0)) == 0)
1410 tssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));
1411 else
1412 tssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);
1413 }
1414 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1415 "tssi->tssi_kfree_efuse[%d][%d]=%d\n", 0, j, tssi->tssi_kfree_efuse[0][j]);
1416 j++;
1417
1418 odm_efuse_one_byte_read(dm, 0x1bc, &pg_tssi, false);
1419 if (((pg_tssi & BIT(7)) >> 7) == 0) {
1420 if ((pg_tssi & BIT(0)) == 0)
1421 tssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));
1422 else
1423 tssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);
1424 }
1425
1426 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1427 "tssi->tssi_kfree_efuse[%d][%d]=%d\n", 0, j, tssi->tssi_kfree_efuse[0][j]);
1428 j++;
1429
1430 odm_efuse_one_byte_read(dm, 0x1b8, &pg_tssi, false);
1431 if (((pg_tssi & BIT(7)) >> 7) == 0) {
1432 if ((pg_tssi & BIT(0)) == 0)
1433 tssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));
1434 else
1435 tssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);
1436 }
1437
1438 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1439 "tssi->tssi_kfree_efuse[%d][%d]=%d\n", 0, j, tssi->tssi_kfree_efuse[0][j]);
1440 j++;
1441
1442 odm_efuse_one_byte_read(dm, 0x3b4, &pg_tssi, false);
1443 if (((pg_tssi & BIT(7)) >> 7) == 0) {
1444 if ((pg_tssi & BIT(0)) == 0)
1445 tssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));
1446 else
1447 tssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);
1448 }
1449
1450 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1451 "tssi->tssi_kfree_efuse[%d][%d]=%d\n", 0, j, tssi->tssi_kfree_efuse[0][j]);
1452 j++;
1453
1454 /*path s0*/
1455 j = 0;
1456 odm_efuse_one_byte_read(dm, 0x1bf, &pg_tssi, false);
1457 if (((pg_tssi & BIT(7)) >> 7) == 0) {
1458 if ((pg_tssi & BIT(0)) == 0)
1459 tssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));
1460 else
1461 tssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);
1462 }
1463
1464 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1465 "tssi->tssi_kfree_efuse[%d][%d]=%d\n", 1, j, tssi->tssi_kfree_efuse[1][j]);
1466 j++;
1467
1468 odm_efuse_one_byte_read(dm, 0x1bb, &pg_tssi, false);
1469 if (((pg_tssi & BIT(7)) >> 7) == 0) {
1470 if ((pg_tssi & BIT(0)) == 0)
1471 tssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));
1472 else
1473 tssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);
1474 }
1475
1476 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1477 "tssi->tssi_kfree_efuse[%d][%d]=%d\n", 1, j, tssi->tssi_kfree_efuse[1][j]);
1478 j++;
1479
1480 odm_efuse_one_byte_read(dm, 0x3b7, &pg_tssi, false);
1481 if (((pg_tssi & BIT(7)) >> 7) == 0) {
1482 if ((pg_tssi & BIT(0)) == 0)
1483 tssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));
1484 else
1485 tssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);
1486 }
1487
1488 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1489 "tssi->tssi_kfree_efuse[%d][%d]=%d\n", 1, j, tssi->tssi_kfree_efuse[1][j]);
1490 j++;
1491
1492 odm_efuse_one_byte_read(dm, 0x3b3, &pg_tssi, false);
1493 if (((pg_tssi & BIT(7)) >> 7) == 0) {
1494 if ((pg_tssi & BIT(0)) == 0)
1495 tssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));
1496 else
1497 tssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);
1498 }
1499
1500 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1501 "tssi->tssi_kfree_efuse[%d][%d]=%d\n", 1, j, tssi->tssi_kfree_efuse[1][j]);
1502 j++;
1503
1504 #endif
1505
1506 }
1507
halrf_tssi_set_de_8822c(void * dm_void)1508 void halrf_tssi_set_de_8822c(
1509 void *dm_void)
1510 {
1511 struct dm_struct *dm = (struct dm_struct *)dm_void;
1512 struct _hal_rf_ *rf = &dm->rf_table;
1513 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
1514
1515 u8 i;
1516 u32 addr_d[2] = {0x18a8, 0x1eec};
1517 u32 addr_d_bitmask[2] = {0xff000000, 0x3fc00000};
1518 u32 addr_cck_d[2] = {R_0x18e8, R_0x1ef0};
1519 u32 addr_cck_d_bitmask[2] = {0x01fe0000, 0x0001fe00};
1520 s8 tssi_offest_de;
1521 u32 offset_index = 0;
1522 u8 channel = *dm->channel;
1523 s32 tmp;
1524
1525 if (dm->rf_calibrate_info.txpowertrack_control == 4) {
1526 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1527 "==>%s txpowertrack_control=%d return!!!\n", __func__,
1528 dm->rf_calibrate_info.txpowertrack_control);
1529 #if 0
1530 for (i = 0; i < MAX_PATH_NUM_8822C; i++) {
1531 odm_set_bb_reg(dm, addr_cck_d[i], addr_cck_d_bitmask[i], 0x0);
1532 odm_set_bb_reg(dm, addr_d[i], addr_d_bitmask[i], 0x0);
1533 }
1534 #else
1535 if (channel >= 1 && channel <= 2)
1536 offset_index = 0;
1537 else if (channel >= 3 && channel <= 5)
1538 offset_index = 1;
1539 else if (channel >= 6 && channel <= 8)
1540 offset_index = 2;
1541 else if (channel >= 9 && channel <= 11)
1542 offset_index = 3;
1543 else if (channel >= 12 && channel <= 13)
1544 offset_index = 4;
1545 else if (channel == 14)
1546 offset_index = 5;
1547
1548 for (i = 0; i < MAX_PATH_NUM_8822C; i++) {
1549 tmp = phydm_get_tssi_trim_de(dm, i);
1550
1551 if (tmp > 127)
1552 tmp = 127;
1553 else if (tmp < -128)
1554 tmp = -128;
1555
1556 odm_set_bb_reg(dm, addr_cck_d[i], addr_cck_d_bitmask[i],
1557 (tmp & 0xff));
1558
1559 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1560 "==>%s CCK 0x%x[%x] tssi_trim(%d)\n",
1561 __func__,
1562 addr_cck_d[i], addr_cck_d_bitmask[i],
1563 (tmp & 0xff)
1564 );
1565
1566 tmp = phydm_get_tssi_trim_de(dm, i);
1567 odm_set_bb_reg(dm, addr_d[i], addr_d_bitmask[i], (tmp & 0xff));
1568
1569 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1570 "==>%s 0x%x[%x] tssi_offset(%d)\n",
1571 __func__,
1572 addr_d[i], addr_d_bitmask[i],
1573 (tmp & 0xff)
1574 );
1575 }
1576
1577
1578
1579 #endif
1580 return;
1581 }
1582
1583 if (channel >= 1 && channel <= 2)
1584 offset_index = 0;
1585 else if (channel >= 3 && channel <= 5)
1586 offset_index = 1;
1587 else if (channel >= 6 && channel <= 8)
1588 offset_index = 2;
1589 else if (channel >= 9 && channel <= 11)
1590 offset_index = 3;
1591 else if (channel >= 12 && channel <= 13)
1592 offset_index = 4;
1593 else if (channel == 14)
1594 offset_index = 5;
1595
1596 for (i = 0; i < MAX_PATH_NUM_8822C; i++) {
1597 tmp = tssi->tssi_efuse[i][offset_index] + phydm_get_tssi_trim_de(dm, i);
1598
1599 if (tmp > 127)
1600 tmp = 127;
1601 else if (tmp < -128)
1602 tmp = -128;
1603
1604 odm_set_bb_reg(dm, addr_cck_d[i], addr_cck_d_bitmask[i],
1605 (tmp & 0xff));
1606
1607 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1608 "==>%s CCK 0x%x[%x] tssi_offset(%d)=tssi_efuse(%d)+tssi_trim(%d)\n",
1609 __func__,
1610 addr_cck_d[i], addr_cck_d_bitmask[i],
1611 (tmp & 0xff),
1612 tssi->tssi_efuse[i][offset_index],
1613 phydm_get_tssi_trim_de(dm, i));
1614
1615 tssi_offest_de = (s8)_halrf_get_efuse_tssi_offset_8822c(dm, i);
1616 tmp = tssi_offest_de + phydm_get_tssi_trim_de(dm, i);
1617
1618 if (tmp > 127)
1619 tmp = 127;
1620 else if (tmp < -128)
1621 tmp = -128;
1622
1623 odm_set_bb_reg(dm, addr_d[i], addr_d_bitmask[i], (tmp & 0xff));
1624
1625 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1626 "==>%s 0x%x[%x] tssi_offset(%d)=tssi_efuse(%d)+tssi_trim(%d)\n",
1627 __func__,
1628 addr_d[i], addr_d_bitmask[i],
1629 (tmp & 0xff),
1630 tssi_offest_de,
1631 phydm_get_tssi_trim_de(dm, i));
1632 }
1633 }
1634
halrf_tssi_set_de_for_tx_verify_8822c(void * dm_void,u32 tssi_de,u8 path)1635 void halrf_tssi_set_de_for_tx_verify_8822c(
1636 void *dm_void, u32 tssi_de, u8 path)
1637 {
1638 struct dm_struct *dm = (struct dm_struct *)dm_void;
1639
1640 u32 addr_d[2] = {0x18a8, 0x1eec};
1641 u32 addr_d_bitmask[2] = {0xff000000, 0x3fc00000};
1642 u32 addr_cck_d[2] = {R_0x18e8, R_0x1ef0};
1643 u32 addr_cck_d_bitmask[2] = {0x01fe0000, 0x0001fe00};
1644 u32 tssi_offest_de, offset_index = 0;
1645 s32 tmp, tssi_de_tmp;
1646
1647 #if 0
1648 odm_set_bb_reg(dm, addr_cck_d[path], addr_cck_d_bitmask[path],
1649 (tssi_de & 0xff));
1650 odm_set_bb_reg(dm, addr_d[path], addr_d_bitmask[path], (tssi_de & 0xff));
1651
1652 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1653 "==>%s CCK 0x%x[%x] tssi_efuse_offset=%d path=%d\n", __func__,
1654 addr_cck_d[path], addr_cck_d_bitmask[path], (tssi_de & 0xff), path);
1655
1656 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1657 "==>%s 0x%x[%x] tssi_efuse_offset=%d path=%d\n", __func__,
1658 addr_d[path], addr_d_bitmask[path], (tssi_de & 0xff), path);
1659 #endif
1660 if (tssi_de & BIT(7))
1661 tssi_de_tmp = tssi_de | 0xffffff00;
1662 else
1663 tssi_de_tmp = tssi_de;
1664
1665 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1666 "==>%s tssi_de(%d) tssi_de_tmp(%d)\n",
1667 __func__,
1668 tssi_de, tssi_de_tmp);
1669
1670 tmp = tssi_de_tmp + phydm_get_tssi_trim_de(dm, path);
1671
1672 if (tmp > 127)
1673 tmp = 127;
1674 else if (tmp < -128)
1675 tmp = -128;
1676
1677 odm_set_bb_reg(dm, addr_cck_d[path], addr_cck_d_bitmask[path],
1678 (tmp & 0xff));
1679
1680 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1681 "==>%s CCK 0x%x[%x] tssi_offset(%d)=tssi_de_tmp(%d)+tssi_trim(%d)\n",
1682 __func__,
1683 addr_cck_d[path], addr_cck_d_bitmask[path],
1684 (tmp & 0xff),
1685 tssi_de_tmp,
1686 phydm_get_tssi_trim_de(dm, path));
1687
1688 tmp = tssi_de_tmp + phydm_get_tssi_trim_de(dm, path);
1689
1690 if (tmp > 127)
1691 tmp = 127;
1692 else if (tmp < -128)
1693 tmp = -128;
1694
1695 odm_set_bb_reg(dm, addr_d[path], addr_d_bitmask[path], (tmp & 0xff));
1696
1697 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1698 "==>%s 0x%x[%x] tssi_offset(%d)=tssi_de_tmp(%d)+tssi_trim(%d)\n",
1699 __func__,
1700 addr_d[path], addr_d_bitmask[path],
1701 (tmp & 0xff),
1702 tssi_de_tmp,
1703 phydm_get_tssi_trim_de(dm, path));
1704 }
1705
halrf_enable_tssi_8822c(void * dm_void)1706 void halrf_enable_tssi_8822c(
1707 void *dm_void)
1708 {
1709 struct dm_struct *dm = (struct dm_struct *)dm_void;
1710 u8 channel = *dm->channel;
1711
1712 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>%s channel=%d\n", __func__, channel);
1713
1714 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
1715
1716 /*path s0*/
1717 if (channel >= 1 && channel <= 14)
1718 odm_set_bb_reg(dm, R_0x18a4, 0x0003e000, 0xb);
1719 else
1720 odm_set_bb_reg(dm, R_0x18a4, 0x0003e000, 0xd);
1721
1722 odm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);
1723 odm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x1);
1724 odm_set_bb_reg(dm, R_0x1c64, 0x00007f00, 0x00);
1725 odm_set_bb_reg(dm, R_0x1c64, 0x003f8000, 0x00);
1726 odm_set_bb_reg(dm, R_0x1c64, 0x1fc00000, 0x00);
1727 odm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x2);
1728 odm_set_bb_reg(dm, R_0x1c24, 0x07f80000, 0x20);
1729 odm_set_bb_reg(dm, R_0x1c64, 0x00007f00, 0x00);
1730 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
1731 odm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);
1732 odm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x0);
1733 odm_set_bb_reg(dm, R_0x1860, 0x00000800, 0x0);
1734 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
1735 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1736 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
1737 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);
1738
1739 /*path s1*/
1740 if (channel >= 1 && channel <= 14)
1741 odm_set_bb_reg(dm, R_0x41a4, 0x0003e000, 0xb);
1742 else
1743 odm_set_bb_reg(dm, R_0x41a4, 0x0003e000, 0xd);
1744
1745 odm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);
1746 odm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x1);
1747 odm_set_bb_reg(dm, R_0x1c64, 0x00007f00, 0x00);
1748 odm_set_bb_reg(dm, R_0x1c64, 0x003f8000, 0x00);
1749 odm_set_bb_reg(dm, R_0x1c64, 0x1fc00000, 0x00);
1750 odm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);
1751 odm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x2);
1752 odm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);
1753 odm_set_bb_reg(dm, R_0x1c64, 0x00007f00, 0x00);
1754 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
1755 odm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x0);
1756 odm_set_bb_reg(dm, R_0x4160, 0x00000800, 0x0);
1757 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
1758 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1759 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
1760 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);
1761 }
1762
halrf_disable_tssi_8822c(void * dm_void)1763 void halrf_disable_tssi_8822c(
1764 void *dm_void)
1765 {
1766 struct dm_struct *dm = (struct dm_struct *)dm_void;
1767
1768 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>%s\n", __func__);
1769
1770 /*path s0*/
1771 odm_set_bb_reg(dm, R_0x18a4, 0x0003e000, 0x0);
1772 odm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x0);
1773 odm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x0);
1774 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
1775 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1776
1777 odm_set_bb_reg(dm, R_0x18a0, 0x7f, 0x0);
1778
1779 /*path s1*/
1780 odm_set_bb_reg(dm, R_0x41a4, 0x0003e000, 0x0);
1781 odm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x0);
1782 odm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x0);
1783 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
1784 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1785
1786 odm_set_bb_reg(dm, R_0x41a0, 0x7f, 0x0);
1787
1788 /*ADDA Serring*/
1789 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffa1005e);
1790 }
1791
halrf_do_tssi_8822c(void * dm_void)1792 void halrf_do_tssi_8822c(
1793 void *dm_void)
1794 {
1795 struct dm_struct *dm = (struct dm_struct *)dm_void;
1796 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1797 struct _hal_rf_ *rf = &(dm->rf_table);
1798 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
1799 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1800
1801 u32 bb_reg[7] = {R_0x820, R_0x1e2c, R_0x1d08, R_0x1c3c, R_0x1e28,
1802 R_0x18a0, R_0x41a0};
1803 u32 bb_reg_backup[7] = {0};
1804 u32 backup_num = 7;
1805
1806 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] ======>%s\n", __func__);
1807
1808 /*odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);*/
1809 rf->is_tssi_in_progress = 1;
1810
1811 _backup_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
1812
1813 #if 0
1814 if ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) && (dm->priv->pmib->dot11RFEntry.tssi_enable) == 1) {
1815 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] ======>%s\n", __func__);
1816 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1817 "[TSSI] rf_supportability HAL_RF_TX_PWR_TRACK on\n");
1818 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1819 "[TSSI] dm->priv->pmib->dot11RFEntry.tssi_enable=%d\n",
1820 dm->priv->pmib->dot11RFEntry.tssi_enable);
1821 } else {
1822 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[TSSI] ======>%s, return!\n", __func__);
1823 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1824 "[TSSI] rf_supportability HAL_RF_TX_PWR_TRACK off, return!!\n");
1825
1826 halrf_disable_tssi_8812f(dm);
1827 return;
1828 }
1829 #endif
1830
1831
1832 halrf_tssi_set_de_8822c(dm);
1833 halrf_disable_tssi_8822c(dm);
1834 _halrf_tssi_init_8822c(dm);
1835 /*halrf_tssi_dck_8822c(dm);*/
1836 _halrf_tssi_8822c(dm);
1837
1838 if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
1839 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1840 "[TSSI] rf_supportability HAL_RF_TX_PWR_TRACK=%d, return!!!\n",
1841 (rf->rf_supportability & HAL_RF_TX_PWR_TRACK));
1842 _reload_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
1843 rf->is_tssi_in_progress = 0;
1844 /*odm_release_spin_lock(dm, RT_IQK_SPINLOCK);*/
1845 return;
1846 }
1847
1848 if (*dm->mp_mode == 1) {
1849 if (cali_info->txpowertrack_control == 3) {
1850 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1851 "[TSSI] cali_info->txpowertrack_control=%d, TSSI Mode\n",
1852 cali_info->txpowertrack_control);
1853 halrf_enable_tssi_8822c(dm);
1854 _reload_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
1855 rf->is_tssi_in_progress = 0;
1856 /*odm_release_spin_lock(dm, RT_IQK_SPINLOCK);*/
1857 return;
1858 }
1859 } else {
1860 if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {
1861 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1862 "[TSSI] cali_info->txpowertrack_control=%d, TSSI Mode\n",
1863 cali_info->txpowertrack_control);
1864 /*halrf_disable_tssi_8822c(dm);*/
1865 halrf_enable_tssi_8822c(dm);
1866 _reload_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
1867 rf->is_tssi_in_progress = 0;
1868 /*odm_release_spin_lock(dm, RT_IQK_SPINLOCK);*/
1869 return;
1870 }
1871 }
1872
1873 _reload_bb_registers_8822c(dm, bb_reg, bb_reg_backup, backup_num);
1874 rf->is_tssi_in_progress = 0;
1875 /*odm_release_spin_lock(dm, RT_IQK_SPINLOCK);*/
1876 }
1877
halrf_do_thermal_8822c(void * dm_void)1878 void halrf_do_thermal_8822c(
1879 void *dm_void)
1880 {
1881 #if 0
1882 struct dm_struct *dm = (struct dm_struct *)dm_void;
1883 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1884 struct _hal_rf_ *rf = &(dm->rf_table);
1885 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
1886
1887 u8 channel = *dm->channel;
1888 u8 rate = phydm_get_tx_rate(dm);
1889
1890 if (tssi->index[RF_PATH_A][channel - 1] != 0 || tssi->index[RF_PATH_B][channel - 1] != 0) {
1891 odm_set_bb_reg(dm, R_0x18e8, 0x0001fc00,
1892 (tssi->index[RF_PATH_A][channel - 1] & 0x7f));
1893 odm_set_bb_reg(dm, R_0x41e8, 0x0001fc00,
1894 (tssi->index[RF_PATH_B][channel - 1] & 0x7f));
1895
1896 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1897 "===>%s Set coex power index PathA:%d PathB:%d\n",
1898 __func__, tssi->index[RF_PATH_A][channel - 1],
1899 tssi->index[RF_PATH_B][channel - 1]);
1900 }
1901
1902 if ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) == 1) {
1903 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1904 "===>%s\n", __func__);
1905 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1906 "rf_supportability HAL_RF_TX_PWR_TRACK on\n");
1907 } else {
1908 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1909 "===>%s, return!\n", __func__);
1910 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1911 "rf_supportability HAL_RF_TX_PWR_TRACK off, return!!\n");
1912
1913 halrf_disable_tssi_8822c(dm);
1914 return;
1915 }
1916
1917 if (tssi->thermal[0] == 0xff || tssi->thermal[1] == 0xff) {
1918 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1919 "===>%s thermal[0]=0x%x thermal[1]=0x%x return!!!\n",
1920 __func__, tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);
1921 return;
1922 }
1923
1924 halrf_disable_tssi_8822c(dm);
1925 _halrf_thermal_init_8822c(dm);
1926
1927 /*halrf_tssi_dck_8822c(dm);*/
1928
1929 if (rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M) {
1930 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
1931 "===>%s, in CCK Rate return!!!\n", __func__);
1932 return;
1933 }
1934
1935 /*path s0*/
1936 if (channel >= 1 && channel <= 14) {
1937 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1938 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
1939 odm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);
1940 odm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x3);
1941 odm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x1);
1942 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
1943 odm_set_bb_reg(dm, R_0x18e8, 0x00000001, 0x0);
1944 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
1945 odm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);
1946 odm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x0000);
1947 odm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);
1948 odm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);
1949 odm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x000);
1950 odm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x1);
1951 odm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);
1952 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
1953 odm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);
1954 odm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);
1955 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
1956 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
1957 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1958 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
1959 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
1960 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);
1961 } else {
1962 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1963 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
1964 odm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);
1965 odm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x3);
1966 odm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x1);
1967 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
1968 odm_set_bb_reg(dm, R_0x18e8, 0x00000001, 0x0);
1969 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
1970 odm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);
1971 odm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x0000);
1972 odm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);
1973 odm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);
1974 odm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x000);
1975 odm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x1);
1976 odm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);
1977 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
1978 odm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);
1979 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
1980 odm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);
1981 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
1982 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1983 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
1984 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
1985 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);
1986 }
1987
1988 #if 1
1989 /*path s1*/
1990 if (channel >= 1 && channel <= 14) {
1991 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
1992 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
1993 odm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);
1994 odm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x3);
1995 odm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x1);
1996 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
1997 odm_set_bb_reg(dm, R_0x41e8, 0x00000001, 0x0);
1998 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
1999 odm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);
2000 odm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x0000);
2001 odm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);
2002 odm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);
2003 odm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x000);
2004 odm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x1);
2005 odm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);
2006 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
2007 odm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);
2008 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
2009 odm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);
2010 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
2011 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
2012 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
2013 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
2014 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);
2015 } else {
2016 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
2017 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
2018 odm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);
2019 odm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x3);
2020 odm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x1);
2021 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
2022 odm_set_bb_reg(dm, R_0x41e8, 0x00000001, 0x0);
2023 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
2024 odm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);
2025 odm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x0000);
2026 odm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);
2027 odm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);
2028 odm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x000);
2029 odm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x1);
2030 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
2031 odm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);
2032 odm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);
2033 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
2034 odm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);
2035 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
2036 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
2037 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
2038 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
2039 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);
2040 }
2041 #endif
2042 halrf_enable_tssi_8822c(dm);
2043 #endif
2044
2045 }
2046
2047
halrf_set_tssi_value_8822c(void * dm_void,u32 tssi_value)2048 u32 halrf_set_tssi_value_8822c(
2049 void *dm_void,
2050 u32 tssi_value)
2051 {
2052 #if 0
2053 struct dm_struct *dm = (struct dm_struct *)dm_void;
2054 struct _hal_rf_ *rf = &dm->rf_table;
2055 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
2056 u16 tssi_codeword_tmp[TSSI_CODE_NUM] = {0};
2057 s16 txagc_codeword_tmp[TSSI_CODE_NUM] = {0};
2058 u8 tx_rate = phydm_get_tx_rate(dm);
2059 u8 tssi_rate = _halrf_driver_rate_to_tssi_rate_8822c(dm, tx_rate);
2060 u8 rate = phydm_get_tx_rate(dm);
2061 s8 efuse, kfree;
2062
2063 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X tssi_rate=%d\n"
2064 , __func__, tx_rate, tssi_rate);
2065
2066 odm_move_memory(dm, tssi_codeword_tmp, tssi->tssi_codeword,
2067 sizeof(tssi_codeword_tmp));
2068
2069 tssi_codeword_tmp[tssi_rate] = (u8)tssi_value;
2070
2071 _halrf_calculate_txagc_codeword_8822c(dm, tssi_codeword_tmp, txagc_codeword_tmp);
2072 _halrf_set_txagc_codeword_8822c(dm, txagc_codeword_tmp);
2073 halrf_set_tssi_codeword_8822c(dm, tssi_codeword_tmp);
2074
2075 kfree = _halrf_get_kfree_tssi_offset_8822c(dm);
2076
2077 tssi_value = tssi_value - tssi->tssi_codeword[tssi_rate] - kfree;
2078
2079 /*path s0*/
2080 /*2G CCK*/
2081 odm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, 0);
2082
2083 /*2G & 5G OFDM*/
2084 odm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0);
2085
2086 /*path s1*/
2087 /*2G CCK*/
2088 odm_set_bb_reg(dm, R_0x1ef0, 0x0001fe00, 0);
2089
2090 /*2G & 5G OFDM*/
2091 odm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0);
2092
2093 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2094 "===>%s Set DE = 0\n", __func__);
2095
2096 return tssi_value;
2097 #endif
2098 return 0;
2099 }
2100
2101
halrf_set_tssi_poewr_8822c(void * dm_void,s8 power)2102 void halrf_set_tssi_poewr_8822c(
2103 void *dm_void,
2104 s8 power)
2105 {
2106 s32 tssi_codeword = 0;
2107 #if 0
2108 struct dm_struct *dm = (struct dm_struct *)dm_void;
2109 struct _hal_rf_ *rf = &dm->rf_table;
2110 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
2111 u16 tssi_codeword_tmp[TSSI_CODE_NUM] = {0};
2112 s16 txagc_codeword_tmp[TSSI_CODE_NUM] = {0};
2113 u8 tx_rate = phydm_get_tx_rate(dm);
2114 u8 tssi_rate = _halrf_driver_rate_to_tssi_rate_8822c(dm, tx_rate);
2115 u8 rate = phydm_get_tx_rate(dm), i;
2116 u8 channel = *dm->channel, bw = *dm->band_width;
2117 s8 efuse, kfree;
2118 s32 index_tmp_a = 0, index_tmp_b = 0;
2119 u8 indexa , indexb;
2120
2121 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X tssi_rate=%d channel=%d\n"
2122 , __func__, tx_rate, tssi_rate, channel);
2123
2124 if (channel > 14) {
2125 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Not in 2G channel=%d\n", channel);
2126 return;
2127 }
2128
2129 if ((power >= -13 && power <= 13) || power == 0x7f)
2130 {
2131 #if 0
2132 power = power * TSSI_SLOPE_2G;
2133
2134 odm_move_memory(dm, tssi_codeword_tmp, tssi->tssi_codeword,
2135 sizeof(tssi_codeword_tmp));
2136
2137 if (power != 0x7f) {
2138 for (i = 0; i < TSSI_CODE_NUM; i++) {
2139 tssi_codeword_tmp[i] = tssi_codeword_tmp[i] + power;
2140
2141 if (tssi_codeword_tmp[i] > 255)
2142 tssi_codeword_tmp[i] = 255;
2143 else if ((s16)tssi_codeword_tmp[i] < 0)
2144 tssi_codeword_tmp[i] = 0;
2145 }
2146 }
2147
2148 _halrf_calculate_txagc_codeword_8822c(dm, tssi_codeword_tmp, txagc_codeword_tmp);
2149 _halrf_set_txagc_codeword_8822c(dm, txagc_codeword_tmp);
2150 /*halrf_set_tssi_codeword_8822c(dm, tssi_codeword_tmp);*/
2151 #endif
2152 #if 0
2153 if (power != 0x7f) {
2154 for (i = 0; i < TSSI_CODE_NUM; i++) {
2155 txagc_codeword_tmp[i] = power * 4;
2156
2157 if (txagc_codeword_tmp[i] > 63)
2158 tssi_codeword_tmp[i] = 63;
2159 else if (txagc_codeword_tmp[i] < -64)
2160 tssi_codeword_tmp[i] = -64;
2161 }
2162 }
2163
2164 _halrf_set_txagc_codeword_8822c(dm, txagc_codeword_tmp);
2165
2166 #endif
2167
2168 if (power != 0x7f) {
2169 indexa = odm_get_tx_power_index(dm, RF_PATH_A, rate, bw, channel);
2170 indexb = odm_get_tx_power_index(dm, RF_PATH_B, rate, bw, channel);
2171
2172 index_tmp_a = indexa + power * 4;
2173
2174 if (index_tmp_a > 127)
2175 index_tmp_a = 127;
2176 else if (index_tmp_a < 0)
2177 index_tmp_a = 0;
2178
2179 tssi->index[RF_PATH_A][channel - 1] = (u32)index_tmp_a;
2180
2181 index_tmp_b = indexb + power * 4;
2182
2183 if (index_tmp_b > 127)
2184 index_tmp_b = 127;
2185 else if (index_tmp_b < 0)
2186 index_tmp_b = 0;
2187
2188 tssi->index[RF_PATH_B][channel - 1] = (u32)index_tmp_b;
2189
2190 odm_set_bb_reg(dm, R_0x18e8, 0x0001fc00, (index_tmp_a & 0x7f));
2191 odm_set_bb_reg(dm, R_0x41e8, 0x0001fc00, (index_tmp_b & 0x7f));
2192
2193 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2194 "===>%s Set coex Tx index PathA:%d PathB:%d\n",
2195 __func__,
2196 odm_get_bb_reg(dm, R_0x18e8, 0x0001fc00),
2197 odm_get_bb_reg(dm, R_0x41e8, 0x0001fc00));
2198 } else {
2199 indexa = odm_get_tx_power_index(dm, RF_PATH_A, rate, bw, channel);
2200 indexb = odm_get_tx_power_index(dm, RF_PATH_B, rate, bw, channel);
2201
2202 odm_set_bb_reg(dm, R_0x18e8, 0x0001fc00, (indexa & 0x7f));
2203 odm_set_bb_reg(dm, R_0x41e8, 0x0001fc00, (indexb & 0x7f));
2204
2205 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2206 "===>%s Set coex Tx default index PathA:%d PathB:%d\n",
2207 __func__,
2208 odm_get_bb_reg(dm, R_0x18e8, 0x0001fc00),
2209 odm_get_bb_reg(dm, R_0x41e8, 0x0001fc00));
2210
2211 for (i = 1; i <= 14; i++) {
2212 tssi->index[RF_PATH_A][i - 1] = 0;
2213 tssi->index[RF_PATH_B][i - 1] = 0;
2214 }
2215 }
2216
2217 }
2218 #endif
2219
2220 }
2221
halrf_get_efuse_thermal_pwrtype_8822c(void * dm_void)2222 void halrf_get_efuse_thermal_pwrtype_8822c(
2223 void *dm_void)
2224 {
2225 struct dm_struct *dm = (struct dm_struct *)dm_void;
2226 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
2227 struct _hal_rf_ *rf = &dm->rf_table;
2228 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
2229
2230 u32 thermal_tmp, pg_tmp;
2231
2232 tssi->thermal[RF_PATH_A] = 0xff;
2233 tssi->thermal[RF_PATH_B] = 0xff;
2234
2235 /*path s0*/
2236 odm_efuse_logical_map_read(dm, 1, 0xd0, &thermal_tmp);
2237 tssi->thermal[RF_PATH_A] = (u8)thermal_tmp;
2238
2239 /*path s1*/
2240 odm_efuse_logical_map_read(dm, 1, 0xd1, &thermal_tmp);
2241 tssi->thermal[RF_PATH_B] = (u8)thermal_tmp;
2242
2243 /*power tracking type*/
2244 odm_efuse_logical_map_read(dm, 1, 0xc8, &pg_tmp);
2245 if (((pg_tmp >> 4) & 0xf) == 0xf)
2246 rf->power_track_type = 0x0;
2247 else
2248 rf->power_track_type = (u8)((pg_tmp >> 4) & 0xf);
2249
2250 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2251 "===>%s thermal pahtA=0x%x pahtB=0x%x power_track_type=0x%x\n",
2252 __func__, tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B],
2253 rf->power_track_type);
2254
2255 }
2256
halrf_query_tssi_value_8822c(void * dm_void)2257 u32 halrf_query_tssi_value_8822c(
2258 void *dm_void)
2259 {
2260 s32 tssi_codeword = 0;
2261
2262 struct dm_struct *dm = (struct dm_struct *)dm_void;
2263 struct _hal_rf_ *rf = &dm->rf_table;
2264 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
2265 u8 tssi_rate;
2266 u8 rate = phydm_get_tx_rate(dm);
2267 /*s8 efuse, kfree;*/
2268
2269 tssi_rate = _halrf_driver_rate_to_tssi_rate_8822c(dm, rate);
2270 /*tssi_codeword = tssi->tssi_codeword[tssi_rate];*/
2271
2272 #if 0
2273 if (rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M) {
2274 efuse = _halrf_get_efuse_tssi_offset_8822c(dm, 3);
2275 kfree = _halrf_get_kfree_tssi_offset_8822c(dm);
2276 } else {
2277 efuse = _halrf_get_efuse_tssi_offset_8822c(dm, 19);
2278 kfree = _halrf_get_kfree_tssi_offset_8822c(dm);
2279 }
2280
2281 tssi_codeword = tssi_codeword + efuse + kfree;
2282
2283 if (tssi_codeword <= 0)
2284 tssi_codeword = 0;
2285 else if (tssi_codeword >= 255)
2286 tssi_codeword = 255;
2287 #endif
2288 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2289 "===>%s tx_rate=0x%x tssi_codeword=0x%x\n",
2290 __func__, rate, tssi->tssi_codeword[tssi_rate]);
2291
2292 return (u32)tssi->tssi_codeword[tssi_rate];
2293 }
2294
halrf_tssi_cck_8822c(void * dm_void)2295 void halrf_tssi_cck_8822c(
2296 void *dm_void)
2297 {
2298 #if 0
2299 struct dm_struct *dm = (struct dm_struct *)dm_void;
2300 struct _hal_rf_ *rf = &dm->rf_table;
2301 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
2302 u8 rate = phydm_get_tx_rate(dm);
2303 u32 alogk, regc, regde, regf;
2304 s32 sregde, sregf;
2305
2306 if (!(rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M))
2307 return;
2308
2309 /*path s0*/
2310 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
2311 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);
2312 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0044);
2313 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0044);
2314 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0044);
2315 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0044);
2316 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);
2317 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0044);
2318 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);
2319 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);
2320 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);
2321 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);
2322 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);
2323 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);
2324 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);
2325 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);
2326 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);
2327 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
2328 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
2329 odm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);
2330 odm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x2);
2331 odm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x1);
2332 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
2333 odm_set_bb_reg(dm, R_0x18e8, 0x00000001, 0x0);
2334 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
2335 odm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);
2336 odm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x1266);
2337 odm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);
2338 odm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);
2339 odm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, 0x00);
2340 odm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x110);
2341 odm_set_rf_reg(dm, RF_PATH_A, RF_0x7f, 0x00002, 0x1);
2342 odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);
2343 odm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x0000c, 0x3);
2344 odm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x000c0, 0x3);
2345 odm_set_rf_reg(dm, RF_PATH_A, RF_0x6e, 0x001e0, 0x0);
2346 odm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);
2347 odm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);
2348 odm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x1);
2349 odm_set_bb_reg(dm, R_0x1800, 0x80000000, 0x1);
2350 odm_set_bb_reg(dm, R_0x1804, 0x80000000, 0x1);
2351 odm_set_bb_reg(dm, R_0x1800, 0x40000000, 0x0);
2352 odm_set_bb_reg(dm, R_0x1804, 0x40000000, 0x0);
2353 odm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x0);
2354 odm_set_bb_reg(dm, R_0x18ec, 0x40000000, 0x0);
2355 odm_set_bb_reg(dm, R_0x1860, 0x00000800, 0x0);
2356 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);
2357 odm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);
2358 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
2359 odm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);
2360 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
2361 odm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);
2362 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
2363
2364 /*read AlogK u9bit*/
2365 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x936);
2366 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
2367 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);
2368 alogk = odm_get_bb_reg(dm, R_0x2dbc, 0xff800000);
2369
2370 /*read c u8bit*/
2371 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x933);
2372 regc = odm_get_bb_reg(dm, R_0x2dbc, 0x003fc000);
2373
2374 /*read de s8bit*/
2375 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x933);
2376 regde = odm_get_bb_reg(dm, R_0x2dbc, 0x3fc00000);
2377
2378 if (regde & 0x80)
2379 sregde = regde - 256;
2380 else
2381 sregde = regde;
2382
2383 /*read f s7bit*/
2384 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x934);
2385 regf = odm_get_bb_reg(dm, R_0x2dbc, 0x0000007f);
2386
2387 if (regf & 0x40)
2388 sregf = regf - 128;
2389 else
2390 sregf = regf;
2391
2392 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2393 "tssi->cck_offset_patha(%d)\n",
2394 tssi->cck_offset_patha);
2395
2396 tssi->cck_offset_patha = tssi->cck_offset_patha + ((s32)(regc - sregde - alogk - sregf) / 2);
2397
2398 if (tssi->cck_offset_patha >= 63)
2399 tssi->cck_offset_patha = 63;
2400 else if (tssi->cck_offset_patha <= -64)
2401 tssi->cck_offset_patha = -64;
2402
2403 odm_set_bb_reg(dm, R_0x18a0, 0x0000007f, (tssi->cck_offset_patha & 0x7f));
2404
2405 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2406 "tssi->cck_offset_patha(%d) = (regc(%d) - sregde(%d) - alogk(%d) - sregf(%d)) / 2\n",
2407 tssi->cck_offset_patha, regc, sregde, alogk, sregf);
2408
2409
2410 /*path s1*/
2411 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
2412 odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4);
2413 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);
2414 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0044);
2415 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0044);
2416 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0044);
2417 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0044);
2418 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);
2419 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0044);
2420 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);
2421 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);
2422 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);
2423 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);
2424 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);
2425 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);
2426 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);
2427 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);
2428 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);
2429 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
2430 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
2431 odm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);
2432 odm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x2);
2433 odm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x1);
2434 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
2435 odm_set_bb_reg(dm, R_0x41e8, 0x00000001, 0x0);
2436 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
2437 odm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);
2438 odm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x1266);
2439 odm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);
2440 odm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);
2441 odm_set_bb_reg(dm, R_0x1ef0, 0x0001fe00, 0x00);
2442 odm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x110);
2443 odm_set_rf_reg(dm, RF_PATH_B, RF_0x7f, 0x00002, 0x1);
2444 odm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);
2445 odm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x0000c, 0x3);
2446 odm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x000c0, 0x3);
2447 odm_set_rf_reg(dm, RF_PATH_A, RF_0x6e, 0x001e0, 0x0);
2448 odm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);
2449 odm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);
2450 odm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x1);
2451 odm_set_bb_reg(dm, R_0x4100, 0x80000000, 0x1);
2452 odm_set_bb_reg(dm, R_0x4104, 0x80000000, 0x1);
2453 odm_set_bb_reg(dm, R_0x4100, 0x40000000, 0x0);
2454 odm_set_bb_reg(dm, R_0x4104, 0x40000000, 0x0);
2455 odm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x0);
2456 odm_set_bb_reg(dm, R_0x41ec, 0x40000000, 0x0);
2457 odm_set_bb_reg(dm, R_0x4160, 0x00000800, 0x0);
2458 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);
2459 odm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);
2460 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
2461 odm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);
2462 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
2463 odm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);
2464 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
2465
2466 /*read AlogK u9bit*/
2467 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb36);
2468 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
2469 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);
2470 alogk = odm_get_bb_reg(dm, R_0x2dbc, 0xff800000);
2471
2472 /*read c u8bit*/
2473 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb33);
2474 regc = odm_get_bb_reg(dm, R_0x2dbc, 0x003fc000);
2475
2476 /*read de s8bit*/
2477 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb33);
2478 regde = odm_get_bb_reg(dm, R_0x2dbc, 0x3fc00000);
2479
2480 if (regde & 0x80)
2481 sregde = regde - 256;
2482 else
2483 sregde = regde;
2484
2485 /*read f s7bit*/
2486 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb34);
2487 regf = odm_get_bb_reg(dm, R_0x2dbc, 0x0000007f);
2488
2489 if (regf & 0x40)
2490 sregf = regf - 128;
2491 else
2492 sregf = regf;
2493
2494 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2495 "tssi->cck_offset_pathb(%d)\n",
2496 tssi->cck_offset_pathb);
2497
2498 tssi->cck_offset_pathb = tssi->cck_offset_pathb + ((s32)(regc - sregde - alogk - sregf) / 2);
2499
2500 if (tssi->cck_offset_pathb >= 63)
2501 tssi->cck_offset_pathb = 63;
2502 else if (tssi->cck_offset_pathb <= -64)
2503 tssi->cck_offset_pathb = -64;
2504
2505 odm_set_bb_reg(dm, R_0x41a0, 0x0000007f, (tssi->cck_offset_pathb & 0x7f));
2506
2507 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2508 "tssi->cck_offset_pathb(%d) = (regc(%d) - sregde(%d) - alogk(%d) - sregf(%d)) / 2\n",
2509 tssi->cck_offset_pathb, regc, sregde, alogk, sregf);
2510 #endif
2511
2512 }
2513
halrf_thermal_cck_8822c(void * dm_void)2514 void halrf_thermal_cck_8822c(
2515 void *dm_void)
2516 {
2517 #if 0
2518 struct dm_struct *dm = (struct dm_struct *)dm_void;
2519 struct _hal_rf_ *rf = &dm->rf_table;
2520 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
2521 u8 rate = phydm_get_tx_rate(dm);
2522 u32 alogk, regc, regde, regf;
2523 s32 sregde, sregf;
2524
2525 if ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) == 1) {
2526 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2527 "===>%s\n", __func__);
2528 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2529 "rf_supportability HAL_RF_TX_PWR_TRACK on\n");
2530 } else {
2531 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2532 "===>%s, return!\n", __func__);
2533 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2534 "rf_supportability HAL_RF_TX_PWR_TRACK off, return!!\n");
2535
2536 /*halrf_disable_tssi_8822c(dm);*/
2537 return;
2538 }
2539
2540 if (!tssi->get_thermal) {
2541 odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
2542 odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
2543 odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
2544
2545 odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
2546 odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
2547 odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
2548
2549 tssi->get_thermal = 1;
2550
2551 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Trigger current thmermal\n");
2552 } else {
2553 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "s0 current thmermal=0x%x(%d)\n",
2554 odm_get_rf_reg(dm, RF_PATH_A, R_0x42, 0xfc00),
2555 odm_get_rf_reg(dm, RF_PATH_A, R_0x42, 0xfc00));
2556
2557 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "s1 current thmermal=0x%x(%d)\n",
2558 odm_get_rf_reg(dm, RF_PATH_B, R_0x42, 0xfc00),
2559 odm_get_rf_reg(dm, RF_PATH_B, R_0x42, 0xfc00));
2560
2561 tssi->get_thermal = 0;
2562 }
2563
2564 if ((DBG_RF_TX_PWR_TRACK & dm->rf_table.rf_dbg_comp) == 1) {
2565 /*set debug port to 0x944*/
2566 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x944)) {
2567 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "s0 Power Tracking offset %d\n",
2568 (phydm_get_bb_dbg_port_val(dm) & 0x7f00) >> 8);
2569 phydm_release_bb_dbg_port(dm);
2570 }
2571
2572 /*set debug port to 0xb44*/
2573 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0xb44)) {
2574 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "s1 Power Tracking offset %d\n",
2575 (phydm_get_bb_dbg_port_val(dm) & 0x7f00) >> 8);
2576 phydm_release_bb_dbg_port(dm);
2577 }
2578 }
2579
2580 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>%s \n", __func__);
2581
2582 if (!(rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M))
2583 return;
2584
2585 /*path s0*/
2586 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
2587 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
2588 odm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);
2589 odm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x3);
2590 odm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x1);
2591 odm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);
2592 odm_set_bb_reg(dm, R_0x18e8, 0x00000001, 0x0);
2593 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
2594 odm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);
2595 odm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x0000);
2596 odm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);
2597 odm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);
2598 odm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, 0x00);
2599 odm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x000);
2600 odm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x1);
2601 odm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);
2602 odm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);
2603 odm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);
2604 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
2605 odm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);
2606 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
2607
2608 /*read f s7bit*/
2609 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x934);
2610 regf = odm_get_bb_reg(dm, R_0x2dbc, 0x0000007f);
2611
2612 if (regf & 0x40)
2613 sregf = regf - 128;
2614 else
2615 sregf = regf;
2616
2617 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2618 "tssi->cck_offset_patha(%d)\n",
2619 tssi->cck_offset_patha);
2620
2621 //tssi->cck_offset_patha = tssi->cck_offset_patha + sregf;
2622 tssi->cck_offset_patha = sregf;
2623
2624 if (tssi->cck_offset_patha >= 63)
2625 tssi->cck_offset_patha = 63;
2626 else if (tssi->cck_offset_patha <= -64)
2627 tssi->cck_offset_patha = -64;
2628
2629 odm_set_bb_reg(dm, R_0x18a0, 0x0000007f, (tssi->cck_offset_patha & 0x7f));
2630
2631 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2632 "tssi->cck_offset_patha(%d)\n", tssi->cck_offset_patha);
2633
2634
2635 /*path s1*/
2636 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
2637 odm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);
2638 odm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);
2639 odm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x3);
2640 odm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x1);
2641 odm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);
2642 odm_set_bb_reg(dm, R_0x41e8, 0x00000001, 0x0);
2643 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
2644 odm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);
2645 odm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x0000);
2646 odm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);
2647 odm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);
2648 odm_set_bb_reg(dm, R_0x1ef0, 0x0001fe00, 0x00);
2649 odm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x000);
2650 odm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x1);
2651 odm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);
2652 odm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);
2653 odm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);
2654 odm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);
2655 odm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);
2656 odm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);
2657
2658 /*read f s7bit*/
2659 odm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb34);
2660 regf = odm_get_bb_reg(dm, R_0x2dbc, 0x0000007f);
2661
2662 if (regf & 0x40)
2663 sregf = regf - 128;
2664 else
2665 sregf = regf;
2666
2667 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2668 "tssi->cck_offset_pathb(%d)\n",
2669 tssi->cck_offset_pathb);
2670
2671 //tssi->cck_offset_pathb = tssi->cck_offset_pathb + sregf;
2672 tssi->cck_offset_pathb = sregf;
2673
2674 if (tssi->cck_offset_pathb >= 63)
2675 tssi->cck_offset_pathb = 63;
2676 else if (tssi->cck_offset_pathb <= -64)
2677 tssi->cck_offset_pathb = -64;
2678
2679 odm_set_bb_reg(dm, R_0x41a0, 0x0000007f, (tssi->cck_offset_pathb & 0x7f));
2680
2681 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
2682 "tssi->cck_offset_pathb(%d)\n", tssi->cck_offset_pathb);
2683 #endif
2684
2685 }
2686
2687 #endif
2688