1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_vp8d_vdpu2"
18
19 #include <string.h>
20
21 #include "mpp_env.h"
22 #include "mpp_mem.h"
23 #include "mpp_debug.h"
24
25 #include "hal_vp8d_vdpu2.h"
26 #include "hal_vp8d_vdpu2_reg.h"
27
28 #define CLIP3(l, h, v) ((v) < (l) ? (l) : ((v) > (h) ? (h) : (v)))
29
30 static const RK_U32 mcFilter[8][6] = {
31 { 0, 0, 128, 0, 0, 0 },
32 { 0, -6, 123, 12, -1, 0 },
33 { 2, -11, 108, 36, -8, 1 },
34 { 0, -9, 93, 50, -6, 0 },
35 { 3, -16, 77, 77, -16, 3 },
36 { 0, -6, 50, 93, -9, 0 },
37 { 1, -8, 36, 108, -11, 2 },
38 { 0, -1, 12, 123, -6, 0 }
39 };
40
hal_vp8d_vdpu2_init(void * hal,MppHalCfg * cfg)41 MPP_RET hal_vp8d_vdpu2_init(void *hal, MppHalCfg *cfg)
42 {
43 MPP_RET ret = MPP_OK;
44 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
45
46 FUN_T("FUN_IN");
47
48 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU2);
49 if (ret) {
50 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
51 goto ERR_RET;
52 }
53
54 if (NULL == ctx->regs) {
55 ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t));
56 if (NULL == ctx->regs) {
57 mpp_err("hal_vp8 reg alloc failed\n");
58 ret = MPP_ERR_NOMEM;
59 goto ERR_RET;
60 }
61 }
62
63 if (NULL == ctx->group) {
64 ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
65 if (ret) {
66 mpp_err("hal_vp8 mpp_buffer_group_get failed\n");
67 goto ERR_RET;
68 }
69 }
70
71 ret = mpp_buffer_get(ctx->group, &ctx->probe_table, VP8D_PROB_TABLE_SIZE);
72 if (ret) {
73 mpp_err("hal_vp8 probe_table get buffer failed\n");
74 goto ERR_RET;
75 }
76
77 ret = mpp_buffer_get(ctx->group, &ctx->seg_map, VP8D_MAX_SEGMAP_SIZE);
78 if (ret) {
79 mpp_err("hal_vp8 seg_map get buffer failed\n");
80 goto ERR_RET;
81 }
82
83 //configure
84 ctx->packet_slots = cfg->packet_slots;
85 ctx->frame_slots = cfg->frame_slots;
86 cfg->dev = ctx->dev;
87
88 FUN_T("FUN_OUT");
89 return ret;
90 ERR_RET:
91 if (ctx->dev) {
92 mpp_dev_deinit(ctx->dev);
93 ctx->dev = NULL;
94 }
95
96 if (ctx->regs) {
97 mpp_free(ctx->regs);
98 ctx->regs = NULL;
99 }
100
101 if (ctx->probe_table) {
102 mpp_buffer_put(ctx->probe_table);
103 ctx->probe_table = NULL;
104 }
105
106 if (ctx->seg_map) {
107 mpp_buffer_group_put(ctx->seg_map);
108 ctx->seg_map = NULL;
109 }
110
111 if (ctx->group) {
112 mpp_buffer_put(ctx->group);
113 ctx->group = NULL;
114 }
115 FUN_T("FUN_OUT");
116 return ret;
117 }
118
hal_vp8d_vdpu2_deinit(void * hal)119 MPP_RET hal_vp8d_vdpu2_deinit(void *hal)
120 {
121 MPP_RET ret = MPP_OK;
122 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
123
124 FUN_T("FUN_IN");
125
126 if (ctx->dev) {
127 mpp_dev_deinit(ctx->dev);
128 ctx->dev = NULL;
129 }
130
131 if (ctx->probe_table) {
132 ret = mpp_buffer_put(ctx->probe_table);
133 if (ret) {
134 mpp_err("hal_vp8 probe table put buffer failed\n");
135 }
136 }
137
138 if (ctx->seg_map) {
139 ret = mpp_buffer_put(ctx->seg_map);
140 if (ret) {
141 mpp_err("hal_vp8 seg map put buffer failed\n");
142 }
143 }
144
145 if (ctx->group) {
146 ret = mpp_buffer_group_put(ctx->group);
147 if (ret) {
148 mpp_err("hal_vp8 group free buffer failed\n");
149 }
150 }
151
152 if (ctx->regs) {
153 mpp_free(ctx->regs);
154 ctx->regs = NULL;
155 }
156
157 FUN_T("FUN_OUT");
158 return ret;
159 }
160
hal_vp8_init_hwcfg(VP8DHalContext_t * ctx)161 static MPP_RET hal_vp8_init_hwcfg(VP8DHalContext_t *ctx)
162 {
163
164 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs;
165
166 FUN_T("FUN_IN");
167 memset(reg, 0, sizeof(VP8DRegSet_t));
168 reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0;
169 reg->reg50_dec_ctrl.sw_dec_scmd_dis = 0;
170 reg->reg50_dec_ctrl.sw_dec_adv_pre_dis = 0;
171 reg->reg50_dec_ctrl.sw_dec_latency = 0;
172
173 reg->reg53_dec_mode = DEC_MODE_VP8;
174
175 reg->reg54_endian.sw_dec_in_endian = 1;
176 reg->reg54_endian.sw_dec_out_endian = 1;
177 reg->reg54_endian.sw_dec_inswap32_e = 1;
178 reg->reg54_endian.sw_dec_outswap32_e = 1;
179 reg->reg54_endian.sw_dec_strswap32_e = 1;
180 reg->reg54_endian.sw_dec_strendian_e = 1;
181
182 reg->reg55_Interrupt.sw_dec_irq = 0;
183
184 reg->reg56_axi_ctrl.sw_dec_axi_rn_id = 0;
185 reg->reg56_axi_ctrl.sw_dec_axi_wr_id = 0;
186
187 reg->reg56_axi_ctrl.sw_dec_data_disc_e = 0;
188 reg->reg56_axi_ctrl.sw_dec_max_burst = 16;
189 reg->reg57_enable_ctrl.sw_dec_timeout_e = 1;
190 reg->reg57_enable_ctrl.sw_dec_clk_gate_e = 1;
191 reg->reg57_enable_ctrl.sw_dec_out_dis = 0;
192
193 reg->reg149_segment_map_base = mpp_buffer_get_fd(ctx->seg_map);
194 reg->reg61_qtable_base = mpp_buffer_get_fd(ctx->probe_table);
195
196 FUN_T("FUN_OUT");
197 return MPP_OK;
198 }
199
hal_vp8d_pre_filter_tap_set(VP8DHalContext_t * ctx)200 static MPP_RET hal_vp8d_pre_filter_tap_set(VP8DHalContext_t *ctx)
201 {
202 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
203
204 FUN_T("FUN_IN");
205 regs->reg59.sw_pred_bc_tap_0_0 = mcFilter[0][1];
206 regs->reg59.sw_pred_bc_tap_0_1 = mcFilter[0][2];
207 regs->reg59.sw_pred_bc_tap_0_2 = mcFilter[0][3];
208 regs->reg153.sw_pred_bc_tap_0_3 = mcFilter[0][4];
209 regs->reg153.sw_pred_bc_tap_1_0 = mcFilter[1][1];
210 regs->reg153.sw_pred_bc_tap_1_1 = mcFilter[1][2];
211 regs->reg154.sw_pred_bc_tap_1_2 = mcFilter[1][3];
212 regs->reg154.sw_pred_bc_tap_1_3 = mcFilter[1][4];
213 regs->reg154.sw_pred_bc_tap_2_0 = mcFilter[2][1];
214 regs->reg155.sw_pred_bc_tap_2_1 = mcFilter[2][2];
215 regs->reg155.sw_pred_bc_tap_2_2 = mcFilter[2][3];
216 regs->reg155.sw_pred_bc_tap_2_3 = mcFilter[2][4];
217
218 regs->reg156.sw_pred_bc_tap_3_0 = mcFilter[3][1];
219 regs->reg156.sw_pred_bc_tap_3_1 = mcFilter[3][2];
220 regs->reg156.sw_pred_bc_tap_3_2 = mcFilter[3][3];
221 regs->reg157.sw_pred_bc_tap_3_3 = mcFilter[3][4];
222 regs->reg157.sw_pred_bc_tap_4_0 = mcFilter[4][1];
223 regs->reg157.sw_pred_bc_tap_4_1 = mcFilter[4][2];
224 regs->reg158.sw_pred_bc_tap_4_2 = mcFilter[4][3];
225 regs->reg158.sw_pred_bc_tap_4_3 = mcFilter[4][4];
226 regs->reg158.sw_pred_bc_tap_5_0 = mcFilter[5][1];
227
228 regs->reg125.sw_pred_bc_tap_5_1 = mcFilter[5][2];
229
230 regs->reg125.sw_pred_bc_tap_5_2 = mcFilter[5][3];
231
232 regs->reg125.sw_pred_bc_tap_5_3 = mcFilter[5][4];
233 regs->reg126.sw_pred_bc_tap_6_0 = mcFilter[6][1];
234 regs->reg126.sw_pred_bc_tap_6_1 = mcFilter[6][2];
235 regs->reg126.sw_pred_bc_tap_6_2 = mcFilter[6][3];
236 regs->reg127.sw_pred_bc_tap_6_3 = mcFilter[6][4];
237 regs->reg127.sw_pred_bc_tap_7_0 = mcFilter[7][1];
238 regs->reg127.sw_pred_bc_tap_7_1 = mcFilter[7][2];
239 regs->reg128.sw_pred_bc_tap_7_2 = mcFilter[7][3];
240 regs->reg128.sw_pred_bc_tap_7_3 = mcFilter[7][4];
241
242 regs->reg128.sw_pred_tap_2_M1 = mcFilter[2][0];
243 regs->reg128.sw_pred_tap_2_4 = mcFilter[2][5];
244 regs->reg128.sw_pred_tap_4_M1 = mcFilter[4][0];
245 regs->reg128.sw_pred_tap_4_4 = mcFilter[4][5];
246 regs->reg128.sw_pred_tap_6_M1 = mcFilter[6][0];
247 regs->reg128.sw_pred_tap_6_4 = mcFilter[6][5];
248
249 FUN_T("FUN_OUT");
250 return MPP_OK;
251 }
252
hal_vp8d_dct_partition_cfg(VP8DHalContext_t * ctx,HalTaskInfo * task)253 static MPP_RET hal_vp8d_dct_partition_cfg(VP8DHalContext_t *ctx,
254 HalTaskInfo *task)
255 {
256 RK_U32 i = 0, len = 0, len1 = 0;
257 RK_U32 extraBytesPacked = 0;
258 RK_U32 addr = 0, byte_offset = 0;
259 RK_U32 fd = 0;
260 MppBuffer streambuf = NULL;
261 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
262 DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
263
264 FUN_T("FUN_IN");
265
266 mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
267 fd = mpp_buffer_get_fd(streambuf);
268 regs->reg145_bitpl_ctrl_base = fd;
269 if (pic_param->stream_start_offset)
270 mpp_dev_set_reg_offset(ctx->dev, 145, pic_param->stream_start_offset);
271
272 regs->reg122.sw_strm1_start_bit = pic_param->stream_start_bit;
273
274 /* calculate dct partition length here instead */
275 if (pic_param->decMode == VP8HWD_VP8 && !pic_param->frame_type)
276 extraBytesPacked += 7;
277 len = pic_param->streamEndPos + pic_param->frameTagSize
278 - pic_param->dctPartitionOffsets[0];
279 len += ((1 << pic_param->log2_nbr_of_dct_partitions) - 1) * 3;
280 len1 = extraBytesPacked + pic_param->dctPartitionOffsets[0];
281 len += (len1 & 0x7);
282 regs->reg51_stream_info.sw_stream_len = len;
283
284 len = pic_param->offsetToDctParts + pic_param->frameTagSize -
285 (pic_param->stream_start_offset - extraBytesPacked);
286 len++;
287
288 regs->reg124.sw_stream1_len = len;
289 regs->reg124.sw_coeffs_part_am =
290 (1 << pic_param->log2_nbr_of_dct_partitions) - 1;
291 for (i = 0; i < (RK_U32)(1 << pic_param->log2_nbr_of_dct_partitions); i++) {
292 addr = extraBytesPacked + pic_param->dctPartitionOffsets[i];
293 byte_offset = addr & 0x7;
294 addr = addr & 0xFFFFFFF8;
295
296 if (i == 0) {
297 regs->reg64_input_stream_base = fd;
298 if (addr)
299 mpp_dev_set_reg_offset(ctx->dev, 64, addr);
300 } else if (i <= 5) {
301 regs->reg_dct_strm_base[i - 1] = fd;
302 if (addr)
303 mpp_dev_set_reg_offset(ctx->dev, 139 + i, addr);
304 } else {
305 regs->reg_dct_strm1_base[i - 6] = fd;
306 if (addr)
307 mpp_dev_set_reg_offset(ctx->dev, 140 + i, addr);
308 }
309
310 switch (i) {
311 case 0:
312 regs->reg122.sw_strm_start_bit = byte_offset * 8;
313 break;
314 case 1:
315 regs->reg121.sw_dct1_start_bit = byte_offset * 8;
316 break;
317 case 2:
318 regs->reg121.sw_dct2_start_bit = byte_offset * 8;
319 break;
320 case 3:
321 regs->reg150.sw_dct_start_bit_3 = byte_offset * 8;
322 break;
323 case 4:
324 regs->reg150.sw_dct_start_bit_4 = byte_offset * 8;
325 break;
326 case 5:
327 regs->reg150.sw_dct_start_bit_5 = byte_offset * 8;
328 break;
329 case 6:
330 regs->reg150.sw_dct_start_bit_6 = byte_offset * 8;
331 break;
332 case 7:
333 regs->reg150.sw_dct_start_bit_7 = byte_offset * 8;
334 break;
335 default:
336 break;
337 }
338 }
339
340 FUN_T("FUN_OUT");
341 return MPP_OK;
342 }
343
hal_vp8hw_asic_probe_update(DXVA_PicParams_VP8 * p,RK_U8 * probTbl)344 static void hal_vp8hw_asic_probe_update(DXVA_PicParams_VP8 *p, RK_U8 *probTbl)
345 {
346 RK_U8 *dst;
347 RK_U32 i, j, k;
348
349 FUN_T("FUN_IN");
350 /* first probs */
351 dst = probTbl;
352
353 dst[0] = p->probe_skip_false;
354 dst[1] = p->prob_intra;
355 dst[2] = p->prob_last;
356 dst[3] = p->prob_golden;
357 dst[4] = p->stVP8Segments.mb_segment_tree_probs[0];
358 dst[5] = p->stVP8Segments.mb_segment_tree_probs[1];
359 dst[6] = p->stVP8Segments.mb_segment_tree_probs[2];
360 dst[7] = 0; /*unused*/
361
362 dst += 8;
363 dst[0] = p->intra_16x16_prob[0];
364 dst[1] = p->intra_16x16_prob[1];
365 dst[2] = p->intra_16x16_prob[2];
366 dst[3] = p->intra_16x16_prob[3];
367 dst[4] = p->intra_chroma_prob[0];
368 dst[5] = p->intra_chroma_prob[1];
369 dst[6] = p->intra_chroma_prob[2];
370 dst[7] = 0; /*unused*/
371
372 /* mv probs */
373 dst += 8;
374 dst[0] = p->vp8_mv_update_probs[0][0]; /* is short */
375 dst[1] = p->vp8_mv_update_probs[1][0];
376 dst[2] = p->vp8_mv_update_probs[0][1]; /* sign */
377 dst[3] = p->vp8_mv_update_probs[1][1];
378 dst[4] = p->vp8_mv_update_probs[0][8 + 9];
379 dst[5] = p->vp8_mv_update_probs[0][9 + 9];
380 dst[6] = p->vp8_mv_update_probs[1][8 + 9];
381 dst[7] = p->vp8_mv_update_probs[1][9 + 9];
382 dst += 8;
383 for ( i = 0 ; i < 2 ; ++i ) {
384 for ( j = 0 ; j < 8 ; j += 4 ) {
385 dst[0] = p->vp8_mv_update_probs[i][j + 9 + 0];
386 dst[1] = p->vp8_mv_update_probs[i][j + 9 + 1];
387 dst[2] = p->vp8_mv_update_probs[i][j + 9 + 2];
388 dst[3] = p->vp8_mv_update_probs[i][j + 9 + 3];
389 dst += 4;
390 }
391 }
392 for ( i = 0 ; i < 2 ; ++i ) {
393 dst[0] = p->vp8_mv_update_probs[i][0 + 2];
394 dst[1] = p->vp8_mv_update_probs[i][1 + 2];
395 dst[2] = p->vp8_mv_update_probs[i][2 + 2];
396 dst[3] = p->vp8_mv_update_probs[i][3 + 2];
397 dst[4] = p->vp8_mv_update_probs[i][4 + 2];
398 dst[5] = p->vp8_mv_update_probs[i][5 + 2];
399 dst[6] = p->vp8_mv_update_probs[i][6 + 2];
400 dst[7] = 0; /*unused*/
401 dst += 8;
402 }
403
404 /* coeff probs (header part) */
405 dst = (RK_U8*)probTbl;
406 dst += (8 * 7);
407 for ( i = 0 ; i < 4 ; ++i ) {
408 for ( j = 0 ; j < 8 ; ++j ) {
409 for ( k = 0 ; k < 3 ; ++k ) {
410 dst[0] = p->vp8_coef_update_probs[i][j][k][0];
411 dst[1] = p->vp8_coef_update_probs[i][j][k][1];
412 dst[2] = p->vp8_coef_update_probs[i][j][k][2];
413 dst[3] = p->vp8_coef_update_probs[i][j][k][3];
414 dst += 4;
415 }
416 }
417 }
418
419 /* coeff probs (footer part) */
420 dst = (RK_U8*)probTbl;
421 dst += (8 * 55);
422 for ( i = 0 ; i < 4 ; ++i ) {
423 for ( j = 0 ; j < 8 ; ++j ) {
424 for ( k = 0 ; k < 3 ; ++k ) {
425 dst[0] = p->vp8_coef_update_probs[i][j][k][4];
426 dst[1] = p->vp8_coef_update_probs[i][j][k][5];
427 dst[2] = p->vp8_coef_update_probs[i][j][k][6];
428 dst[3] = p->vp8_coef_update_probs[i][j][k][7];
429 dst[4] = p->vp8_coef_update_probs[i][j][k][8];
430 dst[5] = p->vp8_coef_update_probs[i][j][k][9];
431 dst[6] = p->vp8_coef_update_probs[i][j][k][10];
432 dst[7] = 0; /*unused*/
433 dst += 8;
434 }
435 }
436 }
437 FUN_T("FUN_OUT");
438 return ;
439 }
440
hal_vp8d_vdpu2_gen_regs(void * hal,HalTaskInfo * task)441 MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
442 {
443 MPP_RET ret = MPP_OK;
444 RK_U32 mb_width = 0, mb_height = 0;
445 MppBuffer framebuf = NULL;
446 RK_U8 *segmap_ptr = NULL;
447 RK_U8 *probe_ptr = NULL;
448 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
449 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
450 DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
451
452 FUN_T("FUN_IN");
453
454 hal_vp8_init_hwcfg(ctx);
455 mb_width = (pic_param->width + 15) >> 4;
456 mb_height = (pic_param->height + 15) >> 4;
457 // mpp_log("mb_width = %d mb_height = %d", mb_width, mb_height);
458 regs->reg120.sw_pic_mb_width = mb_width & 0x1FF;
459 regs->reg120.sw_pic_mb_hight_p = mb_height & 0xFF;
460 regs->reg120.sw_pic_mb_w_ext = mb_width >> 9;
461 regs->reg120.sw_pic_mb_h_ext = mb_height >> 8;
462
463 if (!pic_param->frame_type) {
464 segmap_ptr = mpp_buffer_get_ptr(ctx->seg_map);
465 if (NULL != segmap_ptr) {
466 memset(segmap_ptr, 0, VP8D_MAX_SEGMAP_SIZE);
467 }
468 }
469
470 probe_ptr = mpp_buffer_get_ptr(ctx->probe_table);
471 if (NULL != probe_ptr) {
472 hal_vp8hw_asic_probe_update(pic_param, probe_ptr);
473 }
474 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->CurrPic.Index7Bits, SLOT_BUFFER, &framebuf);
475 regs->reg63_cur_pic_base = mpp_buffer_get_fd(framebuf);
476 if (!pic_param->frame_type) { //key frame
477
478 regs->reg131_ref0_base = regs->reg63_cur_pic_base;
479
480 mpp_dev_set_reg_offset(ctx->dev, 131, mb_width * mb_height);
481 } else if (pic_param->lst_fb_idx.Index7Bits < 0x7f) { //config ref0 base
482 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->lst_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
483 regs->reg131_ref0_base = mpp_buffer_get_fd(framebuf);
484 } else {
485 regs->reg131_ref0_base = regs->reg63_cur_pic_base;
486 }
487
488 /* golden reference */
489 if (pic_param->gld_fb_idx.Index7Bits < 0x7f) {
490 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->gld_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
491 regs->reg136_golden_ref_base = mpp_buffer_get_fd(framebuf);
492 } else {
493 regs->reg136_golden_ref_base = regs->reg63_cur_pic_base;
494 }
495
496 regs->reg136_golden_ref_base = regs->reg136_golden_ref_base;
497 if (pic_param->ref_frame_sign_bias_golden) {
498 mpp_dev_set_reg_offset(ctx->dev, 136, pic_param->ref_frame_sign_bias_golden);
499 }
500
501 /* alternate reference */
502 if (pic_param->alt_fb_idx.Index7Bits < 0x7f) {
503 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->alt_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
504 regs->reg137.alternate_ref_base = mpp_buffer_get_fd(framebuf);
505 } else {
506 regs->reg137.alternate_ref_base = regs->reg63_cur_pic_base;
507 }
508
509 regs->reg137.alternate_ref_base = regs->reg137.alternate_ref_base;
510 if (pic_param->ref_frame_sign_bias_altref)
511 mpp_dev_set_reg_offset(ctx->dev, 137, pic_param->ref_frame_sign_bias_altref);
512
513 regs->reg149_segment_map_base = regs->reg149_segment_map_base;
514 if (pic_param->stVP8Segments.segmentation_enabled + (pic_param->stVP8Segments.update_mb_segmentation_map << 1))
515 mpp_dev_set_reg_offset(ctx->dev, 149, pic_param->stVP8Segments.segmentation_enabled
516 + (pic_param->stVP8Segments.update_mb_segmentation_map << 1));
517
518 regs->reg57_enable_ctrl.sw_pic_inter_e = pic_param->frame_type;
519 regs->reg50_dec_ctrl.sw_skip_mode = !pic_param->mb_no_coeff_skip;
520
521 if (!pic_param->stVP8Segments.segmentation_enabled) {
522 regs->reg129.sw_filt_level_0 = pic_param->filter_level;
523 } else if (pic_param->stVP8Segments.update_mb_segmentation_data) {
524 regs->reg129.sw_filt_level_0 = pic_param->stVP8Segments.segment_feature_data[1][0];
525 regs->reg129.sw_filt_level_1 = pic_param->stVP8Segments.segment_feature_data[1][1];
526 regs->reg129.sw_filt_level_2 = pic_param->stVP8Segments.segment_feature_data[1][2];
527 regs->reg129.sw_filt_level_3 = pic_param->stVP8Segments.segment_feature_data[1][3];
528 } else {
529 regs->reg129.sw_filt_level_0 = CLIP3(0, 63, (RK_S32)pic_param->filter_level + pic_param->stVP8Segments.segment_feature_data[1][0]);
530 regs->reg129.sw_filt_level_1 = CLIP3(0, 63, (RK_S32)pic_param->filter_level + pic_param->stVP8Segments.segment_feature_data[1][1]);
531 regs->reg129.sw_filt_level_2 = CLIP3(0, 63, (RK_S32)pic_param->filter_level + pic_param->stVP8Segments.segment_feature_data[1][2]);
532 regs->reg129.sw_filt_level_3 = CLIP3(0, 63, (RK_S32)pic_param->filter_level + pic_param->stVP8Segments.segment_feature_data[1][3]);
533 }
534
535 regs->reg132.sw_filt_type = pic_param->filter_type;
536 regs->reg132.sw_filt_sharpness = pic_param->sharpness;
537
538 if (pic_param->filter_level == 0) {
539 regs->reg50_dec_ctrl.sw_filtering_dis = 1;
540 }
541
542 if (pic_param->version != 3) {
543 regs->reg121.sw_romain_mv = 1;
544 }
545
546 if (pic_param->decMode == VP8HWD_VP8 && (pic_param->version & 0x3)) {
547 regs->reg121.sw_eable_bilinear = 1;
548 }
549 regs->reg122.sw_boolean_value = pic_param->bool_value;
550 regs->reg122.sw_boolean_range = pic_param->bool_range;
551
552 {
553 if (!pic_param->stVP8Segments.segmentation_enabled)
554 regs->reg130.sw_quant_0 = pic_param->y1ac_delta_q;
555 else if (pic_param->stVP8Segments.update_mb_segmentation_data) { /* absolute mode */
556 regs->reg130.sw_quant_0 = pic_param->stVP8Segments.segment_feature_data[0][0];
557 regs->reg130.sw_quant_1 = pic_param->stVP8Segments.segment_feature_data[0][1];
558 regs->reg151.sw_quant_2 = pic_param->stVP8Segments.segment_feature_data[0][2];
559 regs->reg151.sw_quant_3 = pic_param->stVP8Segments.segment_feature_data[0][3];
560 } else { /* delta mode */
561 regs->reg130.sw_quant_0 = CLIP3(0, 127, pic_param->y1ac_delta_q + pic_param->stVP8Segments.segment_feature_data[0][0]);
562 regs->reg130.sw_quant_1 = CLIP3(0, 127, pic_param->y1ac_delta_q + pic_param->stVP8Segments.segment_feature_data[0][1]);
563 regs->reg151.sw_quant_2 = CLIP3(0, 127, pic_param->y1ac_delta_q + pic_param->stVP8Segments.segment_feature_data[0][2]);
564 regs->reg151.sw_quant_3 = CLIP3(0, 127, pic_param->y1ac_delta_q + pic_param->stVP8Segments.segment_feature_data[0][3]);
565 }
566
567 regs->reg130.sw_quant_delta_0 = pic_param->y1dc_delta_q;
568 regs->reg130.sw_quant_delta_1 = pic_param->y2dc_delta_q;
569 regs->reg151.sw_quant_delta_2 = pic_param->y2ac_delta_q;
570 regs->reg151.sw_quant_delta_3 = pic_param->uvdc_delta_q;
571 regs->reg152.sw_quant_delta_4 = pic_param->uvac_delta_q;
572
573 if (pic_param->mode_ref_lf_delta_enabled) {
574 regs->reg133.sw_filt_ref_adj_0 = pic_param->ref_lf_deltas[0];
575 regs->reg133.sw_filt_ref_adj_1 = pic_param->ref_lf_deltas[1];
576 regs->reg133.sw_filt_ref_adj_2 = pic_param->ref_lf_deltas[2];
577 regs->reg133.sw_filt_ref_adj_3 = pic_param->ref_lf_deltas[3];
578 regs->reg132.sw_filt_mb_adj_0 = pic_param->mode_lf_deltas[0];
579 regs->reg132.sw_filt_mb_adj_1 = pic_param->mode_lf_deltas[1];
580 regs->reg132.sw_filt_mb_adj_2 = pic_param->mode_lf_deltas[2];
581 regs->reg132.sw_filt_mb_adj_3 = pic_param->mode_lf_deltas[3];
582 }
583
584 }
585
586 if ((pic_param->version & 0x3) == 0)
587 hal_vp8d_pre_filter_tap_set(ctx);
588
589 hal_vp8d_dct_partition_cfg(ctx, task);
590 regs->reg57_enable_ctrl.sw_dec_e = 1;
591
592 mpp_buffer_sync_end(ctx->probe_table);
593 mpp_buffer_sync_end(ctx->seg_map);
594
595 FUN_T("FUN_OUT");
596 return ret;
597 }
598
hal_vp8d_vdpu2_dump_info(void * hal,HalTaskInfo * task)599 static void hal_vp8d_vdpu2_dump_info(void *hal, HalTaskInfo *task)
600 {
601 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
602 (void)task;
603 FILE *fp;
604 char name[256];
605 static RK_U32 frame_cnt = 0;
606 RK_U32 i;
607 RK_U32 *p;
608
609 sprintf(name, "/data/video/reg_%d.bin", frame_cnt++);
610 fp = fopen(name, "ab+");
611 if (fp) {
612 p = (RK_U32*)ctx->regs;
613
614 for (i = 0; i < VP8D_REG_NUM; i++)
615 fprintf(fp, "reg[%d] %#08x\n", i, p[i]);
616 fclose(fp);
617 }
618
619 sprintf(name, "/data/video/seg_map_%d.bin", frame_cnt);
620 fp = fopen(name, "ab+");
621 if (fp) {
622 p = (RK_U32*)mpp_buffer_get_ptr(ctx->seg_map);
623
624 for (i = 0; i < mpp_buffer_get_size(ctx->seg_map) / 4; i++)
625 fprintf(fp, "%#08x\n", p[i]);
626 fclose(fp);
627 }
628
629 sprintf(name, "/data/video/probe_%d.bin", frame_cnt);
630 fp = fopen(name, "ab+");
631 if (fp) {
632 p = (RK_U32*)mpp_buffer_get_ptr(ctx->probe_table);
633
634 for (i = 0; i < mpp_buffer_get_size(ctx->probe_table) / 4; i++)
635 fprintf(fp, "%#08x\n", p[i]);
636 fclose(fp);
637 }
638 }
639
hal_vp8d_vdpu2_start(void * hal,HalTaskInfo * task)640 MPP_RET hal_vp8d_vdpu2_start(void *hal, HalTaskInfo *task)
641 {
642 MPP_RET ret = MPP_OK;
643 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
644 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
645
646 FUN_T("FUN_IN");
647 if (hal_vp8d_debug & VP8H_DBG_DUMP_REG)
648 hal_vp8d_vdpu2_dump_info(hal, task);
649
650 do {
651 MppDevRegWrCfg wr_cfg;
652 MppDevRegRdCfg rd_cfg;
653 RK_U32 reg_size = sizeof(VP8DRegSet_t);
654
655 wr_cfg.reg = regs;
656 wr_cfg.size = reg_size;
657 wr_cfg.offset = 0;
658
659 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
660 if (ret) {
661 mpp_err_f("set register write failed %d\n", ret);
662 break;
663 }
664
665 rd_cfg.reg = regs;
666 rd_cfg.size = reg_size;
667 rd_cfg.offset = 0;
668
669 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
670 if (ret) {
671 mpp_err_f("set register read failed %d\n", ret);
672 break;
673 }
674
675 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
676 if (ret) {
677 mpp_err_f("send cmd failed %d\n", ret);
678 break;
679 }
680 } while (0);
681
682 FUN_T("FUN_OUT");
683
684 (void)task;
685 return ret;
686 }
687
hal_vp8d_vdpu2_wait(void * hal,HalTaskInfo * task)688 MPP_RET hal_vp8d_vdpu2_wait(void *hal, HalTaskInfo *task)
689 {
690 MPP_RET ret = MPP_OK;
691 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
692
693 FUN_T("FUN_IN");
694
695 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
696 if (ret)
697 mpp_err_f("poll cmd failed %d\n", ret);
698
699 (void)task;
700 FUN_T("FUN_OUT");
701 return ret;
702 }
703