1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_vp8d_vdpu2"
18
19 #include <string.h>
20
21 #include "mpp_env.h"
22 #include "mpp_mem.h"
23 #include "mpp_debug.h"
24
25 #include "hal_vp8d_vdpu2.h"
26 #include "hal_vp8d_vdpu2_reg.h"
27
28 static RK_U32 vp8h_debug;
29
30 #define CLIP3(l, h, v) ((v) < (l) ? (l) : ((v) > (h) ? (h) : (v)))
31
32 static const RK_U32 mcFilter[8][6] = {
33 { 0, 0, 128, 0, 0, 0 },
34 { 0, -6, 123, 12, -1, 0 },
35 { 2, -11, 108, 36, -8, 1 },
36 { 0, -9, 93, 50, -6, 0 },
37 { 3, -16, 77, 77, -16, 3 },
38 { 0, -6, 50, 93, -9, 0 },
39 { 1, -8, 36, 108, -11, 2 },
40 { 0, -1, 12, 123, -6, 0 }
41 };
42
hal_vp8d_vdpu2_init(void * hal,MppHalCfg * cfg)43 MPP_RET hal_vp8d_vdpu2_init(void *hal, MppHalCfg *cfg)
44 {
45 MPP_RET ret = MPP_OK;
46 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
47
48 FUN_T("FUN_IN");
49
50 mpp_env_get_u32("vp8h_debug", &vp8h_debug, 0);
51
52 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU2);
53 if (ret) {
54 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
55 goto ERR_RET;
56 }
57
58 if (NULL == ctx->regs) {
59 ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t));
60 if (NULL == ctx->regs) {
61 mpp_err("hal_vp8 reg alloc failed\n");
62 ret = MPP_ERR_NOMEM;
63 goto ERR_RET;
64 }
65 }
66
67 if (NULL == ctx->group) {
68 ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
69 if (ret) {
70 mpp_err("hal_vp8 mpp_buffer_group_get failed\n");
71 goto ERR_RET;
72 }
73 }
74
75 ret = mpp_buffer_get(ctx->group, &ctx->probe_table, VP8D_PROB_TABLE_SIZE);
76 if (ret) {
77 mpp_err("hal_vp8 probe_table get buffer failed\n");
78 goto ERR_RET;
79 }
80
81 ret = mpp_buffer_get(ctx->group, &ctx->seg_map, VP8D_MAX_SEGMAP_SIZE);
82 if (ret) {
83 mpp_err("hal_vp8 seg_map get buffer failed\n");
84 goto ERR_RET;
85 }
86
87 //configure
88 ctx->packet_slots = cfg->packet_slots;
89 ctx->frame_slots = cfg->frame_slots;
90 cfg->dev = ctx->dev;
91
92 FUN_T("FUN_OUT");
93 return ret;
94 ERR_RET:
95 if (ctx->dev) {
96 mpp_dev_deinit(ctx->dev);
97 ctx->dev = NULL;
98 }
99
100 if (ctx->regs) {
101 mpp_free(ctx->regs);
102 ctx->regs = NULL;
103 }
104
105 if (ctx->probe_table) {
106 mpp_buffer_put(ctx->probe_table);
107 ctx->probe_table = NULL;
108 }
109
110 if (ctx->seg_map) {
111 mpp_buffer_group_put(ctx->seg_map);
112 ctx->seg_map = NULL;
113 }
114
115 if (ctx->group) {
116 mpp_buffer_put(ctx->group);
117 ctx->group = NULL;
118 }
119 FUN_T("FUN_OUT");
120 return ret;
121 }
122
hal_vp8d_vdpu2_deinit(void * hal)123 MPP_RET hal_vp8d_vdpu2_deinit(void *hal)
124 {
125 MPP_RET ret = MPP_OK;
126 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
127
128 FUN_T("FUN_IN");
129
130 if (ctx->dev) {
131 mpp_dev_deinit(ctx->dev);
132 ctx->dev = NULL;
133 }
134
135 if (ctx->probe_table) {
136 ret = mpp_buffer_put(ctx->probe_table);
137 if (ret) {
138 mpp_err("hal_vp8 probe table put buffer failed\n");
139 }
140 }
141
142 if (ctx->seg_map) {
143 ret = mpp_buffer_put(ctx->seg_map);
144 if (ret) {
145 mpp_err("hal_vp8 seg map put buffer failed\n");
146 }
147 }
148
149 if (ctx->group) {
150 ret = mpp_buffer_group_put(ctx->group);
151 if (ret) {
152 mpp_err("hal_vp8 group free buffer failed\n");
153 }
154 }
155
156 if (ctx->regs) {
157 mpp_free(ctx->regs);
158 ctx->regs = NULL;
159 }
160
161 FUN_T("FUN_OUT");
162 return ret;
163 }
164
hal_vp8_init_hwcfg(VP8DHalContext_t * ctx)165 static MPP_RET hal_vp8_init_hwcfg(VP8DHalContext_t *ctx)
166 {
167
168 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs;
169
170 FUN_T("FUN_IN");
171 memset(reg, 0, sizeof(VP8DRegSet_t));
172 reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0;
173 reg->reg50_dec_ctrl.sw_dec_scmd_dis = 0;
174 reg->reg50_dec_ctrl.sw_dec_adv_pre_dis = 0;
175 reg->reg50_dec_ctrl.sw_dec_latency = 0;
176
177 reg->reg53_dec_mode = DEC_MODE_VP8;
178
179 reg->reg54_endian.sw_dec_in_endian = 1;
180 reg->reg54_endian.sw_dec_out_endian = 1;
181 reg->reg54_endian.sw_dec_inswap32_e = 1;
182 reg->reg54_endian.sw_dec_outswap32_e = 1;
183 reg->reg54_endian.sw_dec_strswap32_e = 1;
184 reg->reg54_endian.sw_dec_strendian_e = 1;
185
186 reg->reg55_Interrupt.sw_dec_irq = 0;
187
188 reg->reg56_axi_ctrl.sw_dec_axi_rn_id = 0;
189 reg->reg56_axi_ctrl.sw_dec_axi_wr_id = 0;
190
191 reg->reg56_axi_ctrl.sw_dec_data_disc_e = 0;
192 reg->reg56_axi_ctrl.sw_dec_max_burst = 16;
193 reg->reg57_enable_ctrl.sw_dec_timeout_e = 1;
194 reg->reg57_enable_ctrl.sw_dec_clk_gate_e = 1;
195 reg->reg57_enable_ctrl.sw_dec_out_dis = 0;
196
197 reg->reg149_segment_map_base = mpp_buffer_get_fd(ctx->seg_map);
198 reg->reg61_qtable_base = mpp_buffer_get_fd(ctx->probe_table);
199
200 FUN_T("FUN_OUT");
201 return MPP_OK;
202 }
203
hal_vp8d_pre_filter_tap_set(VP8DHalContext_t * ctx)204 static MPP_RET hal_vp8d_pre_filter_tap_set(VP8DHalContext_t *ctx)
205 {
206 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
207
208 FUN_T("FUN_IN");
209 regs->reg59.sw_pred_bc_tap_0_0 = mcFilter[0][1];
210 regs->reg59.sw_pred_bc_tap_0_1 = mcFilter[0][2];
211 regs->reg59.sw_pred_bc_tap_0_2 = mcFilter[0][3];
212 regs->reg153.sw_pred_bc_tap_0_3 = mcFilter[0][4];
213 regs->reg153.sw_pred_bc_tap_1_0 = mcFilter[1][1];
214 regs->reg153.sw_pred_bc_tap_1_1 = mcFilter[1][2];
215 regs->reg154.sw_pred_bc_tap_1_2 = mcFilter[1][3];
216 regs->reg154.sw_pred_bc_tap_1_3 = mcFilter[1][4];
217 regs->reg154.sw_pred_bc_tap_2_0 = mcFilter[2][1];
218 regs->reg155.sw_pred_bc_tap_2_1 = mcFilter[2][2];
219 regs->reg155.sw_pred_bc_tap_2_2 = mcFilter[2][3];
220 regs->reg155.sw_pred_bc_tap_2_3 = mcFilter[2][4];
221
222 regs->reg156.sw_pred_bc_tap_3_0 = mcFilter[3][1];
223 regs->reg156.sw_pred_bc_tap_3_1 = mcFilter[3][2];
224 regs->reg156.sw_pred_bc_tap_3_2 = mcFilter[3][3];
225 regs->reg157.sw_pred_bc_tap_3_3 = mcFilter[3][4];
226 regs->reg157.sw_pred_bc_tap_4_0 = mcFilter[4][1];
227 regs->reg157.sw_pred_bc_tap_4_1 = mcFilter[4][2];
228 regs->reg158.sw_pred_bc_tap_4_2 = mcFilter[4][3];
229 regs->reg158.sw_pred_bc_tap_4_3 = mcFilter[4][4];
230 regs->reg158.sw_pred_bc_tap_5_0 = mcFilter[5][1];
231
232 regs->reg125.sw_pred_bc_tap_5_1 = mcFilter[5][2];
233
234 regs->reg125.sw_pred_bc_tap_5_2 = mcFilter[5][3];
235
236 regs->reg125.sw_pred_bc_tap_5_3 = mcFilter[5][4];
237 regs->reg126.sw_pred_bc_tap_6_0 = mcFilter[6][1];
238 regs->reg126.sw_pred_bc_tap_6_1 = mcFilter[6][2];
239 regs->reg126.sw_pred_bc_tap_6_2 = mcFilter[6][3];
240 regs->reg127.sw_pred_bc_tap_6_3 = mcFilter[6][4];
241 regs->reg127.sw_pred_bc_tap_7_0 = mcFilter[7][1];
242 regs->reg127.sw_pred_bc_tap_7_1 = mcFilter[7][2];
243 regs->reg128.sw_pred_bc_tap_7_2 = mcFilter[7][3];
244 regs->reg128.sw_pred_bc_tap_7_3 = mcFilter[7][4];
245
246 regs->reg128.sw_pred_tap_2_M1 = mcFilter[2][0];
247 regs->reg128.sw_pred_tap_2_4 = mcFilter[2][5];
248 regs->reg128.sw_pred_tap_4_M1 = mcFilter[4][0];
249 regs->reg128.sw_pred_tap_4_4 = mcFilter[4][5];
250 regs->reg128.sw_pred_tap_6_M1 = mcFilter[6][0];
251 regs->reg128.sw_pred_tap_6_4 = mcFilter[6][5];
252
253 FUN_T("FUN_OUT");
254 return MPP_OK;
255 }
256
hal_vp8d_dct_partition_cfg(VP8DHalContext_t * ctx,HalTaskInfo * task)257 static MPP_RET hal_vp8d_dct_partition_cfg(VP8DHalContext_t *ctx,
258 HalTaskInfo *task)
259 {
260 RK_U32 i = 0, len = 0, len1 = 0;
261 RK_U32 extraBytesPacked = 0;
262 RK_U32 addr = 0, byte_offset = 0;
263 RK_U32 fd = 0;
264 MppBuffer streambuf = NULL;
265 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
266 DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
267
268 FUN_T("FUN_IN");
269
270 mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
271 fd = mpp_buffer_get_fd(streambuf);
272 regs->reg145_bitpl_ctrl_base = fd;
273 if (pic_param->stream_start_offset) {
274 MppDevRegOffsetCfg trans_cfg;
275
276 trans_cfg.reg_idx = 145;
277 trans_cfg.offset = pic_param->stream_start_offset;
278 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
279 }
280
281 regs->reg122.sw_strm1_start_bit = pic_param->stream_start_bit;
282
283 /* calculate dct partition length here instead */
284 if (pic_param->decMode == VP8HWD_VP8 && !pic_param->frame_type)
285 extraBytesPacked += 7;
286 len = pic_param->streamEndPos + pic_param->frameTagSize
287 - pic_param->dctPartitionOffsets[0];
288 len += ((1 << pic_param->log2_nbr_of_dct_partitions) - 1) * 3;
289 len1 = extraBytesPacked + pic_param->dctPartitionOffsets[0];
290 len += (len1 & 0x7);
291 regs->reg51_stream_info.sw_stream_len = len;
292
293 len = pic_param->offsetToDctParts + pic_param->frameTagSize -
294 (pic_param->stream_start_offset - extraBytesPacked);
295 len++;
296
297 regs->reg124.sw_stream1_len = len;
298 regs->reg124.sw_coeffs_part_am =
299 (1 << pic_param->log2_nbr_of_dct_partitions) - 1;
300 for (i = 0; i < (RK_U32)(1 << pic_param->log2_nbr_of_dct_partitions); i++) {
301 MppDevRegOffsetCfg trans_cfg;
302
303 addr = extraBytesPacked + pic_param->dctPartitionOffsets[i];
304 byte_offset = addr & 0x7;
305 addr = addr & 0xFFFFFFF8;
306
307 if (i == 0) {
308 regs->reg64_input_stream_base = fd;
309 if (addr) {
310 trans_cfg.reg_idx = 64;
311 trans_cfg.offset = addr;
312 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
313 }
314 } else if (i <= 5) {
315 regs->reg_dct_strm_base[i - 1] = fd;
316 if (addr) {
317 trans_cfg.reg_idx = 139 + i;
318 trans_cfg.offset = addr;
319 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
320 }
321 } else {
322 regs->reg_dct_strm1_base[i - 6] = fd;
323 if (addr) {
324 trans_cfg.reg_idx = 140 + i;
325 trans_cfg.offset = addr;
326 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
327 }
328 }
329
330 switch (i) {
331 case 0:
332 regs->reg122.sw_strm_start_bit = byte_offset * 8;
333 break;
334 case 1:
335 regs->reg121.sw_dct1_start_bit = byte_offset * 8;
336 break;
337 case 2:
338 regs->reg121.sw_dct2_start_bit = byte_offset * 8;
339 break;
340 case 3:
341 regs->reg150.sw_dct_start_bit_3 = byte_offset * 8;
342 break;
343 case 4:
344 regs->reg150.sw_dct_start_bit_4 = byte_offset * 8;
345 break;
346 case 5:
347 regs->reg150.sw_dct_start_bit_5 = byte_offset * 8;
348 break;
349 case 6:
350 regs->reg150.sw_dct_start_bit_6 = byte_offset * 8;
351 break;
352 case 7:
353 regs->reg150.sw_dct_start_bit_7 = byte_offset * 8;
354 break;
355 default:
356 break;
357 }
358 }
359
360 FUN_T("FUN_OUT");
361 return MPP_OK;
362 }
363
hal_vp8hw_asic_probe_update(DXVA_PicParams_VP8 * p,RK_U8 * probTbl)364 static void hal_vp8hw_asic_probe_update(DXVA_PicParams_VP8 *p, RK_U8 *probTbl)
365 {
366 RK_U8 *dst;
367 RK_U32 i, j, k;
368
369 FUN_T("FUN_IN");
370 /* first probs */
371 dst = probTbl;
372
373 dst[0] = p->probe_skip_false;
374 dst[1] = p->prob_intra;
375 dst[2] = p->prob_last;
376 dst[3] = p->prob_golden;
377 dst[4] = p->stVP8Segments.mb_segment_tree_probs[0];
378 dst[5] = p->stVP8Segments.mb_segment_tree_probs[1];
379 dst[6] = p->stVP8Segments.mb_segment_tree_probs[2];
380 dst[7] = 0; /*unused*/
381
382 dst += 8;
383 dst[0] = p->intra_16x16_prob[0];
384 dst[1] = p->intra_16x16_prob[1];
385 dst[2] = p->intra_16x16_prob[2];
386 dst[3] = p->intra_16x16_prob[3];
387 dst[4] = p->intra_chroma_prob[0];
388 dst[5] = p->intra_chroma_prob[1];
389 dst[6] = p->intra_chroma_prob[2];
390 dst[7] = 0; /*unused*/
391
392 /* mv probs */
393 dst += 8;
394 dst[0] = p->vp8_mv_update_probs[0][0]; /* is short */
395 dst[1] = p->vp8_mv_update_probs[1][0];
396 dst[2] = p->vp8_mv_update_probs[0][1]; /* sign */
397 dst[3] = p->vp8_mv_update_probs[1][1];
398 dst[4] = p->vp8_mv_update_probs[0][8 + 9];
399 dst[5] = p->vp8_mv_update_probs[0][9 + 9];
400 dst[6] = p->vp8_mv_update_probs[1][8 + 9];
401 dst[7] = p->vp8_mv_update_probs[1][9 + 9];
402 dst += 8;
403 for ( i = 0 ; i < 2 ; ++i ) {
404 for ( j = 0 ; j < 8 ; j += 4 ) {
405 dst[0] = p->vp8_mv_update_probs[i][j + 9 + 0];
406 dst[1] = p->vp8_mv_update_probs[i][j + 9 + 1];
407 dst[2] = p->vp8_mv_update_probs[i][j + 9 + 2];
408 dst[3] = p->vp8_mv_update_probs[i][j + 9 + 3];
409 dst += 4;
410 }
411 }
412 for ( i = 0 ; i < 2 ; ++i ) {
413 dst[0] = p->vp8_mv_update_probs[i][0 + 2];
414 dst[1] = p->vp8_mv_update_probs[i][1 + 2];
415 dst[2] = p->vp8_mv_update_probs[i][2 + 2];
416 dst[3] = p->vp8_mv_update_probs[i][3 + 2];
417 dst[4] = p->vp8_mv_update_probs[i][4 + 2];
418 dst[5] = p->vp8_mv_update_probs[i][5 + 2];
419 dst[6] = p->vp8_mv_update_probs[i][6 + 2];
420 dst[7] = 0; /*unused*/
421 dst += 8;
422 }
423
424 /* coeff probs (header part) */
425 dst = (RK_U8*)probTbl;
426 dst += (8 * 7);
427 for ( i = 0 ; i < 4 ; ++i ) {
428 for ( j = 0 ; j < 8 ; ++j ) {
429 for ( k = 0 ; k < 3 ; ++k ) {
430 dst[0] = p->vp8_coef_update_probs[i][j][k][0];
431 dst[1] = p->vp8_coef_update_probs[i][j][k][1];
432 dst[2] = p->vp8_coef_update_probs[i][j][k][2];
433 dst[3] = p->vp8_coef_update_probs[i][j][k][3];
434 dst += 4;
435 }
436 }
437 }
438
439 /* coeff probs (footer part) */
440 dst = (RK_U8*)probTbl;
441 dst += (8 * 55);
442 for ( i = 0 ; i < 4 ; ++i ) {
443 for ( j = 0 ; j < 8 ; ++j ) {
444 for ( k = 0 ; k < 3 ; ++k ) {
445 dst[0] = p->vp8_coef_update_probs[i][j][k][4];
446 dst[1] = p->vp8_coef_update_probs[i][j][k][5];
447 dst[2] = p->vp8_coef_update_probs[i][j][k][6];
448 dst[3] = p->vp8_coef_update_probs[i][j][k][7];
449 dst[4] = p->vp8_coef_update_probs[i][j][k][8];
450 dst[5] = p->vp8_coef_update_probs[i][j][k][9];
451 dst[6] = p->vp8_coef_update_probs[i][j][k][10];
452 dst[7] = 0; /*unused*/
453 dst += 8;
454 }
455 }
456 }
457 FUN_T("FUN_OUT");
458 return ;
459 }
460
hal_vp8d_vdpu2_gen_regs(void * hal,HalTaskInfo * task)461 MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
462 {
463 MPP_RET ret = MPP_OK;
464 RK_U32 mb_width = 0, mb_height = 0;
465 MppBuffer framebuf = NULL;
466 RK_U8 *segmap_ptr = NULL;
467 RK_U8 *probe_ptr = NULL;
468 MppDevRegOffsetCfg trans_cfg;
469 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
470 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
471 DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
472
473 FUN_T("FUN_IN");
474
475 hal_vp8_init_hwcfg(ctx);
476 mb_width = (pic_param->width + 15) >> 4;
477 mb_height = (pic_param->height + 15) >> 4;
478 // mpp_log("mb_width = %d mb_height = %d", mb_width, mb_height);
479 regs->reg120.sw_pic_mb_width = mb_width & 0x1FF;
480 regs->reg120.sw_pic_mb_hight_p = mb_height & 0xFF;
481 regs->reg120.sw_pic_mb_w_ext = mb_width >> 9;
482 regs->reg120.sw_pic_mb_h_ext = mb_height >> 8;
483
484 if (!pic_param->frame_type) {
485 segmap_ptr = mpp_buffer_get_ptr(ctx->seg_map);
486 if (NULL != segmap_ptr) {
487 memset(segmap_ptr, 0, VP8D_MAX_SEGMAP_SIZE);
488 }
489 }
490
491 probe_ptr = mpp_buffer_get_ptr(ctx->probe_table);
492 if (NULL != probe_ptr) {
493 hal_vp8hw_asic_probe_update(pic_param, probe_ptr);
494 }
495 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->CurrPic.Index7Bits, SLOT_BUFFER, &framebuf);
496 regs->reg63_cur_pic_base = mpp_buffer_get_fd(framebuf);
497 if (!pic_param->frame_type) { //key frame
498
499 regs->reg131_ref0_base = regs->reg63_cur_pic_base;
500
501 trans_cfg.reg_idx = 131;
502 trans_cfg.offset = mb_width * mb_height;
503 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
504 } else if (pic_param->lst_fb_idx.Index7Bits < 0x7f) { //config ref0 base
505 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->lst_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
506 regs->reg131_ref0_base = mpp_buffer_get_fd(framebuf);
507 } else {
508 regs->reg131_ref0_base = regs->reg63_cur_pic_base;
509 }
510
511 /* golden reference */
512 if (pic_param->gld_fb_idx.Index7Bits < 0x7f) {
513 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->gld_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
514 regs->reg136_golden_ref_base = mpp_buffer_get_fd(framebuf);
515 } else {
516 regs->reg136_golden_ref_base = regs->reg63_cur_pic_base;
517 }
518
519 regs->reg136_golden_ref_base = regs->reg136_golden_ref_base;
520 if (pic_param->ref_frame_sign_bias_golden) {
521 trans_cfg.reg_idx = 136;
522 trans_cfg.offset = pic_param->ref_frame_sign_bias_golden;
523 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
524 }
525
526 /* alternate reference */
527 if (pic_param->alt_fb_idx.Index7Bits < 0x7f) {
528 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->alt_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
529 regs->reg137.alternate_ref_base = mpp_buffer_get_fd(framebuf);
530 } else {
531 regs->reg137.alternate_ref_base = regs->reg63_cur_pic_base;
532 }
533
534 regs->reg137.alternate_ref_base = regs->reg137.alternate_ref_base;
535 if (pic_param->ref_frame_sign_bias_altref) {
536 trans_cfg.reg_idx = 137;
537 trans_cfg.offset = pic_param->ref_frame_sign_bias_altref;
538 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
539 }
540
541 regs->reg149_segment_map_base = regs->reg149_segment_map_base;
542 if (pic_param->stVP8Segments.segmentation_enabled + (pic_param->stVP8Segments.update_mb_segmentation_map << 1)) {
543 trans_cfg.reg_idx = 149;
544 trans_cfg.offset = pic_param->stVP8Segments.segmentation_enabled + (pic_param->stVP8Segments.update_mb_segmentation_map << 1);
545 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
546 }
547
548 regs->reg57_enable_ctrl.sw_pic_inter_e = pic_param->frame_type;
549 regs->reg50_dec_ctrl.sw_skip_mode = !pic_param->mb_no_coeff_skip;
550
551 if (!pic_param->stVP8Segments.segmentation_enabled) {
552 regs->reg129.sw_filt_level_0 = pic_param->filter_level;
553 } else if (pic_param->stVP8Segments.update_mb_segmentation_data) {
554 regs->reg129.sw_filt_level_0 = pic_param->stVP8Segments.segment_feature_data[1][0];
555 regs->reg129.sw_filt_level_1 = pic_param->stVP8Segments.segment_feature_data[1][1];
556 regs->reg129.sw_filt_level_2 = pic_param->stVP8Segments.segment_feature_data[1][2];
557 regs->reg129.sw_filt_level_3 = pic_param->stVP8Segments.segment_feature_data[1][3];
558 } else {
559 regs->reg129.sw_filt_level_0 = CLIP3(0, 63, (RK_S32)pic_param->filter_level + pic_param->stVP8Segments.segment_feature_data[1][0]);
560 regs->reg129.sw_filt_level_1 = CLIP3(0, 63, (RK_S32)pic_param->filter_level + pic_param->stVP8Segments.segment_feature_data[1][1]);
561 regs->reg129.sw_filt_level_2 = CLIP3(0, 63, (RK_S32)pic_param->filter_level + pic_param->stVP8Segments.segment_feature_data[1][2]);
562 regs->reg129.sw_filt_level_3 = CLIP3(0, 63, (RK_S32)pic_param->filter_level + pic_param->stVP8Segments.segment_feature_data[1][3]);
563 }
564
565 regs->reg132.sw_filt_type = pic_param->filter_type;
566 regs->reg132.sw_filt_sharpness = pic_param->sharpness;
567
568 if (pic_param->filter_level == 0) {
569 regs->reg50_dec_ctrl.sw_filtering_dis = 1;
570 }
571
572 if (pic_param->version != 3) {
573 regs->reg121.sw_romain_mv = 1;
574 }
575
576 if (pic_param->decMode == VP8HWD_VP8 && (pic_param->version & 0x3)) {
577 regs->reg121.sw_eable_bilinear = 1;
578 }
579 regs->reg122.sw_boolean_value = pic_param->bool_value;
580 regs->reg122.sw_boolean_range = pic_param->bool_range;
581
582 {
583 if (!pic_param->stVP8Segments.segmentation_enabled)
584 regs->reg130.sw_quant_0 = pic_param->y1ac_delta_q;
585 else if (pic_param->stVP8Segments.update_mb_segmentation_data) { /* absolute mode */
586 regs->reg130.sw_quant_0 = pic_param->stVP8Segments.segment_feature_data[0][0];
587 regs->reg130.sw_quant_1 = pic_param->stVP8Segments.segment_feature_data[0][1];
588 regs->reg151.sw_quant_2 = pic_param->stVP8Segments.segment_feature_data[0][2];
589 regs->reg151.sw_quant_3 = pic_param->stVP8Segments.segment_feature_data[0][3];
590 } else { /* delta mode */
591 regs->reg130.sw_quant_0 = CLIP3(0, 127, pic_param->y1ac_delta_q + pic_param->stVP8Segments.segment_feature_data[0][0]);
592 regs->reg130.sw_quant_1 = CLIP3(0, 127, pic_param->y1ac_delta_q + pic_param->stVP8Segments.segment_feature_data[0][1]);
593 regs->reg151.sw_quant_2 = CLIP3(0, 127, pic_param->y1ac_delta_q + pic_param->stVP8Segments.segment_feature_data[0][2]);
594 regs->reg151.sw_quant_3 = CLIP3(0, 127, pic_param->y1ac_delta_q + pic_param->stVP8Segments.segment_feature_data[0][3]);
595 }
596
597 regs->reg130.sw_quant_delta_0 = pic_param->y1dc_delta_q;
598 regs->reg130.sw_quant_delta_1 = pic_param->y2dc_delta_q;
599 regs->reg151.sw_quant_delta_2 = pic_param->y2ac_delta_q;
600 regs->reg151.sw_quant_delta_3 = pic_param->uvdc_delta_q;
601 regs->reg152.sw_quant_delta_4 = pic_param->uvac_delta_q;
602
603 if (pic_param->mode_ref_lf_delta_enabled) {
604 regs->reg133.sw_filt_ref_adj_0 = pic_param->ref_lf_deltas[0];
605 regs->reg133.sw_filt_ref_adj_1 = pic_param->ref_lf_deltas[1];
606 regs->reg133.sw_filt_ref_adj_2 = pic_param->ref_lf_deltas[2];
607 regs->reg133.sw_filt_ref_adj_3 = pic_param->ref_lf_deltas[3];
608 regs->reg132.sw_filt_mb_adj_0 = pic_param->mode_lf_deltas[0];
609 regs->reg132.sw_filt_mb_adj_1 = pic_param->mode_lf_deltas[1];
610 regs->reg132.sw_filt_mb_adj_2 = pic_param->mode_lf_deltas[2];
611 regs->reg132.sw_filt_mb_adj_3 = pic_param->mode_lf_deltas[3];
612 }
613
614 }
615
616 if ((pic_param->version & 0x3) == 0)
617 hal_vp8d_pre_filter_tap_set(ctx);
618
619 hal_vp8d_dct_partition_cfg(ctx, task);
620 regs->reg57_enable_ctrl.sw_dec_e = 1;
621
622 FUN_T("FUN_OUT");
623 return ret;
624 }
625
hal_vp8d_vdpu2_start(void * hal,HalTaskInfo * task)626 MPP_RET hal_vp8d_vdpu2_start(void *hal, HalTaskInfo *task)
627 {
628 MPP_RET ret = MPP_OK;
629 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
630 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
631
632 FUN_T("FUN_IN");
633
634 if (vp8h_debug & VP8H_DBG_REG) {
635 RK_U32 *p = ctx->regs;
636 RK_U32 i = 0;
637
638 for (i = 0; i < VP8D_REG_NUM; i++)
639 mpp_log_f("vp8d: regs[%02d]=%08X\n", i, *p++);
640 }
641
642 do {
643 MppDevRegWrCfg wr_cfg;
644 MppDevRegRdCfg rd_cfg;
645 RK_U32 reg_size = sizeof(VP8DRegSet_t);
646
647 wr_cfg.reg = regs;
648 wr_cfg.size = reg_size;
649 wr_cfg.offset = 0;
650
651 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
652 if (ret) {
653 mpp_err_f("set register write failed %d\n", ret);
654 break;
655 }
656
657 rd_cfg.reg = regs;
658 rd_cfg.size = reg_size;
659 rd_cfg.offset = 0;
660
661 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
662 if (ret) {
663 mpp_err_f("set register read failed %d\n", ret);
664 break;
665 }
666
667 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
668 if (ret) {
669 mpp_err_f("send cmd failed %d\n", ret);
670 break;
671 }
672 } while (0);
673
674 FUN_T("FUN_OUT");
675
676 (void)task;
677 return ret;
678 }
679
hal_vp8d_vdpu2_wait(void * hal,HalTaskInfo * task)680 MPP_RET hal_vp8d_vdpu2_wait(void *hal, HalTaskInfo *task)
681 {
682 MPP_RET ret = MPP_OK;
683 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
684
685 FUN_T("FUN_IN");
686
687 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
688 if (ret)
689 mpp_err_f("poll cmd failed %d\n", ret);
690
691 (void)task;
692 FUN_T("FUN_OUT");
693 return ret;
694 }
695