1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_vp8d_vdpu1"
18
19 #include <string.h>
20
21 #include "mpp_env.h"
22 #include "mpp_mem.h"
23 #include "mpp_debug.h"
24
25 #include "hal_vp8d_vdpu1.h"
26 #include "hal_vp8d_vdpu1_reg.h"
27
28 static RK_U32 vp8h_debug;
29
30 #define CLIP3(l, h, v) ((v) < (l) ? (l) : ((v) > (h) ? (h) : (v)))
31
32 static const RK_U32 mcFilter[8][6] = {
33 { 0, 0, 128, 0, 0, 0 },
34 { 0, -6, 123, 12, -1, 0 },
35 { 2, -11, 108, 36, -8, 1 },
36 { 0, -9, 93, 50, -6, 0 },
37 { 3, -16, 77, 77, -16, 3 },
38 { 0, -6, 50, 93, -9, 0 },
39 { 1, -8, 36, 108, -11, 2 },
40 { 0, -1, 12, 123, -6, 0 }
41 };
42
hal_vp8d_vdpu1_init(void * hal,MppHalCfg * cfg)43 MPP_RET hal_vp8d_vdpu1_init(void *hal, MppHalCfg *cfg)
44 {
45 MPP_RET ret = MPP_OK;
46 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
47
48 FUN_T("enter\n");
49
50 mpp_env_get_u32("vp8h_debug", &vp8h_debug, 0);
51
52 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1);
53 if (ret) {
54 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
55 goto ERR_RET;
56 }
57 if (NULL == ctx->regs) {
58 ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t));
59 if (NULL == ctx->regs) {
60 mpp_err("hal_vp8 reg alloc failed\n");
61 ret = MPP_ERR_MALLOC;
62 goto ERR_RET;
63 }
64 }
65
66 if (NULL == ctx->group) {
67 ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
68 if (ret) {
69 mpp_err("hal_vp8 mpp_buffer_group_get failed\n");
70 goto ERR_RET;
71 }
72 }
73
74 ret = mpp_buffer_get(ctx->group, &ctx->probe_table, VP8D_PROB_TABLE_SIZE);
75 if (ret) {
76 mpp_err("hal_vp8 probe_table get buffer failed\n");
77 goto ERR_RET;
78 }
79
80 ret = mpp_buffer_get(ctx->group, &ctx->seg_map, VP8D_MAX_SEGMAP_SIZE);
81 if (ret) {
82 mpp_err("hal_vp8 seg_map get buffer failed\n");
83 goto ERR_RET;
84 }
85 //configure
86 ctx->packet_slots = cfg->packet_slots;
87 ctx->frame_slots = cfg->frame_slots;
88 cfg->dev = ctx->dev;
89
90 FUN_T("leave\n");
91 return ret;
92 ERR_RET:
93 if (ctx->dev) {
94 mpp_dev_deinit(ctx->dev);
95 ctx->dev = NULL;
96 }
97
98 if (ctx->regs) {
99 mpp_free(ctx->regs);
100 ctx->regs = NULL;
101 }
102
103 if (ctx->probe_table) {
104 mpp_buffer_put(ctx->probe_table);
105 ctx->probe_table = NULL;
106 }
107
108 if (ctx->seg_map) {
109 mpp_buffer_group_put(ctx->seg_map);
110 ctx->seg_map = NULL;
111 }
112
113 if (ctx->group) {
114 mpp_buffer_put(ctx->group);
115 ctx->group = NULL;
116 }
117 FUN_T("leave\n");
118 return ret;
119 }
120
hal_vp8d_vdpu1_deinit(void * hal)121 MPP_RET hal_vp8d_vdpu1_deinit(void *hal)
122 {
123 MPP_RET ret = MPP_OK;
124 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
125
126 FUN_T("enter\n");
127
128 if (ctx->dev) {
129 mpp_dev_deinit(ctx->dev);
130 ctx->dev = NULL;
131 }
132
133 if (ctx->probe_table) {
134 ret = mpp_buffer_put(ctx->probe_table);
135 if (ret) {
136 mpp_err("hal_vp8 probe table put buffer failed\n");
137 }
138 }
139
140 if (ctx->seg_map) {
141 ret = mpp_buffer_put(ctx->seg_map);
142 if (ret) {
143 mpp_err("hal_vp8 seg map put buffer failed\n");
144 }
145 }
146
147 if (ctx->group) {
148 ret = mpp_buffer_group_put(ctx->group);
149 if (ret) {
150 mpp_err("hal_vp8 group free buffer failed\n");
151 }
152 }
153
154 if (ctx->regs) {
155 mpp_free(ctx->regs);
156 ctx->regs = NULL;
157 }
158
159 FUN_T("leave\n");
160 return ret;
161 }
162
hal_vp8_init_hwcfg(VP8DHalContext_t * ctx)163 static MPP_RET hal_vp8_init_hwcfg(VP8DHalContext_t *ctx)
164 {
165
166 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs;
167
168 FUN_T("enter\n");
169 memset(reg, 0, sizeof(VP8DRegSet_t));
170
171 reg->reg1_interrupt.sw_dec_e = 1;
172
173 reg->reg2_dec_ctrl.sw_dec_out_tiled_e = 0;
174 reg->reg2_dec_ctrl.sw_dec_scmd_dis = 0;
175 reg->reg2_dec_ctrl.sw_dec_adv_pre_dis = 0;
176 reg->reg2_dec_ctrl.sw_dec_latency = 0;
177
178 reg->reg2_dec_ctrl.sw_dec_in_endian = 1;
179 reg->reg2_dec_ctrl.sw_dec_out_endian = 1;
180 reg->reg2_dec_ctrl.sw_dec_inswap32_e = 1;
181 reg->reg2_dec_ctrl.sw_dec_outswap32_e = 1;
182 reg->reg2_dec_ctrl.sw_dec_strswap32_e = 1;
183 reg->reg2_dec_ctrl.sw_dec_strendian_e = 1;
184 reg->reg2_dec_ctrl.sw_dec_axi_rn_id = 0;
185
186 reg->reg2_dec_ctrl.sw_dec_data_disc_e = 0;
187 reg->reg2_dec_ctrl.sw_dec_max_burst = 16;
188 reg->reg2_dec_ctrl.sw_dec_timeout_e = 1;
189 reg->reg2_dec_ctrl.sw_dec_clk_gate_e = 1;
190
191 reg->reg3.sw_dec_out_dis = 0;
192 reg->reg3.sw_dec_axi_wr_id = 0;
193 reg->reg3.sw_dec_mode = DEC_MODE_VP8;
194
195 reg->reg1_interrupt.sw_dec_irq = 0;
196
197 reg->reg10_segment_map_base = mpp_buffer_get_fd(ctx->seg_map);
198 reg->reg40_qtable_base = mpp_buffer_get_fd(ctx->probe_table);
199
200 FUN_T("leave\n");
201 return MPP_OK;
202 }
203
hal_vp8d_pre_filter_tap_set(VP8DHalContext_t * ctx)204 static MPP_RET hal_vp8d_pre_filter_tap_set(VP8DHalContext_t *ctx)
205 {
206 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
207
208 FUN_T("enter\n");
209 regs->reg49.sw_pred_bc_tap_0_0 = mcFilter[0][1];
210 regs->reg49.sw_pred_bc_tap_0_1 = mcFilter[0][2];
211 regs->reg49.sw_pred_bc_tap_0_2 = mcFilter[0][3];
212 regs->reg34.sw_pred_bc_tap_0_3 = mcFilter[0][4];
213 regs->reg34.sw_pred_bc_tap_1_0 = mcFilter[1][1];
214 regs->reg34.sw_pred_bc_tap_1_1 = mcFilter[1][2];
215 regs->reg35.sw_pred_bc_tap_1_2 = mcFilter[1][3];
216 regs->reg35.sw_pred_bc_tap_1_3 = mcFilter[1][4];
217 regs->reg35.sw_pred_bc_tap_2_0 = mcFilter[2][1];
218 regs->reg36.sw_pred_bc_tap_2_1 = mcFilter[2][2];
219 regs->reg36.sw_pred_bc_tap_2_2 = mcFilter[2][3];
220 regs->reg36.sw_pred_bc_tap_2_3 = mcFilter[2][4];
221
222 regs->reg37.sw_pred_bc_tap_3_0 = mcFilter[3][1];
223 regs->reg37.sw_pred_bc_tap_3_1 = mcFilter[3][2];
224 regs->reg37.sw_pred_bc_tap_3_2 = mcFilter[3][3];
225 regs->reg38.sw_pred_bc_tap_3_3 = mcFilter[3][4];
226 regs->reg38.sw_pred_bc_tap_4_0 = mcFilter[4][1];
227 regs->reg38.sw_pred_bc_tap_4_1 = mcFilter[4][2];
228 regs->reg39.sw_pred_bc_tap_4_2 = mcFilter[4][3];
229 regs->reg39.sw_pred_bc_tap_4_3 = mcFilter[4][4];
230 regs->reg39.sw_pred_bc_tap_5_0 = mcFilter[5][1];
231
232 regs->reg42.sw_pred_bc_tap_5_1 = mcFilter[5][2];
233 regs->reg42.sw_pred_bc_tap_5_2 = mcFilter[5][3];
234 regs->reg42.sw_pred_bc_tap_5_3 = mcFilter[5][4];
235
236 regs->reg43.sw_pred_bc_tap_6_0 = mcFilter[6][1];
237 regs->reg43.sw_pred_bc_tap_6_1 = mcFilter[6][2];
238 regs->reg43.sw_pred_bc_tap_6_2 = mcFilter[6][3];
239
240 regs->reg44.sw_pred_bc_tap_6_3 = mcFilter[6][4];
241 regs->reg44.sw_pred_bc_tap_7_0 = mcFilter[7][1];
242 regs->reg44.sw_pred_bc_tap_7_1 = mcFilter[7][2];
243
244 regs->reg45.sw_pred_bc_tap_7_2 = mcFilter[7][3];
245 regs->reg45.sw_pred_bc_tap_7_3 = mcFilter[7][4];
246
247 regs->reg45.sw_pred_tap_2_M1 = mcFilter[2][0];
248 regs->reg45.sw_pred_tap_2_4 = mcFilter[2][5];
249 regs->reg45.sw_pred_tap_4_M1 = mcFilter[4][0];
250 regs->reg45.sw_pred_tap_4_4 = mcFilter[4][5];
251 regs->reg45.sw_pred_tap_6_M1 = mcFilter[6][0];
252 regs->reg45.sw_pred_tap_6_4 = mcFilter[6][5];
253
254 FUN_T("leave\n");
255 return MPP_OK;
256 }
257
258 static MPP_RET
hal_vp8d_dct_partition_cfg(VP8DHalContext_t * ctx,HalTaskInfo * task)259 hal_vp8d_dct_partition_cfg(VP8DHalContext_t *ctx, HalTaskInfo *task)
260 {
261 RK_U32 i = 0, len = 0, len1 = 0;
262 RK_U32 extraBytesPacked = 0;
263 RK_U32 addr = 0, byte_offset = 0;
264 RK_U32 fd = 0;
265 MppBuffer streambuf = NULL;
266 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
267 DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
268
269
270 FUN_T("enter\n");
271
272 mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input,
273 SLOT_BUFFER, &streambuf);
274 fd = mpp_buffer_get_fd(streambuf);
275 regs->reg27_bitpl_ctrl_base = fd;
276 if (pic_param->stream_start_offset)
277 mpp_dev_set_reg_offset(ctx->dev, 27, pic_param->stream_start_offset);
278 regs->reg5.sw_strm1_start_bit = pic_param->stream_start_bit;
279
280 /* calculate dct partition length here instead */
281 if (pic_param->decMode == VP8HWD_VP8 && !pic_param->frame_type)
282 extraBytesPacked += 7;
283
284 len = pic_param->streamEndPos + pic_param->frameTagSize
285 - pic_param->dctPartitionOffsets[0];
286 len += ((1 << pic_param->log2_nbr_of_dct_partitions) - 1) * 3;
287 len1 = extraBytesPacked + pic_param->dctPartitionOffsets[0];
288 len += (len1 & 0x7);
289 regs->reg6.sw_stream_len = len;
290
291 len = pic_param->offsetToDctParts + pic_param->frameTagSize -
292 (pic_param->stream_start_offset - extraBytesPacked);
293 len++;
294
295 regs->reg9.sw_stream1_len = len;
296 regs->reg9.sw_coeffs_part_am = (1 << pic_param->log2_nbr_of_dct_partitions);
297 regs->reg9.sw_coeffs_part_am--;
298 for (i = 0; i < (RK_U32)(1 << pic_param->log2_nbr_of_dct_partitions); i++) {
299 addr = extraBytesPacked + pic_param->dctPartitionOffsets[i];
300 byte_offset = addr & 0x7;
301 addr = addr & 0xFFFFFFF8;
302
303 if (i == 0) {
304 regs->reg12_input_stream_base = fd;
305 if (addr) {
306 mpp_dev_set_reg_offset(ctx->dev, 12, addr);
307 }
308 } else if (i <= 5) {
309 regs->reg_dct_strm0_base[i - 1] = fd;
310 if (addr) {
311 mpp_dev_set_reg_offset(ctx->dev, 21 + i, addr);
312 }
313 } else {
314 regs->reg_dct_strm1_base[i - 6] = fd;
315 if (addr) {
316 mpp_dev_set_reg_offset(ctx->dev, 22 + i, addr);
317 }
318 }
319
320 switch (i) {
321 case 0:
322 regs->reg5.sw_strm0_start_bit = byte_offset * 8;
323 break;
324 case 1:
325 regs->reg7.sw_dct1_start_bit = byte_offset * 8;
326 break;
327 case 2:
328 regs->reg7.sw_dct2_start_bit = byte_offset * 8;
329 break;
330 case 3:
331 regs->reg11.sw_dct_start_bit_3 = byte_offset * 8;
332 break;
333 case 4:
334 regs->reg11.sw_dct_start_bit_4 = byte_offset * 8;
335 break;
336 case 5:
337 regs->reg11.sw_dct_start_bit_5 = byte_offset * 8;
338 break;
339 case 6:
340 regs->reg11.sw_dct_start_bit_6 = byte_offset * 8;
341 break;
342 case 7:
343 regs->reg11.sw_dct_start_bit_7 = byte_offset * 8;
344 break;
345 default:
346 break;
347 }
348 }
349
350 FUN_T("leave\n");
351 return MPP_OK;
352 }
353
hal_vp8hw_asic_probe_update(DXVA_PicParams_VP8 * p,RK_U8 * probTbl)354 static void hal_vp8hw_asic_probe_update(DXVA_PicParams_VP8 *p, RK_U8 *probTbl)
355 {
356 RK_U8 *dst;
357 RK_U32 i, j, k;
358
359 FUN_T("enter\n");
360 /* first probs */
361 dst = probTbl;
362
363 dst[0] = p->probe_skip_false;
364 dst[1] = p->prob_intra;
365 dst[2] = p->prob_last;
366 dst[3] = p->prob_golden;
367 dst[4] = p->stVP8Segments.mb_segment_tree_probs[0];
368 dst[5] = p->stVP8Segments.mb_segment_tree_probs[1];
369 dst[6] = p->stVP8Segments.mb_segment_tree_probs[2];
370 dst[7] = 0; /*unused*/
371
372 dst += 8;
373 dst[0] = p->intra_16x16_prob[0];
374 dst[1] = p->intra_16x16_prob[1];
375 dst[2] = p->intra_16x16_prob[2];
376 dst[3] = p->intra_16x16_prob[3];
377 dst[4] = p->intra_chroma_prob[0];
378 dst[5] = p->intra_chroma_prob[1];
379 dst[6] = p->intra_chroma_prob[2];
380 dst[7] = 0; /*unused*/
381
382 /* mv probs */
383 dst += 8;
384 dst[0] = p->vp8_mv_update_probs[0][0]; /* is short */
385 dst[1] = p->vp8_mv_update_probs[1][0];
386 dst[2] = p->vp8_mv_update_probs[0][1]; /* sign */
387 dst[3] = p->vp8_mv_update_probs[1][1];
388 dst[4] = p->vp8_mv_update_probs[0][8 + 9];
389 dst[5] = p->vp8_mv_update_probs[0][9 + 9];
390 dst[6] = p->vp8_mv_update_probs[1][8 + 9];
391 dst[7] = p->vp8_mv_update_probs[1][9 + 9];
392 dst += 8;
393 for ( i = 0 ; i < 2 ; ++i ) {
394 for ( j = 0 ; j < 8 ; j += 4 ) {
395 dst[0] = p->vp8_mv_update_probs[i][j + 9 + 0];
396 dst[1] = p->vp8_mv_update_probs[i][j + 9 + 1];
397 dst[2] = p->vp8_mv_update_probs[i][j + 9 + 2];
398 dst[3] = p->vp8_mv_update_probs[i][j + 9 + 3];
399 dst += 4;
400 }
401 }
402 for ( i = 0 ; i < 2 ; ++i ) {
403 dst[0] = p->vp8_mv_update_probs[i][0 + 2];
404 dst[1] = p->vp8_mv_update_probs[i][1 + 2];
405 dst[2] = p->vp8_mv_update_probs[i][2 + 2];
406 dst[3] = p->vp8_mv_update_probs[i][3 + 2];
407 dst[4] = p->vp8_mv_update_probs[i][4 + 2];
408 dst[5] = p->vp8_mv_update_probs[i][5 + 2];
409 dst[6] = p->vp8_mv_update_probs[i][6 + 2];
410 dst[7] = 0; /*unused*/
411 dst += 8;
412 }
413
414 /* coeff probs (header part) */
415 dst = (RK_U8*)probTbl;
416 dst += (8 * 7);
417 for ( i = 0 ; i < 4 ; ++i ) {
418 for ( j = 0 ; j < 8 ; ++j ) {
419 for ( k = 0 ; k < 3 ; ++k ) {
420 dst[0] = p->vp8_coef_update_probs[i][j][k][0];
421 dst[1] = p->vp8_coef_update_probs[i][j][k][1];
422 dst[2] = p->vp8_coef_update_probs[i][j][k][2];
423 dst[3] = p->vp8_coef_update_probs[i][j][k][3];
424 dst += 4;
425 }
426 }
427 }
428
429 /* coeff probs (footer part) */
430 dst = (RK_U8*)probTbl;
431 dst += (8 * 55);
432 for ( i = 0 ; i < 4 ; ++i ) {
433 for ( j = 0 ; j < 8 ; ++j ) {
434 for ( k = 0 ; k < 3 ; ++k ) {
435 dst[0] = p->vp8_coef_update_probs[i][j][k][4];
436 dst[1] = p->vp8_coef_update_probs[i][j][k][5];
437 dst[2] = p->vp8_coef_update_probs[i][j][k][6];
438 dst[3] = p->vp8_coef_update_probs[i][j][k][7];
439 dst[4] = p->vp8_coef_update_probs[i][j][k][8];
440 dst[5] = p->vp8_coef_update_probs[i][j][k][9];
441 dst[6] = p->vp8_coef_update_probs[i][j][k][10];
442 dst[7] = 0; /*unused*/
443 dst += 8;
444 }
445 }
446 }
447 FUN_T("leave\n");
448 return ;
449 }
450
hal_vp8d_vdpu1_gen_regs(void * hal,HalTaskInfo * task)451 MPP_RET hal_vp8d_vdpu1_gen_regs(void* hal, HalTaskInfo *task)
452 {
453 MPP_RET ret = MPP_OK;
454 RK_U32 mb_width = 0, mb_height = 0;
455 MppBuffer framebuf = NULL;
456 RK_U8 *segmap_ptr = NULL;
457 RK_U8 *probe_ptr = NULL;
458 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
459 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
460 DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
461
462 FUN_T("enter\n");
463
464 hal_vp8_init_hwcfg(ctx);
465 mb_width = (pic_param->width + 15) >> 4;
466 mb_height = (pic_param->height + 15) >> 4;
467
468 regs->reg4.sw_pic_mb_width = mb_width & 0x1FF;
469 regs->reg4.sw_pic_mb_hight_p = mb_height & 0xFF;
470 regs->reg4.sw_pic_mb_w_ext = mb_width >> 9;
471 regs->reg4.sw_pic_mb_h_ext = mb_height >> 8;
472
473 if (!pic_param->frame_type) {
474 segmap_ptr = mpp_buffer_get_ptr(ctx->seg_map);
475 if (NULL != segmap_ptr) {
476 memset(segmap_ptr, 0, VP8D_MAX_SEGMAP_SIZE);
477 }
478 }
479
480 probe_ptr = mpp_buffer_get_ptr(ctx->probe_table);
481 if (NULL != probe_ptr) {
482 hal_vp8hw_asic_probe_update(pic_param, probe_ptr);
483 }
484 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->CurrPic.Index7Bits, SLOT_BUFFER, &framebuf);
485 regs->reg13_cur_pic_base = mpp_buffer_get_fd(framebuf);
486 if (!pic_param->frame_type) { //key frame
487 if ((mb_width * mb_height) << 8 > 0x400000) {
488 mpp_log("mb_width*mb_height is big then 0x400000,iommu err");
489 }
490 regs->reg14_ref0_base = regs->reg13_cur_pic_base;
491 mpp_dev_set_reg_offset(ctx->dev, 14, (mb_width * mb_height) << 8);
492 } else if (pic_param->lst_fb_idx.Index7Bits < 0x7f) { //config ref0 base
493 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->lst_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
494 regs->reg14_ref0_base = mpp_buffer_get_fd(framebuf);
495 } else {
496 regs->reg14_ref0_base = regs->reg13_cur_pic_base;
497 }
498
499 /* golden reference */
500 if (pic_param->gld_fb_idx.Index7Bits < 0x7f) {
501 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->gld_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
502 regs->reg18_golden_ref_base = mpp_buffer_get_fd(framebuf);
503 } else {
504 regs->reg18_golden_ref_base = regs->reg13_cur_pic_base;
505 }
506
507 if (pic_param->ref_frame_sign_bias_golden) {
508 mpp_dev_set_reg_offset(ctx->dev, 18, pic_param->ref_frame_sign_bias_golden);
509 }
510
511 /* alternate reference */
512 if (pic_param->alt_fb_idx.Index7Bits < 0x7f) {
513 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->alt_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
514 regs->reg19.alternate_ref_base = mpp_buffer_get_fd(framebuf);
515 } else {
516 regs->reg19.alternate_ref_base = regs->reg13_cur_pic_base;
517 }
518
519 if (pic_param->ref_frame_sign_bias_altref) {
520 mpp_dev_set_reg_offset(ctx->dev, 19, pic_param->ref_frame_sign_bias_altref);
521 }
522
523 if (pic_param->stVP8Segments.segmentation_enabled || pic_param->stVP8Segments.update_mb_segmentation_map) {
524 mpp_dev_set_reg_offset(ctx->dev, 10, (pic_param->stVP8Segments.segmentation_enabled
525 + (pic_param->stVP8Segments.update_mb_segmentation_map << 1)));
526 }
527
528 regs->reg3.sw_pic_inter_e = pic_param->frame_type;
529 regs->reg3.sw_skip_mode = !pic_param->mb_no_coeff_skip;
530
531 if (!pic_param->stVP8Segments.segmentation_enabled) {
532 regs->reg32.sw_filt_level_0 = pic_param->filter_level;
533 } else if (pic_param->stVP8Segments.update_mb_segmentation_data) {
534 regs->reg32.sw_filt_level_0 =
535 pic_param->stVP8Segments.segment_feature_data[1][0];
536 regs->reg32.sw_filt_level_1 =
537 pic_param->stVP8Segments.segment_feature_data[1][1];
538 regs->reg32.sw_filt_level_2 =
539 pic_param->stVP8Segments.segment_feature_data[1][2];
540 regs->reg32.sw_filt_level_3 =
541 pic_param->stVP8Segments.segment_feature_data[1][3];
542 } else {
543 regs->reg32.sw_filt_level_0 = CLIP3(0, 63,
544 (RK_S32)pic_param->filter_level
545 + pic_param->stVP8Segments.segment_feature_data[1][0]);
546 regs->reg32.sw_filt_level_1 = CLIP3(0, 63,
547 (RK_S32)pic_param->filter_level
548 + pic_param->stVP8Segments.segment_feature_data[1][1]);
549 regs->reg32.sw_filt_level_2 = CLIP3(0, 63,
550 (RK_S32)pic_param->filter_level
551 + pic_param->stVP8Segments.segment_feature_data[1][2]);
552 regs->reg32.sw_filt_level_3 = CLIP3(0, 63,
553 (RK_S32)pic_param->filter_level
554 + pic_param->stVP8Segments.segment_feature_data[1][3]);
555 }
556
557 regs->reg30.sw_filt_type = pic_param->filter_type;
558 regs->reg30.sw_filt_sharpness = pic_param->sharpness;
559
560 if (pic_param->filter_level == 0)
561 regs->reg3.sw_filtering_dis = 1;
562
563 if (pic_param->version != 3)
564 regs->reg7.sw_ch_mv_res = 1;
565
566 if (pic_param->decMode == VP8HWD_VP8 && (pic_param->version & 0x3))
567 regs->reg7.sw_bilin_mc_e = 1;
568
569 regs->reg5.sw_boolean_value = pic_param->bool_value;
570 regs->reg5.sw_boolean_range = pic_param->bool_range;
571
572 {
573 if (!pic_param->stVP8Segments.segmentation_enabled)
574 regs->reg33.sw_quant_0 = pic_param->y1ac_delta_q;
575 else if (pic_param->stVP8Segments.update_mb_segmentation_data) { /* absolute mode */
576 regs->reg33.sw_quant_0 =
577 pic_param->stVP8Segments.segment_feature_data[0][0];
578 regs->reg33.sw_quant_1 =
579 pic_param->stVP8Segments.segment_feature_data[0][1];
580 regs->reg46.sw_quant_2 = pic_param->stVP8Segments.segment_feature_data[0][2];
581 regs->reg46.sw_quant_3 = pic_param->stVP8Segments.segment_feature_data[0][3];
582 } else { /* delta mode */
583 regs->reg33.sw_quant_0 = CLIP3(0, 127,
584 pic_param->y1ac_delta_q
585 + pic_param->stVP8Segments.segment_feature_data[0][0]);
586 regs->reg33.sw_quant_1 = CLIP3(0, 127,
587 pic_param->y1ac_delta_q
588 + pic_param->stVP8Segments.segment_feature_data[0][1]);
589 regs->reg46.sw_quant_2 = CLIP3(0, 127,
590 pic_param->y1ac_delta_q
591 + pic_param->stVP8Segments.segment_feature_data[0][2]);
592 regs->reg46.sw_quant_3 = CLIP3(0, 127,
593 pic_param->y1ac_delta_q
594 + pic_param->stVP8Segments.segment_feature_data[0][3]);
595 }
596
597 regs->reg33.sw_quant_delta_0 = pic_param->y1dc_delta_q;
598 regs->reg33.sw_quant_delta_1 = pic_param->y2dc_delta_q;
599 regs->reg46.sw_quant_delta_2 = pic_param->y2ac_delta_q;
600 regs->reg46.sw_quant_delta_3 = pic_param->uvdc_delta_q;
601 regs->reg47.sw_quant_delta_4 = pic_param->uvac_delta_q;
602
603 if (pic_param->mode_ref_lf_delta_enabled) {
604 regs->reg31.sw_filt_ref_adj_0 = pic_param->ref_lf_deltas[0];
605 regs->reg31.sw_filt_ref_adj_1 = pic_param->ref_lf_deltas[1];
606 regs->reg31.sw_filt_ref_adj_2 = pic_param->ref_lf_deltas[2];
607 regs->reg31.sw_filt_ref_adj_3 = pic_param->ref_lf_deltas[3];
608 regs->reg30.sw_filt_mb_adj_0 = pic_param->mode_lf_deltas[0];
609 regs->reg30.sw_filt_mb_adj_1 = pic_param->mode_lf_deltas[1];
610 regs->reg30.sw_filt_mb_adj_2 = pic_param->mode_lf_deltas[2];
611 regs->reg30.sw_filt_mb_adj_3 = pic_param->mode_lf_deltas[3];
612 }
613 }
614
615 if ((pic_param->version & 0x3) == 0)
616 hal_vp8d_pre_filter_tap_set(ctx);
617
618 hal_vp8d_dct_partition_cfg(ctx, task);
619
620 FUN_T("leave\n");
621 return ret;
622 }
623
hal_vp8d_vdpu1_start(void * hal,HalTaskInfo * task)624 MPP_RET hal_vp8d_vdpu1_start(void *hal, HalTaskInfo *task)
625 {
626 MPP_RET ret = MPP_OK;
627 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
628 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
629
630 FUN_T("enter\n");
631
632 if (vp8h_debug & VP8H_DBG_REG) {
633 RK_U32 *p = ctx->regs;
634 RK_U32 i = 0;
635
636 for (i = 0; i < VP8D_REG_NUM; i++)
637 mpp_log_f("vp8d: regs[%02d]=%08X\n", i, *p++);
638 }
639
640 do {
641 MppDevRegWrCfg wr_cfg;
642 MppDevRegRdCfg rd_cfg;
643 RK_U32 reg_size = sizeof(VP8DRegSet_t);
644
645 wr_cfg.reg = regs;
646 wr_cfg.size = reg_size;
647 wr_cfg.offset = 0;
648
649 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
650 if (ret) {
651 mpp_err_f("set register write failed %d\n", ret);
652 break;
653 }
654
655 rd_cfg.reg = regs;
656 rd_cfg.size = reg_size;
657 rd_cfg.offset = 0;
658
659 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
660 if (ret) {
661 mpp_err_f("set register read failed %d\n", ret);
662 break;
663 }
664
665 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
666 if (ret) {
667 mpp_err_f("send cmd failed %d\n", ret);
668 break;
669 }
670 } while (0);
671
672 FUN_T("leave\n");
673
674 (void)task;
675 return ret;
676 }
677
hal_vp8d_vdpu1_wait(void * hal,HalTaskInfo * task)678 MPP_RET hal_vp8d_vdpu1_wait(void *hal, HalTaskInfo *task)
679 {
680 MPP_RET ret = MPP_OK;
681 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
682
683 FUN_T("enter\n");
684
685 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
686 if (ret)
687 mpp_err_f("poll cmd failed %d\n", ret);
688
689 (void)task;
690 FUN_T("leave\n");
691 return ret;
692 }
693