1 /******************************************************************************
2 *
3 * Copyright(c) 2016 - 2019 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTL8852BE_HALINIT_C_
16 #include "../../hal_headers.h"
17 #include "../rtl8852b_hal.h"
18 #include "hal_trx_8852be.h"
19
20 static enum mac_ax_pcie_func_ctrl
_hal_set_each_pcicfg(enum rtw_pcie_bus_func_cap_t ctrl)21 _hal_set_each_pcicfg(enum rtw_pcie_bus_func_cap_t ctrl)
22 {
23 switch(ctrl) {
24
25 case RTW_PCIE_BUS_FUNC_DISABLE:
26 return MAC_AX_PCIE_DISABLE;
27 case RTW_PCIE_BUS_FUNC_ENABLE:
28 return MAC_AX_PCIE_ENABLE;
29 default:
30 return MAC_AX_PCIE_DEFAULT;
31 }
32
33 }
34
_hal_aspm_disable_8852be(struct hal_info_t * hal_info)35 static enum rtw_hal_status _hal_aspm_disable_8852be(struct hal_info_t *hal_info)
36 {
37 struct mac_ax_pcie_cfgspc_param pcicfg;
38 enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
39
40 _os_mem_set(hal_to_drvpriv(hal_info), &pcicfg, 0, sizeof(pcicfg));
41 pcicfg.write = 1;
42
43 /* set disable to l0s l1 l1ss */
44 pcicfg.l0s_ctrl = MAC_AX_PCIE_DISABLE;
45 pcicfg.l1_ctrl = MAC_AX_PCIE_DISABLE;
46 pcicfg.l1ss_ctrl = MAC_AX_PCIE_DISABLE;
47
48 /* set ignore to others */
49 pcicfg.wake_ctrl = MAC_AX_PCIE_IGNORE;
50 pcicfg.crq_ctrl = MAC_AX_PCIE_IGNORE;
51 pcicfg.clkdly_ctrl = MAC_AX_PCIE_IGNORE;
52 pcicfg.l0sdly_ctrl = MAC_AX_PCIE_IGNORE;
53 pcicfg.l1dly_ctrl = MAC_AX_PCIE_IGNORE;
54
55
56 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
57 "%s : l0s/l1/l1ss/wake/crq/l0sdly/l1dly/clkdly = %#X/%#X/%#X/%#X/%#X/%#X/%#X/%#X \n",
58 __func__, pcicfg.l0s_ctrl, pcicfg.l1_ctrl, pcicfg.l1ss_ctrl, pcicfg.wake_ctrl,
59 pcicfg.crq_ctrl, pcicfg.l0sdly_ctrl, pcicfg.l1dly_ctrl, pcicfg.clkdly_ctrl);
60
61 hsts = rtw_hal_mac_set_pcicfg(hal_info, &pcicfg);
62
63 return hsts;
64 }
65
_hal_set_pcicfg_8852be(struct hal_info_t * hal_info)66 enum rtw_hal_status _hal_set_pcicfg_8852be(struct hal_info_t *hal_info)
67 {
68 struct mac_ax_pcie_cfgspc_param pcicfg;
69 enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
70 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
71
72 _os_mem_set(hal_to_drvpriv(hal_info), &pcicfg, 0, sizeof(pcicfg));
73 pcicfg.write = 1;
74 pcicfg.l0s_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l0s_ctrl);
75 pcicfg.l1_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l1_ctrl);
76 pcicfg.l1ss_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l1ss_ctrl);
77 pcicfg.wake_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.wake_ctrl);
78 pcicfg.crq_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.crq_ctrl);
79 pcicfg.clkdly_ctrl = hal_com->bus_cap.clkdly_ctrl;
80 pcicfg.l0sdly_ctrl = hal_com->bus_cap.l0sdly_ctrl;
81 pcicfg.l1dly_ctrl = hal_com->bus_cap.l1dly_ctrl;
82
83
84 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
85 "%s : l0s/l1/l1ss/wake/crq/l0sdly/l1dly/clkdly = %#X/%#X/%#X/%#X/%#X/%#X/%#X/%#X \n",
86 __func__, pcicfg.l0s_ctrl, pcicfg.l1_ctrl, pcicfg.l1ss_ctrl, pcicfg.wake_ctrl,
87 pcicfg.crq_ctrl, pcicfg.l0sdly_ctrl, pcicfg.l1dly_ctrl, pcicfg.clkdly_ctrl);
88
89 hsts = rtw_hal_mac_set_pcicfg(hal_info, &pcicfg);
90
91 return hsts;
92 }
93
_hal_ltr_sw_init_state_8852be(struct hal_info_t * hal_info)94 enum rtw_hal_status _hal_ltr_sw_init_state_8852be(struct hal_info_t *hal_info)
95 {
96
97 enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
98 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
99 enum rtw_pcie_ltr_state state;
100
101 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
102 "%s :sw state = %u \n",__func__, hal_com->bus_cap.ltr_init_state);
103
104 if (hal_com->bus_cap.ltr_init_state > 0) {
105
106 state = hal_com->bus_cap.ltr_init_state;
107 hsts = rtw_hal_mac_ltr_sw_trigger(hal_info,state);
108
109 } else {
110
111 hsts = RTW_HAL_STATUS_SUCCESS;
112 }
113 return hsts;
114 }
115
_hal_ltr_set_pcie_8852be(struct hal_info_t * hal_info)116 enum rtw_hal_status _hal_ltr_set_pcie_8852be(struct hal_info_t *hal_info)
117 {
118 enum rtw_hal_status hsts = RTW_HAL_STATUS_SUCCESS;
119 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
120 struct bus_cap_t *bus_cap = &hal_com->bus_cap;
121
122 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
123 "%s :idle_ctrl/idle_val/act_ctrl/act_val = %u/%#X/%u/%#X \n",
124 __func__, bus_cap->ltr_idle.ctrl,
125 bus_cap->ltr_idle.val, bus_cap->ltr_act.ctrl, bus_cap->ltr_act.val);
126
127 if (bus_cap->ltr_idle.ctrl || bus_cap->ltr_act.ctrl) {
128 hsts = rtw_hal_mac_ltr_set_pcie(hal_info, RTW_PCIE_BUS_FUNC_IGNORE,
129 bus_cap->ltr_idle.ctrl, bus_cap->ltr_idle.val,
130 bus_cap->ltr_act.ctrl, bus_cap->ltr_act.val);
131 }
132
133 return hsts;
134 }
135
_hal_aspm_hw_cfg(struct hal_info_t * hal)136 static void _hal_aspm_hw_cfg(struct hal_info_t *hal)
137 {
138
139 struct rtw_hal_com_t *hal_com = hal->hal_com;
140
141 /* func */
142 hal_com->bus_hw_cap.l0s_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
143 hal_com->bus_hw_cap.l1_ctrl = RTW_PCIE_BUS_FUNC_ENABLE;
144 hal_com->bus_hw_cap.l1ss_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
145 hal_com->bus_hw_cap.wake_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
146 hal_com->bus_hw_cap.crq_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
147
148 /*delay*/
149 hal_com->bus_hw_cap.l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_DEF;
150 hal_com->bus_hw_cap.l1dly_ctrl = MAC_AX_PCIE_L1DLY_DEF;
151 hal_com->bus_hw_cap.clkdly_ctrl = MAC_AX_PCIE_CLKDLY_DEF;
152
153 }
154
_hal_tx_ch_config_8852be(struct hal_info_t * hal)155 static void _hal_tx_ch_config_8852be(struct hal_info_t *hal)
156 {
157 struct mac_ax_txdma_ch_map *txch_map = (struct mac_ax_txdma_ch_map *)hal->txch_map;
158
159 txch_map->ch0 = MAC_AX_PCIE_ENABLE;
160 txch_map->ch1 = MAC_AX_PCIE_ENABLE;
161 txch_map->ch2 = MAC_AX_PCIE_ENABLE;
162 txch_map->ch3 = MAC_AX_PCIE_ENABLE;
163 txch_map->ch4 = MAC_AX_PCIE_DISABLE;
164 txch_map->ch5 = MAC_AX_PCIE_DISABLE;
165 txch_map->ch6 = MAC_AX_PCIE_DISABLE;
166 txch_map->ch7 = MAC_AX_PCIE_DISABLE;
167 txch_map->ch8 = MAC_AX_PCIE_ENABLE;
168 txch_map->ch9 = MAC_AX_PCIE_ENABLE;
169 txch_map->ch10 = MAC_AX_PCIE_DISABLE;
170 txch_map->ch11 = MAC_AX_PCIE_DISABLE;
171 txch_map->ch12 = MAC_AX_PCIE_ENABLE;
172 }
173
_hal_pre_init_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct hal_init_info_t * init_52be)174 static void _hal_pre_init_8852be(struct rtw_phl_com_t *phl_com,
175 struct hal_info_t *hal_info,
176 struct hal_init_info_t *init_52be)
177 {
178 struct mac_ax_trx_info *trx_info = &init_52be->trx_info;
179 struct mac_ax_intf_info *intf_info = &init_52be->intf_info;
180 struct mac_ax_host_rpr_cfg *rpr_cfg = (struct mac_ax_host_rpr_cfg *)hal_info->rpr_cfg;
181 void *txbd_buf = NULL;
182 void *rxbd_buf = NULL;
183
184 /* trx_info */
185 if (true == phl_com->dev_cap.tx_mu_ru)
186 trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
187 else
188 trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
189
190 if (hal_info->hal_com->dbcc_en == false)
191 trx_info->qta_mode = MAC_AX_QTA_SCC;
192 else
193 trx_info->qta_mode = MAC_AX_QTA_DBCC;
194
195 #ifdef RTW_WKARD_LAMODE
196 PHL_INFO("%s : la_mode %d\n", __func__, phl_com->dev_cap.la_mode);
197 if (phl_com->dev_cap.la_mode)
198 trx_info->qta_mode = MAC_AX_QTA_LAMODE;
199 #endif
200
201 if (phl_com->dev_cap.rpq_agg_num) {
202 rpr_cfg->agg_def = 0;
203 rpr_cfg->agg = phl_com->dev_cap.rpq_agg_num;
204 } else {
205 rpr_cfg->agg_def = 1;
206 }
207
208 rpr_cfg->tmr_def = 1;
209 #ifdef CONFIG_PHL_RELEASE_RPT_ENABLE
210 rpr_cfg->txok_en = MAC_AX_FUNC_EN;
211 rpr_cfg->rty_lmt_en = MAC_AX_FUNC_EN;
212 rpr_cfg->lft_drop_en = MAC_AX_FUNC_EN;
213 rpr_cfg->macid_drop_en = MAC_AX_FUNC_EN;
214 #else
215 rpr_cfg->txok_en = MAC_AX_FUNC_DEF;
216 rpr_cfg->rty_lmt_en = MAC_AX_FUNC_DEF;
217 rpr_cfg->lft_drop_en = MAC_AX_FUNC_DEF;
218 rpr_cfg->macid_drop_en = MAC_AX_FUNC_DEF;
219 #endif /* CONFIG_PHL_RELEASE_RPT_ENABLE */
220 trx_info->rpr_cfg = rpr_cfg;
221
222 /* intf_info */
223 txbd_buf = rtw_phl_get_txbd_buf(phl_com);
224 rxbd_buf = rtw_phl_get_rxbd_buf(phl_com);
225
226 intf_info->txbd_trunc_mode = MAC_AX_BD_TRUNC;
227 intf_info->rxbd_trunc_mode = MAC_AX_BD_TRUNC;
228
229 intf_info->rxbd_mode = MAC_AX_RXBD_PKT;
230 intf_info->tag_mode = MAC_AX_TAG_MULTI;
231 intf_info->tx_burst = MAC_AX_TX_BURST_DEF;
232 intf_info->rx_burst = MAC_AX_RX_BURST_DEF;
233 intf_info->wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_DEF;
234 intf_info->wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_DEF;
235 intf_info->multi_tag_num = MAC_AX_TAG_NUM_DEF;
236 intf_info->rx_sep_append_len = 0;
237 intf_info->txbd_buf = txbd_buf;
238 intf_info->rxbd_buf = rxbd_buf;
239 intf_info->skip_all = false;
240 intf_info->autok_en = MAC_AX_PCIE_ENABLE;
241
242 _hal_tx_ch_config_8852be(hal_info);
243 intf_info->txch_map = (struct mac_ax_txdma_ch_map *)hal_info->txch_map;
244
245 intf_info->lbc_en = MAC_AX_PCIE_DEFAULT;
246 intf_info->lbc_tmr = MAC_AX_LBC_TMR_DEF;
247
248 /* others */
249 init_52be->ic_name = "rtl8852be";
250 }
251
init_hal_spec_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal)252 void init_hal_spec_8852be(struct rtw_phl_com_t *phl_com,
253 struct hal_info_t *hal)
254 {
255 struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com);
256 struct rtw_hal_com_t *hal_com = hal->hal_com;
257 struct bus_hw_cap_t *bus_hw_cap = &hal_com->bus_hw_cap;
258
259 init_hal_spec_8852b(phl_com, hal);
260
261 hal_spec->rx_bd_info_sz = RX_BD_INFO_SIZE;
262 hal_spec->rx_tag[0] = 0;
263 hal_spec->rx_tag[1] = 0;
264
265 bus_hw_cap->max_txbd_num = 0x3FF;
266 bus_hw_cap->max_rxbd_num = 0x3FF;
267 bus_hw_cap->max_rpbd_num = 0x3FF;
268 bus_hw_cap->max_wd_page_size = 128;
269 bus_hw_cap->wdb_size = 24;
270 bus_hw_cap->wdi_size = 24;
271 bus_hw_cap->txbd_len = 8;
272 bus_hw_cap->rxbd_len = 8;
273 bus_hw_cap->addr_info_size = 8;
274 bus_hw_cap->seq_info_size = 8;
275 #ifdef RTW_WKARD_BUSCAP_IN_HALSPEC
276 hal_spec->phyaddr_num = 9;
277 #endif
278
279 phl_com->dev_cap.hw_sup_flags |= HW_SUP_PCIE_PLFH;/*PCIe payload from host*/
280
281 _hal_aspm_hw_cfg(hal);
282
283 if (hal_com->cv == CAV) {
284 bus_hw_cap->ltr_sw_ctrl = true;
285 bus_hw_cap->ltr_hw_ctrl = false;
286 } else {
287 bus_hw_cap->ltr_sw_ctrl = false;
288 bus_hw_cap->ltr_hw_ctrl = true;
289 }
290
291 hal_com->dev_hw_cap.ps_cap.lps_pause_tx = false;
292 }
293
hal_get_efuse_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)294 enum rtw_hal_status hal_get_efuse_8852be(struct rtw_phl_com_t *phl_com,
295 struct hal_info_t *hal_info)
296 {
297 struct hal_init_info_t init_52be;
298 _os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
299 _hal_pre_init_8852be(phl_com, hal_info, &init_52be);
300
301 return hal_get_efuse_8852b(phl_com, hal_info, &init_52be);
302 }
303
hal_init_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)304 enum rtw_hal_status hal_init_8852be(struct rtw_phl_com_t *phl_com,
305 struct hal_info_t *hal_info)
306 {
307 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
308 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
309 void *drv = phlcom_to_drvpriv(phl_com);
310 u32 len = 0;
311 u8 txch_num = 0;
312
313 txch_num = rtw_hal_query_txch_num(hal_info);
314
315 len = sizeof(struct rtw_wp_rpt_stats) * txch_num;
316 hal_com->trx_stat.wp_rpt_stats = _os_mem_alloc(drv, len);
317 if (hal_com->trx_stat.wp_rpt_stats == NULL) {
318 hal_status = RTW_HAL_STATUS_RESOURCE;
319 PHL_ERR("%s: alloc txch_map failed\n", __func__);
320 goto error_trx_stats_wp_rpt;
321 }
322
323 hal_info->txch_map = _os_mem_alloc(drv,
324 sizeof(struct mac_ax_txdma_ch_map));
325 if (hal_info->txch_map == NULL) {
326 hal_status = RTW_HAL_STATUS_RESOURCE;
327 PHL_ERR("%s: alloc txch_map failed\n", __func__);
328 goto error_txch_map;
329 }
330
331 hal_info->rpr_cfg = _os_mem_alloc(drv,
332 sizeof(struct mac_ax_host_rpr_cfg));
333 if (hal_info->rpr_cfg == NULL) {
334 hal_status = RTW_HAL_STATUS_RESOURCE;
335 PHL_ERR("%s: alloc rpr_cfg failed\n", __func__);
336 goto error_rpr_cfg;
337 }
338
339 hal_status = RTW_HAL_STATUS_SUCCESS;
340
341 return hal_status;
342
343 error_rpr_cfg:
344 _os_mem_free(drv,
345 hal_info->txch_map,
346 sizeof(struct mac_ax_txdma_ch_map));
347 error_txch_map:
348 _os_mem_free(drv,
349 hal_com->trx_stat.wp_rpt_stats,
350 sizeof(struct rtw_wp_rpt_stats) * txch_num);
351 error_trx_stats_wp_rpt:
352 return hal_status;
353 }
354
hal_deinit_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)355 void hal_deinit_8852be(struct rtw_phl_com_t *phl_com,
356 struct hal_info_t *hal_info)
357 {
358 u8 txch_num = 0;
359
360 txch_num = rtw_hal_query_txch_num(hal_info);
361
362 _os_mem_free(phlcom_to_drvpriv(phl_com),
363 hal_info->hal_com->trx_stat.wp_rpt_stats,
364 sizeof(struct rtw_wp_rpt_stats) * txch_num);
365 _os_mem_free(phlcom_to_drvpriv(phl_com),
366 hal_info->txch_map,
367 sizeof(struct mac_ax_txdma_ch_map));
368 _os_mem_free(phlcom_to_drvpriv(phl_com),
369 hal_info->rpr_cfg,
370 sizeof(struct mac_ax_host_rpr_cfg));
371 }
372
hal_start_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)373 enum rtw_hal_status hal_start_8852be(struct rtw_phl_com_t *phl_com,
374 struct hal_info_t *hal_info)
375 {
376 struct hal_init_info_t init_52be;
377 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
378
379 _os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
380 _hal_pre_init_8852be(phl_com, hal_info, &init_52be);
381
382 hal_status = hal_start_8852b(phl_com, hal_info, &init_52be);
383 if(RTW_HAL_STATUS_SUCCESS != hal_status) {
384
385 PHL_ERR("hal_init_8852b: status = %u\n",hal_status);
386 return hal_status;
387 }
388
389 hal_status = _hal_set_pcicfg_8852be(hal_info);
390 if(RTW_HAL_STATUS_SUCCESS != hal_status) {
391 PHL_ERR("_hal_set_pcicfg_8852be: status = %u\n",hal_status);
392 return hal_status;
393 }
394
395 hal_status = _hal_ltr_set_pcie_8852be(hal_info);
396 if(RTW_HAL_STATUS_SUCCESS != hal_status) {
397 PHL_ERR("_hal_ltr_set_pcie_8852be: status = %u\n",hal_status);
398 return hal_status;
399 }
400
401 hal_status = _hal_ltr_sw_init_state_8852be(hal_info);
402 if(RTW_HAL_STATUS_SUCCESS != hal_status) {
403 PHL_ERR("_hal_ltr_sw_init_state_8852be: status = %u\n",hal_status);
404 return hal_status;
405 }
406
407 return hal_status;
408 }
409
hal_stop_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal)410 enum rtw_hal_status hal_stop_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal)
411 {
412 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
413
414 if (TEST_STATUS_FLAG(phl_com->dev_state, RTW_DEV_SHUTTING_DOWN)) {
415 hal_status = _hal_aspm_disable_8852be(hal);
416 if (RTW_HAL_STATUS_SUCCESS != hal_status)
417 PHL_ERR("%s: _hal_aspm_disable_8852be status = %u\n",
418 __func__, hal_status);
419 }
420
421 hal_status = hal_stop_8852b(phl_com, hal);
422 return hal_status;
423 }
424
425 #ifdef CONFIG_WOWLAN
426
427 enum rtw_hal_status
hal_wow_init_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct rtw_phl_stainfo_t * sta)428 hal_wow_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
429 struct rtw_phl_stainfo_t *sta)
430 {
431 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
432 struct hal_init_info_t init_52be;
433 struct mac_ax_trx_info *trx_info = &init_52be.trx_info;
434
435 FUNCIN_WSTS(hal_status);
436
437 _os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
438 if (true == phl_com->dev_cap.tx_mu_ru)
439 trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
440 else
441 trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
442 trx_info->qta_mode = MAC_AX_QTA_SCC;
443 /*
444 if (hal_info->hal_com->dbcc_en == false)
445 trx_info->qta_mode = MAC_AX_QTA_SCC;
446 else
447 trx_info->qta_mode = MAC_AX_QTA_DBCC;
448 */
449 init_52be.ic_name = "rtl8852be";
450
451 hal_status = hal_wow_init_8852b(phl_com, hal_info, sta, &init_52be);
452
453 FUNCOUT_WSTS(hal_status);
454 return hal_status;
455 }
456
457 enum rtw_hal_status
hal_wow_deinit_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct rtw_phl_stainfo_t * sta)458 hal_wow_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
459 struct rtw_phl_stainfo_t *sta)
460 {
461 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
462 struct hal_init_info_t init_52be;
463 struct mac_ax_trx_info *trx_info = &init_52be.trx_info;
464
465 FUNCIN_WSTS(hal_status);
466
467 _os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
468 if (true == phl_com->dev_cap.tx_mu_ru)
469 trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
470 else
471 trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
472 trx_info->qta_mode = MAC_AX_QTA_SCC;
473 /*
474 if (hal_info->hal_com->dbcc_en == false)
475 trx_info->qta_mode = MAC_AX_QTA_SCC;
476 else
477 trx_info->qta_mode = MAC_AX_QTA_DBCC;
478 */
479 init_52be.ic_name = "rtl8852be";
480
481 hal_status = hal_wow_deinit_8852b(phl_com, hal_info, sta, &init_52be);
482
483 if (RTW_HAL_STATUS_SUCCESS != hal_status) {
484
485 PHL_ERR("hal_wow_deinit_8852be: status = %u\n", hal_status);
486 return hal_status;
487 }
488
489 if (RTW_HAL_STATUS_SUCCESS != _hal_set_pcicfg_8852be(hal_info))
490 PHL_ERR("_hal_set_pcicfg_8852be: status = %u\n", hal_status);
491
492
493 FUNCOUT_WSTS(hal_status);
494 return hal_status;
495 }
496
497 #endif /* CONFIG_WOWLAN */
498
hal_hci_cfg_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal,struct rtw_ic_info * ic_info)499 u32 hal_hci_cfg_8852be(struct rtw_phl_com_t *phl_com,
500 struct hal_info_t *hal, struct rtw_ic_info *ic_info)
501 {
502 struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com);
503 hal_spec->cts2_thres_en = true;
504 hal_spec->cts2_thres = 1792;
505
506 hal_spec->txbd_multi_tag = 8;
507 #ifdef RTW_WKARD_TXBD_UPD_LMT
508 hal_spec->txbd_upd_lmt = true;
509 #else
510 hal_spec->txbd_upd_lmt = false;
511 #endif
512 return RTW_HAL_STATUS_SUCCESS;
513 }
514
hal_init_default_value_8852be(struct hal_info_t * hal,struct hal_intr_mask_cfg * cfg)515 void hal_init_default_value_8852be(struct hal_info_t *hal, struct hal_intr_mask_cfg *cfg)
516 {
517 struct rtw_hal_com_t *hal_com = hal->hal_com;
518
519 init_default_value_8852b(hal);
520
521 hal_com->int_mask_default[0] = (u32)(
522 B_AX_RPQBD_FULL_INT_EN | /* RPQBD full */
523 B_AX_RDU_INT_EN | /* Rx Descriptor Unavailable */
524 #if 0
525 B_AX_RXDMA_STUCK_INT_EN | /* PCIE RX DMA Stuck */
526 B_AX_TXDMA_STUCK_INT_EN | /* PCIE TX DMA Stuck */
527 B_AX_PCIE_HOTRST_INT_EN | /* PCIE HOT Reset */
528 B_AX_PCIE_FLR_INT_EN | /* PCIE FLR */
529 B_AX_PCIE_PERST_INT_EN | /* PCIE PERST */
530 #endif
531 B_AX_RPQDMA_INT_EN | /* RPQ DMA OK */
532 B_AX_RXDMA_INT_EN | /* RXQ (Packet mode or Part2) DMA OK */
533 B_AX_HS0ISR_IND_INT_EN | /* FW C2H*/
534 B_AX_HD0ISR_IND_INT_EN | /* watchdog timer*/
535 #if 0
536 B_AX_TXDMA_CH12_INT_EN | /* FWCMDQ */
537 B_AX_TXDMA_CH9_INT_EN | /* */
538 B_AX_TXDMA_CH8_INT_EN | /* */
539 B_AX_TXDMA_ACH7_INT_EN | /* */
540 B_AX_TXDMA_ACH6_INT_EN | /* */
541 B_AX_TXDMA_ACH5_INT_EN | /* */
542 B_AX_TXDMA_ACH4_INT_EN | /* */
543 B_AX_TXDMA_ACH3_INT_EN | /* */
544 B_AX_TXDMA_ACH2_INT_EN | /* */
545 B_AX_TXDMA_ACH1_INT_EN | /* */
546 B_AX_TXDMA_ACH0_INT_EN | /* */
547 #endif
548 0);
549
550 hal_com->int_mask_default[1] = (u32)(
551 #if 0
552 B_AX_TXDMA_CH11_INT |
553 B_AX_TXDMA_CH10_INT |
554 #endif
555 0);
556
557 hal_com->intr.halt_c2h_int.val_default = (u32)(
558 (cfg->halt_c2h_en == 1 ? B_AX_HALT_C2H_INT_EN : 0) |
559 0);
560
561 hal_com->intr.watchdog_timer_int.val_default = (u32)(
562 (cfg->wdt_en == 1 ? B_AX_WDT_PTFM_INT_EN : 0) |
563 0);
564
565 hal_com->int_mask[0] = hal_com->int_mask_default[0];
566 hal_com->int_mask[1] = hal_com->int_mask_default[1];
567 hal_com->intr.halt_c2h_int.val_mask = hal_com->intr.halt_c2h_int.val_default;
568 hal_com->intr.watchdog_timer_int.val_mask = hal_com->intr.watchdog_timer_int.val_default;
569
570 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : %08X, %08X, %08x, %08x\n", __func__,
571 hal_com->int_mask[0], hal_com->int_mask[1], hal_com->intr.halt_c2h_int.val_mask,
572 hal_com->intr.watchdog_timer_int.val_mask );
573 }
574
hal_enable_int_8852be(struct hal_info_t * hal)575 void hal_enable_int_8852be(struct hal_info_t *hal)
576 {
577 struct rtw_hal_com_t *hal_com = hal->hal_com;
578
579 hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
580 hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1]);
581 hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask);
582 hal_write32(hal_com, R_AX_HD0IMR, hal_com->intr.watchdog_timer_int.val_mask);
583
584 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : \n%04X : %08X\n%04X : %08X\n%04X : %08X\n%04X : %08X\n",
585 __func__,
586 R_AX_PCIE_HIMR00, hal_read32(hal_com, R_AX_PCIE_HIMR00),
587 R_AX_PCIE_HIMR10, hal_read32(hal_com, R_AX_PCIE_HIMR10),
588 R_AX_HIMR0, hal_read32(hal_com, R_AX_HIMR0),
589 R_AX_HD0IMR, hal_read32(hal_com, R_AX_HD0IMR)
590 );
591
592 }
593
hal_disable_int_8852be(struct hal_info_t * hal)594 void hal_disable_int_8852be(struct hal_info_t *hal)
595 {
596 struct rtw_hal_com_t *hal_com = hal->hal_com;
597
598 hal_write32(hal_com, R_AX_PCIE_HIMR00, 0);
599 hal_write32(hal_com, R_AX_PCIE_HIMR10, 0);
600 hal_write32(hal_com, R_AX_HIMR0, 0);
601 }
602
hal_recognize_int_8852be(struct hal_info_t * hal)603 bool hal_recognize_int_8852be(struct hal_info_t *hal)
604 {
605 struct rtw_hal_com_t *hal_com = hal->hal_com;
606 bool recognized = false;
607
608 #ifndef CONFIG_SYNC_INTERRUPT
609 /* disable imr before cleaning isr */
610 hal_write32(hal_com, R_AX_PCIE_HIMR00, 0);
611 hal_write32(hal_com, R_AX_PCIE_HIMR10, 0);
612 hal_write32(hal_com, R_AX_HIMR0, 0);
613 #endif /* CONFIG_SYNC_INTERRUPT */
614
615 /* save isr for sw usage, handling interrupt */
616 /* isr00 */
617 hal_com->int_array[0] = hal_read32(hal_com, R_AX_PCIE_HISR00);
618 hal_com->int_array[0] &= hal_com->int_mask[0];
619
620 /* isr10 */
621 hal_com->int_array[1] = hal_read32(hal_com, R_AX_PCIE_HISR10);
622 hal_com->int_array[1] &= hal_com->int_mask[1];
623
624 /* isr0 */
625 hal_com->intr.halt_c2h_int.intr = hal_read32(hal_com, R_AX_HISR0);
626 hal_com->intr.halt_c2h_int.intr &= hal_com->intr.halt_c2h_int.val_mask;
627
628 /* isr0 */
629 if (hal_com->int_array[0] & B_AX_HD0ISR_IND_INT_EN) {
630 hal_com->intr.watchdog_timer_int.intr = B_AX_WDT_PTFM_INT;
631 hal_com->intr.watchdog_timer_int.intr &= hal_com->intr.watchdog_timer_int.val_mask;
632 /* clear int mask*/
633 hal_clear_int_mask_8852be(hal);
634 } else {
635 hal_com->intr.watchdog_timer_int.intr = 0;
636 }
637
638 if (hal_com->int_array[0] || hal_com->int_array[1] || hal_com->intr.halt_c2h_int.intr || hal_com->intr.watchdog_timer_int.intr)
639 recognized = true;
640
641 if (hal_com->intr.halt_c2h_int.intr)
642 PHL_WARN("%s : halt c2h interrupt is recognized (0x%x).\n", __func__, hal_com->intr.halt_c2h_int.intr);
643
644 if (hal_com->intr.watchdog_timer_int.intr)
645 PHL_WARN("%s : watchdog timer is recognized (0x%x).\n", __func__, hal_com->intr.watchdog_timer_int.intr);
646
647 #ifndef CONFIG_SYNC_INTERRUPT
648 /* clear isr */
649 hal_write32(hal_com, R_AX_HISR0, hal_com->intr.halt_c2h_int.intr);
650 hal_write32(hal_com, R_AX_PCIE_HISR00, hal_com->int_array[0]);
651 hal_write32(hal_com, R_AX_PCIE_HISR10, hal_com->int_array[1]);
652
653 /* restore imr */
654 hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0] & 0xFFFFFFFF);
655 hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1] & 0xFFFFFFFF);
656 hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask & 0xFFFFFFFF);
657 #endif /* CONFIG_SYNC_INTERRUPT */
658 return recognized;
659 }
660
hal_clear_int_8852be(struct hal_info_t * hal)661 void hal_clear_int_8852be(struct hal_info_t *hal)
662 {
663 struct rtw_hal_com_t *hal_com = hal->hal_com;
664
665 hal_write32(hal_com, R_AX_PCIE_HISR00, hal_com->int_array[0]);
666 hal_write32(hal_com, R_AX_PCIE_HISR10, hal_com->int_array[1]);
667 hal_write32(hal_com, R_AX_HISR0, hal_com->intr.halt_c2h_int.intr);
668 }
669
hal_clear_int_mask_8852be(struct hal_info_t * hal)670 void hal_clear_int_mask_8852be(struct hal_info_t *hal)
671 {
672 struct rtw_hal_com_t *hal_com = hal->hal_com;
673
674 hal_com->int_mask[0] = 0;
675 hal_com->int_mask[1] = 0;
676 hal_com->intr.halt_c2h_int.val_mask = 0;
677 hal_com->intr.watchdog_timer_int.val_mask = 0;
678 }
679
hal_restore_int_8852be(struct hal_info_t * hal)680 void hal_restore_int_8852be(struct hal_info_t *hal)
681 {
682 struct rtw_hal_com_t *hal_com = hal->hal_com;
683
684 hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0] & 0xFFFFFFFF);
685 hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1] & 0xFFFFFFFF);
686 hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask & 0xFFFFFFFF);
687 }
688
689
690 #define BIT_BCNDERR0_MSK BIT(16)
691 #define BIT_BCNDMAINT0_MSK BIT(20)
692 #define BIT_TXBCN0OK_MSK BIT(25)
693 #define BIT_TXBCN0ERR_MSK BIT(26)
694
hal_bcn_handler_8852be(struct hal_info_t * hal,u32 * handled)695 static u32 hal_bcn_handler_8852be(struct hal_info_t *hal, u32 *handled)
696 {
697 u32 ret = 0;
698 struct rtw_hal_com_t *hal_com = hal->hal_com;
699
700 if (hal_com->int_array[0] & BIT_TXBCN0OK_MSK){
701 handled[0] |= BIT_TXBCN0OK_MSK;
702 ret = 1;
703 }
704
705 if (hal_com->int_array[0] & BIT_TXBCN0ERR_MSK){
706 handled[0] |= BIT_TXBCN0ERR_MSK;
707 ret = 1;
708 }
709
710 if (hal_com->int_array[0] & BIT_BCNDERR0_MSK){
711 handled[0] |= BIT_BCNDERR0_MSK;
712 ret = 1;
713 }
714
715 if (hal_com->int_array[0] & BIT_BCNDMAINT0_MSK){
716 handled[0] |= BIT_BCNDMAINT0_MSK;
717 ret = 1;
718 }
719
720 return ret;
721 }
722
hal_rx_handler_8852be(struct hal_info_t * hal,u32 * handled)723 static u32 hal_rx_handler_8852be(struct hal_info_t *hal, u32 *handled)
724 {
725 u32 ret = 0;
726 struct rtw_hal_com_t *hal_com = hal->hal_com;
727 static const u32 rx_handle_irq = (
728 B_AX_RXDMA_INT_EN |
729 B_AX_RDU_INT_EN);
730 u32 handled0 = (hal_com->int_array[0] & rx_handle_irq);
731
732 if (handled0 == 0)
733 return ret;
734
735 PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ B4 : %08X (%08X)\n",
736 handled0, hal_com->int_array[0]);
737 /* Disable RX interrupts, RX tasklet will enable them after processed RX */
738 hal_com->int_mask[0] &= ~rx_handle_irq;
739 #ifndef CONFIG_SYNC_INTERRUPT
740 hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
741 #endif /* CONFIG_SYNC_INTERRUPT */
742
743 handled[0] |= handled0;
744 ret = 1;
745
746 PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ A4 : %08X (%08X)\n",
747 handled0, hal_com->int_array[0]);
748
749 return ret;
750
751 }
752
hal_rp_handler_8852be(struct hal_info_t * hal,u32 * handled)753 static u32 hal_rp_handler_8852be(struct hal_info_t *hal, u32 *handled)
754 {
755 u32 ret = 0;
756 struct rtw_hal_com_t *hal_com = hal->hal_com;
757 static const u32 rp_handle_irq = (
758 B_AX_RPQDMA_INT_EN|
759 B_AX_RPQBD_FULL_INT_EN);
760 u32 handled0 = (hal_com->int_array[0] & rp_handle_irq);
761
762 if (handled0 == 0)
763 return ret;
764
765 PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ B4 : %08X (%08X)\n",
766 handled0, hal_com->int_array[0]);
767 /* Disable RX interrupts, RX tasklet will enable them after processed RX */
768 hal_com->int_mask[0] &= ~rp_handle_irq;
769 #ifndef CONFIG_SYNC_INTERRUPT
770 hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
771 #endif /* CONFIG_SYNC_INTERRUPT */
772
773 handled[0] |= handled0;
774 ret = 1;
775
776 PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ A4 : %08X (%08X)\n",
777 handled0, hal_com->int_array[0]);
778
779 return ret;
780
781 }
782
hal_tx_handler_8852be(struct hal_info_t * hal,u32 * handled)783 static u32 hal_tx_handler_8852be(struct hal_info_t *hal, u32 *handled)
784 {
785 u32 ret = 0;
786 struct rtw_hal_com_t *hal_com = hal->hal_com;
787 u32 event0 = 0x0;
788 u32 event1 = 0x0;
789
790 event0 = hal_com->int_array[0] & (
791 B_AX_TXDMA_ACH0_INT |
792 B_AX_TXDMA_ACH1_INT |
793 B_AX_TXDMA_ACH2_INT |
794 B_AX_TXDMA_ACH3_INT |
795 B_AX_TXDMA_ACH4_INT |
796 B_AX_TXDMA_ACH5_INT |
797 B_AX_TXDMA_ACH6_INT |
798 B_AX_TXDMA_ACH7_INT |
799 B_AX_TXDMA_CH8_INT |
800 B_AX_TXDMA_CH9_INT |
801 B_AX_TXDMA_CH12_INT);
802
803 event1 = hal_com->int_array[1] & (
804 B_AX_TXDMA_CH10_INT |
805 B_AX_TXDMA_CH11_INT);
806
807 if(event0 != 0 || event1 != 0)
808 ret = 1;
809
810 handled[0] |= event0;
811 handled[1] |= event1;
812
813 return ret;
814 }
815
816 #define BIT_SETH2CDOK_MASK BIT(16)
hal_cmd_handler_8852be(struct hal_info_t * hal,u32 * handled)817 static u32 hal_cmd_handler_8852be(struct hal_info_t *hal, u32 *handled)
818 {
819 u32 ret = 0;
820 struct rtw_hal_com_t *hal_com = hal->hal_com;
821
822 if (hal_com->int_array[3] & BIT_SETH2CDOK_MASK) {
823 handled[3] |= BIT_SETH2CDOK_MASK;
824 ret = 1;
825 }
826
827 return ret;
828 }
829
hal_halt_c2h_handler_8852be(struct hal_info_t * hal,u32 * handled)830 static u32 hal_halt_c2h_handler_8852be(struct hal_info_t *hal, u32 *handled)
831 {
832 u32 ret = 0;
833 #if 1
834 struct rtw_hal_com_t *hal_com = hal->hal_com;
835 if (hal_com->intr.halt_c2h_int.intr& B_AX_HALT_C2H_INT_EN) {
836 handled[0] |= B_AX_HALT_C2H_INT_EN;
837 ret = 1;
838 }
839 #endif
840 return ret;
841 }
842
hal_watchdog_timer_handler_8852be(struct hal_info_t * hal,u32 * handled)843 static u32 hal_watchdog_timer_handler_8852be(struct hal_info_t *hal, u32 *handled)
844 {
845 u32 ret = 0;
846 #if 1
847 struct rtw_hal_com_t *hal_com = hal->hal_com;
848 if (hal_com->intr.watchdog_timer_int.intr& B_AX_WDT_PTFM_INT_EN) {
849 handled[1] |= B_AX_WDT_PTFM_INT_EN;
850 ret = 1;
851 }
852 #endif
853 return ret;
854 }
855
hal_int_hdler_8852be(struct hal_info_t * hal)856 u32 hal_int_hdler_8852be(struct hal_info_t *hal)
857 {
858 u32 int_hdler_msk = 0x0;
859
860 struct rtw_hal_com_t *hal_com = hal->hal_com;
861 u32 handled[4] = {0};
862 u32 generalhandled[8] = {0};
863
864 /* <1> beacon related */
865 int_hdler_msk |= (hal_bcn_handler_8852be(hal, handled)<<0);
866
867 /* <2> Rx related */
868 int_hdler_msk |= (hal_rx_handler_8852be(hal, handled)<<1);
869
870 /* <3> Tx related */
871 int_hdler_msk |= (hal_tx_handler_8852be(hal, handled)<<2);
872
873 /* <4> Cmd related */
874 int_hdler_msk |= (hal_cmd_handler_8852be(hal, handled)<<3);
875
876 /*Start General interrupt type*/
877 /* <5> Halt C2H related */
878 int_hdler_msk |= (hal_halt_c2h_handler_8852be(hal, generalhandled)<<4);
879
880 /* <6> watchdog timer related */
881 int_hdler_msk |= (hal_watchdog_timer_handler_8852be(hal, generalhandled)<<5);
882
883 /* <7> RP related */
884 int_hdler_msk |= (hal_rp_handler_8852be(hal, handled) << 7);
885
886 PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : int_hdler_msk = 0x%x\n", __func__, int_hdler_msk);
887
888 if ((hal_com->int_array[0] & (~handled[0]))
889 || (hal_com->int_array[1] & (~handled[1]))
890 || (hal_com->int_array[2] & (~handled[2]))
891 || (hal_com->int_array[3] & (~handled[3]))) {
892 /*if (printk_ratelimit()) */
893 {
894 PHL_WARN("Unhandled ISR => %x, %x, %x, %x\nIMR : %08X\nISR : %08X\n",
895 (hal_com->int_array[0] & (~handled[0])),
896 (hal_com->int_array[1] & (~handled[1])),
897 (hal_com->int_array[2] & (~handled[2])),
898 (hal_com->int_array[3] & (~handled[3])),
899 hal_read32(hal_com, R_AX_PCIE_HIMR00),
900 hal_read32(hal_com, R_AX_PCIE_HISR00)
901 );
902 }
903 }
904
905 //General interrupt type not handled.
906 if ((hal_com->intr.halt_c2h_int.intr & (~generalhandled[0])) ||
907 (hal_com->intr.watchdog_timer_int.intr & (~generalhandled[1]))) {
908 /*if (printk_ratelimit()) */
909 {
910 PHL_WARN("Unhandled ISR => %x\nIMR : %08X\nISR : %08X,\n%x\nIMR : %08X\nISR : %08X\n",
911 (hal_com->intr.halt_c2h_int.intr & (~generalhandled[0])),
912 hal_read32(hal_com, R_AX_HIMR0),
913 hal_read32(hal_com, R_AX_HISR0),
914 (hal_com->intr.watchdog_timer_int.intr & (~generalhandled[1])),
915 hal_read32(hal_com, R_AX_HD0IMR),
916 hal_read32(hal_com, R_AX_HD0ISR));
917 }
918 }
919
920
921 return int_hdler_msk;
922 }
923
924
hal_rx_int_restore_8852be(struct hal_info_t * hal)925 void hal_rx_int_restore_8852be(struct hal_info_t *hal)
926 {
927
928 struct rtw_hal_com_t *hal_com = hal->hal_com;
929
930 hal_com->int_mask[0] |= (B_AX_RXDMA_INT_EN | B_AX_RPQDMA_INT_EN |
931 B_AX_RDU_INT_EN | B_AX_RPQBD_FULL_INT_EN);
932 #ifndef CONFIG_SYNC_INTERRUPT
933 hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
934 PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : \n%04X : %08X\n%04X : %08X\n",
935 __func__,
936 R_AX_PCIE_HIMR00, hal_read32(hal_com, R_AX_PCIE_HIMR00),
937 R_AX_PCIE_HIMR10, hal_read32(hal_com, R_AX_PCIE_HIMR10)
938 );
939 #endif /* CONFIG_SYNC_INTERRUPT */
940
941 }
942
943 enum rtw_hal_status
hal_mp_init_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)944 hal_mp_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
945 {
946 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
947 struct hal_init_info_t init_52be;
948
949 FUNCIN_WSTS(hal_status);
950
951 _os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
952
953 init_52be.ic_name = "rtl8852be";
954
955 hal_status = hal_mp_init_8852b(phl_com, hal_info, &init_52be);
956
957 FUNCOUT_WSTS(hal_status);
958 return hal_status;
959 }
960
961 enum rtw_hal_status
hal_mp_deinit_8852be(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)962 hal_mp_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
963 {
964 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
965 struct hal_init_info_t init_52be;
966
967 FUNCIN_WSTS(hal_status);
968
969 _os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
970
971 init_52be.ic_name = "rtl8852be";
972
973 hal_status = hal_mp_deinit_8852b(phl_com, hal_info, &init_52be);
974
975 if (RTW_HAL_STATUS_SUCCESS != hal_status) {
976
977 PHL_ERR("hal_mp_deinit_8852be: status = %u\n", hal_status);
978 return hal_status;
979 }
980
981 FUNCOUT_WSTS(hal_status);
982 return hal_status;
983 }
984