1 /* 2 * Driver for Rockchip Smart Card Reader Controller 3 * 4 * Copyright (C) 2012-2016 ROCKCHIP, Inc. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef __RK_SCR_H__ 17 #define __RK_SCR_H__ 18 19 /* CTRL1 bit fields */ 20 #define INVLEV BIT(0) 21 #define INVORD BIT(1) 22 #define PECH2FIFO BIT(2) 23 #define CLKSTOP BIT(6) 24 #define CLKSTOPVAL BIT(7) 25 #define TXEN BIT(8) 26 #define RXEN BIT(9) 27 #define TS2FIFO BIT(10) 28 #define T0T1 BIT(11) 29 #define ATRSTFLUSH BIT(12) 30 #define TCKEN BIT(13) 31 #define GINTEN BIT(15) 32 33 /* CTRL2 bit fields */ 34 #define WARMRST BIT(2) 35 #define ACT BIT(3) 36 #define DEACT BIT(4) 37 #define VCC18 BIT(5) 38 #define VCC33 BIT(6) 39 #define VCC50 BIT(7) 40 41 /* SCPADS bit fields */ 42 #define DIRACCPADS BIT(0) 43 #define DSCIO BIT(1) 44 #define DSCCLK BIT(2) 45 #define DSCRST BIT(3) 46 #define DSCVCC BIT(4) 47 #define AUTOADEAVPP BIT(5) 48 #define DSCVPPEN BIT(6) 49 #define DSCVPPP BIT(7) 50 #define DSCFCB BIT(8) 51 #define SCPRESENT BIT(9) 52 53 /* INTEN1 & INTSTAT1 bit fields */ 54 #define TXFIDONE BIT(0) 55 #define TXFIEMPTY BIT(1) 56 #define RXFIFULL BIT(2) 57 #define CLKSTOPRUN BIT(3) 58 #define TXDONE BIT(4) 59 #define RXDONE BIT(5) 60 #define TXPERR BIT(6) 61 #define RXPERR BIT(7) 62 #define C2CFULL BIT(8) 63 #define RXTHRESHOLD BIT(9) 64 #define ATRFAIL BIT(10) 65 #define ATRDONE BIT(11) 66 #define SCREM BIT(12) 67 #define SCINS BIT(13) 68 #define SCACT BIT(14) 69 #define SCDEACT BIT(15) 70 71 /* INTEN2 & INTSTAT2 bit fields */ 72 #define TXTHRESHOLD BIT(0) 73 #define TCLKERR BIT(1) 74 75 /* FIFOCTRL bit fields */ 76 #define FC_TXFIEMPTY BIT(0) 77 #define FC_TXFIFULL BIT(1) 78 #define FC_TXFIFLUSH BIT(2) 79 #define FC_RXFIEMPTY BIT(8) 80 #define FC_RXFIFULL BIT(9) 81 #define FC_RXFIFLUSH BIT(10) 82 83 /* FIFO_DEPTH must >= 2 */ 84 #define FIFO_DEPTH 32 85 #define MAX_RXTHR (3 * FIFO_DEPTH / 4) 86 #define MAX_TXTHR (256) /* at least, one less than FIFO_DEPTH */ 87 88 #define RK_SCR_NUM (2) 89 #define SMC_ATR_MAX_LENGTH (512) 90 #define SMC_ATR_MIN_LENGTH (2) 91 92 #define SMC_SUCCESSFUL (0) 93 #define SMC_ERROR_CARD_NOT_INSERT BIT(0) 94 #define SMC_ERROR_NO_ANSWER BIT(1) 95 #define SMC_ERROR_TX_ERR BIT(2) 96 #define SMC_ERROR_RX_ERR BIT(3) 97 #define SMC_ERROR_CONFLICT_ERR BIT(4) 98 #define SMC_ERROR_WRITE_FULL_RECV_FIFO_ERR BIT(5) 99 #define SMC_ERROR_BWT_ERR BIT(6) 100 #define SMC_ERROR_CWT_ERR BIT(7) 101 #define SMC_ERROR_BAD_PARAMETER BIT(8) 102 #define SMC_ERROR_ATR_ERR BIT(9) 103 #define SMC_ERROR_NO_MEMERY BIT(10) 104 #define SMC_ERROR_TIMEOUT BIT(11) 105 106 enum { 107 SC_DRV_INT_CARDOUT = 0, 108 SC_DRV_INT_CARDIN 109 }; 110 111 /* card convention */ 112 enum { 113 SC_CONV_DIRECT = 0, 114 SC_CONV_INVERSE = 1 115 }; 116 117 enum { 118 SC_CARD_INDEX_0 = 0, 119 SC_CARD_INDEX_1 = 1 120 }; 121 122 /* card protocol */ 123 enum { 124 SC_PROTOCOL_INVALID = -1, 125 SC_PROTOCOL_T0 = 0, 126 SC_PROTOCOL_T1 = 1, 127 SC_PROTOCOL_T14 = 14 128 }; 129 130 /* enumerated constants */ 131 enum status_code_e { 132 SUCCESSFUL = 0, /* successful completion */ 133 TASK_EXITTED = 1, /* returned from a thread */ 134 MP_NOT_CONFIGURED = 2, /* multiprocessing not configured */ 135 INVALID_NAME = 3, /* invalid object name */ 136 INVALID_ID = 4, /* invalid object id */ 137 TOO_MANY = 5, /* too many */ 138 TIMEOUT = 6, /* timed out waiting */ 139 OBJECT_WAS_DELETED = 7, /* object deleted while waiting */ 140 INVALID_SIZE = 8, /* specified size was invalid */ 141 INVALID_ADDRESS = 9, /* address specified is invalid */ 142 INVALID_NUMBER = 10, /* number was invalid */ 143 NOT_DEFINED = 11, /* item has not been initialized */ 144 RESOURCE_IN_USE = 12, /* resources still outstanding */ 145 UNSATISFIED = 13, /* request not satisfied */ 146 INCORRECT_STATE = 14, /* thread is in wrong state */ 147 ALREADY_SUSPENDED = 15, /* thread already in state */ 148 ILLEGAL_ON_SELF = 16, /* illegal on calling thread */ 149 ILLEGAL_ON_REMOTE_OBJECT = 17, /* illegal for remote object */ 150 CALLED_FROM_ISR = 18, /* called from wrong environment */ 151 INVALID_PRIORITY = 19, /* invalid thread priority */ 152 INVALID_CLOCK = 20, /* invalid date/time */ 153 INVALID_NODE = 21, /* invalid node id */ 154 NOT_CONFIGURED = 22, /* directive not configured */ 155 NOT_OWNER_OF_RESOURCE = 23, /* not owner of resource */ 156 NOT_IMPLEMENTED = 24, /* directive not implemented */ 157 INTERNAL_ERROR = 25, /* inconsistency detected */ 158 NO_MEMORY = 26, /* could not get enough memory */ 159 IO_ERROR = 27, /* driver IO error */ 160 PROXY_BLOCKING = 28 /* internal error only */ 161 }; 162 163 struct scr_reg_t { 164 unsigned int CTRL1; /* Control Reg 1 */ 165 unsigned int CTRL2; /* Control Reg 2 */ 166 unsigned int SCPADS; /* Direct access to Smart Card pads*/ 167 unsigned int INTEN1; /* Interrupt Enable Reg 1 */ 168 unsigned int INTSTAT1; /* Interrupt Status Reg 1 */ 169 unsigned int FIFOCTRL; /* FIFO control register */ 170 unsigned int LGCYCNT; /* Legacy TX & RX FIFO Counter */ 171 unsigned int RXFIFOTH; /* RXFIFO threshold */ 172 unsigned int REPEAT; /* 173 * number of repeating after 174 * unsuccessful transaction 175 */ 176 unsigned int CGSCDIV; /* SmartCard clock divisor */ 177 unsigned int CGBITDIV; /* Bit clock divisor */ 178 unsigned int SCGT; /* SmartCard GuardTime */ 179 unsigned int ADEATIME; /* Activation/deactivation time (cc)*/ 180 unsigned int LOWRSTTIME; /* 181 * Duration of low state during 182 * Smart Card reset sequence 183 */ 184 unsigned int ATRSTARTLIMIT; /* ATR start limit */ 185 unsigned int C2CLIM; /* 186 * leading edge to leading edge of two 187 * consecutive characters delay limit 188 */ 189 unsigned int INTEN2; /* Interrupt Enable Reg 2 */ 190 unsigned int INTSTAT2; /* Interrupt Status R */ 191 unsigned int TXFIFOTH; /* TXFIFO threshold */ 192 unsigned int TXFIFOCNT; /* TXFIFO counter */ 193 unsigned int RXFIFOCNT; /* RXFIFO counter */ 194 unsigned int CGBITTUNE; /* Bit tune register */ 195 unsigned int reserved[0x200 / 4]; 196 unsigned int FIFODATA; /* 197 * FIFODATA space start 198 * - RX FIFO and TX FIFO 199 */ 200 }; 201 202 enum hal_scr_id_e { 203 HAL_SCR_ID0 = 0, 204 HAL_SCR_ID1, 205 HAL_SCR_ID_MAX 206 }; 207 208 enum hal_scr_clock_stop_mode_e { 209 /* Continuous clock mode, the autostop is disabled */ 210 HAL_SCR_CLOCK_NO_STOP, 211 /* Automatic clock stop mode, stopped at low-level */ 212 HAL_SCR_CLOCK_STOP_L, 213 /* Automatic clock stop mode, stopped at high-level */ 214 HAL_SCR_CLOCK_STOP_H 215 }; 216 217 enum hal_scr_etu_duration_e { 218 /* F and D to default value F=372, D=1 */ 219 HAL_SCR_ETU_F_372_AND_D_1, 220 /* F=512 and D=8 */ 221 HAL_SCR_ETU_F_512_AND_D_8, 222 /* F=512 and D=4 */ 223 HAL_SCR_ETU_F_512_AND_D_4 224 }; 225 226 struct hal_scr_irq_status_t { 227 /* When the reset time-outs. */ 228 unsigned char reset_timeout; 229 /* When a parity error occurs. */ 230 unsigned char parity_error; 231 /* When a bad ts character is received. */ 232 unsigned char bad_ts; 233 /* When the auto-reset is successful. */ 234 unsigned char atr_success; 235 /* When a rx transfer has been finished */ 236 unsigned char rx_success; 237 /* When an auto-reset has been started. */ 238 unsigned char atr_start; 239 /* When a work waiting time factor time-outs. */ 240 unsigned char wwt_timeout; 241 /* 242 * When the number of received character exceeds the 243 * number of awaited bytes:1; (set in the SCI Rx counter register) 244 */ 245 unsigned char extra_rx; 246 }; 247 248 /*check card is in or out*/ 249 enum hal_scr_detect_status_e { 250 SMC_DRV_INT_CARDOUT = 0, 251 SMC_DRV_INT_CARDIN 252 }; 253 254 enum hal_scr_irq_cause_e { 255 HAL_SCR_RESET_TIMEOUT, 256 HAL_SCR_PARITY_ERROR, 257 HAL_SCR_BAD_TS, 258 HAL_SCR_ATR_SUCCESS, 259 HAL_SCR_RX_SUCCESS, 260 HAL_SCR_WWT_TIMEOUT, 261 HAL_SCR_EXTRA_RX, 262 HAL_SCR_IRQ_INVALID = 0x0fffffff 263 }; 264 265 enum hal_scr_voltage_e { 266 /* 5V */ 267 HAL_SCR_VOLTAGE_CLASS_A, 268 /* 3V */ 269 HAL_SCR_VOLTAGE_CLASS_B, 270 /* 1.8V */ 271 HAL_SCR_VOLTAGE_CLASS_C, 272 /* 0V */ 273 HAL_SCR_VOLTAGE_NULL 274 }; 275 276 /* card protocol */ 277 enum { 278 SMC_PROTOCOL_INVALID = -1, 279 SMC_PROTOCOL_T0 = 0, 280 SMC_PROTOCOL_T1 = 1, 281 SMC_PROTOCOL_T14 = 14 282 }; 283 284 /* card convention */ 285 enum { 286 SMC_CONV_DIRECT = 0, 287 SMC_CONV_INVERSE = 1 288 }; 289 290 /*card index*/ 291 enum { 292 SMC_CARD_INDEX_0 = 0, 293 SMC_CARD_INDEX_1 = 1 294 }; 295 296 typedef void (*hal_scr_irq_handler_t) (enum hal_scr_irq_cause_e); 297 298 struct scr_chip_info { 299 struct scr_reg_t *reg_base; 300 int irq; 301 const char *clk_name; 302 }; 303 304 struct rk_scr { 305 const struct scr_chip_info *hw; 306 struct clk *clk; 307 hal_scr_irq_handler_t user_handler; 308 struct hal_scr_irq_status_t user_mask; 309 bool is_open; 310 bool is_active; 311 bool in_process; 312 313 unsigned char *rx_buf; 314 unsigned int rx_expected; 315 unsigned int rx_cnt; 316 const unsigned char *tx_buf; 317 unsigned int tx_expected; 318 unsigned int tx_cnt; 319 unsigned int F; 320 unsigned int D; 321 struct notifier_block freq_changed_notifier; 322 }; 323 324 #endif /* __RK_SCR_H__ */ 325