1 /******************************************************************************
2 *
3 * Copyright(c) 2019 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_PCI_C_
16 #include "hal_headers.h"
17
18 #ifdef CONFIG_PCI_HCI
pci_read8(struct rtw_hal_com_t * hal,u32 addr)19 static u8 pci_read8(struct rtw_hal_com_t *hal, u32 addr)
20 {
21 return _os_read8_pcie(hal->drv_priv, addr);
22 }
pci_read16(struct rtw_hal_com_t * hal,u32 addr)23 static u16 pci_read16(struct rtw_hal_com_t *hal, u32 addr)
24 {
25 return _os_read16_pcie(hal->drv_priv, addr);
26 }
pci_read32(struct rtw_hal_com_t * hal,u32 addr)27 static u32 pci_read32(struct rtw_hal_com_t *hal, u32 addr)
28 {
29 return _os_read32_pcie(hal->drv_priv, addr);
30 }
31
pci_write8(struct rtw_hal_com_t * hal,u32 addr,u8 val)32 static int pci_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val)
33 {
34 return _os_write8_pcie(hal->drv_priv, addr, val);
35 }
pci_write16(struct rtw_hal_com_t * hal,u32 addr,u16 val)36 static int pci_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val)
37 {
38 return _os_write16_pcie(hal->drv_priv, addr, val);
39 }
pci_write32(struct rtw_hal_com_t * hal,u32 addr,u32 val)40 static int pci_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val)
41 {
42 return _os_write32_pcie(hal->drv_priv, addr, val);
43 }
44 #ifdef RTW_WKARD_BUS_WRITE
pci_write_post_cfg(struct rtw_hal_com_t * hal,u32 addr,u32 val)45 static int pci_write_post_cfg(struct rtw_hal_com_t *hal, u32 addr, u32 val)
46 {
47 struct hal_info_t *hal_info = hal->hal_priv;
48 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
49
50 enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
51
52 if(NULL != hal_ops->write_reg_post_cfg) {
53 hal_status = hal_ops->write_reg_post_cfg(hal_info, addr, val);
54 }
55
56 return hal_status;
57 }
58 #endif
hal_pci_set_io_ops(struct rtw_hal_com_t * hal,struct hal_io_ops * pops)59 void hal_pci_set_io_ops(struct rtw_hal_com_t *hal, struct hal_io_ops *pops)
60 {
61 /*_rtw_memset((u8 *)pops, 0, sizeof(struct hal_io_ops));*/
62 _os_mem_set(hal->drv_priv, (u8 *)pops, 0, sizeof(struct hal_io_ops));
63
64 pops->_read8 = &pci_read8;
65 pops->_read16 = &pci_read16;
66 pops->_read32 = &pci_read32;
67
68 pops->_write8 = &pci_write8;
69 pops->_write16 = &pci_write16;
70 pops->_write32 = &pci_write32;
71 #ifdef RTW_WKARD_BUS_WRITE
72 pops->_write_post_cfg = &pci_write_post_cfg;
73 #endif
74 }
75
rtw_hal_set_l2_leave(void * hal)76 enum rtw_hal_status rtw_hal_set_l2_leave(void *hal)
77 {
78 enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
79 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
80
81 /* Only AON registers are accessed */
82 status = hal_mac_set_l2_leave(hal_info);
83
84 if (status != RTW_HAL_STATUS_SUCCESS) {
85 PHL_ERR("%s : fail\n", __func__);
86 }
87 return status;
88 }
rtw_hal_clear_bdidx(void * hal)89 void rtw_hal_clear_bdidx(void *hal)
90 {
91 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
92
93 FUNCIN();
94
95 if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_clr_bdidx(hal_info))
96 PHL_ERR("%s failure \n", __func__);
97 }
98
rtw_hal_rst_bdram(void * hal)99 void rtw_hal_rst_bdram(void *hal)
100 {
101 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
102
103 FUNCIN();
104
105 if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_rst_bdram(hal_info))
106 PHL_ERR("%s failure \n", __func__);
107
108 }
rtw_hal_cfg_dma_io(void * hal,u8 en)109 void rtw_hal_cfg_dma_io(void *hal, u8 en)
110 {
111 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
112
113 PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %u.\n", __func__, en);
114
115 if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_dma_io(hal_info, en))
116 PHL_ERR("%s failure \n", __func__);
117 }
118
119 #ifdef RTW_WKARD_DYNAMIC_LTR
120 enum rtw_hal_status
rtw_hal_ltr_en_hw_mode(void * hal,bool hw_mode)121 rtw_hal_ltr_en_hw_mode(void *hal, bool hw_mode)
122 {
123 enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
124 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
125
126 status = rtw_hal_mac_ltr_set_pcie(hal_info,
127 hw_mode ? RTW_PCIE_BUS_FUNC_ENABLE : RTW_PCIE_BUS_FUNC_DISABLE,
128 0, 0, 0, 0);
129
130 if (status != RTW_HAL_STATUS_SUCCESS) {
131 PHL_ERR("%s : fail\n", __func__);
132 return status;
133 }
134
135 return status;
136 }
137
138 enum rtw_hal_status
rtw_hal_ltr_sw_trigger(void * hal,enum rtw_pcie_ltr_state state)139 rtw_hal_ltr_sw_trigger(void *hal, enum rtw_pcie_ltr_state state)
140 {
141 enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
142 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
143
144 status = rtw_hal_mac_ltr_sw_trigger(hal_info, state);
145
146 if (status != RTW_HAL_STATUS_SUCCESS)
147 PHL_ERR("%s : fail\n", __func__);
148
149 return status;
150 }
151
rtw_hal_ltr_update_stats(void * hal,bool clear)152 void rtw_hal_ltr_update_stats(void *hal, bool clear)
153 {
154 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
155 struct rtw_trx_stat *trx_stat = &hal_info->hal_com->trx_stat;
156 static u32 dly_start_time = 0;
157
158 if(clear) {
159 dly_start_time = 0;
160 } else {
161 /* first in */
162 if (dly_start_time == 0) {
163 dly_start_time = _os_get_cur_time_us();
164 trx_stat->ltr_last_tx_dly_time = 0;
165 }
166 trx_stat->ltr_tx_dly_count++;
167 trx_stat->ltr_last_tx_dly_time =
168 phl_get_passing_time_us(dly_start_time);
169 }
170 }
171
rtw_hal_ltr_is_sw_ctrl(struct rtw_phl_com_t * phl_com,void * hal)172 bool rtw_hal_ltr_is_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal)
173 {
174 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
175 struct bus_cap_t *bus_cap = &hal_info->hal_com->bus_cap;
176
177 return bus_cap->ltr_sw_ctrl ?
178 (phl_com->bus_sw_cap.ltr_sw_ctrl ? true : false) : false;
179 }
180
rtw_hal_ltr_is_hw_ctrl(struct rtw_phl_com_t * phl_com,void * hal)181 bool rtw_hal_ltr_is_hw_ctrl(struct rtw_phl_com_t *phl_com, void *hal)
182 {
183 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
184 struct bus_cap_t *bus_cap = &hal_info->hal_com->bus_cap;
185
186 return bus_cap->ltr_hw_ctrl ?
187 (phl_com->bus_sw_cap.ltr_hw_ctrl ? true : false) : false;
188 }
189
190 #endif
191 #endif /*CONFIG_PCI_HCI*/
192