xref: /rockchip-linux_mpp/mpp/hal/vpu/m2vd/hal_m2vd_api.c (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1 /*
2  * Copyright 2015 Rockchip Electronics Co. LTD
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #define MODULE_TAG "hal_m2vd_api"
18 
19 #include <string.h>
20 
21 #include "mpp_env.h"
22 
23 #include "mpp_platform.h"
24 #include "hal_m2vd_base.h"
25 #include "hal_m2vd_vpu1.h"
26 #include "hal_m2vd_vpu2.h"
27 
28 RK_U32 m2vh_debug = 0;
29 
hal_m2vd_gen_regs(void * hal,HalTaskInfo * task)30 static MPP_RET hal_m2vd_gen_regs(void *hal, HalTaskInfo *task)
31 {
32     M2vdHalCtx *self = (M2vdHalCtx *)hal;
33     return self->hal_api.reg_gen (hal, task);
34 }
35 
hal_m2vd_start(void * hal,HalTaskInfo * task)36 static MPP_RET hal_m2vd_start(void *hal, HalTaskInfo *task)
37 {
38     M2vdHalCtx *self = (M2vdHalCtx *)hal;
39     return self->hal_api.start(hal, task);
40 }
41 
hal_m2vd_wait(void * hal,HalTaskInfo * task)42 static MPP_RET hal_m2vd_wait(void *hal, HalTaskInfo *task)
43 {
44     M2vdHalCtx *self = (M2vdHalCtx *)hal;
45     return self->hal_api.wait(hal, task);
46 }
47 
hal_m2vd_deinit(void * hal)48 static MPP_RET hal_m2vd_deinit(void *hal)
49 {
50     M2vdHalCtx *self = (M2vdHalCtx *)hal;
51     return self->hal_api.deinit(hal);
52 }
53 
hal_m2vd_init(void * hal,MppHalCfg * cfg)54 static MPP_RET hal_m2vd_init (void *hal, MppHalCfg *cfg)
55 {
56     M2vdHalCtx *self = (M2vdHalCtx *)hal;
57     MppHalApi *p_api = NULL;
58     VpuHwMode hw_mode = MODE_NULL;
59     RK_U32 hw_flag = 0;
60 
61     if (self == NULL)
62         return MPP_ERR_VALUE;
63     memset(self, 0, sizeof(M2vdHalCtx));
64 
65     p_api = &self->hal_api;
66 
67     mpp_env_get_u32("m2vh_debug", &m2vh_debug, 0);
68 
69     hw_flag = mpp_get_vcodec_type();
70     if (hw_flag & HAVE_VDPU1)
71         hw_mode = VDPU1_MODE;
72     if (hw_flag & HAVE_VDPU2)
73         hw_mode = VDPU2_MODE;
74 
75     switch (hw_mode) {
76     case VDPU2_MODE:
77         p_api->init = hal_m2vd_vdpu2_init;
78         p_api->deinit = hal_m2vd_vdpu2_deinit;
79         p_api->reg_gen = hal_m2vd_vdpu2_gen_regs;
80         p_api->start = hal_m2vd_vdpu2_start;
81         p_api->wait = hal_m2vd_vdpu2_wait;
82         p_api->reset = NULL;
83         p_api->flush = NULL;
84         p_api->control = NULL;
85         break;
86     case VDPU1_MODE:
87         p_api->init = hal_m2vd_vdpu1_init;
88         p_api->deinit = hal_m2vd_vdpu1_deinit;
89         p_api->reg_gen = hal_m2vd_vdpu1_gen_regs;
90         p_api->start = hal_m2vd_vdpu1_start;
91         p_api->wait = hal_m2vd_vdpu1_wait;
92         p_api->reset = NULL;
93         p_api->flush = NULL;
94         p_api->control = NULL;
95         break;
96     default:
97         mpp_err("unknow vpu mode %d.", hw_mode);
98         return MPP_ERR_INIT;
99     }
100 
101     return p_api->init(hal, cfg);;
102 }
103 
104 const MppHalApi hal_api_m2vd = {
105     .name = "m2vd_vdpu",
106     .type = MPP_CTX_DEC,
107     .coding = MPP_VIDEO_CodingMPEG2,
108     .ctx_size = sizeof(M2vdHalCtx),
109     .flag = 0,
110     .init = hal_m2vd_init,
111     .deinit = hal_m2vd_deinit,
112     .reg_gen = hal_m2vd_gen_regs,
113     .start = hal_m2vd_start,
114     .wait = hal_m2vd_wait,
115     .reset = NULL,
116     .flush = NULL,
117     .control = NULL,
118 };
119