1 /*
2 * Copyright 2021 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h265e_v580"
18
19 #include <string.h>
20 #include <math.h>
21 #include <limits.h>
22
23 #include "mpp_env.h"
24 #include "mpp_mem.h"
25 #include "mpp_soc.h"
26 #include "mpp_common.h"
27 #include "mpp_frame_impl.h"
28 #include "mpp_packet_impl.h"
29
30 #include "hal_h265e_debug.h"
31 #include "h265e_syntax_new.h"
32 #include "hal_bufs.h"
33 #include "rkv_enc_def.h"
34 #include "vepu541_common.h"
35 #include "vepu5xx_common.h"
36 #include "hal_h265e_vepu580.h"
37 #include "hal_h265e_vepu580_reg.h"
38 #include "mpp_enc_cb_param.h"
39 #include "vepu5xx.h"
40
41 #include "mpp_service.h"
42
43 #define MAX_TILE_NUM 4
44
45 #define hal_h265e_err(fmt, ...) \
46 do {\
47 mpp_err_f(fmt, ## __VA_ARGS__);\
48 } while (0)
49
50 typedef struct vepu580_h265_fbk_t {
51 RK_U32 hw_status; /* 0:corret, 1:error */
52 RK_U32 qp_sum;
53 RK_U32 out_strm_size;
54 RK_U32 out_hw_strm_size;
55 RK_S64 sse_sum;
56 RK_U32 st_lvl64_inter_num;
57 RK_U32 st_lvl32_inter_num;
58 RK_U32 st_lvl16_inter_num;
59 RK_U32 st_lvl8_inter_num;
60 RK_U32 st_lvl32_intra_num;
61 RK_U32 st_lvl16_intra_num;
62 RK_U32 st_lvl8_intra_num;
63 RK_U32 st_lvl4_intra_num;
64 RK_U32 st_cu_num_qp[52];
65 RK_U32 st_madp;
66 RK_U32 st_madi;
67 RK_U32 st_md_sad_b16num0;
68 RK_U32 st_md_sad_b16num1;
69 RK_U32 st_md_sad_b16num2;
70 RK_U32 st_md_sad_b16num3;
71 RK_U32 st_madi_b16num0;
72 RK_U32 st_madi_b16num1;
73 RK_U32 st_madi_b16num2;
74 RK_U32 st_madi_b16num3;
75 RK_U32 st_mb_num;
76 RK_U32 st_ctu_num;
77 } vepu580_h265_fbk;
78
79 typedef struct Vepu580RoiH265BsCfg_t {
80 RK_U8 amv_en : 1;
81 RK_U8 qp_adj : 1;
82 RK_U8 force_split : 1;
83 RK_U8 force_intra : 2;
84 RK_U8 force_inter : 2;
85 } Vepu580RoiH265BsCfg;
86
87 typedef struct H265eV580HalContext_t {
88 MppEncHalApi api;
89 MppDev dev;
90 void *regs[MAX_TILE_NUM];
91 void *reg_out[MAX_TILE_NUM];
92
93 vepu580_h265_fbk feedback;
94 void *dump_files;
95 RK_U32 frame_cnt_gen_ready;
96
97 RK_S32 frame_type;
98 RK_S32 last_frame_type;
99
100 /* @frame_cnt starts from ZERO */
101 RK_U32 frame_cnt;
102 Vepu541OsdCfg osd_cfg;
103 MppDevRegOffCfgs *reg_cfg;
104 void *roi_data;
105 RkvRoiCfg_v2 *roi_cfg_tmp;
106 MppBufferGroup roi_grp;
107 MppBuffer roi_base_cfg_buf;
108 void *roi_base_cfg_sw_buf;
109 RK_S32 roi_base_buf_size;
110 MppEncCfgSet *cfg;
111
112 MppBufferGroup tile_grp;
113 MppBuffer hw_tile_buf[MAX_TILE_NUM];
114 MppBuffer hw_tile_stream[MAX_TILE_NUM - 1];
115 MppBuffer buf_pass1;
116
117 RK_U32 enc_mode;
118 RK_U32 frame_size;
119 RK_S32 max_buf_cnt;
120 RK_S32 hdr_status;
121 void *input_fmt;
122 RK_U8 *src_buf;
123 RK_U8 *dst_buf;
124 RK_S32 buf_size;
125 RK_U32 frame_num;
126 HalBufs dpb_bufs;
127 RK_S32 fbc_header_len;
128 RK_U32 tile_num;
129 RK_U32 tile_parall_en;
130 RK_U32 tile_dump_err;
131
132 RK_S32 poll_slice_max;
133 RK_S32 poll_cfg_size;
134 MppDevPollCfg *poll_cfgs;
135 MppCbCtx *output_cb;
136
137 /* finetune */
138 void *tune;
139 } H265eV580HalContext;
140
141 #define TILE_BUF_SIZE MPP_ALIGN(128 * 1024, 256)
142
143 static RK_U32 klut_weight[24] = {
144 0x50800080, 0x00330000, 0xA1000100, 0x00660000, 0x42000200, 0x00CC0001,
145 0x84000400, 0x01980002, 0x08000800, 0x03300005, 0x10001000, 0x0660000A,
146 0x20002000, 0x0CC00014, 0x40004000, 0x19800028, 0x80008000, 0x33000050,
147 0x00010000, 0x660000A1, 0x00020000, 0xCC000142, 0xFF83FFFF, 0x000001FF
148 };
149
150 static RK_U32 aq_thd_default[16] = {
151 0, 0, 0, 0,
152 3, 3, 5, 5,
153 8, 8, 8, 15,
154 15, 20, 25, 35
155 };
156
157 static RK_U32 h265e_mode_bias[16] = {
158 0, 2, 4, 6,
159 8, 10, 12, 14,
160 16, 18, 20, 24,
161 28, 32, 64, 128
162 };
163
164 static RK_S32 aq_qp_dealt_default[16] = {
165 -8, -7, -6, -5,
166 -4, -2, -1, -1,
167 0, 2, 3, 4,
168 5, 7, 8, 9,
169 };
170
171 static RK_U16 lvl32_intra_cst_thd[4] = {2, 6, 16, 36};
172
173 static RK_U16 lvl16_intra_cst_thd[4] = {2, 6, 16, 36};
174
175 static RK_U8 lvl32_intra_cst_wgt[8] = {23, 22, 21, 20, 22, 24, 26};
176
177 static RK_U8 lvl16_intra_cst_wgt[8] = {17, 17, 17, 18, 17, 18, 18};
178
179 static RK_U32 lamd_satd_qp[52] = {
180 0x00000183, 0x000001b2, 0x000001e7, 0x00000223, 0x00000266, 0x000002b1, 0x00000305, 0x00000364,
181 0x000003ce, 0x00000445, 0x000004cb, 0x00000562, 0x0000060a, 0x000006c8, 0x0000079c, 0x0000088b,
182 0x00000996, 0x00000ac3, 0x00000c14, 0x00000d8f, 0x00000f38, 0x00001115, 0x0000132d, 0x00001586,
183 0x00001829, 0x00001b1e, 0x00001e70, 0x0000222b, 0x0000265a, 0x00002b0c, 0x00003052, 0x0000363c,
184 0x00003ce1, 0x00004455, 0x00004cb4, 0x00005618, 0x000060a3, 0x00006c79, 0x000079c2, 0x000088ab,
185 0x00009967, 0x0000ac30, 0x0000c147, 0x0000d8f2, 0x0000f383, 0x00011155, 0x000132ce, 0x00015861,
186 0x0001828d, 0x0001b1e4, 0x0001e706, 0x000222ab
187 };
188
189 static RK_U32 lamd_moda_qp[52] = {
190 0x00000049, 0x0000005c, 0x00000074, 0x00000092, 0x000000b8, 0x000000e8, 0x00000124, 0x00000170,
191 0x000001cf, 0x00000248, 0x000002df, 0x0000039f, 0x0000048f, 0x000005bf, 0x0000073d, 0x0000091f,
192 0x00000b7e, 0x00000e7a, 0x0000123d, 0x000016fb, 0x00001cf4, 0x0000247b, 0x00002df6, 0x000039e9,
193 0x000048f6, 0x00005bed, 0x000073d1, 0x000091ec, 0x0000b7d9, 0x0000e7a2, 0x000123d7, 0x00016fb2,
194 0x0001cf44, 0x000247ae, 0x0002df64, 0x00039e89, 0x00048f5c, 0x0005bec8, 0x00073d12, 0x00091eb8,
195 0x000b7d90, 0x000e7a23, 0x00123d71, 0x0016fb20, 0x001cf446, 0x00247ae1, 0x002df640, 0x0039e88c,
196 0x0048f5c3, 0x005bec81, 0x0073d119, 0x0091eb85
197 };
198
199 static RK_U32 lamd_modb_qp[52] = {
200 0x00000070, 0x00000089, 0x000000b0, 0x000000e0, 0x00000112, 0x00000160, 0x000001c0, 0x00000224,
201 0x000002c0, 0x00000380, 0x00000448, 0x00000580, 0x00000700, 0x00000890, 0x00000b00, 0x00000e00,
202 0x00001120, 0x00001600, 0x00001c00, 0x00002240, 0x00002c00, 0x00003800, 0x00004480, 0x00005800,
203 0x00007000, 0x00008900, 0x0000b000, 0x0000e000, 0x00011200, 0x00016000, 0x0001c000, 0x00022400,
204 0x0002c000, 0x00038000, 0x00044800, 0x00058000, 0x00070000, 0x00089000, 0x000b0000, 0x000e0000,
205 0x00112000, 0x00160000, 0x001c0000, 0x00224000, 0x002c0000, 0x00380000, 0x00448000, 0x00580000,
206 0x00700000, 0x00890000, 0x00b00000, 0x00e00000
207 };
208
209 #include "hal_h265e_vepu580_tune.c"
210
vepu580_h265_set_me_ram(H265eSyntax_new * syn,hevc_vepu580_base * regs,RK_U32 index)211 static void vepu580_h265_set_me_ram(H265eSyntax_new *syn, hevc_vepu580_base *regs, RK_U32 index)
212 {
213 RK_S32 frm_sta = 0, frm_end = 0, pic_w = 0;
214 RK_S32 srch_w = regs->reg0220_me_rnge.cme_srch_h * 4;
215 RK_S32 srch_h = regs->reg0220_me_rnge.cme_srch_v * 4;
216 RK_S32 x_gmv = regs->reg0224_gmv.gmv_x;
217 RK_S32 y_gmv = regs->reg0224_gmv.gmv_y;
218 RK_U32 pic_wd64 = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64;
219
220 if (!syn->pp.tiles_enabled_flag) {
221 if (x_gmv - srch_w < 0) {
222 frm_sta = (x_gmv - srch_w - 15) / 16;
223 } else {
224 frm_sta = (x_gmv - srch_w) / 16;
225 }
226 frm_sta = mpp_clip(frm_sta, 0, pic_wd64 - 1);
227 if (x_gmv + srch_w < 0) {
228 frm_end = pic_wd64 - 1 + (x_gmv + srch_w) / 16;
229 } else {
230 frm_end = pic_wd64 - 1 + (x_gmv + srch_w + 15) / 16;
231 }
232 frm_end = mpp_clip(frm_end, 0, pic_wd64 - 1);
233 } else {
234 RK_S32 tile_ctu_stax = index * pic_wd64 / (syn->pp.num_tile_columns_minus1 + 1);
235 RK_S32 tile_ctu_endx = 0;
236
237 if (index == syn->pp.num_tile_columns_minus1) {
238 tile_ctu_endx = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 - 1;
239 } else {
240 tile_ctu_endx = (index + 1) * pic_wd64 / (syn->pp.num_tile_columns_minus1 + 1) - 1;
241 }
242
243 if (x_gmv - srch_w < 0) {
244 frm_sta = tile_ctu_stax + (x_gmv - srch_w - 15) / 16;
245 } else {
246 frm_sta = tile_ctu_stax + (x_gmv - srch_w) / 16;
247 }
248 frm_sta = mpp_clip(frm_sta, 0, pic_wd64 - 1);
249
250 if (x_gmv + srch_w < 0) {
251 frm_end = tile_ctu_endx + (x_gmv + srch_w) / 16;
252 } else {
253 frm_end = tile_ctu_endx + (x_gmv + srch_w + 15) / 16;
254 }
255 frm_end = mpp_clip(frm_end, 0, pic_wd64 - 1);
256 }
257 pic_w = (frm_end - frm_sta + 1) * 64;
258 regs->reg0222_me_cach.cme_linebuf_w = (pic_w ? pic_w : 64) / 64;
259 {
260 RK_U32 cime_rama_max = 2464;
261 RK_U32 ctu_4_h = 4, ramb_h;
262 RK_U32 cur_srch_16_w, cur_srch_4_h, cur_srch_max;
263 RK_U32 cime_rama_h = ctu_4_h;
264
265 if ((x_gmv % 16 - srch_w % 16) < 0) {
266 cur_srch_16_w = (16 + (x_gmv % 16 - srch_w % 16) % 16 + srch_w * 2 + 15) / 16 + 1;
267 } else {
268 cur_srch_16_w = ((x_gmv % 16 - srch_w % 16) % 16 + srch_w * 2 + 15) / 16 + 1;
269 }
270 if ((y_gmv % 4 - srch_h % 4) < 0) {
271 cur_srch_4_h = (4 + (y_gmv % 4 - srch_h % 4) % 4 + srch_h * 2 + 3) / 4 + ctu_4_h;
272 } else {
273 cur_srch_4_h = ((y_gmv % 4 - srch_h % 4) % 4 + srch_h * 2 + 3) / 4 + ctu_4_h;
274 }
275 cur_srch_max = MPP_ALIGN(cur_srch_4_h, 4);
276 if (regs->reg0222_me_cach.cme_linebuf_w < cur_srch_16_w) {
277 cur_srch_16_w = regs->reg0222_me_cach.cme_linebuf_w;
278 }
279 ramb_h = cur_srch_4_h;
280 while ((cime_rama_h < cur_srch_max) && (cime_rama_max >
281 ((cime_rama_h - ctu_4_h) * regs->reg0222_me_cach.cme_linebuf_w * 4 + (ramb_h * 4 * cur_srch_16_w)))) {
282 cime_rama_h = cime_rama_h + ctu_4_h;
283 if (ramb_h > 2 * ctu_4_h) {
284 ramb_h = ramb_h - ctu_4_h;
285 } else {
286 ramb_h = ctu_4_h;
287 }
288 }
289 if (cur_srch_4_h == ctu_4_h) {
290 cime_rama_h = cime_rama_h + ctu_4_h;
291 ramb_h = 0;
292 }
293 if (cime_rama_max < ((cime_rama_h - ctu_4_h) * regs->reg0222_me_cach.cme_linebuf_w * 4 + (ramb_h * 4 * cur_srch_16_w))) {
294 cime_rama_h = cime_rama_h - ctu_4_h;
295 }
296 regs->reg0222_me_cach.cme_rama_h = cime_rama_h; /* cime_rama_max */
297
298 {
299 RK_U32 ram_col_h = (cime_rama_h - ctu_4_h) / ctu_4_h;
300 regs->reg0222_me_cach.cme_rama_max = ram_col_h * regs->reg0222_me_cach.cme_linebuf_w + cur_srch_16_w;
301 }
302
303 }
304
305 hal_h265e_dbg_detail("cime_rama_h %d, cime_rama_max %d, cime_linebuf_w %d",
306 regs->reg0222_me_cach.cme_rama_h, regs->reg0222_me_cach.cme_rama_max, regs->reg0222_me_cach.cme_linebuf_w);
307 }
308
vepu580_h265_setup_hal_bufs(H265eV580HalContext * ctx)309 static MPP_RET vepu580_h265_setup_hal_bufs(H265eV580HalContext *ctx)
310 {
311 MPP_RET ret = MPP_OK;
312 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
313 RK_U32 frame_size;
314 RK_S32 mb_wd64, mb_h64;
315 MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
316 MppEncPrepCfg *prep = &ctx->cfg->prep;
317 RK_S32 old_max_cnt = ctx->max_buf_cnt;
318 RK_S32 new_max_cnt = 2;
319
320 hal_h265e_enter();
321
322 mb_wd64 = (prep->width + 63) / 64;
323 mb_h64 = (prep->height + 63) / 64 + 1;
324
325 frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
326 vepu541_set_fmt(fmt, ctx->cfg->prep.format);
327
328 if (ref_cfg) {
329 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
330 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
331 }
332
333 if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
334 size_t size[3] = {0};
335
336 hal_bufs_deinit(ctx->dpb_bufs);
337 hal_bufs_init(&ctx->dpb_bufs);
338
339 ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
340 size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
341 size[1] = (mb_wd64 * mb_h64 << 8);
342 size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 6, 256);
343 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
344
345 hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
346 ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
347
348 hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, 3, size);
349
350 ctx->frame_size = frame_size;
351 ctx->max_buf_cnt = new_max_cnt;
352 }
353 hal_h265e_leave();
354 return ret;
355 }
356
vepu580_h265_sobel_cfg(hevc_vepu580_wgt * reg)357 static void vepu580_h265_sobel_cfg(hevc_vepu580_wgt *reg)
358 {
359 reg->pre_intra_cla0_B0.pre_intra_cla0_m0 = 10;
360 reg->pre_intra_cla0_B0.pre_intra_cla0_m1 = 11;
361 reg->pre_intra_cla0_B0.pre_intra_cla0_m2 = 12;
362 reg->pre_intra_cla0_B0.pre_intra_cla0_m3 = 13;
363 reg->pre_intra_cla0_B0.pre_intra_cla0_m4 = 14;
364
365 reg->pre_intra_cla0_B1.pre_intra_cla0_m5 = 9;
366 reg->pre_intra_cla0_B1.pre_intra_cla0_m6 = 15;
367 reg->pre_intra_cla0_B1.pre_intra_cla0_m7 = 8;
368 reg->pre_intra_cla0_B1.pre_intra_cla0_m8 = 16;
369 reg->pre_intra_cla0_B1.pre_intra_cla0_m9 = 7;
370
371 reg->pre_intra_cla1_B0.pre_intra_cla1_m0 = 10;
372 reg->pre_intra_cla1_B0.pre_intra_cla1_m1 = 9;
373 reg->pre_intra_cla1_B0.pre_intra_cla1_m2 = 8;
374 reg->pre_intra_cla1_B0.pre_intra_cla1_m3 = 7;
375 reg->pre_intra_cla1_B0.pre_intra_cla1_m4 = 6;
376 reg->pre_intra_cla1_B1.pre_intra_cla1_m5 = 11;
377 reg->pre_intra_cla1_B1.pre_intra_cla1_m6 = 5;
378 reg->pre_intra_cla1_B1.pre_intra_cla1_m7 = 12;
379 reg->pre_intra_cla1_B1.pre_intra_cla1_m8 = 4;
380 reg->pre_intra_cla1_B1.pre_intra_cla1_m9 = 13;
381
382 reg->pre_intra_cla2_B0.pre_intra_cla2_m0 = 18;
383 reg->pre_intra_cla2_B0.pre_intra_cla2_m1 = 17;
384 reg->pre_intra_cla2_B0.pre_intra_cla2_m2 = 16;
385 reg->pre_intra_cla2_B0.pre_intra_cla2_m3 = 15;
386 reg->pre_intra_cla2_B0.pre_intra_cla2_m4 = 14;
387 reg->pre_intra_cla2_B1.pre_intra_cla2_m5 = 19;
388 reg->pre_intra_cla2_B1.pre_intra_cla2_m6 = 13;
389 reg->pre_intra_cla2_B1.pre_intra_cla2_m7 = 20;
390 reg->pre_intra_cla2_B1.pre_intra_cla2_m8 = 12;
391 reg->pre_intra_cla2_B1.pre_intra_cla2_m9 = 21;
392
393 reg->pre_intra_cla3_B0.pre_intra_cla3_m0 = 18;
394 reg->pre_intra_cla3_B0.pre_intra_cla3_m1 = 19;
395 reg->pre_intra_cla3_B0.pre_intra_cla3_m2 = 20;
396 reg->pre_intra_cla3_B0.pre_intra_cla3_m3 = 21;
397 reg->pre_intra_cla3_B0.pre_intra_cla3_m4 = 22;
398 reg->pre_intra_cla3_B1.pre_intra_cla3_m5 = 17;
399 reg->pre_intra_cla3_B1.pre_intra_cla3_m6 = 23;
400 reg->pre_intra_cla3_B1.pre_intra_cla3_m7 = 16;
401 reg->pre_intra_cla3_B1.pre_intra_cla3_m8 = 24;
402 reg->pre_intra_cla3_B1.pre_intra_cla3_m9 = 15;
403
404 reg->pre_intra_cla4_B0.pre_intra_cla4_m0 = 25;
405 reg->pre_intra_cla4_B0.pre_intra_cla4_m1 = 26;
406 reg->pre_intra_cla4_B0.pre_intra_cla4_m2 = 24;
407 reg->pre_intra_cla4_B0.pre_intra_cla4_m3 = 23;
408 reg->pre_intra_cla4_B0.pre_intra_cla4_m4 = 22;
409 reg->pre_intra_cla4_B1.pre_intra_cla4_m5 = 27;
410 reg->pre_intra_cla4_B1.pre_intra_cla4_m6 = 21;
411 reg->pre_intra_cla4_B1.pre_intra_cla4_m7 = 28;
412 reg->pre_intra_cla4_B1.pre_intra_cla4_m8 = 20;
413 reg->pre_intra_cla4_B1.pre_intra_cla4_m9 = 29;
414
415 reg->pre_intra_cla5_B0.pre_intra_cla5_m0 = 27;
416 reg->pre_intra_cla5_B0.pre_intra_cla5_m1 = 26;
417 reg->pre_intra_cla5_B0.pre_intra_cla5_m2 = 28;
418 reg->pre_intra_cla5_B0.pre_intra_cla5_m3 = 29;
419 reg->pre_intra_cla5_B0.pre_intra_cla5_m4 = 30;
420 reg->pre_intra_cla5_B1.pre_intra_cla5_m5 = 25;
421 reg->pre_intra_cla5_B1.pre_intra_cla5_m6 = 31;
422 reg->pre_intra_cla5_B1.pre_intra_cla5_m7 = 24;
423 reg->pre_intra_cla5_B1.pre_intra_cla5_m8 = 32;
424 reg->pre_intra_cla5_B1.pre_intra_cla5_m9 = 23;
425
426 reg->pre_intra_cla6_B0.pre_intra_cla6_m0 = 34;
427 reg->pre_intra_cla6_B0.pre_intra_cla6_m1 = 33;
428 reg->pre_intra_cla6_B0.pre_intra_cla6_m2 = 32;
429 reg->pre_intra_cla6_B0.pre_intra_cla6_m3 = 31;
430 reg->pre_intra_cla6_B0.pre_intra_cla6_m4 = 30;
431 reg->pre_intra_cla6_B1.pre_intra_cla6_m5 = 2;
432 reg->pre_intra_cla6_B1.pre_intra_cla6_m6 = 29;
433 reg->pre_intra_cla6_B1.pre_intra_cla6_m7 = 3;
434 reg->pre_intra_cla6_B1.pre_intra_cla6_m8 = 28;
435 reg->pre_intra_cla6_B1.pre_intra_cla6_m9 = 4;
436
437 reg->pre_intra_cla7_B0.pre_intra_cla7_m0 = 34;
438 reg->pre_intra_cla7_B0.pre_intra_cla7_m1 = 2;
439 reg->pre_intra_cla7_B0.pre_intra_cla7_m2 = 3;
440 reg->pre_intra_cla7_B0.pre_intra_cla7_m3 = 4;
441 reg->pre_intra_cla7_B0.pre_intra_cla7_m4 = 5;
442 reg->pre_intra_cla7_B1.pre_intra_cla7_m5 = 33;
443 reg->pre_intra_cla7_B1.pre_intra_cla7_m6 = 6;
444 reg->pre_intra_cla7_B1.pre_intra_cla7_m7 = 32;
445 reg->pre_intra_cla7_B1.pre_intra_cla7_m8 = 7;
446 reg->pre_intra_cla7_B1.pre_intra_cla7_m9 = 31;
447
448 reg->pre_intra_cla8_B0.pre_intra_cla8_m0 = 10;
449 reg->pre_intra_cla8_B0.pre_intra_cla8_m1 = 26;
450 reg->pre_intra_cla8_B0.pre_intra_cla8_m2 = 18;
451 reg->pre_intra_cla8_B0.pre_intra_cla8_m3 = 34;
452 reg->pre_intra_cla8_B0.pre_intra_cla8_m4 = 6;
453 reg->pre_intra_cla8_B1.pre_intra_cla8_m5 = 14;
454 reg->pre_intra_cla8_B1.pre_intra_cla8_m6 = 22;
455 reg->pre_intra_cla8_B1.pre_intra_cla8_m7 = 30;
456 reg->pre_intra_cla8_B1.pre_intra_cla8_m8 = 2;
457 reg->pre_intra_cla8_B1.pre_intra_cla8_m9 = 24;
458
459 reg->pre_intra_cla9_B0.pre_intra_cla9_m0 = 0;
460 reg->pre_intra_cla9_B0.pre_intra_cla9_m1 = 0;
461 reg->pre_intra_cla9_B0.pre_intra_cla9_m2 = 0;
462 reg->pre_intra_cla9_B0.pre_intra_cla9_m3 = 0;
463 reg->pre_intra_cla9_B0.pre_intra_cla9_m4 = 0;
464 reg->pre_intra_cla9_B1.pre_intra_cla9_m5 = 0;
465 reg->pre_intra_cla9_B1.pre_intra_cla9_m6 = 0;
466 reg->pre_intra_cla9_B1.pre_intra_cla9_m7 = 0;
467 reg->pre_intra_cla9_B1.pre_intra_cla9_m8 = 0;
468 reg->pre_intra_cla9_B1.pre_intra_cla9_m9 = 0;
469
470 reg->pre_intra_cla10_B0.pre_intra_cla10_m0 = 0;
471 reg->pre_intra_cla10_B0.pre_intra_cla10_m1 = 0;
472 reg->pre_intra_cla10_B0.pre_intra_cla10_m2 = 0;
473 reg->pre_intra_cla10_B0.pre_intra_cla10_m3 = 0;
474 reg->pre_intra_cla10_B0.pre_intra_cla10_m4 = 0;
475 reg->pre_intra_cla10_B1.pre_intra_cla10_m5 = 0;
476 reg->pre_intra_cla10_B1.pre_intra_cla10_m6 = 0;
477 reg->pre_intra_cla10_B1.pre_intra_cla10_m7 = 0;
478 reg->pre_intra_cla10_B1.pre_intra_cla10_m8 = 0;
479 reg->pre_intra_cla10_B1.pre_intra_cla10_m9 = 0;
480
481 reg->pre_intra_cla11_B0.pre_intra_cla11_m0 = 0;
482 reg->pre_intra_cla11_B0.pre_intra_cla11_m1 = 0;
483 reg->pre_intra_cla11_B0.pre_intra_cla11_m2 = 0;
484 reg->pre_intra_cla11_B0.pre_intra_cla11_m3 = 0;
485 reg->pre_intra_cla11_B0.pre_intra_cla11_m4 = 0;
486 reg->pre_intra_cla11_B1.pre_intra_cla11_m5 = 0;
487 reg->pre_intra_cla11_B1.pre_intra_cla11_m6 = 0;
488 reg->pre_intra_cla11_B1.pre_intra_cla11_m7 = 0;
489 reg->pre_intra_cla11_B1.pre_intra_cla11_m8 = 0;
490 reg->pre_intra_cla11_B1.pre_intra_cla11_m9 = 0;
491
492 reg->pre_intra_cla12_B0.pre_intra_cla12_m0 = 0;
493 reg->pre_intra_cla12_B0.pre_intra_cla12_m1 = 0;
494 reg->pre_intra_cla12_B0.pre_intra_cla12_m2 = 0;
495 reg->pre_intra_cla12_B0.pre_intra_cla12_m3 = 0;
496 reg->pre_intra_cla12_B0.pre_intra_cla12_m4 = 0;
497 reg->pre_intra_cla12_B1.pre_intra_cla12_m5 = 0;
498 reg->pre_intra_cla12_B1.pre_intra_cla12_m6 = 0;
499 reg->pre_intra_cla12_B1.pre_intra_cla12_m7 = 0;
500 reg->pre_intra_cla12_B1.pre_intra_cla12_m8 = 0;
501 reg->pre_intra_cla12_B1.pre_intra_cla12_m9 = 0;
502
503 reg->pre_intra_cla13_B0.pre_intra_cla13_m0 = 0;
504 reg->pre_intra_cla13_B0.pre_intra_cla13_m1 = 0;
505 reg->pre_intra_cla13_B0.pre_intra_cla13_m2 = 0;
506 reg->pre_intra_cla13_B0.pre_intra_cla13_m3 = 0;
507 reg->pre_intra_cla13_B0.pre_intra_cla13_m4 = 0;
508 reg->pre_intra_cla13_B1.pre_intra_cla13_m5 = 0;
509 reg->pre_intra_cla13_B1.pre_intra_cla13_m6 = 0;
510 reg->pre_intra_cla13_B1.pre_intra_cla13_m7 = 0;
511 reg->pre_intra_cla13_B1.pre_intra_cla13_m8 = 0;
512 reg->pre_intra_cla13_B1.pre_intra_cla13_m9 = 0;
513
514 reg->pre_intra_cla14_B0.pre_intra_cla14_m0 = 0;
515 reg->pre_intra_cla14_B0.pre_intra_cla14_m1 = 0;
516 reg->pre_intra_cla14_B0.pre_intra_cla14_m2 = 0;
517 reg->pre_intra_cla14_B0.pre_intra_cla14_m3 = 0;
518 reg->pre_intra_cla14_B0.pre_intra_cla14_m4 = 0;
519 reg->pre_intra_cla14_B1.pre_intra_cla14_m5 = 0;
520 reg->pre_intra_cla14_B1.pre_intra_cla14_m6 = 0;
521 reg->pre_intra_cla14_B1.pre_intra_cla14_m7 = 0;
522 reg->pre_intra_cla14_B1.pre_intra_cla14_m8 = 0;
523 reg->pre_intra_cla14_B1.pre_intra_cla14_m9 = 0;
524
525 reg->pre_intra_cla15_B0.pre_intra_cla15_m0 = 0;
526 reg->pre_intra_cla15_B0.pre_intra_cla15_m1 = 0;
527 reg->pre_intra_cla15_B0.pre_intra_cla15_m2 = 0;
528 reg->pre_intra_cla15_B0.pre_intra_cla15_m3 = 0;
529 reg->pre_intra_cla15_B0.pre_intra_cla15_m4 = 0;
530 reg->pre_intra_cla15_B1.pre_intra_cla15_m5 = 0;
531 reg->pre_intra_cla15_B1.pre_intra_cla15_m6 = 0;
532 reg->pre_intra_cla15_B1.pre_intra_cla15_m7 = 0;
533 reg->pre_intra_cla15_B1.pre_intra_cla15_m8 = 0;
534 reg->pre_intra_cla15_B1.pre_intra_cla15_m9 = 0;
535
536 reg->pre_intra_cla16_B0.pre_intra_cla16_m0 = 0;
537 reg->pre_intra_cla16_B0.pre_intra_cla16_m1 = 0;
538 reg->pre_intra_cla16_B0.pre_intra_cla16_m2 = 0;
539 reg->pre_intra_cla16_B0.pre_intra_cla16_m3 = 0;
540 reg->pre_intra_cla16_B0.pre_intra_cla16_m4 = 0;
541 reg->pre_intra_cla16_B1.pre_intra_cla16_m5 = 0;
542 reg->pre_intra_cla16_B1.pre_intra_cla16_m6 = 0;
543 reg->pre_intra_cla16_B1.pre_intra_cla16_m7 = 0;
544 reg->pre_intra_cla16_B1.pre_intra_cla16_m8 = 0;
545 reg->pre_intra_cla16_B1.pre_intra_cla16_m9 = 0;
546
547 reg->i16_sobel_t.intra_l16_sobel_t0 = 64;
548 reg->i16_sobel_t.intra_l16_sobel_t1 = 200;
549 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp0 = 32;
550 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp1 = 32;
551 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp2 = 32;
552 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp3 = 32;
553 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp4 = 32;
554 reg->i16_sobel_a_01.intra_l16_sobel_a0_qp5 = 32;
555 reg->i16_sobel_a_01.intra_l16_sobel_a0_qp6 = 32;
556 reg->i16_sobel_a_01.intra_l16_sobel_a0_qp7 = 32;
557 reg->i16_sobel_a_01.intra_l16_sobel_a0_qp8 = 32;
558 reg->i16_sobel_b_00.intra_l16_sobel_b0_qp0 = 0;
559 reg->i16_sobel_b_00.intra_l16_sobel_b0_qp1 = 0;
560 reg->i16_sobel_b_01.intra_l16_sobel_b0_qp2 = 0;
561 reg->i16_sobel_b_01.intra_l16_sobel_b0_qp3 = 0;
562 reg->i16_sobel_b_02.intra_l16_sobel_b0_qp4 = 0;
563 reg->i16_sobel_b_02.intra_l16_sobel_b0_qp5 = 0;
564 reg->i16_sobel_b_03.intra_l16_sobel_b0_qp6 = 0;
565 reg->i16_sobel_b_03.intra_l16_sobel_b0_qp7 = 0;
566 reg->i16_sobel_b_04.intra_l16_sobel_b0_qp8 = 0;
567 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp0 = 13;
568 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp1 = 13;
569 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp2 = 13;
570 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp3 = 13;
571 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp4 = 13;
572 reg->i16_sobel_c_01.intra_l16_sobel_c0_qp5 = 13;
573 reg->i16_sobel_c_01.intra_l16_sobel_c0_qp6 = 13;
574 reg->i16_sobel_c_01.intra_l16_sobel_c0_qp7 = 13;
575 reg->i16_sobel_c_01.intra_l16_sobel_c0_qp8 = 13;
576 reg->i16_sobel_d_00.intra_l16_sobel_d0_qp0 = 23750;
577 reg->i16_sobel_d_00.intra_l16_sobel_d0_qp1 = 23750;
578 reg->i16_sobel_d_01.intra_l16_sobel_d0_qp2 = 23750;
579 reg->i16_sobel_d_01.intra_l16_sobel_d0_qp3 = 23750;
580 reg->i16_sobel_d_02.intra_l16_sobel_d0_qp4 = 23750;
581 reg->i16_sobel_d_02.intra_l16_sobel_d0_qp5 = 23750;
582 reg->i16_sobel_d_03.intra_l16_sobel_d0_qp6 = 23750;
583 reg->i16_sobel_d_03.intra_l16_sobel_d0_qp7 = 23750;
584 reg->i16_sobel_d_04.intra_l16_sobel_d0_qp8 = 23750;
585
586 reg->intra_l16_sobel_e0_qp0_low = 20000;
587 reg->intra_l16_sobel_e0_qp1_low = 20000;
588 reg->intra_l16_sobel_e0_qp2_low = 20000;
589 reg->intra_l16_sobel_e0_qp3_low = 20000;
590 reg->intra_l16_sobel_e0_qp4_low = 20000;
591 reg->intra_l16_sobel_e0_qp5_low = 20000;
592 reg->intra_l16_sobel_e0_qp6_low = 20000;
593 reg->intra_l16_sobel_e0_qp7_low = 20000;
594 reg->intra_l16_sobel_e0_qp8_low = 20000;
595 reg->i16_sobel_e_01.intra_l16_sobel_e0_qp0_high = 0;
596 reg->i16_sobel_e_03.intra_l16_sobel_e0_qp1_high = 0;
597 reg->i16_sobel_e_05.intra_l16_sobel_e0_qp2_high = 0;
598 reg->i16_sobel_e_07.intra_l16_sobel_e0_qp3_high = 0;
599 reg->i16_sobel_e_09.intra_l16_sobel_e0_qp4_high = 0;
600 reg->i16_sobel_e_11.intra_l16_sobel_e0_qp5_high = 0;
601 reg->i16_sobel_e_13.intra_l16_sobel_e0_qp6_high = 0;
602 reg->i16_sobel_e_15.intra_l16_sobel_e0_qp7_high = 0;
603 reg->i16_sobel_e_17.intra_l16_sobel_e0_qp8_high = 0;
604
605 reg->i32_sobel_t_00.intra_l32_sobel_t2 = 64;
606 reg->i32_sobel_t_00.intra_l32_sobel_t3 = 400;
607 reg->i32_sobel_t_01.intra_l32_sobel_t4 = 8;
608 reg->i32_sobel_t_02.intra_l32_sobel_t5 = 100;
609 reg->i32_sobel_t_02.intra_l32_sobel_t6 = 100;
610
611 reg->i32_sobel_a.intra_l32_sobel_a1_qp0 = 18;
612 reg->i32_sobel_a.intra_l32_sobel_a1_qp1 = 18;
613 reg->i32_sobel_a.intra_l32_sobel_a1_qp2 = 18;
614 reg->i32_sobel_a.intra_l32_sobel_a1_qp3 = 18;
615 reg->i32_sobel_a.intra_l32_sobel_a1_qp4 = 18;
616
617 reg->i32_sobel_b_00.intra_l32_sobel_b1_qp0 = 0;
618 reg->i32_sobel_b_00.intra_l32_sobel_b1_qp1 = 0;
619 reg->i32_sobel_b_01.intra_l32_sobel_b1_qp2 = 0;
620 reg->i32_sobel_b_01.intra_l32_sobel_b1_qp3 = 0;
621 reg->i32_sobel_b_02.intra_l32_sobel_b1_qp4 = 0;
622
623 reg->i32_sobel_c.intra_l32_sobel_c1_qp0 = 16;
624 reg->i32_sobel_c.intra_l32_sobel_c1_qp1 = 16;
625 reg->i32_sobel_c.intra_l32_sobel_c1_qp2 = 16;
626 reg->i32_sobel_c.intra_l32_sobel_c1_qp3 = 16;
627 reg->i32_sobel_c.intra_l32_sobel_c1_qp4 = 16;
628
629 reg->i32_sobel_d_00.intra_l32_sobel_d1_qp0 = 0;
630 reg->i32_sobel_d_00.intra_l32_sobel_d1_qp1 = 0;
631 reg->i32_sobel_d_01.intra_l32_sobel_d1_qp2 = 0;
632 reg->i32_sobel_d_01.intra_l32_sobel_d1_qp3 = 0;
633 reg->i32_sobel_d_02.intra_l32_sobel_d1_qp4 = 0;
634
635 reg->intra_l32_sobel_e1_qp0_low = 20000;
636 reg->intra_l32_sobel_e1_qp1_low = 20000;
637 reg->intra_l32_sobel_e1_qp2_low = 20000;
638 reg->intra_l32_sobel_e1_qp3_low = 20000;
639 reg->intra_l32_sobel_e1_qp4_low = 20000;
640
641 reg->i32_sobel_e_01.intra_l32_sobel_e1_qp0_high = 0;
642 reg->i32_sobel_e_03.intra_l32_sobel_e1_qp1_high = 0;
643 reg->i32_sobel_e_05.intra_l32_sobel_e1_qp2_high = 0;
644 reg->i32_sobel_e_07.intra_l32_sobel_e1_qp3_high = 0;
645 reg->i32_sobel_e_09.intra_l32_sobel_e1_qp4_high = 0;
646 }
647
vepu580_h265_rdo_bias_cfg(vepu580_rdo_cfg * reg,MppEncHwCfg * hw)648 static void vepu580_h265_rdo_bias_cfg (vepu580_rdo_cfg *reg, MppEncHwCfg *hw)
649 {
650 RdoAtfCfg* p_rdo_atf;
651 RdoAtfSkipCfg* p_rdo_atf_skip;
652 RK_U8 bias = h265e_mode_bias[hw->mode_bias[4]];
653
654 p_rdo_atf = ®->rdo_b64_inter_atf;
655 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
656 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
657 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
658 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
659 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
660 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
661 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
662 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
663 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
664 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
665 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
666 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
667
668 if (hw->skip_bias_en) {
669 bias = h265e_mode_bias[hw->skip_bias];
670
671 p_rdo_atf_skip = ®->rdo_b64_skip_atf;
672 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
673 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 4 ? hw->skip_sad : 4;
674 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 6 ? hw->skip_sad : 6;
675 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
676 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = bias > 24 ? bias : 24;
677 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = bias < 4 ? bias : 4;
678 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = bias < 6 ? bias : 6;
679 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = bias < 8 ? bias : 8;
680 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
681 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias < 10 ? bias : 10;
682 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias < 10 ? bias : 10;
683 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias < 10 ? bias : 10;
684 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias < 14 ? bias : 14;
685 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias < 14 ? bias : 14;
686 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias < 15 ? bias : 15;
687 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias < 15 ? bias : 15;
688 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias < 15 ? bias : 15;
689 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
690 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
691 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
692 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
693 }
694
695 bias = h265e_mode_bias[hw->mode_bias[0]];
696
697 p_rdo_atf = ®->rdo_b32_intra_atf;
698 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
699 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
700 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
701 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
702 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
703 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
704 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
705 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
706 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
707 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
708 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
709 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
710
711 bias = h265e_mode_bias[hw->mode_bias[5]];
712
713 p_rdo_atf = ®->rdo_b32_inter_atf;
714 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
715 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
716 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
717 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
718 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
719 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
720 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
721 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
722 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
723 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
724 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
725 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
726
727 if (hw->skip_bias_en) {
728 bias = h265e_mode_bias[hw->skip_bias];
729
730 p_rdo_atf_skip = ®->rdo_b32_skip_atf;
731 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
732 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 4 ? hw->skip_sad : 4;
733 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 6 ? hw->skip_sad : 6;
734 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
735 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 18 ? bias : 18;
736 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias < 11 ? bias : 11;
737 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias < 11 ? bias : 11;
738 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias < 11 ? bias : 11;
739 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias < 13 ? bias : 13;
740 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias < 13 ? bias : 13;
741 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias < 13 ? bias : 13;
742 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias < 15 ? bias : 15;
743 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias < 15 ? bias : 15;
744 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias < 15 ? bias : 15;
745 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
746 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
747 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
748 }
749
750 bias = h265e_mode_bias[hw->mode_bias[1]];
751
752 p_rdo_atf = ®->rdo_b16_intra_atf;
753 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
754 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
755 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
756 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
757 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
758 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
759 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
760 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
761 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
762 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
763 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
764 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
765
766 bias = h265e_mode_bias[hw->mode_bias[6]];
767
768 p_rdo_atf = ®->rdo_b16_inter_atf;
769 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
770 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
771 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
772 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
773 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
774 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
775 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
776 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
777 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
778 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
779 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
780 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
781
782 if (hw->skip_bias_en) {
783 bias = h265e_mode_bias[hw->skip_bias];
784
785 p_rdo_atf_skip = ®->rdo_b16_skip_atf;
786 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
787 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 24 ? hw->skip_sad : 24;
788 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 48 ? hw->skip_sad : 48;
789 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
790 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
791 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias;
792 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias;
793 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias;
794 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias;
795 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias;
796 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias;
797 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias;
798 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias;
799 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
800 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
801 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
802 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
803 }
804
805 bias = h265e_mode_bias[hw->mode_bias[2]];
806
807 p_rdo_atf = ®->rdo_b8_intra_atf;
808 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
809 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
810 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
811 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
812 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
813 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
814 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
815 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
816 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
817 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
818 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
819 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
820
821 bias = h265e_mode_bias[hw->mode_bias[7]];
822
823 p_rdo_atf = ®->rdo_b8_inter_atf;
824 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
825 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
826 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
827 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
828 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
829 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
830 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
831 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
832 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
833 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
834 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
835 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
836
837 if (hw->skip_bias_en) {
838 bias = h265e_mode_bias[hw->skip_bias];
839
840 p_rdo_atf_skip = ®->rdo_b8_skip_atf;
841 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
842 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 24 ? hw->skip_sad : 24;
843 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 48 ? hw->skip_sad : 48;
844 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
845 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
846 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias;
847 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias;
848 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias;
849 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias;
850 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias;
851 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias;
852 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias;
853 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias;
854 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
855 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
856 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
857 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
858 }
859 }
860
vepu580_h265_rdo_cfg(vepu580_rdo_cfg * reg)861 static void vepu580_h265_rdo_cfg (vepu580_rdo_cfg *reg)
862 {
863 RdoAtfCfg* p_rdo_atf;
864 RdoAtfSkipCfg* p_rdo_atf_skip;
865 reg->rdo_sqi_cfg.rdo_segment_en = 1;
866 reg->rdo_sqi_cfg.rdo_smear_en = 1;
867 p_rdo_atf = ®->rdo_b64_inter_atf;
868 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 32;
869 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 144;
870 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 300;
871 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
872 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
873 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
874 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
875 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
876 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
877 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
878 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
879 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
880 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 16;
881 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 16;
882 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 16;
883 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 16;
884 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 16;
885 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 16;
886 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 16;
887 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 16;
888 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
889 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
890 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
891
892 p_rdo_atf_skip = ®->rdo_b64_skip_atf;
893 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
894 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 4;
895 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 6;
896 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 8;
897 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd10 = 31;
898 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd11 = 400;
899 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd20 = 31;
900 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd21 = 400;
901 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd30 = 31;
902 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd31 = 400;
903 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd40 = 31;
904 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd41 = 400;
905 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
906 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = 10;
907 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = 10;
908 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = 10;
909 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = 14;
910 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = 14;
911 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = 15;
912 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = 15;
913 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = 15;
914 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = 16;
915 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = 16;
916 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = 16;
917 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = 16;
918
919 p_rdo_atf = ®->rdo_b32_intra_atf;
920 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
921 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
922 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
923 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
924 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
925 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
926 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
927 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
928 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
929 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
930 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
931 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 26;
932 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 25;
933 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 25;
934 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 25;
935 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 24;
936 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 23;
937 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 21;
938 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 19;
939 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 18;
940 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
941 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
942 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
943
944 p_rdo_atf = ®->rdo_b32_inter_atf;
945 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 32;
946 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 144;
947 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 300;
948 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
949 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
950 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
951 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
952 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
953 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
954 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
955 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
956 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
957 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 16;
958 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 16;
959 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 16;
960 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 16;
961 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 16;
962 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 16;
963 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 16;
964 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 16;
965 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
966 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
967 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
968
969 p_rdo_atf_skip = ®->rdo_b32_skip_atf;
970 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
971 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 4;
972 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 6;
973 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 8;
974 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd10 = 31;
975 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd11 = 400;
976 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd20 = 31;
977 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd21 = 400;
978 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd30 = 31;
979 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd31 = 400;
980 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd40 = 31;
981 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd41 = 400;
982 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 18;
983 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = 11;
984 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = 11;
985 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = 11;
986 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = 13;
987 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = 13;
988 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = 13;
989 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = 15;
990 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = 15;
991 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = 15;
992 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = 16;
993 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = 16;
994 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = 16;
995
996 p_rdo_atf = ®->rdo_b16_intra_atf;
997 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
998 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
999 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
1000 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
1001 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
1002 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
1003 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
1004 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
1005 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
1006 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
1007 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1008 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 26;
1009 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 25;
1010 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 25;
1011 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 25;
1012 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 24;
1013 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 23;
1014 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 21;
1015 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 19;
1016 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 18;
1017 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1018 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1019 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1020
1021 p_rdo_atf = ®->rdo_b16_inter_atf;
1022 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 32;
1023 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 144;
1024 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 300;
1025 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
1026 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
1027 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
1028 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
1029 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
1030 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
1031 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
1032 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1033 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1034 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 16;
1035 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 16;
1036 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 16;
1037 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 16;
1038 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 16;
1039 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 16;
1040 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 16;
1041 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 16;
1042 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1043 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1044 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1045
1046 p_rdo_atf_skip = ®->rdo_b16_skip_atf;
1047 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
1048 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 24;
1049 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 48;
1050 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 96;
1051 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd10 = 31;
1052 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd11 = 400;
1053 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd20 = 31;
1054 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd21 = 400;
1055 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd30 = 31;
1056 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd31 = 400;
1057 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd40 = 31;
1058 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd41 = 400;
1059 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1060 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = 16;
1061 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = 16;
1062 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = 16;
1063 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = 16;
1064 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = 16;
1065 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = 16;
1066 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = 16;
1067 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = 16;
1068 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = 16;
1069 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = 16;
1070 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = 16;
1071 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = 16;
1072
1073 p_rdo_atf = ®->rdo_b8_intra_atf;
1074 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
1075 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
1076 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
1077 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
1078 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
1079 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
1080 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
1081 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
1082 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
1083 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
1084 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1085 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 26;
1086 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 25;
1087 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 25;
1088 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 25;
1089 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 24;
1090 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 23;
1091 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 21;
1092 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 19;
1093 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 18;
1094 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1095 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1096 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1097
1098 p_rdo_atf = ®->rdo_b8_inter_atf;
1099 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 32;
1100 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 144;
1101 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 300;
1102 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
1103 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
1104 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
1105 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
1106 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
1107 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
1108 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
1109 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1110 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1111 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 16;
1112 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 16;
1113 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 16;
1114 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 16;
1115 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 16;
1116 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 16;
1117 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 16;
1118 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 16;
1119 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1120 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1121 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1122
1123 p_rdo_atf_skip = ®->rdo_b8_skip_atf;
1124 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
1125 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 24;
1126 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 48;
1127 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 96;
1128 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd10 = 31;
1129 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd11 = 400;
1130 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd20 = 31;
1131 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd21 = 400;
1132 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd30 = 31;
1133 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd31 = 400;
1134 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd40 = 31;
1135 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd41 = 400;
1136 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1137 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = 16;
1138 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = 16;
1139 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = 16;
1140 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = 16;
1141 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = 16;
1142 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = 16;
1143 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = 16;
1144 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = 16;
1145 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = 16;
1146 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = 16;
1147 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = 16;
1148 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = 16;
1149
1150 reg->rdo_segment_b64_thd0.rdo_segment_cu64_th0 = 160;
1151 reg->rdo_segment_b64_thd0.rdo_segment_cu64_th1 = 96;
1152 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th2 = 30;
1153 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th3 = 0;
1154 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th4 = 1;
1155 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th5_minus1 = 4;
1156 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th6_minus1 = 11;
1157
1158 reg->rdo_segment_b32_thd0.rdo_segment_cu32_th0 = 160;
1159 reg->rdo_segment_b32_thd0.rdo_segment_cu32_th1 = 96;
1160 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th2 = 30;
1161 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th3 = 0;
1162 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th4 = 1;
1163 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th5_minus1 = 2;
1164 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th6_minus1 = 3;
1165
1166 reg->rdo_segment_multi.rdo_segment_cu64_multi = 22;
1167 reg->rdo_segment_multi.rdo_segment_cu32_multi = 22;
1168 reg->rdo_segment_multi.rdo_smear_cu16_multi = 6;
1169
1170 reg->rdo_b16_smear_thd0.rdo_smear_cu16_cime_sad_th0 = 64;
1171 reg->rdo_b16_smear_thd0.rdo_smear_cu16_cime_sad_th1 = 32;
1172 reg->rdo_b16_smear_thd1.rdo_smear_cu16_cime_sad_th2 = 36;
1173 reg->rdo_b16_smear_thd1.rdo_smear_cu16_cime_sad_th3 = 64;
1174
1175
1176 reg->preintra_b32_cst_var_thd.pre_intra32_cst_var_th00 = 9;
1177 reg->preintra_b32_cst_var_thd.pre_intra32_cst_var_th01 = 4;
1178 reg->preintra_b32_cst_var_thd.pre_intra32_mode_th = 5;
1179
1180 reg->preintra_b32_cst_wgt.pre_intra32_cst_wgt00 = 31;
1181 reg->preintra_b32_cst_wgt.pre_intra32_cst_wgt01 = 25;
1182
1183 reg->preintra_b16_cst_var_thd.pre_intra16_cst_var_th00 = 9;
1184 reg->preintra_b16_cst_var_thd.pre_intra16_cst_var_th01 = 4;
1185 reg->preintra_b16_cst_var_thd.pre_intra16_mode_th = 5;
1186
1187 reg->preintra_b16_cst_wgt.pre_intra16_cst_wgt00 = 31;
1188 reg->preintra_b16_cst_wgt.pre_intra16_cst_wgt01 = 25;
1189 }
1190
vepu580_h265_scl_cfg(vepu580_rdo_cfg * reg)1191 static void vepu580_h265_scl_cfg(vepu580_rdo_cfg *reg)
1192 {
1193 static RK_U32 vepu580_h265_scl_tab[] = {
1194 /* 0x2200 */
1195 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x10001000, 0x0d790f0f, 0x0a3d0ba3,
1196 0x10001000, 0x0e390f0f, 0x0ba30ccd, 0x08d40a3d, 0x10001000, 0x0c310e39, 0x097b0aab, 0x071c0842,
1197 0x0f0f0f0f, 0x0aab0ccd, 0x07500889, 0x0572063e, 0x0d790e39, 0x097b0ba3, 0x05d10750, 0x03f004be,
1198 0x0ba30c31, 0x08420a3d, 0x04be063e, 0x02e903a8, 0x0a3d0aab, 0x071c08d4, 0x03f00572, 0x023a02e9,
1199 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x10001000, 0x0d790f0f, 0x0a3d0ba3,
1200 0x10001000, 0x0e390f0f, 0x0ba30ccd, 0x08d40a3d, 0x10001000, 0x0c310e39, 0x097b0aab, 0x071c0842,
1201 0x0f0f0f0f, 0x0aab0ccd, 0x07500889, 0x0572063e, 0x0d790e39, 0x097b0ba3, 0x05d10750, 0x03f004be,
1202 0x0ba30c31, 0x08420a3d, 0x04be063e, 0x02e903a8, 0x0a3d0aab, 0x071c08d4, 0x03f00572, 0x023a02e9,
1203 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x10001000, 0x0d790f0f, 0x0a3d0ba3,
1204 0x10001000, 0x0e390f0f, 0x0ba30ccd, 0x08d40a3d, 0x10001000, 0x0c310e39, 0x097b0aab, 0x071c0842,
1205 0x0f0f0f0f, 0x0aab0ccd, 0x07500889, 0x0572063e, 0x0d790e39, 0x097b0ba3, 0x05d10750, 0x03f004be,
1206 0x0ba30c31, 0x08420a3d, 0x04be063e, 0x02e903a8, 0x0a3d0aab, 0x071c08d4, 0x03f00572, 0x023a02e9,
1207 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x10001000, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab,
1208 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925,
1209 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925, 0x04be063e,
1210 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x039b04be, 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x02d0039b,
1211 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x10001000, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab,
1212 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925,
1213 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925, 0x04be063e,
1214 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x039b04be, 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x02d0039b,
1215 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x10001000, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab,
1216 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925,
1217 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925, 0x04be063e,
1218 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x039b04be, 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x02d0039b,
1219 0x10001000, 0x10001000, 0x10001000, 0x10101010, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x18151211,
1220 0x10001000, 0x10001000, 0x0e390f0f, 0x10101010, 0x0d790f0f, 0x0a3d0ba3, 0x0aab0c31, 0x19161311,
1221 0x10001000, 0x0e390f0f, 0x10001000, 0x12111010, 0x0ba30ccd, 0x08d40a3d, 0x10001000, 0x1d191614,
1222 0x10001000, 0x0c310e39, 0x0d790f0f, 0x15121010, 0x097b0aab, 0x071c0842, 0x0a3d0ba3, 0x241f1b18,
1223 0x0f0f0f0f, 0x0aab0ccd, 0x10001000, 0x18141111, 0x07500889, 0x0572063e, 0x0e390f0f, 0x2f29231e,
1224 0x0d790e39, 0x097b0ba3, 0x0ba30ccd, 0x1b161312, 0x05d10750, 0x03f004be, 0x08d40a3d, 0x41362c23,
1225 0x0ba30c31, 0x08420a3d, 0x10001000, 0x1f191615, 0x04be063e, 0x02e903a8, 0x0c310e39, 0x58463629,
1226 0x0a3d0aab, 0x071c08d4, 0x097b0aab, 0x241d1918, 0x03f00572, 0x023a02e9, 0x071c0842, 0x7358412f,
1227 0x10001000, 0x10001000, 0x0f0f0f0f, 0x10101010, 0x0e390f0f, 0x0aab0c31, 0x0aab0ccd, 0x18151211,
1228 0x10001000, 0x10001000, 0x07500889, 0x10101010, 0x0d790f0f, 0x0a3d0ba3, 0x0572063e, 0x19161311,
1229 0x10001000, 0x0e390f0f, 0x0d790e39, 0x12111010, 0x0ba30ccd, 0x08d40a3d, 0x097b0ba3, 0x1d191614,
1230 0x10001000, 0x0c310e39, 0x05d10750, 0x15121010, 0x097b0aab, 0x071c0842, 0x03f004be, 0x241f1b18,
1231 0x0f0f0f0f, 0x0aab0ccd, 0x0ba30c31, 0x18141111, 0x07500889, 0x0572063e, 0x08420a3d, 0x2f29231e,
1232 0x0d790e39, 0x097b0ba3, 0x04be063e, 0x1b161312, 0x05d10750, 0x03f004be, 0x02e903a8, 0x41362c23,
1233 0x0ba30c31, 0x08420a3d, 0x0a3d0aab, 0x1f191615, 0x04be063e, 0x02e903a8, 0x071c08d4, 0x58463629,
1234 0x0a3d0aab, 0x071c08d4, 0x03f00572, 0x241d1918, 0x03f00572, 0x023a02e9, 0x023a02e9, 0x7358412f,
1235 0x10001000, 0x10001000, 0x10001000, 0x10101010, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x18151211,
1236 0x10001000, 0x10001000, 0x0e390f0f, 0x10101010, 0x0d790f0f, 0x0a3d0ba3, 0x0aab0ccd, 0x19161311,
1237 0x10001000, 0x0e390f0f, 0x10001000, 0x12111010, 0x0ba30ccd, 0x08d40a3d, 0x0f0f1000, 0x1d191614,
1238 0x10001000, 0x0c310e39, 0x0ccd0e39, 0x15121010, 0x097b0aab, 0x071c0842, 0x0a3d0aab, 0x241f1b18,
1239 0x0f0f0f0f, 0x0aab0ccd, 0x10001000, 0x18141111, 0x07500889, 0x0572063e, 0x0e390f0f, 0x2f29231e,
1240 0x0d790e39, 0x097b0ba3, 0x0aab0ccd, 0x1b161312, 0x05d10750, 0x03f004be, 0x09250a3d, 0x41362c23,
1241 0x0ba30c31, 0x08420a3d, 0x0f0f1000, 0x1f191615, 0x04be063e, 0x02e903a8, 0x0ccd0e39, 0x58463629,
1242 0x0a3d0aab, 0x071c08d4, 0x0a3d0aab, 0x241d1918, 0x03f00572, 0x023a02e9, 0x07c20925, 0x7358412f,
1243 0x10001000, 0x10001000, 0x0e390f0f, 0x10101010, 0x0e390f0f, 0x0aab0ccd, 0x0aab0ccd, 0x18141211,
1244 0x10001000, 0x0f0f1000, 0x09250a3d, 0x11101010, 0x0ccd0e39, 0x0a3d0aab, 0x063e07c2, 0x19181412,
1245 0x10001000, 0x0e390f0f, 0x0ccd0e39, 0x12111010, 0x0aab0ccd, 0x09250a3d, 0x0a3d0aab, 0x1c191814,
1246 0x0f0f1000, 0x0ccd0e39, 0x07c20925, 0x14121110, 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x211c1918,
1247 0x0e390f0f, 0x0aab0ccd, 0x0aab0ccd, 0x18141211, 0x09250a3d, 0x063e07c2, 0x09250a3d, 0x29211c19,
1248 0x0ccd0e39, 0x0a3d0aab, 0x063e07c2, 0x19181412, 0x07c20925, 0x04be063e, 0x039b04be, 0x3629211c,
1249 0x0aab0ccd, 0x09250a3d, 0x0a3d0aab, 0x1c191814, 0x063e07c2, 0x039b04be, 0x07c20925, 0x47362921,
1250 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x211c1918, 0x04be063e, 0x02d0039b, 0x02d0039b, 0x5b473629,
1251 0x10001000, 0x10001000, 0x10101010, 0x10101010, 0x0e390f0f, 0x0aab0ccd, 0x10101010, 0x18141211,
1252 0x10001000, 0x0f0f1000, 0x12111211, 0x11101010, 0x0ccd0e39, 0x0a3d0aab, 0x18141815, 0x19181412,
1253 0x10001000, 0x0e390f0f, 0x10101010, 0x12111010, 0x0aab0ccd, 0x09250a3d, 0x11101010, 0x1c191814,
1254 0x0f0f1000, 0x0ccd0e39, 0x14121311, 0x14121110, 0x0a3d0aab, 0x07c20925, 0x19181916, 0x211c1918,
1255 0x0e390f0f, 0x0aab0ccd, 0x10101010, 0x18141211, 0x09250a3d, 0x063e07c2, 0x12111211, 0x29211c19,
1256 0x0ccd0e39, 0x0a3d0aab, 0x18141614, 0x19181412, 0x07c20925, 0x04be063e, 0x1c191d19, 0x3629211c,
1257 0x0aab0ccd, 0x09250a3d, 0x11101010, 0x1c191814, 0x063e07c2, 0x039b04be, 0x14121512, 0x47362921,
1258 0x0a3d0aab, 0x07c20925, 0x19181b18, 0x211c1918, 0x04be063e, 0x02d0039b, 0x211c241f, 0x5b473629,
1259 0x10001000, 0x10001000, 0x12111111, 0x10101010, 0x0e390f0f, 0x0aab0ccd, 0x18141814, 0x18141211,
1260 0x10001000, 0x0f0f1000, 0x1c19231e, 0x11101010, 0x0ccd0e39, 0x0a3d0aab, 0x29212f29, 0x19181412,
1261 0x10001000, 0x0e390f0f, 0x14121312, 0x12111010, 0x0aab0ccd, 0x09250a3d, 0x19181b16, 0x1c191814,
1262 0x0f0f1000, 0x0ccd0e39, 0x211c2c23, 0x14121110, 0x0a3d0aab, 0x07c20925, 0x36294136, 0x211c1918,
1263 0x0e390f0f, 0x0aab0ccd, 0x18141615, 0x18141211, 0x09250a3d, 0x063e07c2, 0x1c191f19, 0x29211c19,
1264 0x0ccd0e39, 0x0a3d0aab, 0x29213629, 0x19181412, 0x07c20925, 0x04be063e, 0x47365846, 0x3629211c,
1265 0x0aab0ccd, 0x09250a3d, 0x19181918, 0x1c191814, 0x063e07c2, 0x039b04be, 0x211c241d, 0x47362921,
1266 0x0a3d0aab, 0x07c20925, 0x3629412f, 0x211c1918, 0x04be063e, 0x02d0039b, 0x5b477358, 0x5b473629,
1267 0x10101010, 0x18151211, 0x10101010, 0x18141211, 0x10101010, 0x19161311, 0x11101010, 0x19181412,
1268 0x12111010, 0x1d191614, 0x12111010, 0x1c191814, 0x15121010, 0x241f1b18, 0x14121110, 0x211c1918,
1269 0x18141111, 0x2f29231e, 0x18141211, 0x29211c19, 0x1b161312, 0x41362c23, 0x19181412, 0x3629211c,
1270 0x1f191615, 0x58463629, 0x1c191814, 0x47362921, 0x241d1918, 0x7358412f, 0x211c1918, 0x5b473629,
1271 0x10101010, 0x18151211, 0x10101010, 0x18141211, 0x10101010, 0x19161311, 0x11101010, 0x19181412,
1272 0x12111010, 0x1d191614, 0x12111010, 0x1c191814, 0x15121010, 0x241f1b18, 0x14121110, 0x211c1918,
1273 0x18141111, 0x2f29231e, 0x18141211, 0x29211c19, 0x1b161312, 0x41362c23, 0x19181412, 0x3629211c,
1274 0x1f191615, 0x58463629, 0x1c191814, 0x47362921, 0x241d1918, 0x7358412f, 0x211c1918, 0x5b473629,
1275 0x10101010, 0x18151211, 0x10101010, 0x18141211, 0x10101010, 0x19161311, 0x11101010, 0x19181412,
1276 0x12111010, 0x1d191614, 0x12111010, 0x1c191814, 0x15121010, 0x241f1b18, 0x14121110, 0x211c1918,
1277 0x18141111, 0x2f29231e, 0x18141211, 0x29211c19, 0x1b161312, 0x41362c23, 0x19181412, 0x3629211c,
1278 0x1f191615, 0x58463629, 0x1c191814, 0x47362921, 0x241d1918, 0x7358412f, 0x211c1918, 0x5b473629,
1279 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10101010, 0x10101010,
1280 };
1281
1282 hal_h265e_dbg_func("enter\n");
1283
1284 memcpy(®->scaling_list_reg[0], vepu580_h265_scl_tab, sizeof(vepu580_h265_scl_tab));
1285
1286 hal_h265e_dbg_func("leave\n");
1287 }
vepu580_h265_global_cfg_set(H265eV580HalContext * ctx,H265eV580RegSet * regs)1288 static void vepu580_h265_global_cfg_set(H265eV580HalContext *ctx, H265eV580RegSet *regs)
1289 {
1290 MppEncHwCfg *hw = &ctx->cfg->hw;
1291 RK_U32 i;
1292 hevc_vepu580_rc_klut *rc_regs = ®s->reg_rc_klut;
1293 hevc_vepu580_wgt *reg_wgt = ®s->reg_wgt;
1294 vepu580_rdo_cfg *reg_rdo = ®s->reg_rdo;
1295 vepu580_h265_sobel_cfg(reg_wgt);
1296 vepu580_h265_rdo_cfg(reg_rdo);
1297 vepu580_h265_rdo_bias_cfg(reg_rdo, hw);
1298 vepu580_h265_scl_cfg(reg_rdo);
1299
1300 memcpy(®_wgt->iprd_wgt_qp_hevc_0_51[0], lamd_satd_qp, sizeof(lamd_satd_qp));
1301
1302 if (ctx->frame_type == INTRA_FRAME) {
1303 RK_U8 *thd = (RK_U8 *)&rc_regs->aq_tthd0;
1304 RK_S8 *step = (RK_S8 *)&rc_regs->aq_stp0;
1305
1306 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
1307 thd[i] = hw->aq_thrd_i[i];
1308 step[i] = hw->aq_step_i[i] & 0x3f;
1309 }
1310
1311 memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_moda_qp, sizeof(lamd_moda_qp));
1312 } else {
1313 RK_U8 *thd = (RK_U8 *)&rc_regs->aq_tthd0;
1314 RK_S8 *step = (RK_S8 *)&rc_regs->aq_stp0;
1315
1316 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
1317 thd[i] = hw->aq_thrd_p[i];
1318 step[i] = hw->aq_step_p[i] & 0x3f;
1319 }
1320 memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_modb_qp, sizeof(lamd_modb_qp));
1321 }
1322 //to be done
1323 rc_regs->madi_cfg.madi_mode = 0;
1324 rc_regs->madi_cfg.madi_thd = 25;
1325 rc_regs->md_sad_thd.md_sad_thd0 = 20;
1326 rc_regs->md_sad_thd.md_sad_thd1 = 30;
1327 rc_regs->md_sad_thd.md_sad_thd2 = 40;
1328 rc_regs->madi_thd.madi_thd0 = 25;
1329 rc_regs->madi_thd.madi_thd1 = 35;
1330 rc_regs->madi_thd.madi_thd2 = 45;
1331
1332 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171;
1333 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85;
1334
1335 memcpy(®_wgt->lvl32_intra_CST_THD0, lvl32_intra_cst_thd, sizeof(lvl32_intra_cst_thd));
1336 memcpy(®_wgt->lvl16_intra_CST_THD0, lvl16_intra_cst_thd, sizeof(lvl16_intra_cst_thd));
1337 memcpy(®_wgt->lvl32_intra_CST_WGT0, lvl32_intra_cst_wgt, sizeof(lvl32_intra_cst_wgt));
1338 memcpy(®_wgt->lvl16_intra_CST_WGT0, lvl16_intra_cst_wgt, sizeof(lvl16_intra_cst_wgt));
1339
1340 reg_wgt->cime_sqi_cfg.cime_sad_mod_sel = 0;
1341 reg_wgt->cime_sqi_cfg.cime_sad_use_big_block = 0;
1342 reg_wgt->cime_sqi_cfg.cime_pmv_set_zero = 1;
1343 reg_wgt->cime_sqi_cfg.cime_pmv_num = 3;
1344 reg_wgt->cime_sqi_thd.cime_mvd_th0 = 32;
1345 reg_wgt->cime_sqi_thd.cime_mvd_th1 = 80;
1346 reg_wgt->cime_sqi_thd.cime_mvd_th2 = 128;
1347 reg_wgt->cime_sqi_multi0.cime_multi0 = 16;
1348 reg_wgt->cime_sqi_multi0.cime_multi1 = 32;
1349 reg_wgt->cime_sqi_multi1.cime_multi2 = 96;
1350 reg_wgt->cime_sqi_multi1.cime_multi3 = 96;
1351 reg_wgt->rime_sqi_thd.cime_sad_th0 = 48;
1352 reg_wgt->rime_sqi_thd.rime_mvd_th0 = 3;
1353 reg_wgt->rime_sqi_thd.rime_mvd_th1 = 8;
1354 reg_wgt->rime_sqi_multi.rime_multi0 = 16;
1355 reg_wgt->rime_sqi_multi.rime_multi1 = 16;
1356 reg_wgt->rime_sqi_multi.rime_multi2 = 128;
1357 reg_wgt->fme_sqi_thd0.cime_sad_pu16_th = 16;
1358 reg_wgt->fme_sqi_thd0.cime_sad_pu32_th = 16;
1359 reg_wgt->fme_sqi_thd1.cime_sad_pu64_th = 16;
1360 reg_wgt->fme_sqi_thd1.move_lambda = 1;
1361
1362
1363 }
1364
hal_h265e_v580_deinit(void * hal)1365 MPP_RET hal_h265e_v580_deinit(void *hal)
1366 {
1367 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
1368 RK_U32 i = 0;
1369
1370 hal_h265e_enter();
1371
1372 for (i = 0; i < MAX_TILE_NUM; i++) {
1373 MPP_FREE(ctx->regs[i]);
1374 MPP_FREE(ctx->reg_out[i]);
1375 }
1376
1377 MPP_FREE(ctx->poll_cfgs);
1378 MPP_FREE(ctx->input_fmt);
1379 hal_bufs_deinit(ctx->dpb_bufs);
1380
1381 for (i = 0; i < MAX_TILE_NUM; i++) {
1382 if (ctx->hw_tile_buf[i]) {
1383 mpp_buffer_put(ctx->hw_tile_buf[i]);
1384 ctx->hw_tile_buf[i] = NULL;
1385 }
1386 }
1387
1388 for (i = 0; i < MAX_TILE_NUM - 1; i ++) {
1389 if (ctx->hw_tile_stream[i]) {
1390 mpp_buffer_put(ctx->hw_tile_stream[i]);
1391 ctx->hw_tile_stream[i] = NULL;
1392 }
1393 }
1394
1395 if (ctx->tile_grp) {
1396 mpp_buffer_group_put(ctx->tile_grp);
1397 ctx->tile_grp = NULL;
1398 }
1399
1400 if (ctx->roi_base_cfg_buf) {
1401 mpp_buffer_put(ctx->roi_base_cfg_buf);
1402 ctx->roi_base_cfg_buf = NULL;
1403 ctx->roi_base_buf_size = 0;
1404 }
1405
1406 if (ctx->roi_grp) {
1407 mpp_buffer_group_put(ctx->roi_grp);
1408 ctx->roi_grp = NULL;
1409 }
1410
1411 if (ctx->roi_base_cfg_sw_buf)
1412 MPP_FREE(ctx->roi_base_cfg_sw_buf);
1413
1414 if (ctx->roi_cfg_tmp) {
1415 MPP_FREE(ctx->roi_cfg_tmp);
1416 ctx->roi_cfg_tmp = NULL;
1417 }
1418
1419 if (ctx->buf_pass1) {
1420 mpp_buffer_put(ctx->buf_pass1);
1421 ctx->buf_pass1 = NULL;
1422 }
1423
1424 if (ctx->dev) {
1425 mpp_dev_deinit(ctx->dev);
1426 ctx->dev = NULL;
1427 }
1428
1429 if (ctx->reg_cfg) {
1430 mpp_dev_multi_offset_deinit(ctx->reg_cfg);
1431 ctx->reg_cfg = NULL;
1432 }
1433
1434 if (ctx->tune) {
1435 vepu580_h265e_tune_deinit(ctx->tune);
1436 ctx->tune = NULL;
1437 }
1438 hal_h265e_leave();
1439 return MPP_OK;
1440 }
1441
hal_h265e_v580_init(void * hal,MppEncHalCfg * cfg)1442 MPP_RET hal_h265e_v580_init(void *hal, MppEncHalCfg *cfg)
1443 {
1444 MPP_RET ret = MPP_OK;
1445 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
1446 RK_U32 i = 0;
1447 H265eV580RegSet *regs = NULL;
1448
1449 mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
1450
1451 hal_h265e_enter();
1452
1453 for (i = 0; i < MAX_TILE_NUM; i++) {
1454 ctx->regs[i] = mpp_calloc(H265eV580RegSet, 1);
1455 ctx->reg_out[i] = mpp_calloc(H265eV580StatusElem, 1);
1456 }
1457
1458 ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
1459 ctx->cfg = cfg->cfg;
1460 hal_bufs_init(&ctx->dpb_bufs);
1461
1462 ctx->frame_cnt = 0;
1463 ctx->frame_cnt_gen_ready = 0;
1464 ctx->enc_mode = RKV_ENC_MODE;
1465 cfg->type = VPU_CLIENT_RKVENC;
1466 ret = mpp_dev_init(&cfg->dev, cfg->type);
1467 if (ret) {
1468 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
1469 goto DONE;
1470 }
1471 regs = (H265eV580RegSet *)ctx->regs[0];
1472 ctx->dev = cfg->dev;
1473 ctx->osd_cfg.reg_base = (void *)®s->reg_osd_cfg;
1474 ctx->osd_cfg.dev = ctx->dev;
1475 ctx->osd_cfg.plt_cfg = &ctx->cfg->plt_cfg;
1476 ctx->osd_cfg.osd_data = NULL;
1477 ctx->osd_cfg.osd_data2 = NULL;
1478
1479 mpp_dev_multi_offset_init(&ctx->reg_cfg, 24);
1480 ctx->osd_cfg.reg_cfg = ctx->reg_cfg;
1481
1482 ctx->frame_type = INTRA_FRAME;
1483
1484 { /* setup default hardware config */
1485 MppEncHwCfg *hw = &cfg->cfg->hw;
1486
1487 hw->qp_delta_row_i = 2;
1488 hw->qp_delta_row = 2;
1489
1490 memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
1491 memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
1492 memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i));
1493 memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p));
1494
1495 for (i = 0; i < MPP_ARRAY_ELEMS(hw->mode_bias); i++)
1496 hw->mode_bias[i] = 8;
1497
1498 hw->skip_sad = 8;
1499 hw->skip_bias = 8;
1500 }
1501
1502 ctx->tune = vepu580_h265e_tune_init(ctx);
1503
1504 {
1505 // check parall tile ability
1506 const MppServiceCmdCap *cap = mpp_get_mpp_service_cmd_cap();
1507
1508 ctx->tile_parall_en = cap->send_cmd > MPP_CMD_SET_SESSION_FD;
1509 }
1510
1511 ctx->poll_slice_max = 8;
1512 ctx->poll_cfg_size = (sizeof(ctx->poll_cfgs) + sizeof(RK_S32) * ctx->poll_slice_max) * 2;
1513 ctx->poll_cfgs = mpp_malloc_size(MppDevPollCfg, ctx->poll_cfg_size);
1514
1515 if (NULL == ctx->poll_cfgs) {
1516 ret = MPP_ERR_MALLOC;
1517 mpp_err_f("init poll cfg buffer failed\n");
1518 goto DONE;
1519 }
1520 ctx->output_cb = cfg->output_cb;
1521 cfg->cap_recn_out = 1;
1522 DONE:
1523 if (ret)
1524 hal_h265e_v580_deinit(hal);
1525
1526 hal_h265e_leave();
1527 return ret;
1528 }
hal_h265e_vepu580_prepare(void * hal)1529 static MPP_RET hal_h265e_vepu580_prepare(void *hal)
1530 {
1531 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
1532 MppEncPrepCfg *prep = &ctx->cfg->prep;
1533
1534 hal_h265e_dbg_func("enter %p\n", hal);
1535
1536 if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
1537 RK_S32 i;
1538
1539 // pre-alloc required buffers to reduce first frame delay
1540 vepu580_h265_setup_hal_bufs(ctx);
1541 for (i = 0; i < ctx->max_buf_cnt; i++)
1542 hal_bufs_get_buf(ctx->dpb_bufs, i);
1543
1544 prep->change = 0;
1545 }
1546
1547 hal_h265e_dbg_func("leave %p\n", hal);
1548
1549 return MPP_OK;
1550 }
1551
1552 static MPP_RET
vepu580_h265_set_patch_info(MppDevRegOffCfgs * cfgs,H265eSyntax_new * syn,Vepu541Fmt input_fmt,HalEncTask * task)1553 vepu580_h265_set_patch_info(MppDevRegOffCfgs *cfgs, H265eSyntax_new *syn,
1554 Vepu541Fmt input_fmt, HalEncTask *task)
1555 {
1556 MppFrameFormat fmt = mpp_frame_get_fmt(task->frame);
1557 RK_U32 hor_stride = syn->pp.hor_stride;
1558 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
1559 RK_U32 frame_size = hor_stride * ver_stride;
1560 RK_U32 u_offset = 0, v_offset = 0;
1561 MPP_RET ret = MPP_OK;
1562
1563 if (task->rc_task->frm.use_pass1)
1564 fmt = MPP_FMT_YUV420SP;
1565
1566 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1567 u_offset = mpp_frame_get_fbc_offset(task->frame);
1568 v_offset = 0;
1569 } else {
1570 switch (input_fmt) {
1571 case VEPU541_FMT_YUV420P: {
1572 u_offset = frame_size;
1573 v_offset = frame_size * 5 / 4;
1574 } break;
1575 case VEPU541_FMT_YUV420SP:
1576 case VEPU541_FMT_YUV422SP: {
1577 u_offset = frame_size;
1578 v_offset = frame_size;
1579 } break;
1580 case VEPU541_FMT_YUV422P: {
1581 u_offset = frame_size;
1582 v_offset = frame_size * 3 / 2;
1583 } break;
1584 case VEPU541_FMT_YUYV422:
1585 case VEPU541_FMT_UYVY422: {
1586 u_offset = 0;
1587 v_offset = 0;
1588 } break;
1589 case VEPU580_FMT_YUV444SP : {
1590 u_offset = hor_stride * ver_stride;
1591 v_offset = hor_stride * ver_stride;
1592 } break;
1593 case VEPU580_FMT_YUV444P : {
1594 u_offset = hor_stride * ver_stride;
1595 v_offset = hor_stride * ver_stride * 2;
1596 } break;
1597 case VEPU541_FMT_BGR565:
1598 case VEPU541_FMT_BGR888:
1599 case VEPU541_FMT_BGRA8888: {
1600 u_offset = 0;
1601 v_offset = 0;
1602 } break;
1603 default: {
1604 hal_h265e_err("unknown color space: %d\n", input_fmt);
1605 u_offset = frame_size;
1606 v_offset = frame_size * 5 / 4;
1607 }
1608 }
1609 }
1610
1611 /* input cb addr */
1612 ret = mpp_dev_multi_offset_update(cfgs, 161, u_offset);
1613 if (ret)
1614 mpp_err_f("set input cb addr offset failed %d\n", ret);
1615
1616 /* input cr addr */
1617 ret = mpp_dev_multi_offset_update(cfgs, 162, v_offset);
1618 if (ret)
1619 mpp_err_f("set input cr addr offset failed %d\n", ret);
1620
1621 return ret;
1622 }
1623
1624 typedef struct refresh_area {
1625 RK_S32 roi_ctu_x_sta;
1626 RK_S32 roi_ctu_y_sta;
1627 RK_S32 roi_ctu_x_end;
1628 RK_S32 roi_ctu_y_end;
1629 } RefreshArea;
1630
cal_refresh_area(RK_S32 ctu_w,RK_S32 ctu_h,RK_U32 refresh_idx,MppEncRcRefreshMode refresh_mode,RK_U32 refresh_num,RefreshArea * area)1631 static MPP_RET cal_refresh_area(RK_S32 ctu_w, RK_S32 ctu_h, RK_U32 refresh_idx,
1632 MppEncRcRefreshMode refresh_mode, RK_U32 refresh_num, RefreshArea *area)
1633 {
1634 MPP_RET ret = MPP_OK;
1635 RK_U32 refresh_ctu_h = 0;
1636
1637 if (refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW) {
1638 area->roi_ctu_x_sta = 0;
1639 area->roi_ctu_x_end = ctu_w - 1;
1640
1641 if (refresh_idx > 0) {
1642 refresh_ctu_h = refresh_num + 1;
1643 area->roi_ctu_y_sta = refresh_num * refresh_idx - 1;
1644 } else {
1645 refresh_ctu_h = refresh_num;
1646 area->roi_ctu_y_sta = 0;
1647 }
1648
1649 area->roi_ctu_y_end = area->roi_ctu_y_sta + refresh_ctu_h - 1;
1650 } else {
1651 area->roi_ctu_y_sta = 0;
1652 area->roi_ctu_y_end = ctu_h - 1;
1653
1654 if (refresh_idx > 0) {
1655 refresh_ctu_h = refresh_num + 1;
1656 area->roi_ctu_x_sta = refresh_num * refresh_idx - 1;
1657 } else {
1658 refresh_ctu_h = refresh_num;
1659 area->roi_ctu_x_sta = 0;
1660 }
1661
1662 area->roi_ctu_x_end = area->roi_ctu_x_sta + refresh_ctu_h - 1;
1663 }
1664
1665 area->roi_ctu_x_end = MPP_MIN(area->roi_ctu_x_end, ctu_w - 1);
1666 area->roi_ctu_y_end = MPP_MIN(area->roi_ctu_y_end, ctu_h - 1);
1667 area->roi_ctu_x_sta = MPP_MAX(area->roi_ctu_x_sta, 0);
1668 area->roi_ctu_y_sta = MPP_MAX(area->roi_ctu_y_sta, 0);
1669
1670 hal_h265e_dbg_detail("size in ctu : %d x %d, refresh_num %d, refresh_idx %d, area x[%d, %d], y[%d, %d]",
1671 ctu_w, ctu_h, refresh_num, refresh_idx,
1672 area->roi_ctu_x_sta, area->roi_ctu_x_end,
1673 area->roi_ctu_y_sta, area->roi_ctu_y_end);
1674
1675 return ret;
1676 }
1677
setup_intra_refresh(H265eV580RegSet * regs,H265eV580HalContext * ctx,RK_U32 refresh_idx)1678 static MPP_RET setup_intra_refresh(H265eV580RegSet *regs, H265eV580HalContext *ctx, RK_U32 refresh_idx)
1679 {
1680 MPP_RET ret = MPP_OK;
1681 RK_U32 w = ctx->cfg->prep.width;
1682 RK_U32 h = ctx->cfg->prep.height;
1683 RK_S32 ctu_w = MPP_ALIGN(w, 64) / 64;
1684 RK_S32 ctu_h = MPP_ALIGN(h, 64) / 64;
1685 RK_U32 roi_base_cfg_buf_size = ctu_w * ctu_h * 64;
1686 MppEncROICfg2 *external_roi_cfg = ( MppEncROICfg2 *)ctx->roi_data;
1687 RK_U8 *roi_base_cfg_hw_ptr = NULL;
1688 RK_U8 *roi_base_cfg_sw_ptr = NULL;
1689 RK_S32 roi_base_cfg_buf_fd = 0;
1690 RefreshArea cur_area;
1691 RK_S32 j, k;
1692
1693 hal_h265e_dbg_func("enter\n");
1694
1695 if (!ctx->cfg->rc.refresh_en) {
1696 ret = MPP_ERR_VALUE;
1697 goto __RET;
1698 }
1699
1700 if (ctx->roi_data) {
1701 roi_base_cfg_hw_ptr = mpp_buffer_get_ptr(external_roi_cfg->base_cfg_buf);
1702 roi_base_cfg_buf_fd = mpp_buffer_get_fd(external_roi_cfg->base_cfg_buf);
1703 } else {
1704 if (NULL == ctx->roi_base_cfg_buf) {
1705 if (NULL == ctx->roi_grp)
1706 mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
1707 mpp_buffer_get(ctx->roi_grp, &ctx->roi_base_cfg_buf, roi_base_cfg_buf_size);
1708 }
1709 roi_base_cfg_hw_ptr = mpp_buffer_get_ptr(ctx->roi_base_cfg_buf);
1710 roi_base_cfg_buf_fd = mpp_buffer_get_fd(ctx->roi_base_cfg_buf);
1711 }
1712
1713 ctx->roi_base_buf_size = roi_base_cfg_buf_size;
1714
1715 if (NULL == ctx->roi_base_cfg_sw_buf) {
1716 ctx->roi_base_cfg_sw_buf = mpp_malloc(RK_U8, roi_base_cfg_buf_size);
1717 }
1718 roi_base_cfg_sw_ptr = ctx->roi_base_cfg_sw_buf;
1719
1720 memset(ctx->roi_base_cfg_sw_buf, 0, roi_base_cfg_buf_size);
1721
1722 if (MPP_OK != cal_refresh_area(ctu_w, ctu_h, refresh_idx, ctx->cfg->rc.refresh_mode, ctx->cfg->rc.refresh_num, &cur_area)) {
1723 ret = MPP_ERR_VALUE;
1724 mpp_err_f("setting refresh area out of range");
1725 goto __RET;
1726 }
1727
1728 RK_U8 *ptr = roi_base_cfg_sw_ptr;
1729 for (j = 0; j < ctu_h; j++) {
1730 for (k = 0; k < ctu_w; k++) {
1731 if (j <= cur_area.roi_ctu_y_end && j >= cur_area.roi_ctu_y_sta &&
1732 k <= cur_area.roi_ctu_x_end && k >= cur_area.roi_ctu_x_sta) {
1733
1734 memset(ptr + 22, 0x55, 20); //176~336
1735 *(ptr + 21) = 0x54; //170~175
1736 *(ptr + 42) = 0x05; //336~339
1737 }
1738 ptr += 64;
1739 }
1740 }
1741
1742 memcpy(roi_base_cfg_hw_ptr, roi_base_cfg_sw_ptr, roi_base_cfg_buf_size);
1743
1744 if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW)
1745 regs->reg_base.reg0220_me_rnge.cme_srch_v = 1;
1746 else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL)
1747 regs->reg_base.reg0220_me_rnge.cme_srch_h = 1;
1748
1749 regs->reg_base.reg0192_enc_pic.roi_en = 1;
1750 regs->reg_base.reg0178_roi_addr = roi_base_cfg_buf_fd;
1751
1752 __RET:
1753 hal_h265e_dbg_func("leave, ret %d\n", ret);
1754 return ret;
1755 }
1756
1757
vepu580_h265_set_roi_regs(H265eV580HalContext * ctx,hevc_vepu580_base * regs)1758 static MPP_RET vepu580_h265_set_roi_regs(H265eV580HalContext *ctx, hevc_vepu580_base *regs)
1759 {
1760 /* memset register on start so do not clear registers again here */
1761 if (ctx->roi_data) {
1762 /* roi setup */
1763 RK_U32 ctu_w = MPP_ALIGN(ctx->cfg->prep.width, 64) / 64;
1764 RK_U32 ctu_h = MPP_ALIGN(ctx->cfg->prep.height, 64) / 64;
1765 RK_U32 base_cfg_size = ctu_w * ctu_h * 64;
1766 RK_U32 qp_cfg_size = ctu_w * ctu_h * 256;
1767 RK_U32 amv_cfg_size = ctu_w * ctu_h * 512;
1768 RK_U32 mv_cfg_size = ctu_w * ctu_h * 4;
1769 MppEncROICfg2 *cfg = (MppEncROICfg2 *)ctx->roi_data;
1770
1771 if (mpp_buffer_get_size(cfg->base_cfg_buf) >= base_cfg_size) {
1772 regs->reg0192_enc_pic.roi_en = 1;
1773 regs->reg0178_roi_addr = mpp_buffer_get_fd(cfg->base_cfg_buf);
1774 } else {
1775 mpp_err("roi base cfg buf not enough, roi is invalid");
1776 }
1777
1778 if (cfg->roi_qp_en) {
1779 if (mpp_buffer_get_size(cfg->qp_cfg_buf) >= qp_cfg_size) {
1780 regs->reg0179_roi_qp_addr = mpp_buffer_get_fd(cfg->qp_cfg_buf);
1781 regs->reg0228_roi_en.roi_qp_en = 1;
1782 } else {
1783 mpp_err("roi qp cfg buf not enough, roi is invalid");
1784 }
1785 }
1786
1787 if (cfg->roi_amv_en) {
1788 if (mpp_buffer_get_size(cfg->amv_cfg_buf) >= amv_cfg_size) {
1789 regs->reg0180_roi_amv_addr = mpp_buffer_get_fd(cfg->amv_cfg_buf);
1790 regs->reg0228_roi_en.roi_amv_en = 1;
1791 } else {
1792 mpp_err("roi amv cfg buf not enough, roi is invalid");
1793 }
1794 }
1795
1796 if (cfg->roi_mv_en) {
1797 if (mpp_buffer_get_size(cfg->mv_cfg_buf) >= mv_cfg_size) {
1798 regs->reg0181_roi_mv_addr = mpp_buffer_get_fd(cfg->mv_cfg_buf);
1799 regs->reg0228_roi_en.roi_mv_en = 1;
1800 } else {
1801 mpp_err("roi mv cfg buf not enough, roi is invalid");
1802 }
1803 }
1804 }
1805
1806 return MPP_OK;
1807 }
1808
vepu580_h265_set_rc_regs(H265eV580HalContext * ctx,H265eV580RegSet * regs,HalEncTask * task)1809 static MPP_RET vepu580_h265_set_rc_regs(H265eV580HalContext *ctx, H265eV580RegSet *regs, HalEncTask *task)
1810 {
1811 H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
1812 EncRcTaskInfo *rc_cfg = &task->rc_task->info;
1813 hevc_vepu580_base *reg_base = ®s->reg_base;
1814 hevc_vepu580_rc_klut *reg_rc = ®s->reg_rc_klut;
1815 MppEncCfgSet *cfg = ctx->cfg;
1816 MppEncRcCfg *rc = &cfg->rc;
1817 MppEncHwCfg *hw = &cfg->hw;
1818 MppEncCodecCfg *codec = &cfg->codec;
1819 MppEncH265Cfg *h265 = &codec->h265;
1820 RK_S32 mb_wd64, mb_h64;
1821 mb_wd64 = (syn->pp.pic_width + 63) / 64;
1822 mb_h64 = (syn->pp.pic_height + 63) / 64;
1823
1824 RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd64 * mb_h64);
1825 RK_U32 ctu_target_bits;
1826 RK_S32 negative_bits_thd, positive_bits_thd;
1827
1828 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
1829 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target;
1830 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target;
1831
1832 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target;
1833 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target;
1834 } else {
1835 if (ctu_target_bits_mul_16 >= 0x100000) {
1836 ctu_target_bits_mul_16 = 0x50000;
1837 }
1838 ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd64) >> 4;
1839 negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
1840 positive_bits_thd = 5 * ctu_target_bits / 16;
1841
1842 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target;
1843 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target;
1844 reg_base->reg212_rc_cfg.rc_en = 1;
1845 reg_base->reg212_rc_cfg.aq_en = 1;
1846 reg_base->reg212_rc_cfg.aq_mode = 1;
1847 reg_base->reg212_rc_cfg.rc_ctu_num = mb_wd64;
1848 reg_base->reg213_rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
1849 hw->qp_delta_row_i : hw->qp_delta_row;
1850 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_max;
1851 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_min;
1852 reg_base->reg214_rc_tgt.ctu_ebit = ctu_target_bits_mul_16;
1853
1854 reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd;
1855 reg_rc->rc_dthd_0_8[1] = negative_bits_thd;
1856 reg_rc->rc_dthd_0_8[2] = positive_bits_thd;
1857 reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd;
1858 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF;
1859 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF;
1860 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF;
1861 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF;
1862 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF;
1863
1864 reg_rc->rc_adj0.qp_adj0 = -2;
1865 reg_rc->rc_adj0.qp_adj1 = -1;
1866 reg_rc->rc_adj0.qp_adj2 = 0;
1867 reg_rc->rc_adj0.qp_adj3 = 1;
1868 reg_rc->rc_adj0.qp_adj4 = 2;
1869 reg_rc->rc_adj1.qp_adj5 = 0;
1870 reg_rc->rc_adj1.qp_adj6 = 0;
1871 reg_rc->rc_adj1.qp_adj7 = 0;
1872 reg_rc->rc_adj1.qp_adj8 = 0;
1873
1874 reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
1875 reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
1876 reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
1877 reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
1878 reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;;
1879 reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
1880 reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;;
1881 reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
1882 reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;;
1883 reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
1884 reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;;
1885 reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
1886 reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;;
1887 reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
1888 reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;;
1889 reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
1890 reg_rc->roi_qthd3.qpmap_mode = h265->qpmap_mode;
1891 }
1892 return MPP_OK;
1893 }
1894
vepu580_h265_set_pp_regs(H265eV580RegSet * regs,VepuFmtCfg * fmt,MppEncPrepCfg * prep_cfg,HalEncTask * task)1895 static MPP_RET vepu580_h265_set_pp_regs(H265eV580RegSet *regs, VepuFmtCfg *fmt,
1896 MppEncPrepCfg *prep_cfg, HalEncTask *task)
1897 {
1898 hevc_vepu580_control_cfg *reg_ctl = ®s->reg_ctl;
1899 hevc_vepu580_base *reg_base = ®s->reg_base;
1900 RK_S32 stridey = 0;
1901 RK_S32 stridec = 0;
1902
1903 reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;
1904 reg_base->reg0198_src_fmt.src_cfmt = fmt->format;
1905 reg_base->reg0198_src_fmt.alpha_swap = fmt->alpha_swap;
1906 reg_base->reg0198_src_fmt.rbuv_swap = fmt->rbuv_swap;
1907 reg_base->reg0198_src_fmt.src_range = (prep_cfg->range == MPP_FRAME_RANGE_JPEG ? 1 : 0);
1908 reg_base->reg0198_src_fmt.out_fmt = 1;
1909 reg_base->reg0203_src_proc.src_mirr = prep_cfg->mirroring > 0;
1910 reg_base->reg0203_src_proc.src_rot = prep_cfg->rotation;
1911
1912 if (MPP_FRAME_FMT_IS_FBC(prep_cfg->format)) {
1913 stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
1914 if (!stridey)
1915 stridey = MPP_ALIGN(prep_cfg->width, 16);
1916 } else if (prep_cfg->hor_stride) {
1917 stridey = prep_cfg->hor_stride;
1918 } else {
1919 if (fmt->format == VEPU541_FMT_BGRA8888 )
1920 stridey = prep_cfg->width * 4;
1921 else if (fmt->format == VEPU541_FMT_BGR888 )
1922 stridey = prep_cfg->width * 3;
1923 else if (fmt->format == VEPU541_FMT_BGR565 ||
1924 fmt->format == VEPU541_FMT_YUYV422 ||
1925 fmt->format == VEPU541_FMT_UYVY422)
1926 stridey = prep_cfg->width * 2;
1927 else
1928 stridey = prep_cfg->width;
1929 }
1930
1931 switch (fmt->format) {
1932 case VEPU580_FMT_YUV444SP : {
1933 stridec = stridey * 2;
1934 } break;
1935 case VEPU541_FMT_YUV422SP :
1936 case VEPU541_FMT_YUV420SP :
1937 case VEPU580_FMT_YUV444P : {
1938 stridec = stridey;
1939 } break;
1940 default : {
1941 stridec = stridey / 2;
1942 } break;
1943 }
1944
1945 if (reg_base->reg0198_src_fmt.src_cfmt < VEPU541_FMT_NONE) {
1946 const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color);
1947
1948 hal_h265e_dbg_simple("input color range %d colorspace %d", prep_cfg->range, prep_cfg->color);
1949
1950 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;
1951 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;
1952 reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;
1953
1954 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;
1955 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;
1956 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;
1957
1958 reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;
1959 reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;
1960 reg_base->reg0201_src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;
1961
1962 reg_base->reg0202_src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset;
1963 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset;
1964 reg_base->reg0202_src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset;
1965
1966 hal_h265e_dbg_simple("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
1967 }
1968
1969 reg_base->reg0205_src_strd0.src_strd0 = stridey;
1970 reg_base->reg0206_src_strd1.src_strd1 = stridec;
1971
1972 return MPP_OK;
1973 }
1974
vepu580_h265_set_slice_regs(H265eSyntax_new * syn,hevc_vepu580_base * regs)1975 static void vepu580_h265_set_slice_regs(H265eSyntax_new *syn, hevc_vepu580_base *regs)
1976 {
1977 regs->reg0237_synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag;//slice->m_sps->m_bUseSAO;
1978 regs->reg0237_synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets;
1979 regs->reg0237_synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps;
1980 regs->reg0237_synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag;
1981 regs->reg0237_synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag;
1982 regs->reg0237_synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
1983 regs->reg0237_synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag;
1984
1985 regs->reg0238_synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag;
1986 regs->reg0238_synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag;
1987 regs->reg0238_synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits;
1988 regs->reg0238_synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag;
1989 regs->reg0238_synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag;
1990 regs->reg0238_synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26;
1991 regs->reg0238_synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag;
1992 regs->reg0238_synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
1993 regs->reg0238_synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag;
1994 regs->reg0238_synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag;
1995 regs->reg0238_synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag;
1996 regs->reg0238_synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
1997 regs->reg0238_synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
1998 regs->reg0238_synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
1999
2000 regs->reg0239_synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
2001 regs->reg0239_synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;
2002 regs->reg0239_synt_sli0.mrg_up_flg = syn->sp.merge_up_flag;
2003 regs->reg0239_synt_sli0.mrg_lft_flg = syn->sp.merge_left_flag;
2004 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
2005
2006 regs->reg0239_synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act;
2007 regs->reg0239_synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act;
2008
2009 regs->reg0239_synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
2010
2011 regs->reg0239_synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg;
2012 regs->reg0239_synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg;
2013 regs->reg0239_synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en;
2014 regs->reg0192_enc_pic.num_pic_tot_cur = syn->sp.tot_poc_num;
2015
2016 regs->reg0239_synt_sli0.pic_out_flg = syn->sp.pic_out_flg;
2017 regs->reg0239_synt_sli0.sli_type = syn->sp.slice_type;
2018 regs->reg0239_synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg;
2019 regs->reg0239_synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg;
2020 regs->reg0239_synt_sli0.sli_pps_id = syn->sp.sli_pps_id;
2021 regs->reg0239_synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic;
2022
2023
2024 regs->reg0240_synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;;
2025 regs->reg0240_synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2;
2026 regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli;
2027 regs->reg0240_synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
2028 regs->reg0240_synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
2029 regs->reg0240_synt_sli1.sli_cb_qp_ofst = syn->pp.pps_slice_chroma_qp_offsets_present_flag ?
2030 syn->sp.sli_cb_qp_ofst : syn->pp.pps_cb_qp_offset;
2031 regs->reg0240_synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd;
2032
2033 regs->reg0240_synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
2034 regs->reg0240_synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;
2035 regs->reg0241_synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb;
2036 regs->reg0241_synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len;
2037
2038 }
2039
vepu580_h265_set_ref_regs(H265eSyntax_new * syn,hevc_vepu580_base * regs)2040 static void vepu580_h265_set_ref_regs(H265eSyntax_new *syn, hevc_vepu580_base *regs)
2041 {
2042 regs->reg0242_synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
2043 regs->reg0242_synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
2044 regs->reg0242_synt_refm0.num_lt_pic = syn->sp.num_lt_pic;
2045
2046 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
2047 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
2048 regs->reg0243_synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
2049 regs->reg0243_synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
2050 regs->reg0243_synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
2051 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
2052 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
2053 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
2054 regs->reg0243_synt_refm1.num_negative_pics = syn->sp.num_neg_pic;
2055 regs->reg0243_synt_refm1.num_pos_pic = syn->sp.num_pos_pic;
2056
2057 regs->reg0243_synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;
2058 regs->reg0244_synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
2059 regs->reg0244_synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
2060 regs->reg0245_synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
2061 regs->reg0245_synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
2062
2063 regs->reg0246_synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
2064 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
2065 regs->reg0246_synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
2066 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
2067 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
2068 regs->reg0240_synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
2069 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
2070
2071 return;
2072 }
2073
hal_h265e_v580_send_regs(MppDev dev,H265eV580RegSet * hw_regs,H265eV580StatusElem * reg_out)2074 static MPP_RET hal_h265e_v580_send_regs(MppDev dev, H265eV580RegSet *hw_regs, H265eV580StatusElem *reg_out)
2075 {
2076 RK_U32 *regs = (RK_U32*)hw_regs;
2077 MppDevRegWrCfg cfg;
2078 MppDevRegRdCfg cfg1;
2079 MPP_RET ret = MPP_OK;
2080 RK_U32 i;
2081
2082 cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
2083 cfg.size = sizeof(hevc_vepu580_control_cfg);
2084 cfg.offset = VEPU580_CTL_OFFSET;
2085
2086 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2087 if (ret) {
2088 mpp_err_f("set register write failed %d\n", ret);
2089 goto FAILE;
2090 }
2091
2092 if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) {
2093 regs = (RK_U32*)&hw_regs->reg_ctl;
2094 for (i = 0; i < sizeof(hevc_vepu580_control_cfg) / 4; i++) {
2095 hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]);
2096 }
2097 }
2098
2099 cfg.reg = &hw_regs->reg_base;
2100 cfg.size = sizeof(hevc_vepu580_base);
2101 cfg.offset = VEPU580_BASE_OFFSET;
2102
2103 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2104 if (ret) {
2105 mpp_err_f("set register write failed %d\n", ret);
2106 goto FAILE;
2107 }
2108
2109 if (hal_h265e_debug & HAL_H265E_DBG_REGS) {
2110 regs = (RK_U32*)(&hw_regs->reg_base);
2111 for (i = 0; i < 32; i++) {
2112 hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0%08x\n", i * 4, regs[i]);
2113 }
2114 regs += 32;
2115 for (i = 0; i < (sizeof(hevc_vepu580_base) - 128) / 4; i++) {
2116 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2117 }
2118 }
2119
2120 cfg.reg = &hw_regs->reg_rc_klut;
2121 cfg.size = sizeof(hevc_vepu580_rc_klut);
2122 cfg.offset = VEPU580_RCKULT_OFFSET;
2123
2124 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2125
2126 if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) {
2127 regs = (RK_U32*)&hw_regs->reg_rc_klut;
2128 for (i = 0; i < sizeof(hevc_vepu580_rc_klut) / 4; i++) {
2129 hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2130 }
2131 }
2132
2133 if (ret) {
2134 mpp_err_f("set rc kult write failed %d\n", ret);
2135 goto FAILE;
2136 }
2137
2138 cfg.reg = &hw_regs->reg_wgt;
2139 cfg.size = sizeof(hevc_vepu580_wgt);
2140 cfg.offset = VEPU580_WEG_OFFSET;
2141
2142 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2143 if (ret) {
2144 mpp_err_f("set register write failed %d\n", ret);
2145 goto FAILE;
2146 }
2147
2148 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
2149 regs = (RK_U32*)&hw_regs->reg_wgt;
2150 for (i = 0; i < sizeof(hevc_vepu580_wgt) / 4; i++) {
2151 hal_h265e_dbg_wgt("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2152 }
2153 }
2154
2155 cfg.reg = &hw_regs->reg_rdo;
2156 cfg.size = sizeof(vepu580_rdo_cfg);
2157 cfg.offset = VEPU580_RDOCFG_OFFSET;
2158
2159 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2160 if (ret) {
2161 mpp_err_f("set register write failed %d\n", ret);
2162 goto FAILE;
2163 }
2164
2165 cfg.reg = &hw_regs->reg_osd_cfg;
2166 cfg.size = sizeof(vepu580_osd_cfg);
2167 cfg.offset = VEPU580_OSD_OFFSET;
2168
2169 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2170 if (ret) {
2171 mpp_err_f("set register write failed %d\n", ret);
2172 goto FAILE;
2173 }
2174
2175 cfg1.reg = ®_out->hw_status;
2176 cfg1.size = sizeof(RK_U32);
2177 cfg1.offset = VEPU580_REG_BASE_HW_STATUS;
2178
2179 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &cfg1);
2180 if (ret) {
2181 mpp_err_f("set register read failed %d\n", ret);
2182 goto FAILE;
2183 }
2184
2185 cfg1.reg = ®_out->st;
2186 cfg1.size = sizeof(H265eV580StatusElem) - 4;
2187 cfg1.offset = VEPU580_STATUS_OFFSET;
2188
2189 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &cfg1);
2190 if (ret) {
2191 mpp_err_f("set register read failed %d\n", ret);
2192 goto FAILE;
2193 }
2194 FAILE:
2195 return ret;
2196 }
2197
vepu580_h265_set_me_regs(H265eV580HalContext * ctx,H265eSyntax_new * syn,hevc_vepu580_base * regs)2198 static void vepu580_h265_set_me_regs(H265eV580HalContext *ctx, H265eSyntax_new *syn, hevc_vepu580_base *regs)
2199 {
2200
2201 RK_U32 cime_w = 11, cime_h = 7;
2202 RK_S32 merangx = (cime_w + 1) * 32;
2203 RK_S32 merangy = (cime_h + 1) * 32;
2204 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6;
2205
2206 if (merangx > 384) {
2207 merangx = 384;
2208 }
2209 if (merangy > 320) {
2210 merangy = 320;
2211 }
2212
2213 if (syn->pp.pic_width < merangx + 60 || syn->pp.pic_width <= 352) {
2214 if (merangx > syn->pp.pic_width ) {
2215 merangx = syn->pp.pic_width;
2216 }
2217 merangx = merangx / 4 * 2;
2218 }
2219
2220 if (syn->pp.pic_height < merangy + 60 || syn->pp.pic_height <= 288) {
2221 if (merangy > syn->pp.pic_height) {
2222 merangy = syn->pp.pic_height;
2223 }
2224 merangy = merangy / 4 * 2;
2225 }
2226
2227 {
2228 RK_S32 merange_x = merangx / 2;
2229 RK_S32 merange_y = merangy / 2;
2230 RK_S32 mxneg = ((-(merange_x << 2)) >> 2) / 4;
2231 RK_S32 myneg = ((-(merange_y << 2)) >> 2) / 4;
2232 RK_S32 mxpos = (((merange_x << 2) - 4) >> 2) / 4;
2233 RK_S32 mypos = (((merange_y << 2) - 4) >> 2) / 4;
2234
2235 mxneg = MPP_MIN(abs(mxneg), mxpos) * 4;
2236 myneg = MPP_MIN(abs(myneg), mypos) * 4;
2237
2238 merangx = mxneg * 2;
2239 merangy = myneg * 2;
2240 }
2241 regs->reg0220_me_rnge.cme_srch_h = merangx / 32;
2242 regs->reg0220_me_rnge.cme_srch_v = merangy / 32;
2243
2244 regs->reg0220_me_rnge.rme_srch_h = 7;
2245 regs->reg0220_me_rnge.rme_srch_v = 5;
2246 regs->reg0220_me_rnge.dlt_frm_num = 0x1;
2247
2248 regs->reg0221_me_cfg.pmv_mdst_h = 5;
2249 regs->reg0221_me_cfg.pmv_mdst_v = 5;
2250 regs->reg0221_me_cfg.mv_limit = 0;
2251 regs->reg0221_me_cfg.pmv_num = 2;
2252
2253 //regs->reg0221_me_cfg.rme_dis = 0;
2254 // regs->reg0221_me_cfg.rme_dis = 2;
2255
2256
2257
2258 if (syn->pp.sps_temporal_mvp_enabled_flag &&
2259 (ctx->frame_type != INTRA_FRAME)) {
2260 if (ctx->last_frame_type == INTRA_FRAME) {
2261 regs->reg0221_me_cfg.colmv_load = 0;
2262 } else {
2263 regs->reg0221_me_cfg.colmv_load = 1;
2264 }
2265 regs->reg0221_me_cfg.colmv_stor = 1;
2266 }
2267
2268 if (syn->pp.pic_width > 2688) {
2269 regs->reg0222_me_cach.cme_rama_h = 12;
2270 } else if (syn->pp.pic_width > 2048) {
2271 regs->reg0222_me_cach.cme_rama_h = 16;
2272 } else {
2273 regs->reg0222_me_cach.cme_rama_h = 20;
2274 }
2275
2276 {
2277 RK_S32 swin_scope_wd16 = (regs->reg0220_me_rnge.cme_srch_h + 3 + 1) / 4 * 2 + 1;
2278 RK_S32 tmpMin = (regs->reg0220_me_rnge.cme_srch_v + 3) / 4 * 2 + 1;
2279 if (regs->reg0222_me_cach.cme_rama_h / 4 < tmpMin) {
2280 tmpMin = regs->reg0222_me_cach.cme_rama_h / 4;
2281 }
2282 regs->reg0222_me_cach.cme_rama_max =
2283 (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2);
2284 }
2285 regs->reg0222_me_cach.cach_l2_tag = 0x0;
2286
2287 pic_wd64 = pic_wd64 << 6;
2288
2289 if (pic_wd64 <= 512)
2290 regs->reg0222_me_cach.cach_l2_tag = 0x0;
2291 else if (pic_wd64 <= 1024)
2292 regs->reg0222_me_cach.cach_l2_tag = 0x1;
2293 else if (pic_wd64 <= 2048)
2294 regs->reg0222_me_cach.cach_l2_tag = 0x2;
2295 else if (pic_wd64 <= 4096)
2296 regs->reg0222_me_cach.cach_l2_tag = 0x3;
2297
2298 }
2299
vepu580_h265_set_hw_address(H265eV580HalContext * ctx,hevc_vepu580_base * regs,HalEncTask * task)2300 void vepu580_h265_set_hw_address(H265eV580HalContext *ctx, hevc_vepu580_base *regs, HalEncTask *task)
2301 {
2302 HalEncTask *enc_task = task;
2303 HalBuf *recon_buf, *ref_buf;
2304 MppBuffer md_info_buf = enc_task->md_info;
2305 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
2306
2307 hal_h265e_enter();
2308
2309 regs->reg0160_adr_src0 = mpp_buffer_get_fd(enc_task->input);
2310 regs->reg0161_adr_src1 = regs->reg0160_adr_src0;
2311 regs->reg0162_adr_src2 = regs->reg0160_adr_src0;
2312
2313 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
2314 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
2315
2316 if (!syn->sp.non_reference_flag) {
2317 regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]);
2318 regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr;
2319
2320 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);
2321 }
2322 regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
2323 regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr;
2324 regs->reg0167_cmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]);
2325 regs->reg0168_cmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]);
2326 regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
2327 regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
2328
2329 mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);
2330
2331 if (syn->pp.tiles_enabled_flag) {
2332 RK_U32 tile_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1);
2333 RK_U32 i = 0;
2334
2335 if (NULL == ctx->tile_grp)
2336 mpp_buffer_group_get_internal(&ctx->tile_grp, MPP_BUFFER_TYPE_ION);
2337
2338 mpp_assert(ctx->tile_grp);
2339
2340 for (i = 0; i < MAX_TILE_NUM; i++) {
2341 if (NULL == ctx->hw_tile_buf[i]) {
2342 mpp_buffer_get(ctx->tile_grp, &ctx->hw_tile_buf[i], TILE_BUF_SIZE);
2343 }
2344 }
2345
2346 if (NULL == ctx->hw_tile_stream[0]) {
2347 mpp_buffer_get(ctx->tile_grp, &ctx->hw_tile_stream[0], ctx->frame_size / tile_num);
2348 }
2349
2350 if (tile_num > 2) {
2351 if (NULL == ctx->hw_tile_stream[1]) {
2352 mpp_buffer_get(ctx->tile_grp, &ctx->hw_tile_stream[1], ctx->frame_size / tile_num);
2353 }
2354 if (NULL == ctx->hw_tile_stream[2]) {
2355 mpp_buffer_get(ctx->tile_grp, &ctx->hw_tile_stream[2], ctx->frame_size / tile_num);
2356 }
2357 }
2358
2359 regs->reg0176_lpfw_addr = mpp_buffer_get_fd(ctx->hw_tile_buf[0]);
2360 regs->reg0177_lpfr_addr = mpp_buffer_get_fd(ctx->hw_tile_buf[1]);
2361 }
2362
2363 if (md_info_buf) {
2364 regs->reg0192_enc_pic.mei_stor = 1;
2365 regs->reg0171_meiw_addr = mpp_buffer_get_fd(md_info_buf);
2366 } else {
2367 regs->reg0192_enc_pic.mei_stor = 0;
2368 regs->reg0171_meiw_addr = 0;
2369 }
2370
2371 regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output);
2372 /* TODO: stream size relative with syntax */
2373 regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr;
2374 regs->reg0174_bsbr_addr = regs->reg0172_bsbt_addr;
2375 regs->reg0175_adr_bsbs = regs->reg0172_bsbt_addr;
2376
2377 mpp_dev_multi_offset_update(ctx->reg_cfg, 175, mpp_packet_get_length(task->packet));
2378 mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
2379
2380 regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
2381 regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
2382 }
2383
vepu580_h265e_save_pass1_patch(H265eV580RegSet * regs,H265eV580HalContext * ctx,RK_S32 tiles_enabled_flag)2384 static MPP_RET vepu580_h265e_save_pass1_patch(H265eV580RegSet *regs, H265eV580HalContext *ctx,
2385 RK_S32 tiles_enabled_flag)
2386 {
2387 hevc_vepu580_base *reg_base = ®s->reg_base;
2388 RK_S32 width = ctx->cfg->prep.width;
2389 RK_S32 height = ctx->cfg->prep.height;
2390 RK_S32 width_align = MPP_ALIGN(width, 64);
2391 RK_S32 height_align = MPP_ALIGN(height, 16);
2392
2393 if (NULL == ctx->buf_pass1) {
2394 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
2395 if (!ctx->buf_pass1) {
2396 mpp_err("buf_pass1 malloc fail, debreath invaild");
2397 return MPP_NOK;
2398 }
2399 }
2400
2401 reg_base->reg0192_enc_pic.cur_frm_ref = 1;
2402 reg_base->reg0163_rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
2403 reg_base->reg0164_rfpw_b_addr = reg_base->reg0163_rfpw_h_addr;
2404 reg_base->reg0192_enc_pic.rec_fbc_dis = 1;
2405
2406 if (tiles_enabled_flag)
2407 reg_base->reg0238_synt_pps.lpf_fltr_acrs_til = 0;
2408
2409 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height);
2410
2411 /* NOTE: disable split to avoid lowdelay slice output */
2412 regs->reg_base.reg0216_sli_splt.sli_splt = 0;
2413 regs->reg_base.reg0192_enc_pic.slen_fifo = 0;
2414
2415 return MPP_OK;
2416 }
2417
vepu580_h265e_use_pass1_patch(H265eV580RegSet * regs,H265eV580HalContext * ctx)2418 static MPP_RET vepu580_h265e_use_pass1_patch(H265eV580RegSet *regs, H265eV580HalContext *ctx)
2419 {
2420 hevc_vepu580_control_cfg *reg_ctl = ®s->reg_ctl;
2421 hevc_vepu580_base *reg_base = ®s->reg_base;
2422 RK_U32 hor_stride = MPP_ALIGN(ctx->cfg->prep.width, 64);
2423 RK_U32 ver_stride = MPP_ALIGN(ctx->cfg->prep.height, 16);
2424 RK_U32 frame_size = hor_stride * ver_stride;
2425 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
2426 MPP_RET ret = MPP_OK;
2427
2428 reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;
2429 reg_base->reg0198_src_fmt.src_cfmt = VEPU541_FMT_YUV420SP;
2430 reg_base->reg0198_src_fmt.out_fmt = 1;
2431 reg_base->reg0203_src_proc.afbcd_en = 0;
2432 reg_base->reg0205_src_strd0.src_strd0 = hor_stride;
2433 reg_base->reg0206_src_strd1.src_strd1 = hor_stride;
2434 reg_base->reg0160_adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1);
2435 reg_base->reg0161_adr_src1 = reg_base->reg0160_adr_src0;
2436 reg_base->reg0162_adr_src2 = reg_base->reg0160_adr_src0;
2437
2438 /* input cb addr */
2439 ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, frame_size);
2440 if (ret)
2441 mpp_err_f("set input cb addr offset failed %d\n", ret);
2442
2443 /* input cr addr */
2444 ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 162, frame_size);
2445 if (ret)
2446 mpp_err_f("set input cr addr offset failed %d\n", ret);
2447
2448 return MPP_OK;
2449 }
2450
setup_vepu580_split(H265eV580RegSet * regs,MppEncCfgSet * enc_cfg,RK_U32 title_en)2451 static void setup_vepu580_split(H265eV580RegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)
2452 {
2453 MppEncSliceSplit *cfg = &enc_cfg->split;
2454
2455 hal_h265e_dbg_func("enter\n");
2456
2457 switch (cfg->split_mode) {
2458 case MPP_ENC_SPLIT_NONE : {
2459 regs->reg_base.reg0216_sli_splt.sli_splt = 0;
2460 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;
2461 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
2462 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 0;
2463 regs->reg_base.reg0216_sli_splt.sli_flsh = 0;
2464 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;
2465
2466 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
2467 regs->reg_base.reg0192_enc_pic.slen_fifo = 0;
2468 } break;
2469 case MPP_ENC_SPLIT_BY_BYTE : {
2470 regs->reg_base.reg0216_sli_splt.sli_splt = 1;
2471 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;
2472 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
2473 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;
2474 regs->reg_base.reg0216_sli_splt.sli_flsh = 1;
2475 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;
2476
2477 regs->reg_base.reg0217_sli_byte.sli_splt_byte = cfg->split_arg;
2478 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
2479 } break;
2480 case MPP_ENC_SPLIT_BY_CTU : {
2481 RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 64) / 64;
2482 RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 64) / 64;
2483 RK_U32 slice_num = 0;
2484
2485 if (title_en)
2486 mb_w = mb_w / 2;
2487
2488 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
2489
2490 regs->reg_base.reg0216_sli_splt.sli_splt = 1;
2491 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 1;
2492 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
2493 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;
2494 regs->reg_base.reg0216_sli_splt.sli_flsh = 1;
2495 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
2496
2497 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
2498 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
2499 regs->reg_ctl.reg0008_int_en.slc_done_en = (cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ? 1 : 0;
2500
2501 if (slice_num > VEPU580_SLICE_FIFO_LEN)
2502 regs->reg_ctl.reg0008_int_en.slc_done_en = 1;
2503 } break;
2504 default : {
2505 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
2506 } break;
2507 }
2508
2509 cfg->change = 0;
2510
2511 hal_h265e_dbg_func("leave\n");
2512 }
2513
hal_h265e_v580_gen_regs(void * hal,HalEncTask * task)2514 MPP_RET hal_h265e_v580_gen_regs(void *hal, HalEncTask *task)
2515 {
2516 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
2517 HalEncTask *enc_task = task;
2518 EncRcTask *rc_task = enc_task->rc_task;
2519 EncFrmStatus *frm = &rc_task->frm;
2520 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
2521 H265eV580RegSet *regs = (H265eV580RegSet *)ctx->regs[0];
2522 RK_U32 pic_width_align8, pic_height_align8;
2523 RK_S32 pic_wd64, pic_h64;
2524 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
2525 hevc_vepu580_control_cfg *reg_ctl = ®s->reg_ctl;
2526 hevc_vepu580_base *reg_base = ®s->reg_base;
2527 hevc_vepu580_rc_klut *reg_klut = ®s->reg_rc_klut;
2528 EncFrmStatus *frm_status = &task->rc_task->frm;
2529
2530 hal_h265e_enter();
2531 pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
2532 pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
2533 pic_wd64 = (syn->pp.pic_width + 63) / 64;
2534 pic_h64 = (syn->pp.pic_height + 63) / 64;
2535
2536 hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
2537 ctx->frame_cnt, ctx->frame_type);
2538
2539 memset(regs, 0, sizeof(H265eV580RegSet));
2540
2541 reg_ctl->reg0004_enc_strt.lkt_num = 0;
2542 reg_ctl->reg0004_enc_strt.vepu_cmd = ctx->enc_mode;
2543 reg_ctl->reg0005_enc_clr.safe_clr = 0x0;
2544 reg_ctl->reg0005_enc_clr.force_clr = 0x0;
2545
2546 reg_ctl->reg0008_int_en.enc_done_en = 1;
2547 reg_ctl->reg0008_int_en.lkt_node_done_en = 1;
2548 reg_ctl->reg0008_int_en.sclr_done_en = 1;
2549 reg_ctl->reg0008_int_en.slc_done_en = 0;
2550 reg_ctl->reg0008_int_en.bsf_oflw_en = 1;
2551 reg_ctl->reg0008_int_en.brsp_otsd_en = 1;
2552 reg_ctl->reg0008_int_en.wbus_err_en = 1;
2553 reg_ctl->reg0008_int_en.rbus_err_en = 1;
2554 reg_ctl->reg0008_int_en.wdg_en = 1;
2555 reg_ctl->reg0008_int_en.lkt_err_int_en = 0;
2556
2557 reg_ctl->reg0012_dtrns_map.lpfw_bus_ordr = 0x0;
2558 reg_ctl->reg0012_dtrns_map.cmvw_bus_ordr = 0x0;
2559 reg_ctl->reg0012_dtrns_map.dspw_bus_ordr = 0x0;
2560 reg_ctl->reg0012_dtrns_map.rfpw_bus_ordr = 0x0;
2561 reg_ctl->reg0012_dtrns_map.src_bus_edin = 0x0;
2562 reg_ctl->reg0012_dtrns_map.meiw_bus_edin = 0x0;
2563 reg_ctl->reg0012_dtrns_map.bsw_bus_edin = 0x7;
2564 reg_ctl->reg0012_dtrns_map.lktr_bus_edin = 0x0;
2565 reg_ctl->reg0012_dtrns_map.roir_bus_edin = 0x0;
2566 reg_ctl->reg0012_dtrns_map.lktw_bus_edin = 0x0;
2567 reg_ctl->reg0012_dtrns_map.afbc_bsize = 0x1;
2568 reg_ctl->reg0012_dtrns_map.ebufw_bus_ordr = 0x0;
2569
2570 reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME);
2571 reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0;
2572 reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff;
2573 reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0;
2574
2575 reg_ctl->reg0021_func_en.cke = 1;
2576 reg_ctl->reg0021_func_en.resetn_hw_en = 1;
2577 reg_ctl->reg0021_func_en.enc_done_tmvp_en = 1;
2578
2579 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
2580 reg_base->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7)
2581 ? (8 - (syn->pp.pic_width & 0x7)) : 0;
2582 reg_base->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
2583 reg_base->reg0197_src_fill.pic_hfill = (syn->pp.pic_height & 0x7)
2584 ? (8 - (syn->pp.pic_height & 0x7)) : 0;
2585
2586 reg_base->reg0192_enc_pic.enc_stnd = 1; //H265
2587 reg_base->reg0192_enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered
2588 reg_base->reg0192_enc_pic.bs_scp = 1;
2589 reg_base->reg0192_enc_pic.log2_ctu_num = ceil(log2((double)pic_wd64 * pic_h64));
2590
2591 reg_base->reg0203_src_proc.src_mirr = 0;
2592 reg_base->reg0203_src_proc.src_rot = 0;
2593 reg_base->reg0203_src_proc.txa_en = 1;
2594 reg_base->reg0203_src_proc.afbcd_en = (MPP_FRAME_FMT_IS_FBC(syn->pp.mpp_format)) ? 1 : 0;
2595
2596 reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 0 : 3;
2597 memcpy(®_klut->klut_wgt0, &klut_weight[0], sizeof(klut_weight));
2598
2599 vepu580_h265_set_me_regs(ctx, syn, reg_base);
2600
2601 reg_base->reg0232_rdo_cfg.chrm_spcl = 1;
2602 reg_base->reg0232_rdo_cfg.cu_inter_e = 0x06db;
2603 reg_base->reg0232_rdo_cfg.cu_intra_e = 0xf;
2604
2605 if (syn->pp.num_long_term_ref_pics_sps) {
2606 reg_base->reg0232_rdo_cfg.ltm_col = 0;
2607 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 1;
2608 } else {
2609 reg_base->reg0232_rdo_cfg.ltm_col = 0;
2610 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 0;
2611 }
2612
2613 reg_base->reg0232_rdo_cfg.ccwa_e = 1;
2614 reg_base->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;
2615 {
2616 RK_U32 i_nal_type = 0;
2617
2618 /* TODO: extend syn->frame_coding_type definition */
2619 if (ctx->frame_type == INTRA_FRAME) {
2620 /* reset ref pictures */
2621 i_nal_type = NAL_IDR_W_RADL;
2622 } else if (ctx->frame_type == INTER_P_FRAME ) {
2623 i_nal_type = NAL_TRAIL_R;
2624 } else {
2625 i_nal_type = NAL_TRAIL_R;
2626 }
2627 reg_base->reg0236_synt_nal.nal_unit_type = i_nal_type;
2628 }
2629
2630 vepu580_h265_set_hw_address(ctx, reg_base, task);
2631 vepu580_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep, task);
2632 vepu580_h265_set_rc_regs(ctx, regs, task);
2633 vepu580_h265_set_slice_regs(syn, reg_base);
2634 vepu580_h265_set_ref_regs(syn, reg_base);
2635
2636 vepu580_set_osd(&ctx->osd_cfg);
2637 /* ROI configure */
2638 vepu580_h265_set_roi_regs(ctx, reg_base);
2639 if (frm_status->is_i_refresh)
2640 setup_intra_refresh(regs, ctx, frm_status->seq_idx % ctx->cfg->rc.gop);
2641
2642 /*paramet cfg*/
2643 vepu580_h265_global_cfg_set(ctx, regs);
2644
2645 vepu580_h265e_tune_reg_patch(ctx->tune);
2646 setup_vepu580_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag);
2647 /* two pass register patch */
2648 if (frm->save_pass1)
2649 vepu580_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag);
2650
2651 if (frm->use_pass1)
2652 vepu580_h265e_use_pass1_patch(regs, ctx);
2653
2654 ctx->frame_num++;
2655
2656 hal_h265e_leave();
2657 return MPP_OK;
2658 }
2659
hal_h265e_v580_set_uniform_tile(hevc_vepu580_base * regs,H265eSyntax_new * syn,RK_U32 index)2660 void hal_h265e_v580_set_uniform_tile(hevc_vepu580_base *regs, H265eSyntax_new *syn, RK_U32 index)
2661 {
2662 if (syn->pp.tiles_enabled_flag) {
2663 RK_S32 mb_w = MPP_ALIGN(syn->pp.pic_width, 64) / 64;
2664 RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64;
2665 RK_S32 tile_width = (index + 1) * mb_w / (syn->pp.num_tile_columns_minus1 + 1) -
2666 index * mb_w / (syn->pp.num_tile_columns_minus1 + 1);
2667
2668 if (index > 0) {
2669 regs->reg0193_dual_core.dchs_txid = index;
2670 regs->reg0193_dual_core.dchs_rxid = index - 1;
2671 regs->reg0193_dual_core.dchs_txe = 1;
2672 regs->reg0193_dual_core.dchs_rxe = 1;
2673 } else {
2674 regs->reg0193_dual_core.dchs_txid = index;
2675 regs->reg0193_dual_core.dchs_rxid = 0;
2676 regs->reg0193_dual_core.dchs_txe = 1;
2677 regs->reg0193_dual_core.dchs_rxe = 0;
2678 }
2679 /* dual core runtime offset should set to 2 to avoid data access conflict */
2680 regs->reg0193_dual_core.dchs_ofst = 2;
2681
2682 if (index == syn->pp.num_tile_columns_minus1) {
2683 tile_width = mb_w - index * mb_w / (syn->pp.num_tile_columns_minus1 + 1);
2684 regs->reg0193_dual_core.dchs_txid = 0;
2685 regs->reg0193_dual_core.dchs_txe = 0;
2686 }
2687 regs->reg0252_tile_cfg.tile_w_m1 = tile_width - 1;
2688 regs->reg0252_tile_cfg.tile_h_m1 = mb_h - 1;
2689 regs->reg212_rc_cfg.rc_ctu_num = tile_width;
2690 regs->reg0252_tile_cfg.tile_en = syn->pp.tiles_enabled_flag;
2691 regs->reg0253_tile_pos.tile_x = (index * mb_w / (syn->pp.num_tile_columns_minus1 + 1));
2692 regs->reg0253_tile_pos.tile_y = 0;
2693
2694 hal_h265e_dbg_detail("tile_x %d, rc_ctu_num %d, tile_width_m1 %d",
2695 regs->reg0253_tile_pos.tile_x, regs->reg212_rc_cfg.rc_ctu_num,
2696 regs->reg0252_tile_cfg.tile_w_m1);
2697 }
2698 }
2699
hal_h265e_v580_start(void * hal,HalEncTask * enc_task)2700 MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
2701 {
2702 MPP_RET ret = MPP_OK;
2703 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
2704 RK_U32 k = 0;
2705 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
2706 RK_U32 tile_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1);
2707 hal_h265e_enter();
2708 RK_U32 stream_len = 0;
2709 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
2710
2711 ctx->tile_num = tile_num;
2712
2713 if (enc_task->flags.err) {
2714 hal_h265e_err("enc_task->flags.err %08x, return e arly",
2715 enc_task->flags.err);
2716 return MPP_NOK;
2717 }
2718
2719 if (tile_num > MAX_TILE_NUM) {
2720 mpp_log("tile_num big then support %d, max %d", tile_num, MAX_TILE_NUM);
2721 return MPP_NOK;
2722 }
2723
2724 for (k = 0; k < tile_num; k++) {
2725 H265eV580RegSet *hw_regs = (H265eV580RegSet *)ctx->regs[k];
2726 hevc_vepu580_base *reg_base = &hw_regs->reg_base;
2727 H265eV580StatusElem *reg_out = (H265eV580StatusElem *)ctx->reg_out[k];
2728
2729 if (k)
2730 memcpy(hw_regs, ctx->regs[0], sizeof(*hw_regs));
2731
2732 vepu580_h265_set_me_ram(syn, &hw_regs->reg_base, k);
2733
2734 /* set input info */
2735 vepu580_h265_set_patch_info(ctx->reg_cfg, syn, (Vepu541Fmt)fmt->format, enc_task);
2736 if (tile_num > 1)
2737 hal_h265e_v580_set_uniform_tile(&hw_regs->reg_base, syn, k);
2738
2739 if (k) {
2740 RK_U32 offset = 0;
2741
2742 reg_base->reg0176_lpfw_addr = mpp_buffer_get_fd(ctx->hw_tile_buf[k]);
2743 reg_base->reg0177_lpfr_addr = mpp_buffer_get_fd(ctx->hw_tile_buf[k - 1]);
2744
2745 if (!ctx->tile_parall_en) {
2746 offset = mpp_packet_get_length(enc_task->packet);
2747 offset += stream_len;
2748
2749 reg_base->reg0173_bsbb_addr = mpp_buffer_get_fd(enc_task->output);
2750
2751 mpp_dev_multi_offset_update(ctx->reg_cfg, 175, offset);
2752 mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
2753 } else {
2754 reg_base->reg0172_bsbt_addr = mpp_buffer_get_fd(ctx->hw_tile_stream[k - 1]);
2755 /* TODO: stream size relative with syntax */
2756 reg_base->reg0173_bsbb_addr = reg_base->reg0172_bsbt_addr;
2757 reg_base->reg0174_bsbr_addr = reg_base->reg0172_bsbt_addr;
2758 reg_base->reg0175_adr_bsbs = reg_base->reg0172_bsbt_addr;
2759
2760 mpp_dev_multi_offset_update(ctx->reg_cfg, 175, 0);
2761 mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(ctx->hw_tile_stream[k - 1]));
2762 }
2763
2764 offset = ctx->fbc_header_len;
2765
2766 mpp_dev_multi_offset_update(ctx->reg_cfg, 166, offset);
2767 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, offset);
2768
2769 if (enc_task->rc_task->frm.save_pass1)
2770 vepu580_h265e_save_pass1_patch(hw_regs, ctx, syn->pp.tiles_enabled_flag);
2771
2772 if (enc_task->rc_task->frm.use_pass1)
2773 vepu580_h265e_use_pass1_patch(hw_regs, ctx);
2774 }
2775 hal_h265e_v580_send_regs(ctx->dev, hw_regs, reg_out);
2776
2777 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->reg_cfg);
2778
2779 if (k < tile_num - 1) {
2780 if (!ctx->tile_parall_en) {
2781 vepu580_h265_fbk *fb = &ctx->feedback;
2782
2783 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
2784 if (ret) {
2785 mpp_err_f("send cmd failed %d\n", ret);
2786 }
2787
2788 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
2789 if (ret) {
2790 mpp_err_f("poll cmd failed %d\n", ret);
2791 ret = MPP_ERR_VPUHW;
2792 }
2793 stream_len += reg_out->st.bs_lgth_l32;
2794 fb->qp_sum += reg_out->st.qp_sum;
2795 fb->out_strm_size += reg_out->st.bs_lgth_l32;
2796 fb->sse_sum += (RK_S64)(reg_out->st.sse_h32 << 16) +
2797 ((reg_out->st.st_sse_bsl.sse_l16 >> 16) & 0xffff);
2798 fb->st_madi += reg_out->st.madi;
2799 fb->st_madp += reg_out->st.madp;
2800 fb->st_mb_num += reg_out->st.st_bnum_b16.num_b16;
2801 fb->st_ctu_num += reg_out->st.st_bnum_cme.num_ctu;
2802 } else
2803 mpp_dev_ioctl(ctx->dev, MPP_DEV_DELIMIT, NULL);
2804 }
2805 }
2806
2807 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
2808 if (ret) {
2809 mpp_err_f("send cmd failed %d\n", ret);
2810 }
2811 hal_h265e_leave();
2812 return ret;
2813 }
2814
vepu580_h265_set_feedback(H265eV580HalContext * ctx,HalEncTask * enc_task,RK_U32 index)2815 static MPP_RET vepu580_h265_set_feedback(H265eV580HalContext *ctx, HalEncTask *enc_task, RK_U32 index)
2816 {
2817 EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
2818 vepu580_h265_fbk *fb = &ctx->feedback;
2819 MppEncCfgSet *cfg = ctx->cfg;
2820 RK_S32 mb64_num = ((cfg->prep.width + 63) / 64) * ((cfg->prep.height + 63) / 64);
2821 RK_S32 mb8_num = (mb64_num << 6);
2822 RK_S32 mb4_num = (mb8_num << 2);
2823
2824 hal_h265e_enter();
2825 H265eV580StatusElem *elem = (H265eV580StatusElem *)ctx->reg_out[index];
2826 RK_U32 hw_status = elem->hw_status;
2827
2828 fb->qp_sum += elem->st.qp_sum;
2829
2830 fb->out_strm_size += elem->st.bs_lgth_l32;
2831
2832 fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
2833 ((elem->st.st_sse_bsl.sse_l16 >> 16) & 0xffff);
2834
2835 fb->hw_status = hw_status;
2836 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
2837 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
2838 hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
2839
2840 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
2841 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
2842
2843 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
2844 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
2845
2846 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
2847 hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
2848
2849 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
2850 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
2851
2852 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
2853 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
2854
2855 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
2856 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
2857
2858 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
2859 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
2860
2861 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
2862 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
2863
2864 fb->st_madi += elem->st.madi;
2865 fb->st_madp += elem->st.madp;
2866 fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
2867 fb->st_ctu_num += elem->st.st_bnum_cme.num_ctu;
2868
2869 fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;
2870 fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;
2871 fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;
2872 fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;
2873 fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;
2874 fb->st_lvl8_inter_num += elem->st.st_pnum_p8.pnum_p8;
2875 fb->st_lvl8_intra_num += elem->st.st_pnum_i8.pnum_i8;
2876 fb->st_lvl4_intra_num += elem->st.st_pnum_i4.pnum_i4;
2877 memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp0, 52 * sizeof(RK_U32));
2878
2879 if (index == (ctx->tile_num - 1)) {
2880 hal_rc_ret->bit_real += fb->out_strm_size * 8;
2881
2882 if (fb->st_mb_num) {
2883 fb->st_madi = fb->st_madi / fb->st_mb_num;
2884 } else {
2885 fb->st_madi = 0;
2886 }
2887 if (fb->st_ctu_num) {
2888 fb->st_madp = fb->st_madp / fb->st_ctu_num;
2889 } else {
2890 fb->st_madp = 0;
2891 }
2892
2893 if (mb4_num > 0)
2894 hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
2895 (fb->st_lvl16_intra_num << 4) +
2896 (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
2897
2898 if (mb64_num > 0) {
2899 /*
2900 hal_cfg[k].inter_lv8_prop = ((fb->st_lvl8_inter_num + (fb->st_lvl16_inter_num << 2) +
2901 (fb->st_lvl32_inter_num << 4) +
2902 (fb->st_lvl64_inter_num << 6)) << 8) / mb8_num;*/
2903
2904 hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
2905 // hal_cfg[k].sse = fb->sse_sum / mb64_num;
2906 }
2907
2908 hal_rc_ret->madi += fb->st_madi;
2909 hal_rc_ret->madp += fb->st_madp;
2910 }
2911 hal_h265e_leave();
2912 return MPP_OK;
2913 }
2914
save_to_file(char * name,void * ptr,size_t size)2915 void save_to_file(char *name, void *ptr, size_t size)
2916 {
2917 FILE *fp = fopen(name, "w+b");
2918 if (fp) {
2919 fwrite(ptr, 1, size, fp);
2920 fclose(fp);
2921 } else
2922 mpp_err("create file %s failed\n", name);
2923 }
2924
dump_files(H265eV580HalContext * ctx,HalEncTask * enc_task)2925 void dump_files(H265eV580HalContext *ctx, HalEncTask *enc_task)
2926 {
2927 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
2928 HalBuf *hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
2929 size_t buf_size = mpp_buffer_get_size(hal_buf->buf[0]);
2930 size_t dws_size = mpp_buffer_get_size(hal_buf->buf[1]);
2931 void *ptr = mpp_buffer_get_ptr(hal_buf->buf[0]);
2932 void *dws_ptr = mpp_buffer_get_ptr(hal_buf->buf[1]);
2933 RK_U32 frm_num = ctx->frame_num;
2934 RK_S32 pid = getpid();
2935 char name[128];
2936 size_t name_len = sizeof(name) - 1;
2937
2938 snprintf(name, name_len, "/data/refr_fbd_%d_frm%d.bin", pid, frm_num);
2939 save_to_file(name, ptr + ctx->fbc_header_len, buf_size - ctx->fbc_header_len);
2940
2941 snprintf(name, name_len, "/data/refr_fbh_%d_frm%d.bin", pid, frm_num);
2942 save_to_file(name, ptr, ctx->fbc_header_len);
2943
2944 snprintf(name, name_len, "/data/refr_dsp_%d_frm%d.bin", pid, frm_num);
2945 save_to_file(name, dws_ptr, dws_size);
2946
2947 hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
2948 buf_size = mpp_buffer_get_size(hal_buf->buf[0]);
2949 dws_size = mpp_buffer_get_size(hal_buf->buf[1]);
2950 ptr = mpp_buffer_get_ptr(hal_buf->buf[0]);
2951 dws_ptr = mpp_buffer_get_ptr(hal_buf->buf[1]);
2952
2953 snprintf(name, name_len, "/data/recn_fbd_%d_frm%d.bin", pid, frm_num);
2954 save_to_file(name, ptr + ctx->fbc_header_len, buf_size - ctx->fbc_header_len);
2955
2956 snprintf(name, name_len, "/data/recn_fbh_%d_frm%d.bin", pid, frm_num);
2957 save_to_file(name, ptr, ctx->fbc_header_len);
2958
2959 snprintf(name, name_len, "/data/recn_dsp_%d_frm%d.bin", pid, frm_num);
2960 save_to_file(name, dws_ptr, dws_size);
2961 }
2962
hal_h265e_vepu580_status_check(RK_U32 hw_status)2963 static MPP_RET hal_h265e_vepu580_status_check(RK_U32 hw_status)
2964 {
2965 MPP_RET ret = MPP_OK;
2966
2967 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
2968 hal_h265e_dbg_detail("RKV_ENC_INT_LINKTABLE_FINISH");
2969
2970 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
2971 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
2972
2973 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
2974 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
2975
2976 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
2977 hal_h265e_dbg_detail("RKV_ENC_INT_SAFE_CLEAR_FINISH");
2978
2979 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW) {
2980 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
2981 ret = MPP_NOK;
2982 }
2983
2984 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL) {
2985 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
2986 ret = MPP_NOK;
2987 }
2988
2989 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR) {
2990 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
2991 ret = MPP_NOK;
2992 }
2993
2994 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR) {
2995 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
2996 ret = MPP_NOK;
2997 }
2998
2999 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR) {
3000 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
3001 ret = MPP_NOK;
3002 }
3003
3004 return ret;
3005 }
3006
hal_h265e_v580_wait(void * hal,HalEncTask * task)3007 MPP_RET hal_h265e_v580_wait(void *hal, HalEncTask *task)
3008 {
3009 MPP_RET ret = MPP_OK;
3010 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
3011 HalEncTask *enc_task = task;
3012 RK_U32 split_out = ctx->cfg->split.split_out;
3013
3014 hal_h265e_enter();
3015
3016 if (enc_task->flags.err) {
3017 hal_h265e_err("enc_task->flags.err %08x, return early",
3018 enc_task->flags.err);
3019 return MPP_NOK;
3020 }
3021
3022 if (split_out) {
3023 EncOutParam param;
3024 RK_U32 slice_len = 0;
3025 RK_U32 slice_last = 0;
3026 RK_U32 finish_cnt = 0;
3027 RK_U32 tile1_offset = 0;
3028 MppPacket pkt = enc_task->packet;
3029 RK_U32 offset = mpp_packet_get_length(pkt);
3030 RK_U32 seg_offset = offset;
3031 void* ptr = mpp_packet_get_pos(pkt);
3032 H265eV580RegSet *regs = (H265eV580RegSet *)ctx->regs[0];
3033 hevc_vepu580_base *reg_base = ®s->reg_base;
3034 RK_U32 type = reg_base->reg0236_synt_nal.nal_unit_type;
3035 MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs);
3036
3037 param.task = task;
3038 param.base = mpp_packet_get_data(task->packet);
3039
3040 do {
3041 RK_S32 i = 0;
3042 poll_cfg->poll_type = 0;
3043 poll_cfg->poll_ret = 0;
3044 poll_cfg->count_max = ctx->poll_slice_max;
3045 poll_cfg->count_ret = 0;
3046
3047 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
3048
3049 for (i = 0; i < poll_cfg->count_ret; i++) {
3050 slice_last = poll_cfg->slice_info[i].last;
3051 slice_len = poll_cfg->slice_info[i].length;
3052 param.length = slice_len;
3053
3054 if (finish_cnt > 0) {
3055 void *tile1_ptr = mpp_buffer_get_ptr(ctx->hw_tile_stream[finish_cnt - 1]);
3056
3057 memcpy(ptr + seg_offset, tile1_ptr + tile1_offset, slice_len);
3058 tile1_offset += slice_len;
3059 }
3060
3061 ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
3062 if (slice_last) {
3063 finish_cnt++;
3064 tile1_offset = 0;
3065 if (ctx->tile_parall_en) {
3066 if (finish_cnt + 1 > ctx->tile_num) {
3067 ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
3068 }
3069 }
3070 }
3071
3072 mpp_packet_add_segment_info(pkt, type, seg_offset, slice_len);
3073
3074 if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY)
3075 mpp_callback(ctx->output_cb, ¶m);
3076
3077 seg_offset += slice_len;
3078 }
3079
3080 if (ctx->tile_parall_en) {
3081 if (finish_cnt + 1 > ctx->tile_num) {
3082 break;
3083 }
3084 } else if (slice_last) {
3085 break;
3086 }
3087 } while (1);
3088 } else {
3089 H265eV580StatusElem *elem = (H265eV580StatusElem *)ctx->reg_out;
3090 H265eV580RegSet *regs = (H265eV580RegSet *)ctx->regs[0];
3091 hevc_vepu580_base *reg_base = ®s->reg_base;
3092 RK_U32 type = reg_base->reg0236_synt_nal.nal_unit_type;
3093 MppPacket pkt = enc_task->packet;
3094 RK_U32 offset = mpp_packet_get_length(pkt);
3095 RK_U32 i = 0;
3096
3097 if (ctx->tile_parall_en) {
3098 for (i = 0; i < ctx->tile_num; i ++)
3099 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
3100 } else {
3101 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
3102 }
3103
3104 for (i = 0; i < ctx->tile_num; i++) {
3105 H265eV580StatusElem *elem_ret = (H265eV580StatusElem *)ctx->reg_out[i];
3106 RK_U32 hw_status = elem_ret->hw_status;
3107 RK_U32 tile_size = elem_ret->st.bs_lgth_l32;
3108
3109 ret = hal_h265e_vepu580_status_check(hw_status);
3110 if (ret)
3111 break;
3112 mpp_packet_add_segment_info(pkt, type, offset, tile_size);
3113 offset += tile_size;
3114
3115 if (ctx->tile_dump_err &&
3116 (hw_status & (RKV_ENC_INT_BUS_WRITE_ERROR | RKV_ENC_INT_BUS_READ_ERROR))) {
3117 dump_files(ctx, enc_task);
3118 break;
3119 }
3120 }
3121
3122 if (ret)
3123 mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
3124 }
3125
3126 hal_h265e_leave();
3127
3128 return ret;
3129 }
3130
hal_h265e_v580_get_task(void * hal,HalEncTask * task)3131 MPP_RET hal_h265e_v580_get_task(void *hal, HalEncTask *task)
3132 {
3133 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
3134 MppFrame frame = task->frame;
3135 EncFrmStatus *frm_status = &task->rc_task->frm;
3136
3137 hal_h265e_enter();
3138
3139 if (vepu580_h265_setup_hal_bufs(ctx)) {
3140 hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
3141 task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
3142 return MPP_ERR_MALLOC;
3143 }
3144
3145 if (!frm_status->reencode)
3146 ctx->last_frame_type = ctx->frame_type;
3147
3148 if (frm_status->is_intra) {
3149 ctx->frame_type = INTRA_FRAME;
3150 } else {
3151 ctx->frame_type = INTER_P_FRAME;
3152 }
3153 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
3154 MppMeta meta = mpp_frame_get_meta(frame);
3155
3156 mpp_meta_get_ptr_d(meta, KEY_ROI_DATA2, (void **)&ctx->roi_data, NULL);
3157 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data, NULL);
3158 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA2, (void **)&ctx->osd_cfg.osd_data2, NULL);
3159 }
3160 memset(&ctx->feedback, 0, sizeof(vepu580_h265_fbk));
3161 task->part_first = 1;
3162 task->part_last = 0;
3163
3164 mpp_dev_multi_offset_reset(ctx->reg_cfg);
3165
3166 hal_h265e_leave();
3167 return MPP_OK;
3168 }
3169
hal_h265e_v580_ret_task(void * hal,HalEncTask * task)3170 MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
3171 {
3172 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
3173 HalEncTask *enc_task = task;
3174 vepu580_h265_fbk *fb = &ctx->feedback;
3175
3176 hal_h265e_enter();
3177
3178 if (ctx->tile_parall_en) {
3179 RK_U32 i = 0, stream_len = 0;;
3180 RK_U32 offset = mpp_packet_get_length(enc_task->packet);
3181 void* ptr = mpp_packet_get_pos(enc_task->packet);
3182
3183 for (i = 0; i < ctx->tile_num; i ++) {
3184 vepu580_h265_set_feedback(ctx, enc_task, i);
3185 if (!ctx->cfg->split.split_out) {
3186 if (i) { //copy tile 1 stream
3187 RK_U32 len = fb->out_strm_size - stream_len;
3188 void *tile1_ptr = mpp_buffer_get_ptr(ctx->hw_tile_stream[i - 1]);
3189 memcpy(ptr + stream_len + offset, tile1_ptr, len);
3190 }
3191 stream_len = fb->out_strm_size;
3192 }
3193 }
3194 } else {
3195 vepu580_h265_set_feedback(ctx, enc_task, ctx->tile_num - 1);
3196 }
3197
3198 enc_task->hw_length = fb->out_strm_size;
3199 enc_task->length += fb->out_strm_size;
3200
3201 vepu580_h265e_tune_stat_update(ctx->tune);
3202
3203 hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
3204
3205 hal_h265e_leave();
3206 return MPP_OK;
3207 }
3208
3209 const MppEncHalApi hal_h265e_vepu580 = {
3210 "hal_h265e_v580",
3211 MPP_VIDEO_CodingHEVC,
3212 sizeof(H265eV580HalContext),
3213 0,
3214 hal_h265e_v580_init,
3215 hal_h265e_v580_deinit,
3216 hal_h265e_vepu580_prepare,
3217 hal_h265e_v580_get_task,
3218 hal_h265e_v580_gen_regs,
3219 hal_h265e_v580_start,
3220 hal_h265e_v580_wait,
3221 NULL,
3222 NULL,
3223 hal_h265e_v580_ret_task,
3224 };
3225