1 /*
2 * Copyright 2022 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h264e_vepu540c"
18
19 #include <string.h>
20
21 #include "mpp_env.h"
22 #include "mpp_mem.h"
23 #include "mpp_common.h"
24 #include "mpp_frame_impl.h"
25 #include "mpp_rc.h"
26
27 #include "h264e_sps.h"
28 #include "h264e_pps.h"
29 #include "h264e_slice.h"
30
31 #include "hal_h264e_debug.h"
32 #include "hal_bufs.h"
33 #include "mpp_enc_hal.h"
34 #include "vepu541_common.h"
35 #include "vepu540c_common.h"
36
37 #include "hal_h264e_vepu540c_reg.h"
38
39 #define DUMP_REG 0
40 #define MAX_CORE_NUM 2
41
42 typedef struct vepu540c_h264e_reg_ctx_t {
43 void *reg;
44 RK_U32 used;
45 } Vepu540cH264eRegCtx;
46
47 typedef struct HalH264eVepu540cCtx_t {
48 MppEncCfgSet *cfg;
49
50 MppDev dev;
51 RK_S32 frame_cnt;
52
53 /* buffers management */
54 HalBufs hw_recn;
55 RK_S32 pixel_buf_fbc_hdr_size;
56 RK_S32 pixel_buf_fbc_bdy_size;
57 RK_S32 pixel_buf_size;
58 RK_S32 thumb_buf_size;
59 RK_S32 max_buf_cnt;
60
61 /* syntax for input from enc_impl */
62 RK_U32 updated;
63 H264eSps *sps;
64 H264ePps *pps;
65 H264eSlice *slice;
66 H264eFrmInfo *frms;
67 H264eReorderInfo *reorder;
68 H264eMarkingInfo *marking;
69 H264ePrefixNal *prefix;
70
71 /* syntax for output to enc_impl */
72 EncRcTaskInfo hal_rc_cfg;
73
74 /* roi */
75 void *roi_data;
76
77 /* register */
78 HalVepu540cRegSet *regs_set;
79
80 /* external line buffer over 3K */
81 MppBufferGroup ext_line_buf_grp;
82 RK_S32 ext_line_buf_size;
83 MppBuffer ext_line_buf;
84 } HalH264eVepu540cCtx;
85
86 static RK_U32 dump_l1_reg = 0;
87 static RK_U32 dump_l2_reg = 0;
88
89 static RK_S32 h264_aq_tthd_default[16] = {
90 0, 0, 0, 0,
91 3, 3, 5, 5,
92 8, 8, 8, 15,
93 15, 20, 25, 25,
94 };
95
96 static RK_S32 h264_P_aq_step_default[16] = {
97 -8, -7, -6, -5,
98 -4, -3, -2, -1,
99 0, 1, 2, 3,
100 4, 5, 7, 8,
101 };
102
103 static RK_S32 h264_I_aq_step_default[16] = {
104 -8, -7, -6, -5,
105 -4, -3, -2, -1,
106 0, 1, 3, 3,
107 4, 5, 8, 8,
108 };
109
hal_h264e_vepu540c_deinit(void * hal)110 static MPP_RET hal_h264e_vepu540c_deinit(void *hal)
111 {
112 HalH264eVepu540cCtx *p = (HalH264eVepu540cCtx *)hal;
113 hal_h264e_dbg_func("enter %p\n", p);
114
115 if (p->dev) {
116 mpp_dev_deinit(p->dev);
117 p->dev = NULL;
118 }
119
120 if (p->ext_line_buf) {
121 mpp_buffer_put(p->ext_line_buf);
122 p->ext_line_buf = NULL;
123 }
124
125 if (p->ext_line_buf_grp) {
126 mpp_buffer_group_put(p->ext_line_buf_grp);
127 p->ext_line_buf_grp = NULL;
128 }
129
130 if (p->hw_recn) {
131 hal_bufs_deinit(p->hw_recn);
132 p->hw_recn = NULL;
133 }
134
135 MPP_FREE(p->regs_set);
136
137
138 hal_h264e_dbg_func("leave %p\n", p);
139
140 return MPP_OK;
141 }
142
hal_h264e_vepu540c_init(void * hal,MppEncHalCfg * cfg)143 static MPP_RET hal_h264e_vepu540c_init(void *hal, MppEncHalCfg *cfg)
144 {
145 HalH264eVepu540cCtx *p = (HalH264eVepu540cCtx *)hal;
146 MPP_RET ret = MPP_OK;
147 hal_h264e_dbg_func("enter %p\n", p);
148
149 p->cfg = cfg->cfg;
150
151 /* update output to MppEnc */
152 cfg->type = VPU_CLIENT_RKVENC;
153 ret = mpp_dev_init(&cfg->dev, cfg->type);
154 if (ret) {
155 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
156 goto DONE;
157 }
158 p->dev = cfg->dev;
159
160 ret = hal_bufs_init(&p->hw_recn);
161 if (ret) {
162 mpp_err_f("init vepu buffer failed ret: %d\n", ret);
163 goto DONE;
164 }
165
166 { /* setup default hardware config */
167 MppEncHwCfg *hw = &cfg->cfg->hw;
168
169 hw->qp_delta_row_i = 0;
170 hw->qp_delta_row = 1;
171
172 memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i));
173 memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p));
174 memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i));
175 memcpy(hw->aq_step_p, h264_P_aq_step_default, sizeof(hw->aq_step_p));
176 }
177
178 p->regs_set = mpp_calloc(HalVepu540cRegSet, 1);
179
180 if (!p->regs_set) {
181 mpp_err("HalVepu540cRegSet alloc fail");
182 return MPP_ERR_MALLOC;
183 }
184
185 DONE:
186 if (ret)
187 hal_h264e_vepu540c_deinit(hal);
188
189 hal_h264e_dbg_func("leave %p\n", p);
190 return ret;
191 }
192
setup_hal_bufs(HalH264eVepu540cCtx * ctx)193 static void setup_hal_bufs(HalH264eVepu540cCtx *ctx)
194 {
195 MppEncCfgSet *cfg = ctx->cfg;
196 MppEncPrepCfg *prep = &cfg->prep;
197 RK_S32 alignment = 64;
198 RK_S32 aligned_w = MPP_ALIGN(prep->width, alignment);
199 RK_S32 aligned_h = MPP_ALIGN(prep->height, alignment);
200 RK_S32 pixel_buf_fbc_hdr_size = MPP_ALIGN(aligned_w * aligned_h / 64, SZ_8K);
201 RK_S32 pixel_buf_fbc_bdy_size = aligned_w * aligned_h * 3 / 2;
202 RK_S32 pixel_buf_size = pixel_buf_fbc_hdr_size + pixel_buf_fbc_bdy_size;
203 RK_S32 thumb_buf_size = MPP_ALIGN(aligned_w / 64 * aligned_h / 64 * 256, SZ_8K);
204 RK_S32 old_max_cnt = ctx->max_buf_cnt;
205 RK_S32 new_max_cnt = 2;
206 MppEncRefCfg ref_cfg = cfg->ref_cfg;
207
208 if (ref_cfg) {
209 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
210 if (new_max_cnt < MPP_MAX(new_max_cnt, info->dpb_size + 1))
211 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
212 }
213
214 if (aligned_w > (3 * SZ_1K)) {
215 RK_S32 ext_line_buf_size = (aligned_w / 64 - 36) * 56 * 16;
216
217 if (NULL == ctx->ext_line_buf_grp)
218 mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
219 else if (ext_line_buf_size != ctx->ext_line_buf_size) {
220 mpp_buffer_put(ctx->ext_line_buf);
221 ctx->ext_line_buf = NULL;
222 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
223 }
224
225 mpp_assert(ctx->ext_line_buf_grp);
226
227 if (NULL == ctx->ext_line_buf)
228 mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_buf, ext_line_buf_size);
229
230 ctx->ext_line_buf_size = ext_line_buf_size;
231 } else {
232 if (ctx->ext_line_buf) {
233 mpp_buffer_put(ctx->ext_line_buf);
234 ctx->ext_line_buf = NULL;
235 }
236
237 if (ctx->ext_line_buf_grp) {
238 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
239 mpp_buffer_group_put(ctx->ext_line_buf_grp);
240 ctx->ext_line_buf_grp = NULL;
241 }
242 ctx->ext_line_buf_size = 0;
243 }
244
245 if ((ctx->pixel_buf_fbc_hdr_size != pixel_buf_fbc_hdr_size) ||
246 (ctx->pixel_buf_fbc_bdy_size != pixel_buf_fbc_bdy_size) ||
247 (ctx->pixel_buf_size != pixel_buf_size) ||
248 (ctx->thumb_buf_size != thumb_buf_size) ||
249 (new_max_cnt > old_max_cnt)) {
250 size_t sizes[2];
251
252 hal_h264e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
253 ctx->pixel_buf_size, pixel_buf_size,
254 old_max_cnt, new_max_cnt);
255
256 /* pixel buffer */
257 sizes[0] = pixel_buf_size;
258 /* thumb buffer */
259 sizes[1] = thumb_buf_size;
260 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
261
262 hal_bufs_setup(ctx->hw_recn, new_max_cnt, 2, sizes);
263
264 ctx->pixel_buf_fbc_hdr_size = pixel_buf_fbc_hdr_size;
265 ctx->pixel_buf_fbc_bdy_size = pixel_buf_fbc_bdy_size;
266 ctx->pixel_buf_size = pixel_buf_size;
267 ctx->thumb_buf_size = thumb_buf_size;
268 ctx->max_buf_cnt = new_max_cnt;
269 }
270 }
271
hal_h264e_vepu540c_prepare(void * hal)272 static MPP_RET hal_h264e_vepu540c_prepare(void *hal)
273 {
274 HalH264eVepu540cCtx *ctx = (HalH264eVepu540cCtx *)hal;
275 MppEncPrepCfg *prep = &ctx->cfg->prep;
276
277 hal_h264e_dbg_func("enter %p\n", hal);
278
279 if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
280 RK_S32 i;
281
282 // pre-alloc required buffers to reduce first frame delay
283 setup_hal_bufs(ctx);
284 for (i = 0; i < ctx->max_buf_cnt; i++)
285 hal_bufs_get_buf(ctx->hw_recn, i);
286
287 prep->change = 0;
288 }
289
290 hal_h264e_dbg_func("leave %p\n", hal);
291
292 return MPP_OK;
293 }
294
update_vepu540c_syntax(HalH264eVepu540cCtx * ctx,MppSyntax * syntax)295 static RK_U32 update_vepu540c_syntax(HalH264eVepu540cCtx *ctx, MppSyntax *syntax)
296 {
297 H264eSyntaxDesc *desc = syntax->data;
298 RK_S32 syn_num = syntax->number;
299 RK_U32 updated = 0;
300 RK_S32 i;
301
302 for (i = 0; i < syn_num; i++, desc++) {
303 switch (desc->type) {
304 case H264E_SYN_CFG : {
305 hal_h264e_dbg_detail("update cfg");
306 ctx->cfg = desc->p;
307 } break;
308 case H264E_SYN_SPS : {
309 hal_h264e_dbg_detail("update sps");
310 ctx->sps = desc->p;
311 } break;
312 case H264E_SYN_PPS : {
313 hal_h264e_dbg_detail("update pps");
314 ctx->pps = desc->p;
315 } break;
316 case H264E_SYN_DPB : {
317 hal_h264e_dbg_detail("update dpb");
318 } break;
319 case H264E_SYN_SLICE : {
320 hal_h264e_dbg_detail("update slice");
321 ctx->slice = desc->p;
322 } break;
323 case H264E_SYN_FRAME : {
324 hal_h264e_dbg_detail("update frames");
325 ctx->frms = desc->p;
326 } break;
327 case H264E_SYN_PREFIX : {
328 hal_h264e_dbg_detail("update prefix nal");
329 ctx->prefix = desc->p;
330 } break;
331 default : {
332 mpp_log_f("invalid syntax type %d\n", desc->type);
333 } break;
334 }
335
336 updated |= SYN_TYPE_FLAG(desc->type);
337 }
338
339 return updated;
340 }
341
hal_h264e_vepu540c_get_task(void * hal,HalEncTask * task)342 static MPP_RET hal_h264e_vepu540c_get_task(void *hal, HalEncTask *task)
343 {
344 HalH264eVepu540cCtx *ctx = (HalH264eVepu540cCtx *)hal;
345 RK_U32 updated = update_vepu540c_syntax(ctx, &task->syntax);
346 EncFrmStatus *frm_status = &task->rc_task->frm;
347 hal_h264e_dbg_func("enter %p\n", hal);
348
349 if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG))
350 setup_hal_bufs(ctx);
351
352
353 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
354 MppMeta meta = mpp_frame_get_meta(task->frame);
355
356 mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
357 }
358 hal_h264e_dbg_func("leave %p\n", hal);
359
360 return MPP_OK;
361 }
362
setup_vepu540c_normal(HalVepu540cRegSet * regs)363 static void setup_vepu540c_normal(HalVepu540cRegSet *regs)
364 {
365 hal_h264e_dbg_func("enter\n");
366 /* reg000 VERSION is read only */
367
368 /* reg001 ENC_STRT */
369 regs->reg_ctl.enc_strt.lkt_num = 0;
370 regs->reg_ctl.enc_strt.vepu_cmd = 1;
371
372 regs->reg_ctl.func_en.cke = 1;
373 regs->reg_ctl.func_en.resetn_hw_en = 1;
374 regs->reg_ctl.func_en.enc_done_tmvp_en = 1;
375
376 /* reg002 ENC_CLR */
377 regs->reg_ctl.enc_clr.safe_clr = 0;
378 regs->reg_ctl.enc_clr.force_clr = 0;
379
380 /* reg003 LKT_ADDR */
381 // regs->reg_ctl.lkt_addr = 0;
382
383 /* reg004 INT_EN */
384 regs->reg_ctl.int_en.enc_done_en = 1;
385 regs->reg_ctl.int_en.lkt_node_done_en = 1;
386 regs->reg_ctl.int_en.sclr_done_en = 1;
387 regs->reg_ctl.int_en.vslc_done_en = 1;
388 regs->reg_ctl.int_en.vbsf_oflw_en = 1;
389 regs->reg_ctl.int_en.vbuf_lens_en = 1;
390 regs->reg_ctl.int_en.enc_err_en = 1;
391 regs->reg_ctl.int_en.dvbm_fcfg_en = 1;
392 regs->reg_ctl.int_en.wdg_en = 1;
393 regs->reg_ctl.int_en.lkt_err_int_en = 1;
394 regs->reg_ctl.int_en.lkt_err_stop_en = 1;
395 regs->reg_ctl.int_en.lkt_force_stop_en = 1;
396 regs->reg_ctl.int_en.jslc_done_en = 1;
397 regs->reg_ctl.int_en.jbsf_oflw_en = 1;
398 regs->reg_ctl.int_en.jbuf_lens_en = 1;
399 regs->reg_ctl.int_en.dvbm_dcnt_en = 1;
400
401 /* reg005 INT_MSK */
402 regs->reg_ctl.int_msk.enc_done_msk = 0;
403 regs->reg_ctl.int_msk.lkt_node_done_msk = 0;
404 regs->reg_ctl.int_msk.sclr_done_msk = 0;
405 regs->reg_ctl.int_msk.vslc_done_msk = 0;
406 regs->reg_ctl.int_msk.vbsf_oflw_msk = 0;
407 regs->reg_ctl.int_msk.vbuf_lens_msk = 0;
408 regs->reg_ctl.int_msk.enc_err_msk = 0;
409 regs->reg_ctl.int_msk.dvbm_fcfg_msk = 0;
410 regs->reg_ctl.int_msk.wdg_msk = 0;
411 regs->reg_ctl.int_msk.lkt_err_int_msk = 0;
412 regs->reg_ctl.int_msk.lkt_err_stop_msk = 0;
413 regs->reg_ctl.int_msk.lkt_force_stop_msk = 0;
414 regs->reg_ctl.int_msk.jslc_done_msk = 0;
415 regs->reg_ctl.int_msk.jbsf_oflw_msk = 0;
416 regs->reg_ctl.int_msk.jbuf_lens_msk = 0;
417 regs->reg_ctl.int_msk.dvbm_dcnt_msk = 0;
418
419 /* reg006 INT_CLR is not set */
420 /* reg007 INT_STA is read only */
421 /* reg008 ~ reg0011 gap */
422 regs->reg_ctl.enc_wdg.vs_load_thd = 0x5ffff;
423 regs->reg_ctl.enc_wdg.rfp_load_thd = 0;//xff;
424
425 /* reg015 DTRNS_MAP */
426 regs->reg_ctl.dtrns_map.jpeg_bus_edin = 0;
427 regs->reg_ctl.dtrns_map.src_bus_edin = 0;
428 regs->reg_ctl.dtrns_map.meiw_bus_edin = 0;
429 regs->reg_ctl.dtrns_map.bsw_bus_edin = 7;
430 regs->reg_ctl.dtrns_map.lktr_bus_edin = 0;
431 regs->reg_ctl.dtrns_map.roir_bus_edin = 0;
432 regs->reg_ctl.dtrns_map.lktw_bus_edin = 0;
433 regs->reg_ctl.dtrns_map.rec_nfbc_bus_edin = 0;
434
435 regs->reg_ctl.dtrns_cfg.axi_brsp_cke = 0;
436 hal_h264e_dbg_func("leave\n");
437 }
438
setup_vepu540c_prep(HalVepu540cRegSet * regs,MppEncPrepCfg * prep)439 static MPP_RET setup_vepu540c_prep(HalVepu540cRegSet *regs, MppEncPrepCfg *prep)
440 {
441 VepuFmtCfg cfg;
442 MppFrameFormat fmt = prep->format;
443 MPP_RET ret = vepu541_set_fmt(&cfg, fmt);
444 RK_U32 hw_fmt = cfg.format;
445 RK_S32 y_stride;
446 RK_S32 c_stride;
447
448 hal_h264e_dbg_func("enter\n");
449
450 /* do nothing when color format is not supported */
451 if (ret)
452 return ret;
453
454 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1;
455 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width;
456 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1;
457 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height;
458
459 regs->reg_ctl.dtrns_map.src_bus_edin = cfg.src_endian;
460
461 regs->reg_base.src_fmt.src_cfmt = hw_fmt;
462 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap;
463 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap;
464 // regs->reg_base.src_fmt.src_range = cfg.src_range;
465 regs->reg_base.src_fmt.out_fmt = 1;
466
467 y_stride = (MPP_FRAME_FMT_IS_FBC(fmt)) ? (MPP_ALIGN(prep->width, 16)) :
468 (prep->hor_stride) ? (prep->hor_stride) : (prep->width);
469
470 c_stride = (hw_fmt == VEPU541_FMT_YUV422SP || hw_fmt == VEPU541_FMT_YUV420SP) ?
471 y_stride : y_stride / 2;
472
473 if (hw_fmt < VEPU541_FMT_NONE) {
474 regs->reg_base.src_udfy.csc_wgt_b2y = 25;
475 regs->reg_base.src_udfy.csc_wgt_g2y = 129;
476 regs->reg_base.src_udfy.csc_wgt_r2y = 66;
477
478 regs->reg_base.src_udfu.csc_wgt_b2u = 112;
479 regs->reg_base.src_udfu.csc_wgt_g2u = -74;
480 regs->reg_base.src_udfu.csc_wgt_r2u = -38;
481
482 regs->reg_base.src_udfv.csc_wgt_b2v = -18;
483 regs->reg_base.src_udfv.csc_wgt_g2v = -94;
484 regs->reg_base.src_udfv.csc_wgt_r2v = 112;
485
486 regs->reg_base.src_udfo.csc_ofst_y = 15;
487 regs->reg_base.src_udfo.csc_ofst_u = 128;
488 regs->reg_base.src_udfo.csc_ofst_v = 128;
489 } else {
490 regs->reg_base.src_udfy.csc_wgt_b2y = cfg.weight[0];
491 regs->reg_base.src_udfy.csc_wgt_g2y = cfg.weight[1];
492 regs->reg_base.src_udfy.csc_wgt_r2y = cfg.weight[2];
493
494
495 regs->reg_base.src_udfu.csc_wgt_b2u = cfg.weight[3];
496 regs->reg_base.src_udfu.csc_wgt_g2u = cfg.weight[4];
497 regs->reg_base.src_udfu.csc_wgt_r2u = cfg.weight[5];
498
499
500 regs->reg_base.src_udfv.csc_wgt_b2v = cfg.weight[6];
501 regs->reg_base.src_udfv.csc_wgt_g2v = cfg.weight[7];
502 regs->reg_base.src_udfv.csc_wgt_r2v = cfg.weight[8];
503
504
505 regs->reg_base.src_udfo.csc_ofst_y = cfg.offset[0];
506 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1];
507 regs->reg_base.src_udfo.csc_ofst_v = cfg.offset[2];
508 }
509
510 regs->reg_base.src_strd0.src_strd0 = y_stride;
511 regs->reg_base.src_strd1.src_strd1 = c_stride;
512
513 regs->reg_base.src_proc.src_mirr = prep->mirroring > 0;
514 regs->reg_base.src_proc.src_rot = prep->rotation;
515 // regs->reg_base.src_proc.txa_en = 0;
516
517 regs->reg_base.sli_cfg.mv_v_lmt_thd = 0;
518 regs->reg_base.sli_cfg.mv_v_lmt_en = 0;
519
520 regs->reg_base.pic_ofst.pic_ofst_y = 0;
521 regs->reg_base.pic_ofst.pic_ofst_x = 0;
522
523 hal_h264e_dbg_func("leave\n");
524
525 return ret;
526 }
527
setup_vepu540c_codec(HalVepu540cRegSet * regs,H264eSps * sps,H264ePps * pps,H264eSlice * slice)528 static void setup_vepu540c_codec(HalVepu540cRegSet *regs, H264eSps *sps,
529 H264ePps *pps, H264eSlice *slice)
530 {
531 hal_h264e_dbg_func("enter\n");
532
533 regs->reg_base.enc_pic.enc_stnd = 0;
534 regs->reg_base.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0;
535 regs->reg_base.enc_pic.bs_scp = 1;
536 //regs->reg013.lamb_mod_sel = (slice->slice_type == H264_I_SLICE) ? 0 : 1;
537 //regs->reg013.atr_thd_sel = 0;
538 // regs->reg_ctl.lkt_node_cfg.node_int = 0;
539
540 regs->reg_base.synt_nal.nal_ref_idc = slice->nal_reference_idc;
541 regs->reg_base.synt_nal.nal_unit_type = slice->nalu_type;
542
543 regs->reg_base.synt_sps.max_fnum = sps->log2_max_frame_num_minus4;
544 regs->reg_base.synt_sps.drct_8x8 = sps->direct8x8_inference;
545 regs->reg_base.synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4;
546
547 regs->reg_base.synt_pps.etpy_mode = pps->entropy_coding_mode;
548 regs->reg_base.synt_pps.trns_8x8 = pps->transform_8x8_mode;
549 regs->reg_base.synt_pps.csip_flag = pps->constrained_intra_pred;
550 regs->reg_base.synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1;
551 regs->reg_base.synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1;
552 regs->reg_base.synt_pps.pic_init_qp = pps->pic_init_qp;
553 regs->reg_base.synt_pps.cb_ofst = pps->chroma_qp_index_offset;
554 regs->reg_base.synt_pps.cr_ofst = pps->second_chroma_qp_index_offset;
555 // regs->reg_base.synt_pps.wght_pred = pps->weighted_pred;
556 regs->reg_base.synt_pps.dbf_cp_flg = pps->deblocking_filter_control;
557
558 regs->reg_base.synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0);
559 regs->reg_base.synt_sli0.pps_id = slice->pic_parameter_set_id;
560 regs->reg_base.synt_sli0.drct_smvp = 0;
561 regs->reg_base.synt_sli0.num_ref_ovrd = slice->num_ref_idx_override;
562 regs->reg_base.synt_sli0.cbc_init_idc = slice->cabac_init_idc;
563 regs->reg_base.synt_sli0.frm_num = slice->frame_num;
564
565 regs->reg_base.synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_U32)(-1);
566 regs->reg_base.synt_sli1.poc_lsb = slice->pic_order_cnt_lsb;
567
568
569 regs->reg_base.synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc;
570 regs->reg_base.synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2;
571
572 h264e_reorder_rd_rewind(slice->reorder);
573 { /* reorder process */
574 H264eRplmo rplmo;
575 MPP_RET ret = h264e_reorder_rd_op(slice->reorder, &rplmo);
576
577 if (MPP_OK == ret) {
578 regs->reg_base.synt_sli2.ref_list0_rodr = 1;
579 regs->reg_base.synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc;
580
581 switch (rplmo.modification_of_pic_nums_idc) {
582 case 0 :
583 case 1 : {
584 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1;
585 } break;
586 case 2 : {
587 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx;
588 } break;
589 default : {
590 mpp_err_f("invalid modification_of_pic_nums_idc %d\n",
591 rplmo.modification_of_pic_nums_idc);
592 } break;
593 }
594 } else {
595 // slice->ref_pic_list_modification_flag;
596 regs->reg_base.synt_sli2.ref_list0_rodr = 0;
597 regs->reg_base.synt_sli2.rodr_pic_idx = 0;
598 regs->reg_base.synt_sli2.rodr_pic_num = 0;
599 }
600 }
601
602 /* clear all mmco arg first */
603 regs->reg_base.synt_refm0.nopp_flg = 0;
604 regs->reg_base.synt_refm0.ltrf_flg = 0;
605 regs->reg_base.synt_refm0.arpm_flg = 0;
606 regs->reg_base.synt_refm0.mmco4_pre = 0;
607 regs->reg_base.synt_refm0.mmco_type0 = 0;
608 regs->reg_base.synt_refm0.mmco_parm0 = 0;
609 regs->reg_base.synt_refm0.mmco_type1 = 0;
610 regs->reg_base.synt_refm1.mmco_parm1 = 0;
611 regs->reg_base.synt_refm0.mmco_type2 = 0;
612 regs->reg_base.synt_refm1.mmco_parm2 = 0;
613 regs->reg_base.synt_refm2.long_term_frame_idx0 = 0;
614 regs->reg_base.synt_refm2.long_term_frame_idx1 = 0;
615 regs->reg_base.synt_refm2.long_term_frame_idx2 = 0;
616
617 h264e_marking_rd_rewind(slice->marking);
618
619 /* only update used parameter */
620 if (slice->slice_type == H264_I_SLICE) {
621 regs->reg_base.synt_refm0.nopp_flg = slice->no_output_of_prior_pics;
622 regs->reg_base.synt_refm0.ltrf_flg = slice->long_term_reference_flag;
623 } else {
624 if (!h264e_marking_is_empty(slice->marking)) {
625 H264eMmco mmco;
626
627 regs->reg_base.synt_refm0.arpm_flg = 1;
628
629 /* max 3 mmco */
630 do {
631 RK_S32 type = 0;
632 RK_S32 param_0 = 0;
633 RK_S32 param_1 = 0;
634
635 h264e_marking_rd_op(slice->marking, &mmco);
636 type = mmco.mmco;
637 switch (type) {
638 case 1 : {
639 param_0 = mmco.difference_of_pic_nums_minus1;
640 } break;
641 case 2 : {
642 param_0 = mmco.long_term_pic_num;
643 } break;
644 case 3 : {
645 param_0 = mmco.difference_of_pic_nums_minus1;
646 param_1 = mmco.long_term_frame_idx;
647 } break;
648 case 4 : {
649 param_0 = mmco.max_long_term_frame_idx_plus1;
650 } break;
651 case 5 : {
652 } break;
653 case 6 : {
654 param_0 = mmco.long_term_frame_idx;
655 } break;
656 default : {
657 mpp_err_f("unsupported mmco 0 %d\n", type);
658 type = 0;
659 } break;
660 }
661
662 regs->reg_base.synt_refm0.mmco_type0 = type;
663 regs->reg_base.synt_refm0.mmco_parm0 = param_0;
664 regs->reg_base.synt_refm2.long_term_frame_idx0 = param_1;
665
666 if (h264e_marking_is_empty(slice->marking))
667 break;
668
669 h264e_marking_rd_op(slice->marking, &mmco);
670 type = mmco.mmco;
671 param_0 = 0;
672 param_1 = 0;
673 switch (type) {
674 case 1 : {
675 param_0 = mmco.difference_of_pic_nums_minus1;
676 } break;
677 case 2 : {
678 param_0 = mmco.long_term_pic_num;
679 } break;
680 case 3 : {
681 param_0 = mmco.difference_of_pic_nums_minus1;
682 param_1 = mmco.long_term_frame_idx;
683 } break;
684 case 4 : {
685 param_0 = mmco.max_long_term_frame_idx_plus1;
686 } break;
687 case 5 : {
688 } break;
689 case 6 : {
690 param_0 = mmco.long_term_frame_idx;
691 } break;
692 default : {
693 mpp_err_f("unsupported mmco 0 %d\n", type);
694 type = 0;
695 } break;
696 }
697
698 regs->reg_base.synt_refm0.mmco_type1 = type;
699 regs->reg_base.synt_refm1.mmco_parm1 = param_0;
700 regs->reg_base.synt_refm2.long_term_frame_idx1 = param_1;
701
702 if (h264e_marking_is_empty(slice->marking))
703 break;
704
705 h264e_marking_rd_op(slice->marking, &mmco);
706 type = mmco.mmco;
707 param_0 = 0;
708 param_1 = 0;
709 switch (type) {
710 case 1 : {
711 param_0 = mmco.difference_of_pic_nums_minus1;
712 } break;
713 case 2 : {
714 param_0 = mmco.long_term_pic_num;
715 } break;
716 case 3 : {
717 param_0 = mmco.difference_of_pic_nums_minus1;
718 param_1 = mmco.long_term_frame_idx;
719 } break;
720 case 4 : {
721 param_0 = mmco.max_long_term_frame_idx_plus1;
722 } break;
723 case 5 : {
724 } break;
725 case 6 : {
726 param_0 = mmco.long_term_frame_idx;
727 } break;
728 default : {
729 mpp_err_f("unsupported mmco 0 %d\n", type);
730 type = 0;
731 } break;
732 }
733
734 regs->reg_base.synt_refm0.mmco_type2 = type;
735 regs->reg_base.synt_refm1.mmco_parm2 = param_0;
736 regs->reg_base.synt_refm2.long_term_frame_idx2 = param_1;
737 } while (0);
738 }
739 }
740
741 hal_h264e_dbg_func("leave\n");
742 }
743
setup_vepu540c_rdo_pred(HalVepu540cRegSet * regs,H264eSps * sps,H264ePps * pps,H264eSlice * slice)744 static void setup_vepu540c_rdo_pred(HalVepu540cRegSet *regs, H264eSps *sps,
745 H264ePps *pps, H264eSlice *slice)
746 {
747 hal_h264e_dbg_func("enter\n");
748
749 if (slice->slice_type == H264_I_SLICE) {
750 regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = 0;
751 } else {
752 regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = 3;
753 }
754
755 regs->reg_base.rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE &&
756 sps->level_idc <= H264_LEVEL_3_0) ? 1 : 0;
757 regs->reg_base.rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) &&
758 !pps->entropy_coding_mode;
759 regs->reg_base.rdo_cfg.chrm_spcl = 1;
760 regs->reg_base.rdo_cfg.ccwa_e = 1;
761 regs->reg_base.rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present;
762 regs->reg_base.rdo_cfg.atf_e = 0;
763 regs->reg_base.rdo_cfg.atr_e = 0;
764
765 regs->reg_base.iprd_csts.rdo_mark_mode = 0x100;
766
767 hal_h264e_dbg_func("leave\n");
768 }
769
setup_vepu540c_rdo_cfg(vepu540c_rdo_cfg * reg)770 static void setup_vepu540c_rdo_cfg(vepu540c_rdo_cfg *reg)
771 {
772 hal_h264e_dbg_func("enter\n");
773 rdo_skip_par *p_rdo_skip = NULL;
774 rdo_noskip_par *p_rdo_noskip = NULL;
775
776 reg->rdo_smear_cfg_comb.rdo_smear_en = 0;
777 reg->rdo_smear_cfg_comb.rdo_smear_lvl16_multi = 12;
778 reg->rdo_smear_cfg_comb.rdo_smear_dlt_qp = 0 ;
779 reg->rdo_smear_cfg_comb.rdo_smear_order_state = 0;
780 reg->rdo_smear_cfg_comb.stated_mode = 0;
781 reg->rdo_smear_cfg_comb.online_en = 0;
782 reg->rdo_smear_cfg_comb.smear_stride = 0;
783 reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd0 = 0 ;
784 reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd1 = 24;
785 reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd2 = 48;
786 reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd3 = 64;
787 reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd0 = 16;
788 reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd1 = 32;
789 reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd2 = 48;
790 reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd3 = 96;
791 reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd4 = 48;
792 reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd5 = 24;
793 reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd0 = 96;
794 reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd1 = 48;
795 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd0 = 1 ;
796 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd1 = 4 ;
797 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd2 = 1 ;
798 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd3 = 4 ;
799 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd0 = 1 ;
800 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd1 = 4 ;
801 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd2 = 1 ;
802 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd3 = 4 ;
803 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd4 = 1 ;
804 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd5 = 4 ;
805 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd6 = 1 ;
806 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd7 = 4 ;
807 reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd0 = 1 ;
808 reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd1 = 4 ;
809 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th0 = 6;
810 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th0 = 8;
811 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th1 = 6;
812 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th1 = 11;
813 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th0 = 6;
814 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th0 = 8;
815 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th1 = 6;
816 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th1 = 11;
817 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th2 = 9;
818 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th2 = 20;
819 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th3 = 9;
820 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th3 = 20;
821 reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_small_ref_th0 = 9;
822 reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_big_ref_th0 = 20;
823 reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th0 = 12;
824 reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th1 = 12;
825 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th0 = 1;
826 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th1 = 2;
827 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th2 = 1;
828 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th3 = 2;
829 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th4 = 1;
830 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th5 = 2;
831
832 p_rdo_skip = ®->rdo_b16_skip;
833 p_rdo_skip->atf_thd0.madp_thd0 = 5 ;
834 p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
835 p_rdo_skip->atf_thd1.madp_thd2 = 15 ;
836 p_rdo_skip->atf_thd1.madp_thd3 = 25 ;
837 p_rdo_skip->atf_wgt0.wgt0 = 20 ;
838 p_rdo_skip->atf_wgt0.wgt1 = 14 ;
839 p_rdo_skip->atf_wgt0.wgt2 = 15 ;
840 p_rdo_skip->atf_wgt0.wgt3 = 16 ;
841 p_rdo_skip->atf_wgt1.wgt4 = 16 ;
842
843 p_rdo_noskip = ®->rdo_b16_inter;
844 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
845 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
846 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
847 p_rdo_noskip->atf_wgt.wgt0 = 16;
848 p_rdo_noskip->atf_wgt.wgt1 = 16;
849 p_rdo_noskip->atf_wgt.wgt2 = 16;
850 p_rdo_noskip->atf_wgt.wgt3 = 16;
851
852 p_rdo_noskip = ®->rdo_b16_intra;
853 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
854 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
855 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
856 p_rdo_noskip->atf_wgt.wgt0 = 27;
857 p_rdo_noskip->atf_wgt.wgt1 = 25;
858 p_rdo_noskip->atf_wgt.wgt2 = 20;
859 p_rdo_noskip->atf_wgt.wgt3 = 16;
860
861 reg->rdo_b16_intra_atf_cnt_thd_comb.thd0 = 8 ;
862 reg->rdo_b16_intra_atf_cnt_thd_comb.thd1 = 9 ;
863 reg->rdo_b16_intra_atf_cnt_thd_comb.thd2 = 10 ;
864 reg->rdo_b16_intra_atf_cnt_thd_comb.thd3 = 11 ;
865 reg->rdo_atf_resi_thd_comb.big_th0 = 10;
866 reg->rdo_atf_resi_thd_comb.big_th1 = 12;
867 reg->rdo_atf_resi_thd_comb.small_th0 = 11;
868 reg->rdo_atf_resi_thd_comb.small_th1 = 13;
869
870 hal_h264e_dbg_func("leave\n");
871 }
872
setup_vepu540c_scl_cfg(vepu540c_scl_cfg * regs)873 static void setup_vepu540c_scl_cfg(vepu540c_scl_cfg *regs)
874 {
875 static RK_U32 vepu540c_h264_scl_tab[] = {
876 /* 0x2200 */
877 0x2fbe3333, 0x2fbe4189, 0x2fbe3333, 0x2fbe4189, 0x2ca42fbe, 0x2ca43c79, 0x2ca42fbe, 0x2ca43c79,
878 0x3c794189, 0x3c7951ec, 0x3c794189, 0x3c7951ec, 0x2ca42fbe, 0x2ca43c79, 0x2ca42fbe, 0x2ca43c79,
879 0x2fbe3333, 0x2fbe4189, 0x2fbe3333, 0x2fbe4189, 0x2ca42fbe, 0x2ca43c79, 0x2ca42fbe, 0x2ca43c79,
880 0x3c794189, 0x3c7951ec, 0x3c794189, 0x3c7951ec, 0x2ca42fbe, 0x2ca43c79, 0x2ca42fbe, 0x2ca43c79,
881 0x2b322e8c, 0x2b323a84, 0x2b322e8c, 0x2b323a84, 0x2a4a2b32, 0x2a4a37d2, 0x2a4a2b32, 0x2a4a37d2,
882 0x37d23a84, 0x37d24ae6, 0x37d23a84, 0x37d24ae6, 0x2a4a2b32, 0x2a4a37d2, 0x2a4a2b32, 0x2a4a37d2,
883 0x2b322e8c, 0x2b323a84, 0x2b322e8c, 0x2b323a84, 0x2a4a2b32, 0x2a4a37d2, 0x2a4a2b32, 0x2a4a37d2,
884 0x37d23a84, 0x37d24ae6, 0x37d23a84, 0x37d24ae6, 0x2a4a2b32, 0x2a4a37d2, 0x2a4a2b32, 0x2a4a37d2,
885 0x25cb2762, 0x25cb31a6, 0x25cb2762, 0x25cb31a6, 0x22ef25cb, 0x22ef2ed1, 0x22ef25cb, 0x22ef2ed1,
886 0x2ed131a6, 0x2ed13e6a, 0x2ed131a6, 0x2ed13e6a, 0x22ef25cb, 0x22ef2ed1, 0x22ef25cb, 0x22ef2ed1,
887 0x25cb2762, 0x25cb31a6, 0x25cb2762, 0x25cb31a6, 0x22ef25cb, 0x22ef2ed1, 0x22ef25cb, 0x22ef2ed1,
888 0x2ed131a6, 0x2ed13e6a, 0x2ed131a6, 0x2ed13e6a, 0x22ef25cb, 0x22ef2ed1, 0x22ef25cb, 0x22ef2ed1,
889 0x22e32492, 0x22e32ed0, 0x22e32492, 0x22e32ed0, 0x202422e3, 0x20242bfb, 0x202422e3, 0x20242bfb,
890 0x2bfb2ed0, 0x2bfb3a41, 0x2bfb2ed0, 0x2bfb3a41, 0x202422e3, 0x20242bfb, 0x202422e3, 0x20242bfb,
891 0x22e32492, 0x22e32ed0, 0x22e32492, 0x22e32ed0, 0x202422e3, 0x20242bfb, 0x202422e3, 0x20242bfb,
892 0x2bfb2ed0, 0x2bfb3a41, 0x2bfb2ed0, 0x2bfb3a41, 0x202422e3, 0x20242bfb, 0x202422e3, 0x20242bfb,
893 0x1e3c2000, 0x1e3c28f6, 0x1e3c2000, 0x1e3c28f6, 0x1cb21e3c, 0x1cb22631, 0x1cb21e3c, 0x1cb22631,
894 0x263128f6, 0x26313367, 0x263128f6, 0x26313367, 0x1cb21e3c, 0x1cb22631, 0x1cb21e3c, 0x1cb22631,
895 0x1e3c2000, 0x1e3c28f6, 0x1e3c2000, 0x1e3c28f6, 0x1cb21e3c, 0x1cb22631, 0x1cb21e3c, 0x1cb22631,
896 0x263128f6, 0x26313367, 0x263128f6, 0x26313367, 0x1cb21e3c, 0x1cb22631, 0x1cb21e3c, 0x1cb22631,
897 0x1aae1c72, 0x1aae239e, 0x1aae1c72, 0x1aae239e, 0x191c1aae, 0x191c21c0, 0x191c1aae, 0x191c21c0,
898 0x21c0239e, 0x21c02d32, 0x21c0239e, 0x21c02d32, 0x191c1aae, 0x191c21c0, 0x191c1aae, 0x191c21c0,
899 0x1aae1c72, 0x1aae239e, 0x1aae1c72, 0x1aae239e, 0x191c1aae, 0x191c21c0, 0x191c1aae, 0x191c21c0,
900 0x21c0239e, 0x21c02d32, 0x21c0239e, 0x21c02d32, 0x191c1aae, 0x191c21c0, 0x191c1aae, 0x191c21c0,
901 0x00be0033, 0x00be0089, 0x00be0033, 0x00be0089, 0x00a400be, 0x00a40079, 0x00a400be, 0x00a40079,
902 0x00790089, 0x007900ec, 0x00790089, 0x007900ec, 0x00a400be, 0x00a40079, 0x00a400be, 0x00a40079,
903 0x00be0033, 0x00be0089, 0x00be0033, 0x00be0089, 0x00a400be, 0x00a40079, 0x00a400be, 0x00a40079,
904 0x00790089, 0x007900ec, 0x00790089, 0x007900ec, 0x00a400be, 0x00a40079, 0x00a400be, 0x00a40079,
905 0x0032008c, 0x00320084, 0x0032008c, 0x00320084, 0x004a0032, 0x004a00d2, 0x004a0032, 0x004a00d2,
906 0x00d20084, 0x00d200e6, 0x00d20084, 0x00d200e6, 0x004a0032, 0x004a00d2, 0x004a0032, 0x004a00d2,
907 0x0032008c, 0x00320084, 0x0032008c, 0x00320084, 0x004a0032, 0x004a00d2, 0x004a0032, 0x004a00d2,
908 0x00d20084, 0x00d200e6, 0x00d20084, 0x00d200e6, 0x004a0032, 0x004a00d2, 0x004a0032, 0x004a00d2,
909 0x00cb0062, 0x00cb00a6, 0x00cb0062, 0x00cb00a6, 0x00ef00cb, 0x00ef00d1, 0x00ef00cb, 0x00ef00d1,
910 0x00d100a6, 0x00d1006a, 0x00d100a6, 0x00d1006a, 0x00ef00cb, 0x00ef00d1, 0x00ef00cb, 0x00ef00d1,
911 0x00cb0062, 0x00cb00a6, 0x00cb0062, 0x00cb00a6, 0x00ef00cb, 0x00ef00d1, 0x00ef00cb, 0x00ef00d1,
912 0x00d100a6, 0x00d1006a, 0x00d100a6, 0x00d1006a, 0x00ef00cb, 0x00ef00d1, 0x00ef00cb, 0x00ef00d1,
913 0x00e30092, 0x00e300d0, 0x00e30092, 0x00e300d0, 0x002400e3, 0x002400fb, 0x002400e3, 0x002400fb,
914 0x00fb00d0, 0x00fb0041, 0x00fb00d0, 0x00fb0041, 0x002400e3, 0x002400fb, 0x002400e3, 0x002400fb,
915 0x00e30092, 0x00e300d0, 0x00e30092, 0x00e300d0, 0x002400e3, 0x002400fb, 0x002400e3, 0x002400fb,
916 0x00fb00d0, 0x00fb0041, 0x00fb00d0, 0x00fb0041, 0x002400e3, 0x002400fb, 0x002400e3, 0x002400fb,
917 0x003c0000, 0x003c00f6, 0x003c0000, 0x003c00f6, 0x00b2003c, 0x00b20031, 0x00b2003c, 0x00b20031,
918 0x003100f6, 0x00310067, 0x003100f6, 0x00310067, 0x00b2003c, 0x00b20031, 0x00b2003c, 0x00b20031,
919 0x003c0000, 0x003c00f6, 0x003c0000, 0x003c00f6, 0x00b2003c, 0x00b20031, 0x00b2003c, 0x00b20031,
920 0x003100f6, 0x00310067, 0x003100f6, 0x00310067, 0x00b2003c, 0x00b20031, 0x00b2003c, 0x00b20031,
921 0x00ae0072, 0x00ae009e, 0x00ae0072, 0x00ae009e, 0x001c00ae, 0x001c00c0, 0x001c00ae, 0x001c00c0,
922 0x00c0009e, 0x00c00032, 0x00c0009e, 0x00c00032, 0x001c00ae, 0x001c00c0, 0x001c00ae, 0x001c00c0,
923 0x00ae0072, 0x00ae009e, 0x00ae0072, 0x00ae009e, 0x001c00ae, 0x001c00c0, 0x001c00ae, 0x001c00c0,
924 0x00c0009e, 0x00c00032, 0x00c0009e, 0x00c00032, 0x001c00ae, 0x001c00c0, 0x001c00ae, 0x001c00c0,
925 0x002f0033, 0x002f0041, 0x002f0033, 0x002f0041, 0x002c002f, 0x002c003c, 0x002c002f, 0x002c003c,
926 0x003c0041, 0x003c0051, 0x003c0041, 0x003c0051, 0x002c002f, 0x002c003c, 0x002c002f, 0x002c003c,
927 0x002f0033, 0x002f0041, 0x002f0033, 0x002f0041, 0x002c002f, 0x002c003c, 0x002c002f, 0x002c003c,
928 0x003c0041, 0x003c0051, 0x003c0041, 0x003c0051, 0x002c002f, 0x002c003c, 0x002c002f, 0x002c003c,
929 0x002b002e, 0x002b003a, 0x002b002e, 0x002b003a, 0x002a002b, 0x002a0037, 0x002a002b, 0x002a0037,
930 0x0037003a, 0x0037004a, 0x0037003a, 0x0037004a, 0x002a002b, 0x002a0037, 0x002a002b, 0x002a0037,
931 0x002b002e, 0x002b003a, 0x002b002e, 0x002b003a, 0x002a002b, 0x002a0037, 0x002a002b, 0x002a0037,
932 0x0037003a, 0x0037004a, 0x0037003a, 0x0037004a, 0x002a002b, 0x002a0037, 0x002a002b, 0x002a0037,
933 0x01250127, 0x01250131, 0x01250127, 0x01250131, 0x01220125, 0x0122012e, 0x01220125, 0x0122012e,
934 0x012e0131, 0x012e013e, 0x012e0131, 0x012e013e, 0x01220125, 0x0122012e, 0x01220125, 0x0122012e,
935 0x01250127, 0x01250131, 0x01250127, 0x01250131, 0x01220125, 0x0122012e, 0x01220125, 0x0122012e,
936 0x012e0131, 0x012e013e, 0x012e0131, 0x012e013e, 0x01220125, 0x0122012e, 0x01220125, 0x0122012e,
937 0x01220124, 0x0122012e, 0x01220124, 0x0122012e, 0x01200122, 0x0120012b, 0x01200122, 0x0120012b,
938 0x012b012e, 0x012b013a, 0x012b012e, 0x012b013a, 0x01200122, 0x0120012b, 0x01200122, 0x0120012b,
939 0x01220124, 0x0122012e, 0x01220124, 0x0122012e, 0x01200122, 0x0120012b, 0x01200122, 0x0120012b,
940 0x012b012e, 0x012b013a, 0x012b012e, 0x012b013a, 0x01200122, 0x0120012b, 0x01200122, 0x0120012b,
941 0x001e0020, 0x001e0028, 0x001e0020, 0x001e0028, 0x001c001e, 0x001c0026, 0x001c001e, 0x001c0026,
942 0x00260028, 0x00260033, 0x00260028, 0x00260033, 0x001c001e, 0x001c0026, 0x001c001e, 0x001c0026,
943 0x001e0020, 0x001e0028, 0x001e0020, 0x001e0028, 0x001c001e, 0x001c0026, 0x001c001e, 0x001c0026,
944 0x00260028, 0x00260033, 0x00260028, 0x00260033, 0x001c001e, 0x001c0026, 0x001c001e, 0x001c0026,
945 0x001a001c, 0x001a0023, 0x001a001c, 0x001a0023, 0x0019001a, 0x00190021, 0x0019001a, 0x00190021,
946 0x00210023, 0x0021002d, 0x00210023, 0x0021002d, 0x0019001a, 0x00190021, 0x0019001a, 0x00190021,
947 0x001a001c, 0x001a0023, 0x001a001c, 0x001a0023, 0x0019001a, 0x00190021, 0x0019001a, 0x00190021,
948 0x00210023, 0x0021002d, 0x00210023, 0x0021002d, 0x0019001a, 0x00190021, 0x0019001a, 0x00190021,
949 };
950
951 hal_h264e_dbg_func("enter\n");
952
953 memcpy(®s->q_intra_y8, vepu540c_h264_scl_tab, sizeof(vepu540c_h264_scl_tab));
954
955 hal_h264e_dbg_func("leave\n");
956 }
957
setup_vepu540c_rc_base(HalVepu540cRegSet * regs,H264eSps * sps,H264eSlice * slice,MppEncHwCfg * hw,EncRcTask * rc_task)958 static void setup_vepu540c_rc_base(HalVepu540cRegSet *regs, H264eSps *sps,
959 H264eSlice *slice, MppEncHwCfg *hw,
960 EncRcTask *rc_task)
961 {
962 EncRcTaskInfo *rc_info = &rc_task->info;
963 RK_S32 mb_w = sps->pic_width_in_mbs;
964 RK_S32 mb_h = sps->pic_height_in_mbs;
965 RK_U32 qp_target = rc_info->quality_target;
966 RK_U32 qp_min = rc_info->quality_min;
967 RK_U32 qp_max = rc_info->quality_max;
968 RK_U32 qpmap_mode = 1;
969 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h);
970 RK_S32 mb_target_bits;
971 RK_S32 negative_bits_thd;
972 RK_S32 positive_bits_thd;
973
974 hal_h264e_dbg_rc("bittarget %d qp [%d %d %d]\n", rc_info->bit_target,
975 qp_min, qp_target, qp_max);
976
977 if (mb_target_bits_mul_16 >= 0x100000) {
978 mb_target_bits_mul_16 = 0x50000;
979 }
980
981 mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4;
982 negative_bits_thd = 0 - mb_target_bits / 4;
983 positive_bits_thd = mb_target_bits / 4;
984
985 hal_h264e_dbg_func("enter\n");
986
987 regs->reg_base.enc_pic.pic_qp = qp_target;
988
989 regs->reg_base.rc_cfg.rc_en = 1;
990 regs->reg_base.rc_cfg.aq_en = 1;
991 regs->reg_base.rc_cfg.aq_mode = 0;
992 regs->reg_base.rc_cfg.rc_ctu_num = mb_w;
993
994 regs->reg_base.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ?
995 hw->qp_delta_row_i : hw->qp_delta_row;
996 regs->reg_base.rc_qp.rc_max_qp = qp_max;
997 regs->reg_base.rc_qp.rc_min_qp = qp_min;
998
999 regs->reg_base.rc_tgt.ctu_ebit = mb_target_bits_mul_16;
1000
1001 regs->reg_rc_roi.rc_adj0.qp_adj0 = -1;
1002 regs->reg_rc_roi.rc_adj0.qp_adj1 = 0;
1003 regs->reg_rc_roi.rc_adj0.qp_adj2 = 0;
1004 regs->reg_rc_roi.rc_adj0.qp_adj3 = 0;
1005 regs->reg_rc_roi.rc_adj0.qp_adj4 = 0;
1006 regs->reg_rc_roi.rc_adj1.qp_adj5 = 0;
1007 regs->reg_rc_roi.rc_adj1.qp_adj6 = 0;
1008 regs->reg_rc_roi.rc_adj1.qp_adj7 = 0;
1009 regs->reg_rc_roi.rc_adj1.qp_adj8 = 1;
1010
1011 regs->reg_rc_roi.rc_dthd_0_8[0] = negative_bits_thd;
1012 regs->reg_rc_roi.rc_dthd_0_8[1] = positive_bits_thd;
1013 regs->reg_rc_roi.rc_dthd_0_8[2] = positive_bits_thd;
1014 regs->reg_rc_roi.rc_dthd_0_8[3] = positive_bits_thd;
1015 regs->reg_rc_roi.rc_dthd_0_8[4] = positive_bits_thd;
1016 regs->reg_rc_roi.rc_dthd_0_8[5] = positive_bits_thd;
1017 regs->reg_rc_roi.rc_dthd_0_8[6] = positive_bits_thd;
1018 regs->reg_rc_roi.rc_dthd_0_8[7] = positive_bits_thd;
1019 regs->reg_rc_roi.rc_dthd_0_8[8] = positive_bits_thd;
1020
1021 regs->reg_rc_roi.roi_qthd0.qpmin_area0 = qp_min;
1022 regs->reg_rc_roi.roi_qthd0.qpmax_area0 = qp_max;
1023 regs->reg_rc_roi.roi_qthd0.qpmin_area1 = qp_min;
1024 regs->reg_rc_roi.roi_qthd0.qpmax_area1 = qp_max;
1025 regs->reg_rc_roi.roi_qthd0.qpmin_area2 = qp_min;
1026
1027 regs->reg_rc_roi.roi_qthd1.qpmax_area2 = qp_max;
1028 regs->reg_rc_roi.roi_qthd1.qpmin_area3 = qp_min;
1029 regs->reg_rc_roi.roi_qthd1.qpmax_area3 = qp_max;
1030 regs->reg_rc_roi.roi_qthd1.qpmin_area4 = qp_min;
1031 regs->reg_rc_roi.roi_qthd1.qpmax_area4 = qp_max;
1032
1033 regs->reg_rc_roi.roi_qthd2.qpmin_area5 = qp_min;
1034 regs->reg_rc_roi.roi_qthd2.qpmax_area5 = qp_max;
1035 regs->reg_rc_roi.roi_qthd2.qpmin_area6 = qp_min;
1036 regs->reg_rc_roi.roi_qthd2.qpmax_area6 = qp_max;
1037 regs->reg_rc_roi.roi_qthd2.qpmin_area7 = qp_min;
1038
1039 regs->reg_rc_roi.roi_qthd3.qpmax_area7 = qp_max;
1040 regs->reg_rc_roi.roi_qthd3.qpmap_mode = qpmap_mode;
1041
1042 hal_h264e_dbg_func("leave\n");
1043 }
1044
setup_vepu540c_io_buf(HalVepu540cRegSet * regs,MppDev dev,HalEncTask * task)1045 static void setup_vepu540c_io_buf(HalVepu540cRegSet *regs, MppDev dev,
1046 HalEncTask *task)
1047 {
1048 MppFrame frm = task->frame;
1049 MppPacket pkt = task->packet;
1050 MppBuffer buf_in = mpp_frame_get_buffer(frm);
1051 MppBuffer buf_out = task->output;
1052 MppFrameFormat fmt = mpp_frame_get_fmt(frm);
1053 RK_S32 hor_stride = mpp_frame_get_hor_stride(frm);
1054 RK_S32 ver_stride = mpp_frame_get_ver_stride(frm);
1055 RK_S32 fd_in = mpp_buffer_get_fd(buf_in);
1056 RK_U32 off_in[2] = {0};
1057 RK_U32 off_out = mpp_packet_get_length(pkt);
1058 size_t siz_out = mpp_buffer_get_size(buf_out);
1059 RK_S32 fd_out = mpp_buffer_get_fd(buf_out);
1060
1061 hal_h264e_dbg_func("enter\n");
1062
1063 regs->reg_base.adr_src0 = fd_in;
1064 regs->reg_base.adr_src1 = fd_in;
1065 regs->reg_base.adr_src2 = fd_in;
1066
1067 regs->reg_base.bsbt_addr = fd_out;
1068 regs->reg_base.bsbb_addr = fd_out;
1069 regs->reg_base.adr_bsbs = fd_out;
1070 regs->reg_base.bsbr_addr = fd_out;
1071 mpp_dev_set_reg_offset(dev, 172, siz_out);
1072 mpp_dev_set_reg_offset(dev, 174, off_out);
1073
1074 regs->reg_base.rfpt_h_addr = 0xffffffff;
1075 regs->reg_base.rfpb_h_addr = 0;
1076 regs->reg_base.rfpt_b_addr = 0xffffffff;
1077 regs->reg_base.adr_rfpb_b = 0;
1078 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1079 off_in[0] = mpp_frame_get_fbc_offset(frm);;
1080 off_in[1] = 0;
1081 } else if (MPP_FRAME_FMT_IS_YUV(fmt)) {
1082 VepuFmtCfg cfg;
1083
1084 vepu541_set_fmt(&cfg, fmt);
1085 switch (cfg.format) {
1086 case VEPU541_FMT_BGRA8888 :
1087 case VEPU541_FMT_BGR888 :
1088 case VEPU541_FMT_BGR565 : {
1089 off_in[0] = 0;
1090 off_in[1] = 0;
1091 } break;
1092 case VEPU541_FMT_YUV420SP :
1093 case VEPU541_FMT_YUV422SP : {
1094 off_in[0] = hor_stride * ver_stride;
1095 off_in[1] = hor_stride * ver_stride;
1096 } break;
1097 case VEPU541_FMT_YUV422P : {
1098 off_in[0] = hor_stride * ver_stride;
1099 off_in[1] = hor_stride * ver_stride * 3 / 2;
1100 } break;
1101 case VEPU541_FMT_YUV420P : {
1102 off_in[0] = hor_stride * ver_stride;
1103 off_in[1] = hor_stride * ver_stride * 5 / 4;
1104 } break;
1105 case VEPU541_FMT_YUYV422 :
1106 case VEPU541_FMT_UYVY422 : {
1107 off_in[0] = 0;
1108 off_in[1] = 0;
1109 } break;
1110 case VEPU541_FMT_NONE :
1111 default : {
1112 off_in[0] = 0;
1113 off_in[1] = 0;
1114 } break;
1115 }
1116 }
1117
1118 mpp_dev_set_reg_offset(dev, 161, off_in[0]);
1119 mpp_dev_set_reg_offset(dev, 162, off_in[1]);
1120
1121 hal_h264e_dbg_func("leave\n");
1122 }
1123
setup_vepu540c_recn_refr(HalH264eVepu540cCtx * ctx,HalVepu540cRegSet * regs)1124 static void setup_vepu540c_recn_refr(HalH264eVepu540cCtx *ctx, HalVepu540cRegSet *regs)
1125 {
1126
1127 MppDev dev = ctx->dev;
1128 H264eFrmInfo *frms = ctx->frms;
1129 HalBufs bufs = ctx->hw_recn;
1130 RK_S32 fbc_hdr_size = ctx->pixel_buf_fbc_hdr_size;
1131
1132 HalBuf *curr = hal_bufs_get_buf(bufs, frms->curr_idx);
1133 HalBuf *refr = hal_bufs_get_buf(bufs, frms->refr_idx);
1134
1135 hal_h264e_dbg_func("enter\n");
1136
1137 if (curr && curr->cnt) {
1138 MppBuffer buf_pixel = curr->buf[0];
1139 MppBuffer buf_thumb = curr->buf[1];
1140 RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
1141
1142 mpp_assert(buf_pixel);
1143 mpp_assert(buf_thumb);
1144
1145 regs->reg_base.rfpw_h_addr = fd;
1146 regs->reg_base.rfpw_b_addr = fd;
1147 regs->reg_base.dspw_addr = mpp_buffer_get_fd(buf_thumb);
1148 mpp_dev_set_reg_offset(dev, 164, fbc_hdr_size);
1149 }
1150
1151 if (refr && refr->cnt) {
1152 MppBuffer buf_pixel = refr->buf[0];
1153 MppBuffer buf_thumb = refr->buf[1];
1154 RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
1155
1156 mpp_assert(buf_pixel);
1157 mpp_assert(buf_thumb);
1158
1159 regs->reg_base.rfpr_h_addr = fd;
1160 regs->reg_base.rfpr_b_addr = fd;
1161 regs->reg_base.dspr_addr = mpp_buffer_get_fd(buf_thumb);
1162 mpp_dev_set_reg_offset(dev, 166, fbc_hdr_size);
1163 }
1164 hal_h264e_dbg_func("leave\n");
1165 }
1166
setup_vepu540c_split(HalVepu540cRegSet * regs,MppEncSliceSplit * cfg)1167 static void setup_vepu540c_split(HalVepu540cRegSet *regs, MppEncSliceSplit *cfg)
1168 {
1169 hal_h264e_dbg_func("enter\n");
1170
1171 switch (cfg->split_mode) {
1172 case MPP_ENC_SPLIT_NONE : {
1173 regs->reg_base.sli_splt.sli_splt = 0;
1174 regs->reg_base.sli_splt.sli_splt_mode = 0;
1175 regs->reg_base.sli_splt.sli_splt_cpst = 0;
1176 regs->reg_base.sli_splt.sli_max_num_m1 = 0;
1177 regs->reg_base.sli_splt.sli_flsh = 0;
1178 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0;
1179
1180 regs->reg_base.sli_byte.sli_splt_byte = 0;
1181 regs->reg_base.enc_pic.slen_fifo = 0;
1182 } break;
1183 case MPP_ENC_SPLIT_BY_BYTE : {
1184 regs->reg_base.sli_splt.sli_splt = 1;
1185 regs->reg_base.sli_splt.sli_splt_mode = 0;
1186 regs->reg_base.sli_splt.sli_splt_cpst = 0;
1187 regs->reg_base.sli_splt.sli_max_num_m1 = 500;
1188 regs->reg_base.sli_splt.sli_flsh = 1;
1189 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0;
1190
1191 regs->reg_base.sli_byte.sli_splt_byte = cfg->split_arg;
1192 regs->reg_base.enc_pic.slen_fifo = 0;
1193 } break;
1194 case MPP_ENC_SPLIT_BY_CTU : {
1195 regs->reg_base.sli_splt.sli_splt = 1;
1196 regs->reg_base.sli_splt.sli_splt_mode = 1;
1197 regs->reg_base.sli_splt.sli_splt_cpst = 0;
1198 regs->reg_base.sli_splt.sli_max_num_m1 = 500;
1199 regs->reg_base.sli_splt.sli_flsh = 1;
1200 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
1201
1202 regs->reg_base.sli_byte.sli_splt_byte = 0;
1203 regs->reg_base.enc_pic.slen_fifo = 0;
1204 } break;
1205 default : {
1206 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
1207 } break;
1208 }
1209
1210 cfg->change = 0;
1211
1212 hal_h264e_dbg_func("leave\n");
1213 }
1214
calc_cime_parameter(HalVepu540cRegSet * regs)1215 static void calc_cime_parameter(HalVepu540cRegSet *regs)
1216 {
1217 Vepu540cBaseCfg *base_regs = ®s->reg_base;
1218 RK_S32 x_gmv = 0;
1219 RK_S32 y_gmv = 0;
1220 RK_S32 srch_lftw , srch_rgtw, srch_uph, srch_dwnh;
1221 RK_S32 frm_sta = 0, frm_end = 0, pic_w = 0;
1222 RK_S32 pic_wdt_align = ((base_regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 2;
1223
1224
1225 srch_lftw = base_regs->me_rnge.cime_srch_lftw * 4;
1226 srch_rgtw = base_regs->me_rnge.cime_srch_rgtw * 4;
1227 srch_uph = base_regs->me_rnge.cime_srch_uph * 2;
1228 srch_dwnh = base_regs->me_rnge.cime_srch_dwnh * 2;
1229
1230 // calc cime_linebuf_w
1231 {
1232 {
1233 if (x_gmv - srch_lftw < 0) {
1234 frm_sta = 0;
1235 } else {
1236 frm_sta = (x_gmv - srch_lftw) / 16;
1237 }
1238 if (x_gmv + srch_rgtw < 0) {
1239 frm_end = pic_wdt_align - 1 + (x_gmv + srch_rgtw) / 16;
1240 } else {
1241 frm_end = pic_wdt_align - 1 + (x_gmv + srch_rgtw + 15) / 16;
1242 }
1243 }
1244 if (frm_sta < 0) {
1245 frm_sta = 0;
1246 } else if (frm_sta > pic_wdt_align - 1) {
1247 frm_sta = pic_wdt_align - 1;
1248 }
1249 frm_end = mpp_clip(frm_end, 0, pic_wdt_align - 1);
1250 pic_w = (frm_end - frm_sta + 1) * 32;
1251 base_regs->me_cach.cme_linebuf_w = pic_w / 32;
1252 }
1253
1254 // calc cime_rama_h and cime_rama_max
1255 {
1256 RK_U32 rama_size = 1796;
1257 RK_U32 ramb_h;
1258 RK_U32 ctu_2_h = 2;
1259 RK_U32 cur_srch_8_w, cur_srch_2_h, cur_srch_h;
1260
1261
1262 if ((y_gmv % 4 - srch_uph % 4) < 0) {
1263 cur_srch_2_h = (4 + (y_gmv % 4 - srch_uph % 4) % 4 + srch_uph + srch_dwnh) / 2 + ctu_2_h;
1264 } else {
1265 cur_srch_2_h = ((y_gmv % 4 - srch_uph % 4) % 4 + srch_uph + srch_dwnh) / 2 + ctu_2_h;
1266 }
1267 base_regs->me_cach.cime_size_rama = (cur_srch_2_h + 1) / 2 * 2;
1268
1269 if ((x_gmv % 16 - srch_lftw % 16) < 0) {
1270 cur_srch_8_w = ((16 + (x_gmv % 16 - srch_lftw % 16) % 16 + srch_lftw + srch_rgtw + 15) / 16 + 1) * 2;
1271 } else {
1272 cur_srch_8_w = (((x_gmv % 16 - srch_lftw % 16) % 16 + srch_lftw + srch_rgtw + 15) / 16 + 1) * 2;
1273 }
1274
1275 cur_srch_h = ctu_2_h;
1276 ramb_h = cur_srch_2_h;
1277 while ((rama_size > ((cur_srch_h - ctu_2_h) * base_regs->me_cach.cme_linebuf_w + (ramb_h * cur_srch_8_w)))
1278 && (cur_srch_h < base_regs->me_cach.cime_size_rama)) {
1279 cur_srch_h = cur_srch_h + ctu_2_h;
1280 if (ramb_h > ctu_2_h * 2) {
1281 ramb_h = ramb_h - ctu_2_h;
1282 } else {
1283 ramb_h = ctu_2_h;
1284 }
1285 }
1286
1287 if (cur_srch_2_h == ctu_2_h * 2) {
1288 cur_srch_h = cur_srch_h + ctu_2_h;
1289 ramb_h = ctu_2_h;
1290 }
1291 if (rama_size < ((cur_srch_h - ctu_2_h) * base_regs->me_cach.cme_linebuf_w + (ramb_h * cur_srch_8_w))) {
1292 cur_srch_h = cur_srch_h - ctu_2_h;
1293 }
1294 base_regs->me_cach.cime_size_rama = ((cur_srch_h - ctu_2_h) * base_regs->me_cach.cme_linebuf_w + ctu_2_h * cur_srch_8_w) / 2;
1295 base_regs->me_cach.cime_hgt_rama = cur_srch_h / 2;
1296 }
1297
1298 }
1299
setup_vepu540c_me(HalVepu540cRegSet * regs,H264eSps * sps,H264eSlice * slice)1300 static void setup_vepu540c_me(HalVepu540cRegSet *regs, H264eSps *sps,
1301 H264eSlice *slice)
1302 {
1303 (void)sps;
1304 (void)slice;
1305 regs->reg_base.me_rnge.cime_srch_dwnh = 15;
1306 regs->reg_base.me_rnge.cime_srch_uph = 14;
1307 regs->reg_base.me_rnge.cime_srch_rgtw = 12;
1308 regs->reg_base.me_rnge.cime_srch_lftw = 12;
1309 regs->reg_base.me_cfg.rme_srch_h = 3;
1310 regs->reg_base.me_cfg.rme_srch_v = 3;
1311
1312 regs->reg_base.me_cfg.srgn_max_num = 72;
1313 regs->reg_base.me_cfg.cime_dist_thre = 1024;
1314 regs->reg_base.me_cfg.rme_dis = 0;
1315 regs->reg_base.me_cfg.fme_dis = 0;
1316 regs->reg_base.me_rnge.dlt_frm_num = 0x0;
1317 calc_cime_parameter(regs);
1318 hal_h264e_dbg_func("leave\n");
1319 }
1320
1321 #define H264E_LAMBDA_TAB_SIZE (52 * sizeof(RK_U32))
1322
1323 static RK_U32 h264e_lambda_default[58] = {
1324 0x00000003, 0x00000005, 0x00000006, 0x00000007,
1325 0x00000009, 0x0000000b, 0x0000000e, 0x00000012,
1326 0x00000016, 0x0000001c, 0x00000024, 0x0000002d,
1327 0x00000039, 0x00000048, 0x0000005b, 0x00000073,
1328 0x00000091, 0x000000b6, 0x000000e6, 0x00000122,
1329 0x0000016d, 0x000001cc, 0x00000244, 0x000002db,
1330 0x00000399, 0x00000489, 0x000005b6, 0x00000733,
1331 0x00000912, 0x00000b6d, 0x00000e66, 0x00001224,
1332 0x000016db, 0x00001ccc, 0x00002449, 0x00002db7,
1333 0x00003999, 0x00004892, 0x00005b6f, 0x00007333,
1334 0x00009124, 0x0000b6de, 0x0000e666, 0x00012249,
1335 0x00016dbc, 0x0001cccc, 0x00024492, 0x0002db79,
1336 0x00039999, 0x00048924, 0x0005b6f2, 0x00073333,
1337 0x00091249, 0x000b6de5, 0x000e6666, 0x00122492,
1338 0x0016dbcb, 0x001ccccc,
1339 };
1340
setup_vepu540c_l2(HalVepu540cRegSet * regs,H264eSlice * slice,MppEncHwCfg * hw)1341 static void setup_vepu540c_l2(HalVepu540cRegSet *regs, H264eSlice *slice, MppEncHwCfg *hw)
1342 {
1343 RK_U32 i;
1344
1345 hal_h264e_dbg_func("enter\n");
1346
1347 memcpy(regs->reg_s3.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE);
1348
1349 regs->reg_s3.RDO_QUANT.quant_f_bias_I = 683;
1350 regs->reg_s3.RDO_QUANT.quant_f_bias_P = 341;
1351 regs->reg_s3.iprd_tthdy4_0.iprd_tthdy4_0 = 1;
1352 regs->reg_s3.iprd_tthdy4_0.iprd_tthdy4_1 = 4;
1353 regs->reg_s3.iprd_tthdy4_1.iprd_tthdy4_2 = 9;
1354 regs->reg_s3.iprd_tthdy4_1.iprd_tthdy4_3 = 36;
1355 regs->reg_s3.iprd_tthdc8_0.iprd_tthdc8_0 = 1;
1356 regs->reg_s3.iprd_tthdc8_0.iprd_tthdc8_1 = 4;
1357 regs->reg_s3.iprd_tthdc8_1.iprd_tthdc8_2 = 9;
1358 regs->reg_s3.iprd_tthdc8_1.iprd_tthdc8_3 = 36;
1359 regs->reg_s3.iprd_tthdy8_0.iprd_tthdy8_0 = 1;
1360 regs->reg_s3.iprd_tthdy8_0.iprd_tthdy8_1 = 4;
1361 regs->reg_s3.iprd_tthdy8_1.iprd_tthdy8_2 = 9;
1362 regs->reg_s3.iprd_tthdy8_1.iprd_tthdy8_3 = 36;
1363 regs->reg_s3.iprd_tthd_ul.iprd_tthd_ul = 0;
1364 regs->reg_s3.iprd_wgty8.iprd_wgty8_0 = 48;
1365 regs->reg_s3.iprd_wgty8.iprd_wgty8_1 = 60;
1366 regs->reg_s3.iprd_wgty8.iprd_wgty8_2 = 40;
1367 regs->reg_s3.iprd_wgty8.iprd_wgty8_3 = 48;
1368 regs->reg_s3.iprd_wgty4.iprd_wgty4_0 = 48;
1369 regs->reg_s3.iprd_wgty4.iprd_wgty4_1 = 60;
1370 regs->reg_s3.iprd_wgty4.iprd_wgty4_2 = 40;
1371 regs->reg_s3.iprd_wgty4.iprd_wgty4_3 = 48;
1372 regs->reg_s3.iprd_wgty16.iprd_wgty16_0 = 48;
1373 regs->reg_s3.iprd_wgty16.iprd_wgty16_1 = 60;
1374 regs->reg_s3.iprd_wgty16.iprd_wgty16_2 = 40;
1375 regs->reg_s3.iprd_wgty16.iprd_wgty16_3 = 48;
1376 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_0 = 36;
1377 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_1 = 42;
1378 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_2 = 28;
1379 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_3 = 32;
1380
1381 if (slice->slice_type == H264_I_SLICE) {
1382 regs->reg_s3.ATR_THD0.atr_thd0 = 1;
1383 regs->reg_s3.ATR_THD0.atr_thd1 = 4;
1384 regs->reg_s3.ATR_THD1.atr_thd2 = 36;
1385 } else {
1386 regs->reg_s3.ATR_THD0.atr_thd0 = 1;
1387 regs->reg_s3.ATR_THD0.atr_thd1 = 4;
1388 regs->reg_s3.ATR_THD1.atr_thd2 = 49;
1389 }
1390 regs->reg_s3.ATR_THD1.atr_thdqp = 32;
1391
1392 if (slice->slice_type == H264_I_SLICE) {
1393 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 16;
1394 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 16;
1395 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16;
1396
1397 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 32;
1398 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 32;
1399 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 32;
1400
1401 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 20;
1402 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 18;
1403 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16;
1404 } else {
1405 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 16;
1406 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 17;
1407 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 17;
1408
1409 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 31;
1410 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 31;
1411 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 31;
1412
1413 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 21;
1414 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 19;
1415 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 17;
1416 }
1417 /* CIME */
1418 {
1419 /* 0x1760 */
1420 regs->reg_s3.cime_sqi_cfg.cime_pmv_num = 1;
1421 regs->reg_s3.cime_sqi_cfg.cime_fuse = 1;
1422 regs->reg_s3.cime_sqi_cfg.itp_mode = 0;
1423 regs->reg_s3.cime_sqi_cfg.move_lambda = 12;
1424 regs->reg_s3.cime_sqi_cfg.rime_lvl_mrg = 1;
1425 regs->reg_s3.cime_sqi_cfg.rime_prelvl_en = 0;
1426 regs->reg_s3.cime_sqi_cfg.rime_prersu_en = 0;
1427
1428 /* 0x1764 */
1429 regs->reg_s3.cime_mvd_th.cime_mvd_th0 = 500;
1430 regs->reg_s3.cime_mvd_th.cime_mvd_th1 = 511;
1431 regs->reg_s3.cime_mvd_th.cime_mvd_th2 = 0;
1432
1433 /* 0x1768 */
1434 regs->reg_s3.cime_madp_th.cime_madp_th = 160;
1435
1436 /* 0x176c */
1437 regs->reg_s3.cime_multi.cime_multi0 = 192;
1438 regs->reg_s3.cime_multi.cime_multi1 = 255;
1439 regs->reg_s3.cime_multi.cime_multi2 = 0;
1440 regs->reg_s3.cime_multi.cime_multi3 = 15;
1441 }
1442
1443 /* RIME && FME */
1444 {
1445 /* 0x1770 */
1446 regs->reg_s3.rime_mvd_th.rime_mvd_th0 = 0;
1447 regs->reg_s3.rime_mvd_th.rime_mvd_th1 = 1;
1448 regs->reg_s3.rime_mvd_th.fme_madp_th = 0;
1449
1450 /* 0x1774 */
1451 regs->reg_s3.rime_madp_th.rime_madp_th0 = 192;
1452 regs->reg_s3.rime_madp_th.rime_madp_th1 = 123;
1453
1454 /* 0x1778 */
1455 regs->reg_s3.rime_multi.rime_multi0 = 192;
1456 regs->reg_s3.rime_multi.rime_multi1 = 1023;
1457 regs->reg_s3.rime_multi.rime_multi2 = 0;
1458
1459 /* 0x177C */
1460 regs->reg_s3.cmv_st_th.cmv_th0 = 64;
1461 regs->reg_s3.cmv_st_th.cmv_th1 = 96;
1462 regs->reg_s3.cmv_st_th.cmv_th2 = 128;
1463 }
1464
1465 {
1466 RK_U8* thd = (RK_U8*)®s->reg_rc_roi.aq_tthd0;
1467 RK_U8* step = (RK_U8*)®s->reg_rc_roi.aq_stp0;
1468
1469 if (slice->slice_type == H264_I_SLICE) {
1470 for (i = 0; i < MPP_ARRAY_ELEMS(h264_aq_tthd_default); i++) {
1471 thd[i] = hw->aq_thrd_i[i];
1472 step[i] = hw->aq_step_i[i] & 0x3f;
1473 }
1474 } else {
1475 for (i = 0; i < MPP_ARRAY_ELEMS(h264_P_aq_step_default); i++) {
1476 thd[i] = hw->aq_thrd_p[i];
1477 step[i] = hw->aq_step_p[i] & 0x3f;
1478 }
1479 }
1480 }
1481
1482 mpp_env_get_u32("dump_l2_reg", &dump_l2_reg, 0);
1483
1484 if (dump_l2_reg) {
1485 mpp_log("L2 reg dump start:\n");
1486 RK_U32 *p = (RK_U32 *)regs;
1487
1488 for (i = 0; i < (sizeof(*regs) / sizeof(RK_U32)); i++)
1489 mpp_log("%04x %08x\n", 4 + i * 4, p[i]);
1490
1491 mpp_log("L2 reg done\n");
1492 }
1493
1494 hal_h264e_dbg_func("leave\n");
1495 }
1496
setup_vepu540c_ext_line_buf(HalVepu540cRegSet * regs,HalH264eVepu540cCtx * ctx)1497 static void setup_vepu540c_ext_line_buf(HalVepu540cRegSet *regs, HalH264eVepu540cCtx *ctx)
1498 {
1499 if (ctx->ext_line_buf) {
1500 RK_S32 fd = mpp_buffer_get_fd(ctx->ext_line_buf);
1501
1502 regs->reg_base.ebuft_addr = fd;
1503 regs->reg_base.ebufb_addr = fd;
1504
1505 mpp_dev_set_reg_offset(ctx->dev, 178, ctx->ext_line_buf_size);
1506 } else {
1507 regs->reg_base.ebuft_addr = 0;
1508 regs->reg_base.ebufb_addr = 0;
1509 }
1510 }
1511
hal_h264e_vepu540c_gen_regs(void * hal,HalEncTask * task)1512 static MPP_RET hal_h264e_vepu540c_gen_regs(void *hal, HalEncTask *task)
1513 {
1514 HalH264eVepu540cCtx *ctx = (HalH264eVepu540cCtx *)hal;
1515 HalVepu540cRegSet *regs = ctx->regs_set;
1516 MppEncCfgSet *cfg = ctx->cfg;
1517 H264eSps *sps = ctx->sps;
1518 H264ePps *pps = ctx->pps;
1519 H264eSlice *slice = ctx->slice;
1520 MPP_RET ret = MPP_OK;
1521
1522 hal_h264e_dbg_func("enter %p\n", hal);
1523 hal_h264e_dbg_detail("frame %d generate regs now", ctx->frms->seq_idx);
1524
1525 /* register setup */
1526 memset(regs, 0, sizeof(*regs));
1527
1528 setup_vepu540c_normal(regs);
1529 ret = setup_vepu540c_prep(regs, &ctx->cfg->prep);
1530 if (ret)
1531 return ret;
1532
1533 setup_vepu540c_codec(regs, sps, pps, slice);
1534 setup_vepu540c_rdo_pred(regs, sps, pps, slice);
1535 setup_vepu540c_rdo_cfg(®s->reg_rdo);
1536 setup_vepu540c_scl_cfg(®s->reg_scl);
1537 setup_vepu540c_rc_base(regs, sps, slice, &cfg->hw, task->rc_task);
1538 setup_vepu540c_io_buf(regs, ctx->dev, task);
1539 setup_vepu540c_recn_refr(ctx, regs);
1540
1541 regs->reg_base.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0;
1542
1543 regs->reg_base.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
1544 regs->reg_base.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
1545
1546 setup_vepu540c_split(regs, &cfg->split);
1547 setup_vepu540c_me(regs, sps, slice);
1548
1549 setup_vepu540c_l2(ctx->regs_set, slice, &cfg->hw);
1550 setup_vepu540c_ext_line_buf(regs, ctx);
1551
1552 if (ctx->roi_data)
1553 vepu540c_set_roi(&ctx->regs_set->reg_rc_roi.roi_cfg, ctx->roi_data,
1554 ctx->cfg->prep.width, ctx->cfg->prep.height);
1555
1556 mpp_env_get_u32("dump_l1_reg", &dump_l1_reg, 0);
1557
1558 if (dump_l1_reg) {
1559 mpp_log("L1 reg dump start:\n");
1560 RK_U32 *p = (RK_U32 *)regs;
1561 RK_S32 n = 0x1D0 / sizeof(RK_U32);
1562 RK_S32 i;
1563
1564 for (i = 0; i < n; i++)
1565 mpp_log("%04x %08x\n", i * 4, p[i]);
1566
1567 mpp_log("L1 reg done\n");
1568 }
1569
1570 ctx->frame_cnt++;
1571
1572 hal_h264e_dbg_func("leave %p\n", hal);
1573 return MPP_OK;
1574 }
1575
hal_h264e_vepu540c_start(void * hal,HalEncTask * task)1576 static MPP_RET hal_h264e_vepu540c_start(void *hal, HalEncTask *task)
1577 {
1578 MPP_RET ret = MPP_OK;
1579 HalH264eVepu540cCtx *ctx = (HalH264eVepu540cCtx *)hal;
1580
1581 (void) task;
1582
1583 hal_h264e_dbg_func("enter %p\n", hal);
1584
1585 do {
1586 MppDevRegWrCfg wr_cfg;
1587 MppDevRegRdCfg rd_cfg;
1588
1589 wr_cfg.reg = &ctx->regs_set->reg_ctl;
1590 wr_cfg.size = sizeof(ctx->regs_set->reg_ctl);
1591 wr_cfg.offset = VEPU540C_CTL_OFFSET;
1592 #if DUMP_REG
1593 {
1594 RK_U32 i;
1595 RK_U32 *reg = (RK_U32)wr_cfg.reg;
1596 for ( i = 0; i < sizeof(ctx->regs_set->reg_ctl) / sizeof(RK_U32); i++) {
1597 /* code */
1598 mpp_log("reg[%d] = 0x%08x\n", i, reg[i]);
1599 }
1600
1601 }
1602 #endif
1603 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
1604 if (ret) {
1605 mpp_err_f("set register write failed %d\n", ret);
1606 break;
1607 }
1608 wr_cfg.reg = &ctx->regs_set->reg_base;
1609 wr_cfg.size = sizeof(ctx->regs_set->reg_base);
1610 wr_cfg.offset = VEPU540C_BASE_OFFSET;
1611
1612 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
1613 if (ret) {
1614 mpp_err_f("set register write failed %d\n", ret);
1615 break;
1616 }
1617 wr_cfg.reg = &ctx->regs_set->reg_rc_roi;
1618 wr_cfg.size = sizeof(ctx->regs_set->reg_rc_roi);
1619 wr_cfg.offset = VEPU540C_RCROI_OFFSET;
1620
1621 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
1622 if (ret) {
1623 mpp_err_f("set register write failed %d\n", ret);
1624 break;
1625 }
1626 wr_cfg.reg = &ctx->regs_set->reg_s3;
1627 wr_cfg.size = sizeof(ctx->regs_set->reg_s3);
1628 wr_cfg.offset = VEPU540C_WEG_OFFSET;
1629
1630 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
1631 if (ret) {
1632 mpp_err_f("set register write failed %d\n", ret);
1633 break;
1634 }
1635 wr_cfg.reg = &ctx->regs_set->reg_rdo;
1636 wr_cfg.size = sizeof(ctx->regs_set->reg_rdo);
1637 wr_cfg.offset = VEPU540C_RDOCFG_OFFSET;
1638
1639 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
1640 if (ret) {
1641 mpp_err_f("set register write failed %d\n", ret);
1642 break;
1643 }
1644
1645 wr_cfg.reg = &ctx->regs_set->reg_scl;
1646 wr_cfg.size = sizeof(ctx->regs_set->reg_scl);
1647 wr_cfg.offset = VEPU540C_SCLCFG_OFFSET;
1648
1649 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
1650 if (ret) {
1651 mpp_err_f("set register write failed %d\n", ret);
1652 break;
1653 }
1654
1655 rd_cfg.reg = &ctx->regs_set->reg_st;
1656 rd_cfg.size = sizeof(ctx->regs_set->reg_st);
1657 rd_cfg.offset = VEPU540C_STATUS_OFFSET;
1658
1659 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
1660 if (ret) {
1661 mpp_err_f("set register read failed %d\n", ret);
1662 break;
1663 }
1664 /* send request to hardware */
1665 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1666
1667 if (ret) {
1668 mpp_err_f("send cmd failed %d\n", ret);
1669 break;
1670 }
1671 } while (0);
1672
1673 hal_h264e_dbg_func("leave %p\n", hal);
1674
1675 return ret;
1676 }
1677
hal_h264e_vepu540c_status_check(void * hal)1678 static MPP_RET hal_h264e_vepu540c_status_check(void *hal)
1679 {
1680 HalH264eVepu540cCtx *ctx = (HalH264eVepu540cCtx *)hal;
1681 HalVepu540cRegSet *regs_set = ctx->regs_set;
1682
1683 if (regs_set->reg_ctl.int_sta.lkt_node_done_sta)
1684 hal_h264e_dbg_detail("lkt_done finish");
1685
1686 if (regs_set->reg_ctl.int_sta.enc_done_sta)
1687 hal_h264e_dbg_detail("enc_done finish");
1688
1689 if (regs_set->reg_ctl.int_sta.vslc_done_sta)
1690 hal_h264e_dbg_detail("enc_slice finsh");
1691
1692 if (regs_set->reg_ctl.int_sta.sclr_done_sta)
1693 hal_h264e_dbg_detail("safe clear finsh");
1694
1695 if (regs_set->reg_ctl.int_sta.vbsf_oflw_sta)
1696 mpp_err_f("bit stream overflow");
1697
1698 if (regs_set->reg_ctl.int_sta.vbuf_lens_sta)
1699 mpp_err_f("bus write full");
1700
1701 if (regs_set->reg_ctl.int_sta.enc_err_sta)
1702 mpp_err_f("bus error");
1703
1704 if (regs_set->reg_ctl.int_sta.wdg_sta)
1705 mpp_err_f("wdg timeout");
1706
1707 return MPP_OK;
1708 }
1709
hal_h264e_vepu540c_wait(void * hal,HalEncTask * task)1710 static MPP_RET hal_h264e_vepu540c_wait(void *hal, HalEncTask *task)
1711 {
1712 MPP_RET ret = MPP_OK;
1713 HalH264eVepu540cCtx *ctx = (HalH264eVepu540cCtx *)hal;
1714 HalVepu540cRegSet *regs_set = ctx->regs_set;
1715
1716 hal_h264e_dbg_func("enter %p\n", hal);
1717 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
1718 if (ret) {
1719 mpp_err_f("poll cmd failed %d\n", ret);
1720 ret = MPP_ERR_VPUHW;
1721 } else {
1722 hal_h264e_vepu540c_status_check(hal);
1723 task->hw_length += regs_set->reg_st.bs_lgth_l32;
1724 }
1725
1726 hal_h264e_dbg_func("leave %p\n", hal);
1727
1728 return ret;
1729 }
1730
hal_h264e_vepu540c_ret_task(void * hal,HalEncTask * task)1731 static MPP_RET hal_h264e_vepu540c_ret_task(void *hal, HalEncTask *task)
1732 {
1733 HalH264eVepu540cCtx *ctx = (HalH264eVepu540cCtx *)hal;
1734 EncRcTaskInfo *rc_info = &task->rc_task->info;
1735 RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
1736 RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
1737 RK_U32 mbs = mb_w * mb_h;
1738 HalVepu540cRegSet *regs_set = (HalVepu540cRegSet *)ctx->regs_set;
1739 hal_h264e_dbg_func("enter %p\n", hal);
1740
1741 // update total hardware length
1742 task->length += task->hw_length;
1743
1744 // setup bit length for rate control
1745 rc_info->bit_real = task->hw_length * 8;
1746 rc_info->quality_real = regs_set->reg_st.qp_sum / mbs;
1747 /*
1748 rc_info->madi = (!regs_set->reg_st.st_bnum_b16.num_b16) ? 0 :
1749 regs_set->reg_st.madi / regs_set->reg_st.st_bnum_b16.num_b16;
1750 rc_info->madp = (!regs_set->reg_st.st_bnum_cme.num_ctu) ? 0 :
1751 regs_set->reg_st.madi / regs_set->reg_st.st_bnum_cme.num_ctu;*/
1752
1753 rc_info->iblk4_prop = (regs_set->reg_st.st_pnum_i4.pnum_i4 +
1754 regs_set->reg_st.st_pnum_i8.pnum_i8 +
1755 regs_set->reg_st.st_pnum_i16.pnum_i16) * 256 / mbs;
1756
1757 ctx->hal_rc_cfg.bit_real = rc_info->bit_real;
1758 ctx->hal_rc_cfg.quality_real = rc_info->quality_real;
1759 ctx->hal_rc_cfg.iblk4_prop = rc_info->iblk4_prop;
1760
1761 task->hal_ret.data = &ctx->hal_rc_cfg;
1762 task->hal_ret.number = 1;
1763
1764 hal_h264e_dbg_func("leave %p\n", hal);
1765
1766 return MPP_OK;
1767 }
1768
1769 const MppEncHalApi hal_h264e_vepu540c = {
1770 .name = "hal_h264e_vepu540c",
1771 .coding = MPP_VIDEO_CodingAVC,
1772 .ctx_size = sizeof(HalH264eVepu540cCtx),
1773 .flag = 0,
1774 .init = hal_h264e_vepu540c_init,
1775 .deinit = hal_h264e_vepu540c_deinit,
1776 .prepare = hal_h264e_vepu540c_prepare,
1777 .get_task = hal_h264e_vepu540c_get_task,
1778 .gen_regs = hal_h264e_vepu540c_gen_regs,
1779 .start = hal_h264e_vepu540c_start,
1780 .wait = hal_h264e_vepu540c_wait,
1781 .part_start = NULL,
1782 .part_wait = NULL,
1783 .ret_task = hal_h264e_vepu540c_ret_task,
1784 };
1785