1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h264e_vepu2_v2"
18
19 #include <string.h>
20
21 #include "mpp_env.h"
22 #include "mpp_mem.h"
23 #include "mpp_frame.h"
24 #include "mpp_common.h"
25 #include "mpp_device.h"
26 #include "mpp_rc.h"
27
28 #include "mpp_enc_hal.h"
29 #include "h264e_debug.h"
30 #include "h264e_sps.h"
31 #include "h264e_pps.h"
32 #include "h264e_slice.h"
33
34 #include "hal_h264e_debug.h"
35 #include "hal_h264e_vpu_tbl.h"
36 #include "hal_h264e_vepu_v2.h"
37 #include "hal_h264e_stream_amend.h"
38
39 #include "hal_h264e_vepu2_reg_tbl.h"
40
41 typedef struct HalH264eVepu2Ctx_t {
42 MppEncCfgSet *cfg;
43
44 MppDev dev;
45 RK_S32 frame_cnt;
46
47 /* buffers management */
48 HalH264eVepuBufs hw_bufs;
49
50 /* preprocess config */
51 HalH264eVepuPrep hw_prep;
52
53 /* input / recon / refer address config */
54 HalH264eVepuAddr hw_addr;
55 VepuOffsetCfg hw_offset;
56
57 /* macroblock ratecontrol config */
58 HalH264eVepuMbRc hw_mbrc;
59
60 /* syntax for input from enc_impl */
61 RK_U32 updated;
62 H264eSps *sps;
63 H264ePps *pps;
64 H264eSlice *slice;
65 H264eFrmInfo *frms;
66 H264eReorderInfo *reorder;
67 H264eMarkingInfo *marking;
68 H264ePrefixNal *prefix;
69
70 /* special TSVC stream header fixup */
71 HalH264eVepuStreamAmend amend;
72
73 /* vepu2 macroblock ratecontrol context */
74 HalH264eVepuMbRcCtx rc_ctx;
75
76 H264eVpu2RegSet regs_set;
77 H264eVpu2RegSet regs_get;
78 } HalH264eVepu2Ctx;
79
hal_h264e_vepu2_deinit_v2(void * hal)80 static MPP_RET hal_h264e_vepu2_deinit_v2(void *hal)
81 {
82 HalH264eVepu2Ctx *p = (HalH264eVepu2Ctx *)hal;
83
84 hal_h264e_dbg_func("enter %p\n", p);
85
86 if (p->dev) {
87 mpp_dev_deinit(p->dev);
88 p->dev = NULL;
89 }
90
91 h264e_vepu_buf_deinit(&p->hw_bufs);
92
93 if (p->rc_ctx) {
94 h264e_vepu_mbrc_deinit(p->rc_ctx);
95 p->rc_ctx = NULL;
96 }
97
98 h264e_vepu_stream_amend_deinit(&p->amend);
99
100 hal_h264e_dbg_func("leave %p\n", p);
101
102 return MPP_OK;
103 }
104
hal_h264e_vepu2_init_v2(void * hal,MppEncHalCfg * cfg)105 static MPP_RET hal_h264e_vepu2_init_v2(void *hal, MppEncHalCfg *cfg)
106 {
107 HalH264eVepu2Ctx *p = (HalH264eVepu2Ctx *)hal;
108 MPP_RET ret = MPP_OK;
109
110 hal_h264e_dbg_func("enter %p\n", p);
111
112 p->cfg = cfg->cfg;
113
114 /* update output to MppEnc */
115 cfg->type = VPU_CLIENT_VEPU2;
116
117 ret = mpp_dev_init(&cfg->dev, cfg->type);
118 if (ret) {
119 mpp_err_f("mpp_dev_init failed ret: %d\n", ret);
120 goto DONE;
121 }
122 p->dev = cfg->dev;
123
124 ret = h264e_vepu_buf_init(&p->hw_bufs);
125 if (ret) {
126 mpp_err_f("init vepu buffer failed ret: %d\n", ret);
127 goto DONE;
128 }
129
130 ret = h264e_vepu_mbrc_init(&p->rc_ctx, &p->hw_mbrc);
131 if (ret) {
132 mpp_err_f("init mb rate control failed ret: %d\n", ret);
133 goto DONE;
134 }
135
136 /* create buffer to TSVC stream */
137 h264e_vepu_stream_amend_init(&p->amend);
138
139 DONE:
140 if (ret)
141 hal_h264e_vepu2_deinit_v2(hal);
142
143 hal_h264e_dbg_func("leave %p\n", p);
144 return ret;
145 }
146
update_vepu2_syntax(HalH264eVepu2Ctx * ctx,MppSyntax * syntax)147 static RK_U32 update_vepu2_syntax(HalH264eVepu2Ctx *ctx, MppSyntax *syntax)
148 {
149 H264eSyntaxDesc *desc = syntax->data;
150 RK_S32 syn_num = syntax->number;
151 RK_U32 updated = 0;
152 RK_S32 i;
153
154 for (i = 0; i < syn_num; i++, desc++) {
155 switch (desc->type) {
156 case H264E_SYN_CFG : {
157 hal_h264e_dbg_detail("update cfg");
158 ctx->cfg = desc->p;
159 } break;
160 case H264E_SYN_SPS : {
161 hal_h264e_dbg_detail("update sps");
162 ctx->sps = desc->p;
163 } break;
164 case H264E_SYN_PPS : {
165 hal_h264e_dbg_detail("update pps");
166 ctx->pps = desc->p;
167 } break;
168 case H264E_SYN_DPB : {
169 hal_h264e_dbg_detail("update dpb");
170 } break;
171 case H264E_SYN_SLICE : {
172 hal_h264e_dbg_detail("update slice");
173 ctx->slice = desc->p;
174 } break;
175 case H264E_SYN_FRAME : {
176 hal_h264e_dbg_detail("update frames");
177 ctx->frms = desc->p;
178 } break;
179 case H264E_SYN_PREFIX : {
180 hal_h264e_dbg_detail("update prefix nal");
181 ctx->prefix = desc->p;
182 } break;
183 default : {
184 mpp_log_f("invalid syntax type %d\n", desc->type);
185 } break;
186 }
187
188 updated |= SYN_TYPE_FLAG(desc->type);
189 }
190
191 return updated;
192 }
193
hal_h264e_vepu2_get_task_v2(void * hal,HalEncTask * task)194 static MPP_RET hal_h264e_vepu2_get_task_v2(void *hal, HalEncTask *task)
195 {
196 HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
197 RK_U32 updated = update_vepu2_syntax(ctx, &task->syntax);
198 MppEncPrepCfg *prep = &ctx->cfg->prep;
199 HalH264eVepuPrep *hw_prep = &ctx->hw_prep;
200 HalH264eVepuAddr *hw_addr = &ctx->hw_addr;
201 HalH264eVepuBufs *hw_bufs = &ctx->hw_bufs;
202 VepuOffsetCfg *hw_offset = &ctx->hw_offset;
203 H264eFrmInfo *frms = ctx->frms;
204
205 hal_h264e_dbg_func("enter %p\n", hal);
206
207 if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG)) {
208 h264e_vepu_buf_set_frame_size(hw_bufs, prep->width, prep->height);
209
210 /* preprocess setup */
211 h264e_vepu_prep_setup(hw_prep, prep);
212
213 h264e_vepu_mbrc_setup(ctx->rc_ctx, ctx->cfg);
214 }
215
216 if (updated & SYN_TYPE_FLAG(H264E_SYN_SLICE)) {
217 H264eSlice *slice = ctx->slice;
218
219 h264e_vepu_buf_set_cabac_idc(hw_bufs, slice->cabac_init_idc);
220 }
221
222 h264e_vepu_prep_get_addr(hw_prep, task->input, &hw_addr->orig);
223
224 MppBuffer recn = h264e_vepu_buf_get_frame_buffer(hw_bufs, frms->curr_idx);
225 MppBuffer refr = h264e_vepu_buf_get_frame_buffer(hw_bufs, frms->refr_idx);
226
227 hw_addr->recn[0] = mpp_buffer_get_fd(recn);
228 hw_addr->refr[0] = mpp_buffer_get_fd(refr);
229 hw_addr->recn[1] = hw_addr->recn[0];
230 hw_addr->refr[1] = hw_addr->refr[0];
231
232 hw_offset->fmt = prep->format;
233 hw_offset->width = prep->width;
234 hw_offset->height = prep->height;
235 hw_offset->hor_stride = prep->hor_stride;
236 hw_offset->ver_stride = prep->ver_stride;
237 hw_offset->offset_x = mpp_frame_get_offset_x(task->frame);
238 hw_offset->offset_y = mpp_frame_get_offset_y(task->frame);
239
240 get_vepu_offset_cfg(hw_offset);
241
242 h264e_vepu_stream_amend_config(&ctx->amend, task->packet, ctx->cfg,
243 ctx->slice, ctx->prefix);
244
245 hal_h264e_dbg_func("leave %p\n", hal);
246
247 return MPP_OK;
248 }
249
setup_output_packet(HalH264eVepu2Ctx * ctx,RK_U32 * reg,MppBuffer buf,RK_U32 offset)250 static RK_S32 setup_output_packet(HalH264eVepu2Ctx *ctx, RK_U32 *reg, MppBuffer buf, RK_U32 offset)
251 {
252 RK_U32 offset8 = offset & (~0x7);
253 RK_S32 fd = mpp_buffer_get_fd(buf);
254 RK_U32 hdr_rem_msb = 0;
255 RK_U32 hdr_rem_lsb = 0;
256 RK_U32 limit = 0;
257
258 if (offset) {
259 RK_U8 *buf32 = (RK_U8 *)mpp_buffer_get_ptr(buf) + offset8;
260
261 hdr_rem_msb = MPP_RB32(buf32);
262 hdr_rem_lsb = MPP_RB32(buf32 + 4);
263 }
264
265 hal_h264e_dbg_detail("offset %d offset8 %d\n", offset, offset8);
266 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_STREAM, fd);
267 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_OUTPUT_STREAM >> 2, offset8);
268
269 /* output buffer size is 64 bit address then 8 multiple size */
270 limit = mpp_buffer_get_size(buf);
271 limit -= offset8;
272 limit >>= 3;
273 limit &= ~7;
274 H264E_HAL_SET_REG(reg, VEPU_REG_STR_BUF_LIMIT, limit);
275
276 hal_h264e_dbg_detail("msb %08x lsb %08x", hdr_rem_msb, hdr_rem_lsb);
277
278 H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_MSB, hdr_rem_msb);
279 H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_LSB, hdr_rem_lsb);
280
281 return (offset - offset8) * 8;
282 }
283
setup_intra_refresh(HalH264eVepu2Ctx * ctx,EncFrmStatus * frm)284 static MPP_RET setup_intra_refresh(HalH264eVepu2Ctx *ctx, EncFrmStatus *frm)
285 {
286 MPP_RET ret = MPP_OK;
287 RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
288 RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
289 RK_U32 refresh_num = ctx->cfg->rc.refresh_num;
290 MppEncCfgSet *cfg = ctx->cfg;
291 RK_U32 *reg = ctx->regs_set.val;
292 RK_U32 val = 0;
293 RK_S32 top = 0;
294 RK_S32 left = 0;
295 RK_S32 right = 0;
296 RK_S32 bottom = 0;
297 RK_U32 refresh_idx = frm->seq_idx % cfg->rc.gop;
298
299 hal_h264e_dbg_func("enter\n");
300
301 if (!ctx->cfg->rc.refresh_en || !frm->is_i_refresh) {
302 goto RET;
303 }
304
305 if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW) {
306 left = 0;
307 right = mb_w;
308 top = refresh_idx * refresh_num - 2;
309 bottom = (refresh_idx + 1) * refresh_num - 1;
310 top = mpp_clip(top, 0, mb_h);
311 bottom = mpp_clip(bottom, 0, mb_h);
312 } else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL) {
313 top = 0;
314 bottom = mb_h;
315 left = refresh_idx * refresh_num - 2;
316 right = (refresh_idx + 1) * refresh_num - 1;
317 left = mpp_clip(left, 0, mb_w);
318 right = mpp_clip(right, 0, mb_w);
319 }
320
321 RET:
322 val = VEPU_REG_INTRA_AREA_TOP(top)
323 | VEPU_REG_INTRA_AREA_BOTTOM(bottom)
324 | VEPU_REG_INTRA_AREA_LEFT(left)
325 | VEPU_REG_INTRA_AREA_RIGHT(right);
326 H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_AREA_CTRL, val);
327
328 hal_h264e_dbg_func("leave, ret %d\n", ret);
329
330 return ret;
331 }
332
hal_h264e_vepu2_gen_regs_v2(void * hal,HalEncTask * task)333 static MPP_RET hal_h264e_vepu2_gen_regs_v2(void *hal, HalEncTask *task)
334 {
335 //MPP_RET ret = MPP_OK;
336 HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
337 HalH264eVepuBufs *hw_bufs = &ctx->hw_bufs;
338 HalH264eVepuPrep *hw_prep = &ctx->hw_prep;
339 HalH264eVepuAddr *hw_addr = &ctx->hw_addr;
340 HalH264eVepuMbRc *hw_mbrc = &ctx->hw_mbrc;
341 VepuOffsetCfg *hw_offset = &ctx->hw_offset;
342 EncRcTaskInfo *rc_info = &task->rc_task->info;
343 EncFrmStatus *frm = &task->rc_task->frm;
344 H264eSps *sps = ctx->sps;
345 H264ePps *pps = ctx->pps;
346 H264eSlice *slice = ctx->slice;
347 RK_U32 *reg = ctx->regs_set.val;
348 RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
349 RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
350 RK_U32 offset = mpp_packet_get_length(task->packet);
351 RK_U32 first_free_bit = 0;
352 RK_U32 val = 0;
353 RK_S32 i = 0;
354
355 if (hw_prep->rotation) {
356 mb_w = ctx->sps->pic_height_in_mbs;
357 mb_h = ctx->sps->pic_width_in_mbs;
358 }
359
360 hw_mbrc->qp_init = rc_info->quality_target;
361 hw_mbrc->qp_max = rc_info->quality_max;
362 hw_mbrc->qp_min = rc_info->quality_min;
363
364 hal_h264e_dbg_func("enter %p\n", hal);
365
366 hal_h264e_dbg_detail("frame %d generate regs now", frm->seq_idx);
367
368 // prepare mb rc config
369 h264e_vepu_mbrc_prepare(ctx->rc_ctx, &ctx->hw_mbrc, task->rc_task);
370 h264e_vepu_slice_split_cfg(ctx->slice, &ctx->hw_mbrc, task->rc_task, ctx->cfg);
371
372 /* setup output address with offset */
373 first_free_bit = setup_output_packet(ctx, reg, task->output, offset);
374
375 /* set extra byte for header */
376 hw_mbrc->hdr_strm_size = offset;
377 hw_mbrc->hdr_free_size = first_free_bit / 8;
378 hw_mbrc->out_strm_size = 0;
379
380 /*
381 * The hardware needs only the value for luma plane, because
382 * values of other planes are calculated internally based on
383 * format setting.
384 */
385 setup_intra_refresh(ctx, frm);
386
387 val = VEPU_REG_AXI_CTRL_READ_ID(0);
388 val |= VEPU_REG_AXI_CTRL_WRITE_ID(0);
389 val |= VEPU_REG_AXI_CTRL_BURST_LEN(16);
390 val |= VEPU_REG_AXI_CTRL_INCREMENT_MODE(0);
391 val |= VEPU_REG_AXI_CTRL_BIRST_DISCARD(0);
392 H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val);
393
394 H264E_HAL_SET_REG(reg, VEPU_QP_ADJUST_MAD_DELTA_ROI,
395 hw_mbrc->mad_qp_change);
396
397 val = 0;
398 if (mb_w * mb_h > 3600)
399 val = VEPU_REG_DISABLE_QUARTER_PIXEL_MV;
400 val |= VEPU_REG_CABAC_INIT_IDC(slice->cabac_init_idc);
401 if (pps->entropy_coding_mode)
402 val |= VEPU_REG_ENTROPY_CODING_MODE;
403 if (pps->transform_8x8_mode)
404 val |= VEPU_REG_H264_TRANS8X8_MODE;
405 if (sps->profile_idc > 31)
406 val |= VEPU_REG_H264_INTER4X4_MODE;
407 /*reg |= VEPU_REG_H264_STREAM_MODE;*/
408 val |= VEPU_REG_H264_SLICE_SIZE(hw_mbrc->slice_size_mb_rows);
409 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL0, val);
410
411 RK_U32 scaler = MPP_MAX(1, 200 / (mb_w + mb_h));
412
413 RK_U32 skip_penalty = MPP_MIN(255, h264_skip_sad_penalty[hw_mbrc->qp_init] * scaler);
414
415 RK_U32 overfill_r = (hw_prep->src_w & 0x0f) ?
416 ((16 - (hw_prep->src_w & 0x0f)) / 4) : 0;
417
418 RK_U32 overfill_b = (hw_prep->src_h & 0x0f) ?
419 (16 - (hw_prep->src_h & 0x0f)) : 0;
420
421 val = VEPU_REG_STREAM_START_OFFSET(first_free_bit) |
422 VEPU_REG_SKIP_MACROBLOCK_PENALTY(skip_penalty) |
423 VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(overfill_r) |
424 VEPU_REG_IN_IMG_CTRL_OVRFLB(overfill_b);
425 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET, val);
426
427 // When offset is zero row length should be total 16 aligned width
428 val = VEPU_REG_IN_IMG_CHROMA_OFFSET(0)
429 | VEPU_REG_IN_IMG_LUMA_OFFSET(0)
430 | VEPU_REG_IN_IMG_CTRL_ROW_LEN(hw_prep->pixel_stride);
431
432 H264E_HAL_SET_REG(reg, VEPU_REG_INPUT_LUMA_INFO, val);
433
434 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[0])
435 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[1]);
436 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(0), val);
437
438 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[2])
439 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[3]);
440 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(1), val);
441
442 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[4])
443 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[5]);
444 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(2), val);
445
446 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[6])
447 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[7]);
448 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(3), val);
449
450 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[8])
451 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[9]);
452 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(4), val);
453
454 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[0])
455 | VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[1]);
456 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(0), val);
457
458 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[2])
459 | VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[3]);
460 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(1), val);
461
462 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[4])
463 | VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[5]);
464 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(2), val);
465
466 val = VEPU_REG_CHKPT_DELTA_QP_CHK6(hw_mbrc->cp_delta_qp[6])
467 | VEPU_REG_CHKPT_DELTA_QP_CHK5(hw_mbrc->cp_delta_qp[5])
468 | VEPU_REG_CHKPT_DELTA_QP_CHK4(hw_mbrc->cp_delta_qp[4])
469 | VEPU_REG_CHKPT_DELTA_QP_CHK3(hw_mbrc->cp_delta_qp[3])
470 | VEPU_REG_CHKPT_DELTA_QP_CHK2(hw_mbrc->cp_delta_qp[2])
471 | VEPU_REG_CHKPT_DELTA_QP_CHK1(hw_mbrc->cp_delta_qp[1])
472 | VEPU_REG_CHKPT_DELTA_QP_CHK0(hw_mbrc->cp_delta_qp[0]);
473 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_DELTA_QP, val);
474
475 val = VEPU_REG_MAD_THRESHOLD(hw_mbrc->mad_threshold)
476 | VEPU_REG_IN_IMG_CTRL_FMT(hw_prep->src_fmt)
477 | VEPU_REG_IN_IMG_ROTATE_MODE(hw_prep->rotation)
478 | VEPU_REG_SIZE_TABLE_PRESENT; //FIXED
479 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL1, val);
480
481 val = VEPU_REG_INTRA16X16_MODE(h264_intra16_favor[hw_mbrc->qp_init])
482 | VEPU_REG_INTER_MODE(h264_inter_favor[hw_mbrc->qp_init]);
483 H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_INTER_MODE, val);
484
485 val = VEPU_REG_PPS_INIT_QP(pps->pic_init_qp)
486 | VEPU_REG_SLICE_FILTER_ALPHA(slice->slice_alpha_c0_offset_div2)
487 | VEPU_REG_SLICE_FILTER_BETA(slice->slice_beta_offset_div2)
488 | VEPU_REG_CHROMA_QP_OFFSET(pps->chroma_qp_index_offset)
489 | VEPU_REG_IDR_PIC_ID(slice->idr_pic_id);
490
491 if (slice->disable_deblocking_filter_idc)
492 val |= VEPU_REG_FILTER_DISABLE;
493
494 if (pps->constrained_intra_pred)
495 val |= VEPU_REG_CONSTRAINED_INTRA_PREDICTION;
496 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL2, val);
497
498 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_NEXT_PIC, 0);
499 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_MV_OUT, 0);
500
501 MppBuffer cabac_table = hw_bufs->cabac_table;
502 RK_S32 cabac_table_fd = cabac_table ? mpp_buffer_get_fd(cabac_table) : 0;
503
504 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_CABAC_TBL, cabac_table_fd);
505
506 val = VEPU_REG_ROI1_TOP_MB(mb_h)
507 | VEPU_REG_ROI1_BOTTOM_MB(mb_h)
508 | VEPU_REG_ROI1_LEFT_MB(mb_w)
509 | VEPU_REG_ROI1_RIGHT_MB(mb_w);
510 H264E_HAL_SET_REG(reg, VEPU_REG_ROI1, val);
511
512 val = VEPU_REG_ROI2_TOP_MB(mb_h)
513 | VEPU_REG_ROI2_BOTTOM_MB(mb_h)
514 | VEPU_REG_ROI2_LEFT_MB(mb_w)
515 | VEPU_REG_ROI2_RIGHT_MB(mb_w);
516 H264E_HAL_SET_REG(reg, VEPU_REG_ROI2, val);
517 H264E_HAL_SET_REG(reg, VEPU_REG_STABLILIZATION_OUTPUT, 0);
518
519 val = VEPU_REG_RGB2YUV_CONVERSION_COEFB(hw_prep->color_conversion_coeff_b)
520 | VEPU_REG_RGB2YUV_CONVERSION_COEFA(hw_prep->color_conversion_coeff_a);
521 H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF1, val);
522
523 val = VEPU_REG_RGB2YUV_CONVERSION_COEFE(hw_prep->color_conversion_coeff_e)
524 | VEPU_REG_RGB2YUV_CONVERSION_COEFC(hw_prep->color_conversion_coeff_c);
525 H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF2, val);
526
527 val = VEPU_REG_RGB2YUV_CONVERSION_COEFF(hw_prep->color_conversion_coeff_f);
528 H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF3, val);
529
530 val = VEPU_REG_RGB_MASK_B_MSB(hw_prep->b_mask_msb)
531 | VEPU_REG_RGB_MASK_G_MSB(hw_prep->g_mask_msb)
532 | VEPU_REG_RGB_MASK_R_MSB(hw_prep->r_mask_msb);
533 H264E_HAL_SET_REG(reg, VEPU_REG_RGB_MASK_MSB, val); //FIXED
534
535 {
536 RK_U32 diff_mv_penalty[3] = {0};
537 diff_mv_penalty[0] = h264_diff_mv_penalty4p[hw_mbrc->qp_init];
538 diff_mv_penalty[1] = h264_diff_mv_penalty[hw_mbrc->qp_init];
539 diff_mv_penalty[2] = h264_diff_mv_penalty[hw_mbrc->qp_init];
540
541 val = VEPU_REG_1MV_PENALTY(diff_mv_penalty[1])
542 | VEPU_REG_QMV_PENALTY(diff_mv_penalty[2])
543 | VEPU_REG_4MV_PENALTY(diff_mv_penalty[0]);
544 }
545
546 val |= VEPU_REG_SPLIT_MV_MODE_EN;
547 H264E_HAL_SET_REG(reg, VEPU_REG_MV_PENALTY, val);
548
549 val = VEPU_REG_H264_LUMA_INIT_QP(hw_mbrc->qp_init)
550 | VEPU_REG_H264_QP_MAX(hw_mbrc->qp_max)
551 | VEPU_REG_H264_QP_MIN(hw_mbrc->qp_min)
552 | VEPU_REG_H264_CHKPT_DISTANCE(hw_mbrc->cp_distance_mbs);
553 H264E_HAL_SET_REG(reg, VEPU_REG_QP_VAL, val);
554
555 val = VEPU_REG_ZERO_MV_FAVOR_D2(10);
556 H264E_HAL_SET_REG(reg, VEPU_REG_MVC_RELATE, val);
557
558 val = VEPU_REG_OUTPUT_SWAP32
559 | VEPU_REG_OUTPUT_SWAP16
560 | VEPU_REG_OUTPUT_SWAP8
561 | VEPU_REG_INPUT_SWAP8_(hw_prep->swap_8_in)
562 | VEPU_REG_INPUT_SWAP16_(hw_prep->swap_16_in)
563 | VEPU_REG_INPUT_SWAP32_(hw_prep->swap_32_in);
564 H264E_HAL_SET_REG(reg, VEPU_REG_DATA_ENDIAN, val);
565
566 val = VEPU_REG_PPS_ID(pps->pps_id)
567 | VEPU_REG_INTRA_PRED_MODE(h264_prev_mode_favor[hw_mbrc->qp_init])
568 | VEPU_REG_FRAME_NUM(slice->frame_num);
569 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL3, val);
570
571 val = VEPU_REG_INTERRUPT_TIMEOUT_EN;
572 H264E_HAL_SET_REG(reg, VEPU_REG_INTERRUPT, val);
573
574 {
575 RK_U8 dmv_penalty[128] = {0};
576 RK_U8 dmv_qpel_penalty[128] = {0};
577
578 for (i = 0; i < 128; i++) {
579 dmv_penalty[i] = i;
580 dmv_qpel_penalty[i] = MPP_MIN(255, exp_golomb_signed(i));
581 }
582
583 for (i = 0; i < 128; i += 4) {
584 val = VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i], 3);
585 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 1], 2);
586 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 2], 1);
587 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 3], 0);
588 H264E_HAL_SET_REG(reg, VEPU_REG_DMV_PENALTY_TBL(i / 4), val);
589
590 val = VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(
591 dmv_qpel_penalty[i], 3);
592 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(
593 dmv_qpel_penalty[i + 1], 2);
594 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(
595 dmv_qpel_penalty[i + 2], 1);
596 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(
597 dmv_qpel_penalty[i + 3], 0);
598 H264E_HAL_SET_REG(reg, VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i / 4), val);
599 }
600 }
601
602 /* set buffers addr */
603 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_LUMA, hw_addr->orig[0]);
604 if (hw_offset->offset_byte[0])
605 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_LUMA >> 2,
606 hw_offset->offset_byte[0]);
607 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CB, hw_addr->orig[1]);
608 if (hw_offset->offset_byte[1])
609 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CB >> 2,
610 hw_offset->offset_byte[1]);
611 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CR, hw_addr->orig[2]);
612 if (hw_offset->offset_byte[2])
613 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CR >> 2,
614 hw_offset->offset_byte[2]);
615
616 MppBuffer nal_size_table = h264e_vepu_buf_get_nal_size_table(hw_bufs);
617 RK_S32 nal_size_table_fd = nal_size_table ? mpp_buffer_get_fd(nal_size_table) : 0;
618
619 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_CTRL, nal_size_table_fd);
620
621 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_LUMA, hw_addr->recn[0]);
622 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_CHROMA, hw_addr->recn[1]);
623 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REC_CHROMA >> 2, hw_bufs->yuv_size);
624 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_LUMA, hw_addr->refr[0]);
625 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_CHROMA, hw_addr->refr[1]);
626 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REF_CHROMA >> 2, hw_bufs->yuv_size);
627
628 /* set important encode mode info */
629 val = VEPU_REG_MB_HEIGHT(mb_h)
630 | VEPU_REG_MB_WIDTH(mb_w)
631 | VEPU_REG_PIC_TYPE(slice->idr_flag)
632 | VEPU_REG_ENCODE_FORMAT(3)
633 | VEPU_REG_ENCODE_ENABLE;
634 H264E_HAL_SET_REG(reg, VEPU_REG_ENCODE_START, val);
635
636 ctx->frame_cnt++;
637
638 hal_h264e_dbg_func("leave %p\n", hal);
639 return MPP_OK;
640 }
641
hal_h264e_vepu2_start_v2(void * hal,HalEncTask * task)642 static MPP_RET hal_h264e_vepu2_start_v2(void *hal, HalEncTask *task)
643 {
644 MPP_RET ret = MPP_OK;
645 HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
646 (void)task;
647
648 hal_h264e_dbg_func("enter %p\n", hal);
649
650 if (ctx->dev) {
651 MppDevRegWrCfg wr_cfg;
652 MppDevRegRdCfg rd_cfg;
653 RK_U32 reg_size = sizeof(ctx->regs_set);
654
655 do {
656 wr_cfg.reg = &ctx->regs_set;
657 wr_cfg.size = reg_size;
658 wr_cfg.offset = 0;
659
660 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
661 if (ret) {
662 mpp_err_f("set register write failed %d\n", ret);
663 break;
664 }
665
666 rd_cfg.reg = &ctx->regs_get;
667 rd_cfg.size = reg_size;
668 rd_cfg.offset = 0;
669
670 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
671 if (ret) {
672 mpp_err_f("set register read failed %d\n", ret);
673 break;
674 }
675
676 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
677 if (ret) {
678 mpp_err_f("send cmd failed %d\n", ret);
679 break;
680 }
681 } while (0);
682 } else
683 mpp_err("invalid NULL device ctx\n");
684
685 hal_h264e_dbg_func("leave %p\n", hal);
686
687 return ret;
688 }
689
h264e_vepu2_get_mbrc(HalH264eVepuMbRc * mb_rc,H264eVpu2RegSet * reg)690 static void h264e_vepu2_get_mbrc(HalH264eVepuMbRc *mb_rc, H264eVpu2RegSet *reg)
691 {
692 RK_S32 i = 0;
693 RK_U32 cpt_prev = 0;
694 RK_U32 overflow = 0;
695 RK_U32 cpt_idx = VEPU_REG_CHECKPOINT(0) / 4;
696 RK_U32 *reg_val = reg->val;
697
698 mb_rc->hw_status = reg_val[VEPU_REG_INTERRUPT / 4];
699 mb_rc->out_strm_size = reg_val[VEPU_REG_STR_BUF_LIMIT / 4] / 8 - mb_rc->hdr_free_size;
700 mb_rc->qp_sum = ((reg_val[VEPU_REG_QP_SUM_DIV2 / 4] >> 11) & 0x001fffff) * 2;
701 mb_rc->less_mad_count = (reg_val[VEPU_REG_MB_CTRL / 4] >> 16) & 0xffff;
702 mb_rc->rlc_count = reg_val[VEPU_REG_RLC_SUM / 4] & 0x3fffff;
703
704 for (i = 0; i < VEPU_CHECK_POINTS_MAX; i++) {
705 RK_U32 cpt = VEPU_REG_CHECKPOINT_RESULT(reg_val[cpt_idx]);
706
707 if (cpt < cpt_prev)
708 overflow += (1 << 21);
709
710 cpt_prev = cpt;
711 mb_rc->cp_usage[i] = cpt + overflow;
712 cpt_idx += (i & 1);
713 }
714 }
715
hal_h264e_vepu2_wait_v2(void * hal,HalEncTask * task)716 static MPP_RET hal_h264e_vepu2_wait_v2(void *hal, HalEncTask *task)
717 {
718 HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
719 HalH264eVepuMbRc *hw_mbrc = &ctx->hw_mbrc;
720 MPP_RET ret = MPP_NOK;
721 (void) task;
722
723 hal_h264e_dbg_func("enter %p\n", hal);
724
725 if (ctx->dev) {
726 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
727 if (ret)
728 mpp_err_f("poll cmd failed %d\n", ret);
729 } else {
730 mpp_err("invalid NULL device ctx\n");
731 return ret;
732 }
733
734 h264e_vepu2_get_mbrc(hw_mbrc, &ctx->regs_get);
735 h264e_vepu_mbrc_update(ctx->rc_ctx, hw_mbrc);
736
737 {
738 HalH264eVepuStreamAmend *amend = &ctx->amend;
739 if (amend->enable) {
740 amend->old_length = hw_mbrc->out_strm_size;
741 h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg);
742 ctx->hw_mbrc.out_strm_size = amend->new_length;
743 } else if (amend->prefix) {
744 /* check prefix value */
745 amend->old_length = hw_mbrc->out_strm_size;
746 h264e_vepu_stream_amend_sync_ref_idc(amend);
747 }
748 }
749
750 task->hw_length += ctx->hw_mbrc.out_strm_size;
751
752 hal_h264e_dbg_func("leave %p\n", hal);
753
754 return MPP_OK;
755 }
756
hal_h264e_vepu2_ret_task_v2(void * hal,HalEncTask * task)757 static MPP_RET hal_h264e_vepu2_ret_task_v2(void *hal, HalEncTask *task)
758 {
759 HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
760 EncRcTaskInfo *rc_info = &task->rc_task->info;
761 RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
762 RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
763 RK_U32 mbs = mb_w * mb_h;
764
765 hal_h264e_dbg_func("enter %p\n", hal);
766
767 task->length += task->hw_length;
768
769 rc_info->bit_real = task->hw_length * 8;
770 rc_info->quality_real = ctx->hw_mbrc.qp_sum / mbs;
771
772 hal_h264e_dbg_rc("real bit %d quality %d\n", rc_info->bit_real, rc_info->quality_real);
773
774 task->hal_ret.data = rc_info;
775 task->hal_ret.number = 1;
776
777 hal_h264e_dbg_func("leave %p\n", hal);
778
779 return MPP_OK;
780 }
781
782 const MppEncHalApi hal_h264e_vepu2 = {
783 .name = "hal_h264e_vepu2",
784 .coding = MPP_VIDEO_CodingAVC,
785 .ctx_size = sizeof(HalH264eVepu2Ctx),
786 .flag = 0,
787 .init = hal_h264e_vepu2_init_v2,
788 .deinit = hal_h264e_vepu2_deinit_v2,
789 .prepare = NULL,
790 .get_task = hal_h264e_vepu2_get_task_v2,
791 .gen_regs = hal_h264e_vepu2_gen_regs_v2,
792 .start = hal_h264e_vepu2_start_v2,
793 .wait = hal_h264e_vepu2_wait_v2,
794 .part_start = NULL,
795 .part_wait = NULL,
796 .ret_task = hal_h264e_vepu2_ret_task_v2,
797 };
798