1 /*
2 *
3 * Copyright 2015 Rockchip Electronics Co. LTD
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #define MODULE_TAG "hal_h264d_rkv_reg"
19
20 #include <stdio.h>
21 #include <stdlib.h>
22 #include <string.h>
23
24 #include "rk_type.h"
25 #include "mpp_err.h"
26 #include "mpp_mem.h"
27 #include "mpp_common.h"
28 #include "mpp_bitput.h"
29
30 #include "hal_h264d_global.h"
31 #include "hal_h264d_rkv_reg.h"
32 #include "mpp_dec_cb_param.h"
33
34 /* Number registers for the decoder */
35 #define DEC_RKV_REGISTERS 78
36
37 #define RKV_CABAC_TAB_SIZE (928*4 + 128) /* bytes */
38 #define RKV_SPSPPS_SIZE (256*32 + 128) /* bytes */
39 #define RKV_RPS_SIZE (128 + 128) /* bytes */
40 #define RKV_SCALING_LIST_SIZE (6*16+2*64 + 128) /* bytes */
41 #define RKV_ERROR_INFO_SIZE (256*144*4) /* bytes */
42
43 typedef struct h264d_rkv_buf_t {
44 RK_U32 valid;
45 MppBuffer spspps;
46 MppBuffer rps;
47 MppBuffer sclst;
48 H264dRkvRegs_t *regs;
49 } H264dRkvBuf_t;
50
51 typedef struct h264d_rkv_reg_ctx_t {
52 RK_U8 spspps[32];
53 RK_U8 rps[RKV_RPS_SIZE];
54 RK_U8 sclst[RKV_SCALING_LIST_SIZE];
55
56 MppBuffer cabac_buf;
57 MppBuffer errinfo_buf;
58 H264dRkvBuf_t reg_buf[3];
59
60 MppBuffer spspps_buf;
61 MppBuffer rps_buf;
62 MppBuffer sclst_buf;
63 H264dRkvRegs_t *regs;
64 } H264dRkvRegCtx_t;
65
66 const RK_U32 rkv_cabac_table[928] = {
67 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x21173307,
68 0x00150217, 0x31000901, 0x390576db, 0x41f54ef3, 0x310c3e01, 0x321149fc,
69 0x2b094012, 0x431a001d, 0x68095a10, 0x68ec7fd2, 0x4ef34301, 0x3e0141f5,
70 0x5fef56fa, 0x2d093dfa, 0x51fa45fd, 0x370660f5, 0x56fb4307, 0x3a005802,
71 0x5ef64cfd, 0x45043605, 0x580051fd, 0x4afb43f9, 0x50fb4afc, 0x3a0148f9,
72 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100, 0x3e03290d, 0x4efc2d00,
73 0x7ee560fd, 0x65e762e4, 0x52e443e9, 0x53f05eec, 0x5beb6eea, 0x5df366ee,
74 0x5cf97fe3, 0x60f959fb, 0x2efd6cf3, 0x39ff41ff, 0x4afd5df7, 0x57f85cf7,
75 0x36057ee9, 0x3b063c06, 0x30ff4506, 0x45fc4400, 0x55fe58f8, 0x4bff4efa,
76 0x36024df9, 0x44fd3205, 0x2a063201, 0x3f0151fc, 0x430046fc, 0x4cfe3902,
77 0x4004230b, 0x230b3d01, 0x180c1912, 0x240d1d0d, 0x49f95df6, 0x2e0d49fe,
78 0x64f93109, 0x35023509, 0x3dfe3505, 0x38003800, 0x3cfb3ff3, 0x39043eff,
79 0x390445fa, 0x3304270e, 0x4003440d, 0x3f093d01, 0x27103207, 0x34042c05,
80 0x3cfb300b, 0x3b003bff, 0x2c052116, 0x4eff2b0e, 0x45093c00, 0x28021c0b,
81 0x31002c03, 0x2c022e00, 0x2f003302, 0x3e022704, 0x36002e06, 0x3a023603,
82 0x33063f04, 0x35073906, 0x37063406, 0x240e2d0b, 0x52ff3508, 0x4efd3707,
83 0x1f162e0f, 0x071954ff, 0x031cf91e, 0x0020041c, 0x061eff22, 0x0920061e,
84 0x1b1a131f, 0x14251e1a, 0x4611221c, 0x3b054301, 0x1e104309, 0x23122012,
85 0x1f181d16, 0x2b122617, 0x3f0b2914, 0x40093b09, 0x59fe5eff, 0x4cfa6cf7,
86 0x2d002cfe, 0x40fd3400, 0x46fc3bfe, 0x52f84bfc, 0x4df766ef, 0x2a001803,
87 0x37003000, 0x47f93bfa, 0x57f553f4, 0x3a0177e2, 0x24ff1dfd, 0x2b022601,
88 0x3a0037fa, 0x4afd4000, 0x46005af6, 0x1f051dfc, 0x3b012a07, 0x48fd3afe,
89 0x61f551fd, 0x05083a00, 0x120e0e0a, 0x28021b0d, 0x46fd3a00, 0x55f84ffa,
90 0x6af30000, 0x57f66af0, 0x6eee72eb, 0x6eea62f2, 0x67ee6aeb, 0x6ce96beb,
91 0x60f670e6, 0x5bfb5ff4, 0x5eea5df7, 0x430956fb, 0x55f650fc, 0x3c0746ff,
92 0x3d053a09, 0x320f320c, 0x36113112, 0x2e07290a, 0x310733ff, 0x29093408,
93 0x37022f06, 0x2c0a290d, 0x35053206, 0x3f04310d, 0x45fe4006, 0x46063bfe,
94 0x1f092c0a, 0x35032b0c, 0x260a220e, 0x280d34fd, 0x2c072011, 0x320d2607,
95 0x2b1a390a, 0x0e0b0b0e, 0x0b120b09, 0xfe170915, 0xf120f120, 0xe927eb22,
96 0xe129df2a, 0xf426e42e, 0xe82d1d15, 0xe630d335, 0xed2bd541, 0x091ef627,
97 0x1b141a12, 0x52f23900, 0x61ed4bfb, 0x001b7ddd, 0xfc1f001c, 0x0822061b,
98 0x16180a1e, 0x20161321, 0x29151f1a, 0x2f172c1a, 0x470e4110, 0x3f063c08,
99 0x18154111, 0x171a1417, 0x171c201b, 0x2817181c, 0x1d1c2018, 0x39132a17,
100 0x3d163516, 0x280c560b, 0x3b0e330b, 0x47f94ffc, 0x46f745fb, 0x44f642f8,
101 0x45f449ed, 0x43f146f0, 0x46ed3eec, 0x41ea42f0, 0xfe093fec, 0xf721f71a,
102 0xfe29f927, 0x0931032d, 0x3b241b2d, 0x23f942fa, 0x2df82af9, 0x38f430fb,
103 0x3efb3cfa, 0x4cf842f8, 0x51fa55fb, 0x51f94df6, 0x49ee50ef, 0x53f64afc,
104 0x43f747f7, 0x42f83dff, 0x3b0042f2, 0xf3153b02, 0xf927f221, 0x0233fe2e,
105 0x113d063c, 0x3e2a2237, 0x00000000, 0x00000000, 0x3602f114, 0xf1144a03,
106 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x19163307, 0x00100022, 0x290409fe,
107 0x410276e3, 0x4ff347fa, 0x32093405, 0x360a46fd, 0x1613221a, 0x02390028,
108 0x451a2429, 0x65f17fd3, 0x47fa4cfc, 0x34054ff3, 0x5af34506, 0x2b083400,
109 0x52fb45fe, 0x3b0260f6, 0x57fd4b02, 0x380164fd, 0x55fa4afd, 0x51fd3b00,
110 0x5ffb56f9, 0x4dff42ff, 0x56fe4601, 0x3d0048fb, 0x3f002900, 0x3f003f00,
111 0x560453f7, 0x48f96100, 0x3e03290d, 0x33070f0d, 0x7fd95002, 0x60ef5bee,
112 0x62dd51e6, 0x61e966e8, 0x63e877e5, 0x66ee6eeb, 0x50007fdc, 0x5ef959fb,
113 0x27005cfc, 0x54f14100, 0x49fe7fdd, 0x5bf768f4, 0x37037fe1, 0x37073807,
114 0x35fd3d08, 0x4af94400, 0x67f358f7, 0x59f75bf3, 0x4cf85cf2, 0x6ee957f4,
115 0x4ef669e8, 0x63ef70ec, 0x7fba7fb2, 0x7fd27fce, 0x4efb42fc, 0x48f847fc,
116 0x37ff3b02, 0x4bfa46f9, 0x77de59f8, 0x14204bfd, 0x7fd4161e, 0x3dfb3600,
117 0x3cff3a00, 0x43f83dfd, 0x4af254e7, 0x340541fb, 0x3d003902, 0x46f545f7,
118 0x47fc3712, 0x3d073a00, 0x19122909, 0x2b052009, 0x2c002f09, 0x2e023300,
119 0x42fc2613, 0x2a0c260f, 0x59002209, 0x1c0a2d04, 0xf5211f0a, 0x0f12d534,
120 0xea23001c, 0x0022e726, 0xf420ee27, 0x0000a266, 0xfc21f138, 0xfb250a1d,
121 0xf727e333, 0xc645de34, 0xfb2cc143, 0xe3370720, 0x00000120, 0xe721241b,
122 0xe424e222, 0xe526e426, 0xf023ee22, 0xf820f222, 0x0023fa25, 0x121c0a1e,
123 0x291d191a, 0x48024b00, 0x230e4d08, 0x23111f12, 0x2d111e15, 0x2d122a14,
124 0x36101a1b, 0x38104207, 0x430a490b, 0x70e974f6, 0x3df947f1, 0x42fb3500,
125 0x50f74df5, 0x57f654f7, 0x65eb7fde, 0x35fb27fd, 0x4bf53df9, 0x5bef4df1,
126 0x6fe76be7, 0x4cf57ae4, 0x34f62cf6, 0x3af739f6, 0x45f948f0, 0x4afb45fc,
127 0x420256f7, 0x200122f7, 0x34051f0b, 0x43fe37fe, 0x59f84900, 0x04073403,
128 0x0811080a, 0x25031310, 0x49fb3dff, 0x4efc46ff, 0x7eeb0000, 0x6eec7ce9,
129 0x7ce77ee6, 0x79e569ef, 0x66ef75e5, 0x74e575e6, 0x5ff67adf, 0x5ff864f2,
130 0x72e46fef, 0x50fe59fa, 0x55f752fc, 0x48ff51f8, 0x43014005, 0x45003809,
131 0x45074501, 0x43fa45f9, 0x40fe4df0, 0x43fa3d02, 0x390240fd, 0x42fd41fd,
132 0x33093e00, 0x47fe42ff, 0x46ff4bfe, 0x3c0e48f7, 0x2f002510, 0x250b2312,
133 0x290a290c, 0x290c3002, 0x3b00290d, 0x28133203, 0x32124203, 0xfa12fa13,
134 0xf41a000e, 0xe721f01f, 0xe425ea21, 0xe22ae227, 0xdc2dd62f, 0xef29de31,
135 0xb9450920, 0xc042c13f, 0xd936b64d, 0xf629dd34, 0xff280024, 0x1a1c0e1e,
136 0x370c2517, 0xdf25410b, 0xdb28dc27, 0xdf2ee226, 0xe828e22a, 0xf426e331,
137 0xfd26f628, 0x141ffb2e, 0x2c191e1d, 0x310b300c, 0x16162d1a, 0x151b1617,
138 0x1c1a1421, 0x221b181e, 0x27192a12, 0x460c3212, 0x470e3615, 0x2019530b,
139 0x36153115, 0x51fa55fb, 0x51f94df6, 0x49ee50ef, 0x53f64afc, 0x43f747f7,
140 0x42f83dff, 0x3b0042f2, 0xf6113b02, 0xf72af320, 0x0035fb31, 0x0a440340,
141 0x392f1b42, 0x180047fb, 0x2afe24ff, 0x39f734fe, 0x41fc3ffa, 0x52f943fc,
142 0x4cfd51fd, 0x4efa48f9, 0x44f248f4, 0x4cfa46fd, 0x3efb42fb, 0x3dfc3900,
143 0x36013cf7, 0xf6113a02, 0xf72af320, 0x0035fb31, 0x0a440340, 0x392f1b42,
144 0x00000000, 0x00000000, 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4,
145 0x36ff35fa, 0x101d3307, 0x000e0019, 0x3efd33f6, 0x101a63e5, 0x66e855fc,
146 0x39063905, 0x390e49ef, 0x0a142814, 0x0036001d, 0x610c2a25, 0x75ea7fe0,
147 0x55fc4afe, 0x390566e8, 0x58f25dfa, 0x37042cfa, 0x67f159f5, 0x391374eb,
148 0x54043a14, 0x3f016006, 0x6af355fb, 0x4b063f05, 0x65ff5afd, 0x4ffc3703,
149 0x61f44bfe, 0x3c0132f9, 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100,
150 0x3e03290d, 0x58f72207, 0x7fdc7fec, 0x5ff25bef, 0x56e754e7, 0x5bef59f4,
151 0x4cf27fe1, 0x5af367ee, 0x500b7fdb, 0x54024c05, 0x37fa4e05, 0x53f23d04,
152 0x4ffb7fdb, 0x5bf568f5, 0x41007fe2, 0x48004ffe, 0x38fa5cfc, 0x47f84403,
153 0x56fc62f3, 0x52fb58f4, 0x43fc48fd, 0x59f048f8, 0x3bff45f7, 0x39044205,
154 0x47fe47fc, 0x4aff3a02, 0x45ff2cfc, 0x33f93e00, 0x2afa2ffc, 0x35fa29fd,
155 0x4ef74c08, 0x340953f5, 0x5afb4300, 0x48f14301, 0x50f84bfb, 0x40eb53eb,
156 0x40e71ff3, 0x4b095ee3, 0x4af83f11, 0x1bfe23fb, 0x41035b0d, 0x4d0845f9,
157 0x3e0342f6, 0x51ec44fd, 0x07011e00, 0x4aeb17fd, 0x7ce94210, 0xee2c2511,
158 0x7feade32, 0x2a002704, 0x1d0b2207, 0x25061f08, 0x28032a07, 0x2b0d2108,
159 0x2f04240d, 0x3a023703, 0x2c083c06, 0x2a0e2c0b, 0x38043007, 0x250d3404,
160 0x3a133109, 0x2d0c300a, 0x21144500, 0xee233f08, 0xfd1ce721, 0x001b0a18,
161 0xd434f222, 0x1113e827, 0x1d24191f, 0x0f222118, 0x4916141e, 0x1f132214,
162 0x10132c1b, 0x240f240f, 0x15191c15, 0x0c1f141e, 0x2a18101b, 0x380e5d00,
163 0x261a390f, 0x73e87fe8, 0x3ef752ea, 0x3b003500, 0x59f355f2, 0x5cf55ef3,
164 0x64eb7fe3, 0x43f439f2, 0x4df647f5, 0x58f055eb, 0x62f168e9, 0x52f67fdb,
165 0x3df830f8, 0x46f942f8, 0x4ff64bf2, 0x5cf453f7, 0x4ffc6cee, 0x4bf045ea,
166 0x3a013afe, 0x53f74ef3, 0x63f351fc, 0x26fa51f3, 0x3afa3ef3, 0x49f03bfe,
167 0x56f34cf6, 0x57f653f7, 0x7fea0000, 0x78e77fe7, 0x72ed7fe5, 0x76e775e9,
168 0x71e875e6, 0x78e176e4, 0x5ef67cdb, 0x63f666f1, 0x7fce6af3, 0x39115cfb,
169 0x5ef356fb, 0x4dfe5bf4, 0x49ff4700, 0x51f94004, 0x390f4005, 0x44004301,
170 0x440143f6, 0x40024d00, 0x4efb4400, 0x3b053707, 0x360e4102, 0x3c052c0f,
171 0x4cfe4602, 0x460c56ee, 0x46f44005, 0x3805370b, 0x41024500, 0x36054afa,
172 0x4cfa3607, 0x4dfe52f5, 0x2a194dfe, 0xf710f311, 0xeb1bf411, 0xd829e225,
173 0xd130d72a, 0xd82ee027, 0xd72ecd34, 0xed2bd934, 0xc93d0b20, 0xce3ed238,
174 0xec2dbd51, 0x0f1cfe23, 0x01270122, 0x2614111e, 0x360f2d12, 0xf0244f00,
175 0xef25f225, 0x0f220120, 0x19180f1d, 0x101f1622, 0x1c1f1223, 0x1c242921,
176 0x3e152f1b, 0x1a131f12, 0x17181824, 0x1e18101b, 0x29161d1f, 0x3c102a16,
177 0x3c0e340f, 0x7bf04e03, 0x38163515, 0x21153d19, 0x3d113213, 0x4af84efd,
178 0x48f648f7, 0x47f44bee, 0x46fb3ff5, 0x48f24bef, 0x35f843f0, 0x34f73bf2,
179 0xfe0944f5, 0xfc1ff61e, 0x0721ff21, 0x17250c1f, 0x4014261f, 0x25f947f7,
180 0x31f52cf8, 0x3bf438f6, 0x43f73ff8, 0x4ff644fa, 0x4af84efd, 0x48f648f7,
181 0x47f44bee, 0x46fb3ff5, 0x48f24bef, 0x35f843f0, 0x34f73bf2, 0xfe0944f5,
182 0xfc1ff61e, 0x0721ff21, 0x17250c1f, 0x4014261f, 0x00000000, 0x00000000,
183 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x00003307,
184 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
185 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
186 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
187 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
188 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100, 0x3e03290d, 0x37010b00,
189 0x7fef4500, 0x520066f3, 0x6beb4af9, 0x7fe17fe5, 0x5fee7fe8, 0x72eb7fe5,
190 0x7bef7fe2, 0x7af073f4, 0x3ff473f5, 0x54f144fe, 0x46fd68f3, 0x5af65df8,
191 0x4aff7fe2, 0x5bf961fa, 0x38fc7fec, 0x4cf952fb, 0x5df97dea, 0x4dfd57f5,
192 0x3ffc47fb, 0x54f444fc, 0x41f93ef9, 0x38053d08, 0x400142fe, 0x4efe3d00,
193 0x34073201, 0x2c00230a, 0x2d01260b, 0x2c052e00, 0x3301111f, 0x131c3207,
194 0x3e0e2110, 0x64f16cf3, 0x5bf365f3, 0x58f65ef4, 0x56f654f0, 0x57f353f9,
195 0x46015eed, 0x4afb4800, 0x66f83b12, 0x5f0064f1, 0x48024bfc, 0x47fd4bf5,
196 0x45f32e0f, 0x41003e00, 0x48f12515, 0x36103909, 0x480c3e00, 0x090f0018,
197 0x120d1908, 0x130d090f, 0x120c250a, 0x21141d06, 0x2d041e0f, 0x3e003a01,
198 0x260c3d07, 0x270f2d0b, 0x2c0d2a0b, 0x290c2d10, 0x221e310a, 0x370a2a12,
199 0x2e113311, 0xed1a5900, 0xef1aef16, 0xec1ce71e, 0xe525e921, 0xe428e921,
200 0xf521ef26, 0xfa29f128, 0x11290126, 0x031bfa1e, 0xf025161a, 0xf826fc23,
201 0x0325fd26, 0x002a0526, 0x16271023, 0x251b300e, 0x440c3c15, 0x47fd6102,
202 0x32fb2afa, 0x3efe36fd, 0x3f013a00, 0x4aff48fe, 0x43fb5bf7, 0x27fd1bfb,
203 0x2e002cfe, 0x44f840f0, 0x4dfa4ef6, 0x5cf456f6, 0x3cf637f1, 0x41fc3efa,
204 0x4cf849f4, 0x58f750f9, 0x61f56eef, 0x4ff554ec, 0x4afc49fa, 0x60f356f3,
205 0x75ed61f5, 0x21fb4ef8, 0x35fe30fc, 0x47f33efd, 0x56f44ff6, 0x61f25af3,
206 0x5dfa0000, 0x4ff854fa, 0x47ff4200, 0x3cfe3e00, 0x4bfb3bfe, 0x3afc3efd,
207 0x4fff42f7, 0x44034700, 0x3ef92c0a, 0x280e240f, 0x1d0c1b10, 0x24142c01,
208 0x2a052012, 0x3e0a3001, 0x40092e11, 0x61f568f4, 0x58f960f0, 0x55f955f8,
209 0x58f355f7, 0x4dfd4204, 0x4cfa4cfd, 0x4cff3a0a, 0x63f953ff, 0x5f025ff2,
210 0x4afb4c00, 0x4bf54600, 0x41004401, 0x3e0349f2, 0x44ff3e04, 0x370b4bf3,
211 0x460c4005, 0x1306060f, 0x0e0c1007, 0x0b0d0d12, 0x100f0f0d, 0x170d170c,
212 0x1a0e140f, 0x28112c0e, 0x11182f11, 0x16191515, 0x1d161b1f, 0x320e2313,
213 0x3f07390a, 0x52fc4dfe, 0x45095efd, 0xdd246df4, 0xe620de24, 0xe02ce225,
214 0xf122ee22, 0xf921f128, 0x0021fb23, 0x0d210226, 0x3a0d2317, 0x001afd1d,
215 0xf91f1e16, 0xfd22f123, 0xff240322, 0x0b200522, 0x0c220523, 0x1d1e0b27,
216 0x271d1a22, 0x151f4213, 0x32191f1f, 0x70ec78ef, 0x55f572ee, 0x59f25cf1,
217 0x51f147e6, 0x440050f2, 0x38e846f2, 0x32e844e9, 0xf3174af5, 0xf128f31a,
218 0x032cf231, 0x222c062d, 0x52133621, 0x17ff4bfd, 0x2b012201, 0x37fe3600,
219 0x40013d00, 0x5cf74400, 0x61f36af2, 0x5af45af1, 0x49f658ee, 0x56f24ff7,
220 0x46f649f6, 0x42fb45f6, 0x3afb40f7, 0xf6153b02, 0xf81cf518, 0x031dff1c,
221 0x1423091d, 0x430e241d, 0x00000000, 0x00000000
222 };
223
224 MPP_RET rkv_h264d_deinit(void *hal);
rkv_ver_align(RK_U32 val)225 static RK_U32 rkv_ver_align(RK_U32 val)
226 {
227 return MPP_ALIGN(val, 16);
228 }
229
rkv_hor_align(RK_U32 val)230 static RK_U32 rkv_hor_align(RK_U32 val)
231 {
232 return MPP_ALIGN(val, 16);
233 }
234
rkv_hor_align_256_odds(RK_U32 val)235 static RK_U32 rkv_hor_align_256_odds(RK_U32 val)
236 {
237 return (MPP_ALIGN(val, 256) | 256);
238 }
239
rkv_len_align(RK_U32 val)240 static RK_U32 rkv_len_align(RK_U32 val)
241 {
242 return (2 * MPP_ALIGN(val, 16));
243 }
244
rkv_len_align_422(RK_U32 val)245 static RK_U32 rkv_len_align_422(RK_U32 val)
246 {
247 return ((5 * MPP_ALIGN(val, 16)) / 2);
248 }
249
250
prepare_spspps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)251 static MPP_RET prepare_spspps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
252 {
253 RK_S32 i = 0;
254 RK_S32 is_long_term = 0, voidx = 0;
255 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
256
257 BitputCtx_t bp;
258
259 mpp_set_bitput_ctx(&bp, data, len);
260 //!< sps syntax
261 {
262 mpp_put_bits(&bp, -1, 4); //!< seq_parameter_set_id
263 mpp_put_bits(&bp, -1, 8); //!< profile_idc
264 mpp_put_bits(&bp, -1, 1); //!< constraint_set3_flag
265 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
266 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
267 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
268 mpp_put_bits(&bp, 0, 1); //!< qpprime_y_zero_transform_bypass_flag
269 mpp_put_bits(&bp, pp->log2_max_frame_num_minus4, 4);
270 mpp_put_bits(&bp, pp->num_ref_frames, 5);
271 mpp_put_bits(&bp, pp->pic_order_cnt_type, 2);
272 mpp_put_bits(&bp, pp->log2_max_pic_order_cnt_lsb_minus4, 4);
273 mpp_put_bits(&bp, pp->delta_pic_order_always_zero_flag, 1);
274 mpp_put_bits(&bp, (pp->wFrameWidthInMbsMinus1 + 1), 9);
275 mpp_put_bits(&bp, (pp->wFrameHeightInMbsMinus1 + 1), 9);
276 mpp_put_bits(&bp, pp->frame_mbs_only_flag, 1);
277 mpp_put_bits(&bp, pp->MbaffFrameFlag, 1);
278 mpp_put_bits(&bp, pp->direct_8x8_inference_flag, 1);
279
280 mpp_put_bits(&bp, 1, 1); //!< mvc_extension_enable
281 mpp_put_bits(&bp, (pp->num_views_minus1 + 1), 2);
282 mpp_put_bits(&bp, pp->view_id[0], 10);
283 mpp_put_bits(&bp, pp->view_id[1], 10);
284 mpp_put_bits(&bp, pp->num_anchor_refs_l0[0], 1);
285 if (pp->num_anchor_refs_l0[0]) {
286 mpp_put_bits(&bp, pp->anchor_ref_l0[0][0], 10);
287 } else {
288 mpp_put_bits(&bp, 0, 10);
289 }
290 mpp_put_bits(&bp, pp->num_anchor_refs_l1[0], 1);
291 if (pp->num_anchor_refs_l1[0]) {
292 mpp_put_bits(&bp, pp->anchor_ref_l1[0][0], 10);
293 } else {
294 mpp_put_bits(&bp, 0, 10); //!< anchor_ref_l1
295 }
296 mpp_put_bits(&bp, pp->num_non_anchor_refs_l0[0], 1);
297 if (pp->num_non_anchor_refs_l0[0]) {
298 mpp_put_bits(&bp, pp->non_anchor_ref_l0[0][0], 10);
299 } else {
300 mpp_put_bits(&bp, 0, 10); //!< non_anchor_ref_l0
301 }
302 mpp_put_bits(&bp, pp->num_non_anchor_refs_l1[0], 1);
303 if (pp->num_non_anchor_refs_l1[0]) {
304 mpp_put_bits(&bp, pp->non_anchor_ref_l1[0][0], 10);
305 } else {
306 mpp_put_bits(&bp, 0, 10);//!< non_anchor_ref_l1
307 }
308 mpp_put_align(&bp, 32, 0);
309 }
310 //!< pps syntax
311 {
312 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx;
313
314 mpp_put_bits(&bp, -1, 8); //!< pps_pic_parameter_set_id
315 mpp_put_bits(&bp, -1, 5); //!< pps_seq_parameter_set_id
316 mpp_put_bits(&bp, pp->entropy_coding_mode_flag, 1);
317 mpp_put_bits(&bp, pp->pic_order_present_flag, 1);
318 mpp_put_bits(&bp, pp->num_ref_idx_l0_active_minus1, 5);
319 mpp_put_bits(&bp, pp->num_ref_idx_l1_active_minus1, 5);
320 mpp_put_bits(&bp, pp->weighted_pred_flag, 1);
321 mpp_put_bits(&bp, pp->weighted_bipred_idc, 2);
322 mpp_put_bits(&bp, pp->pic_init_qp_minus26, 7);
323 mpp_put_bits(&bp, pp->pic_init_qs_minus26, 6);
324 mpp_put_bits(&bp, pp->chroma_qp_index_offset, 5);
325 mpp_put_bits(&bp, pp->deblocking_filter_control_present_flag, 1);
326 mpp_put_bits(&bp, pp->constrained_intra_pred_flag, 1);
327 mpp_put_bits(&bp, pp->redundant_pic_cnt_present_flag, 1);
328 mpp_put_bits(&bp, pp->transform_8x8_mode_flag, 1);
329 mpp_put_bits(&bp, pp->second_chroma_qp_index_offset, 5);
330 mpp_put_bits(&bp, pp->scaleing_list_enable_flag, 1);
331 mpp_put_bits(&bp, mpp_buffer_get_fd(reg_ctx->sclst_buf), 32);
332 }
333 //!< set dpb
334 for (i = 0; i < 16; i++) {
335 is_long_term = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefFrameList[i].AssociatedFlag : 0;
336 mpp_put_bits(&bp, is_long_term, 1);
337 }
338 for (i = 0; i < 16; i++) {
339 voidx = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefPicLayerIdList[i] : 0;
340 mpp_put_bits(&bp, voidx, 1);
341 }
342 mpp_put_align(&bp, 64, 0);
343
344 return MPP_OK;
345 }
346
prepare_framerps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)347 static MPP_RET prepare_framerps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
348 {
349 RK_S32 i = 0, j = 0;
350 RK_S32 dpb_idx = 0, voidx = 0;
351 RK_S32 dpb_valid = 0, bottom_flag = 0;
352 RK_U32 max_frame_num = 0;
353 RK_U16 frame_num_wrap = 0;
354
355 BitputCtx_t bp;
356 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
357
358 mpp_set_bitput_ctx(&bp, data, len);
359
360 max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
361 for (i = 0; i < 16; i++) {
362 if ((pp->NonExistingFrameFlags >> i) & 0x01) {
363 frame_num_wrap = 0;
364 } else {
365 if (pp->RefFrameList[i].AssociatedFlag) {
366 frame_num_wrap = pp->FrameNumList[i];
367 } else {
368 frame_num_wrap = (pp->FrameNumList[i] > pp->frame_num) ?
369 (pp->FrameNumList[i] - max_frame_num) : pp->FrameNumList[i];
370 }
371 }
372
373 mpp_put_bits(&bp, frame_num_wrap, 16);
374 }
375 for (i = 0; i < 16; i++) {
376 mpp_put_bits(&bp, 0, 1);//!< NULL
377 }
378 for (i = 0; i < 16; i++) {
379 mpp_put_bits(&bp, pp->RefPicLayerIdList[i], 1); //!< voidx
380 }
381 for (i = 0; i < 32; i++) {
382 dpb_valid = (p_hal->slice_long[0].RefPicList[0][i].bPicEntry == 0xff) ? 0 : 1;
383 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].Index7Bits : 0;
384 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].AssociatedFlag : 0;
385 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
386 mpp_put_bits(&bp, dpb_idx | (dpb_valid << 4), 5); //!< dpb_idx
387 mpp_put_bits(&bp, bottom_flag, 1);
388 mpp_put_bits(&bp, voidx, 1);
389 }
390 for (j = 1; j < 3; j++) {
391 for (i = 0; i < 32; i++) {
392 dpb_valid = (p_hal->slice_long[0].RefPicList[j][i].bPicEntry == 0xff) ? 0 : 1;
393 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].Index7Bits : 0;
394 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].AssociatedFlag : 0;
395 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
396 mpp_put_bits(&bp, dpb_idx | (dpb_valid << 4), 5); //!< dpb_idx
397 mpp_put_bits(&bp, bottom_flag, 1);
398 mpp_put_bits(&bp, voidx, 1);
399 }
400 }
401 mpp_put_align(&bp, 128, 0);
402
403 return MPP_OK;
404 }
405
prepare_scanlist(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)406 static MPP_RET prepare_scanlist(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
407 {
408 RK_S32 i = 0, j = 0;
409
410 if (p_hal->pp->scaleing_list_enable_flag) {
411 BitputCtx_t bp;
412 mpp_set_bitput_ctx(&bp, data, len);
413
414 for (i = 0; i < 6; i++) { //!< 4x4, 6 lists
415 for (j = 0; j < 16; j++) {
416 mpp_put_bits(&bp, p_hal->qm->bScalingLists4x4[i][j], 8);
417 }
418
419 }
420 for (i = 0; i < 2; i++) { //!< 8x8, 2 lists
421 for (j = 0; j < 64; j++) {
422 mpp_put_bits(&bp, p_hal->qm->bScalingLists8x8[i][j], 8);
423 }
424 }
425 }
426 return MPP_OK;
427 }
428
set_registers(H264dHalCtx_t * p_hal,H264dRkvRegs_t * p_regs,HalTaskInfo * task)429 static MPP_RET set_registers(H264dHalCtx_t *p_hal, H264dRkvRegs_t *p_regs, HalTaskInfo *task)
430 {
431 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
432
433 memset(p_regs, 0, sizeof(H264dRkvRegs_t));
434 //!< set dec_mode && rlc_mode && rps_mode && slice_num
435 {
436 p_regs->sw02.dec_mode = 1; //!< h264
437 if (p_regs->sw02.rlc_mode == 1) {
438 p_regs->sw05.stream_len = 0;
439 } else {
440 p_regs->sw05.stream_len = p_hal->strm_len;
441 }
442 if (p_regs->sw02.rps_mode) { // rps_mode == 1
443 p_regs->sw43.rps_base += 0x8;
444 }
445 p_regs->sw03.slice_num_lowbits = 0x7ff;
446 p_regs->sw03.slice_num_highbit = 1;
447 }
448 //!< caculate the yuv_frame_size
449 {
450 MppFrame mframe = NULL;
451 RK_U32 hor_virstride = 0;
452 RK_U32 ver_virstride = 0;
453 RK_U32 y_virstride = 0;
454 RK_U32 yuv_virstride = 0;
455
456 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
457 hor_virstride = mpp_frame_get_hor_stride(mframe);
458 ver_virstride = mpp_frame_get_ver_stride(mframe);
459 y_virstride = hor_virstride * ver_virstride;
460
461 if (pp->chroma_format_idc == 0) { //!< Y400
462 yuv_virstride = y_virstride;
463 } else if (pp->chroma_format_idc == 1) { //!< Y420
464 yuv_virstride = y_virstride + y_virstride / 2;
465 } else if (pp->chroma_format_idc == 2) { //!< Y422
466 yuv_virstride = 2 * y_virstride;
467 }
468 p_regs->sw03.y_hor_virstride = hor_virstride / 16;
469 p_regs->sw03.uv_hor_virstride = hor_virstride / 16;
470 p_regs->sw08.y_virstride = y_virstride / 16;
471 p_regs->sw09.yuv_virstride = yuv_virstride / 16;
472 }
473 //!< set current
474 {
475 MppBuffer mbuffer = NULL;
476 p_regs->sw40.cur_poc = pp->CurrFieldOrderCnt[0];
477 p_regs->sw74.cur_poc1 = pp->CurrFieldOrderCnt[1];
478 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
479 p_regs->sw07.decout_base = mpp_buffer_get_fd(mbuffer);
480 }
481 //!< set reference
482 {
483 RK_S32 i = 0;
484 RK_S32 ref_index = -1;
485 RK_S32 near_index = -1;
486 RK_U32 sw10_24_offset = 0;
487 RK_U32 sw48_offset = 0;
488 MppBuffer mbuffer = NULL;
489
490 for (i = 0; i < 15; i++) {
491 p_regs->sw25_39[i].ref0_14_poc = (i & 1)
492 ? pp->FieldOrderCntList[i / 2][1] : pp->FieldOrderCntList[i / 2][0];
493 p_regs->sw49_63[i].ref15_29_poc = (i & 1)
494 ? pp->FieldOrderCntList[(i + 15) / 2][0] : pp->FieldOrderCntList[(i + 15) / 2][1];
495 sw10_24_offset = ((pp->RefPicFiledFlags >> i) & 0x01) |
496 ((pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01) << 0x01 |
497 ((pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01) << 0x02 |
498 ((pp->RefPicColmvUsedFlags >> i) & 0x01) << 0x03;
499 mpp_dev_set_reg_offset(p_hal->dev, 10 + i, sw10_24_offset);
500
501 if (pp->RefFrameList[i].bPicEntry != 0xff) {
502 ref_index = pp->RefFrameList[i].Index7Bits;
503 near_index = pp->RefFrameList[i].Index7Bits;
504 } else {
505 ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
506 }
507 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
508 p_regs->sw10_24[i].ref0_14_base = mpp_buffer_get_fd(mbuffer);
509 }
510 p_regs->sw72.ref30_poc = pp->FieldOrderCntList[15][0];
511 p_regs->sw73.ref31_poc = pp->FieldOrderCntList[15][1];
512 sw48_offset = ((pp->RefPicFiledFlags >> 15) & 0x01) |
513 ((pp->UsedForReferenceFlags >> 30) & 0x01) << 0x01 |
514 ((pp->UsedForReferenceFlags >> 31) & 0x01) << 0x02 |
515 ((pp->RefPicColmvUsedFlags >> 15) & 0x01) << 0x03;
516 mpp_dev_set_reg_offset(p_hal->dev, 48, sw48_offset);
517
518 if (pp->RefFrameList[15].bPicEntry != 0xff) {
519 ref_index = pp->RefFrameList[15].Index7Bits;
520 } else {
521 ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
522 }
523 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
524 p_regs->sw48.ref15_base = mpp_buffer_get_fd(mbuffer);
525 }
526 {
527 MppBuffer mbuffer = NULL;
528 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx;
529 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer);
530 p_regs->sw04.strm_rlc_base = mpp_buffer_get_fd(mbuffer);
531 p_regs->sw06.cabactbl_base = mpp_buffer_get_fd(reg_ctx->cabac_buf);
532 p_regs->sw41.rlcwrite_base = p_regs->sw04.strm_rlc_base;
533 }
534 return MPP_OK;
535 }
536 /*!
537 ***********************************************************************
538 * \brief
539 * init
540 ***********************************************************************
541 */
542 //extern "C"
rkv_h264d_init(void * hal,MppHalCfg * cfg)543 MPP_RET rkv_h264d_init(void *hal, MppHalCfg *cfg)
544 {
545 MPP_RET ret = MPP_ERR_UNKNOW;
546 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
547
548 INP_CHECK(ret, NULL == p_hal);
549
550 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dRkvRegCtx_t)));
551 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx;
552 //!< malloc buffers
553 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group,
554 ®_ctx->cabac_buf, RKV_CABAC_TAB_SIZE));
555 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group,
556 ®_ctx->errinfo_buf, RKV_ERROR_INFO_SIZE));
557 // malloc buffers
558 RK_U32 i = 0;
559 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
560 for (i = 0; i < loop; i++) {
561 reg_ctx->reg_buf[i].regs = mpp_calloc(H264dRkvRegs_t, 1);
562 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group,
563 ®_ctx->reg_buf[i].spspps, RKV_SPSPPS_SIZE));
564 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group,
565 ®_ctx->reg_buf[i].rps, RKV_RPS_SIZE));
566 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group,
567 ®_ctx->reg_buf[i].sclst, RKV_SCALING_LIST_SIZE));
568 }
569
570 if (!p_hal->fast_mode) {
571 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
572 reg_ctx->spspps_buf = reg_ctx->reg_buf[0].spspps;
573 reg_ctx->rps_buf = reg_ctx->reg_buf[0].rps;
574 reg_ctx->sclst_buf = reg_ctx->reg_buf[0].sclst;
575 }
576
577 //!< copy cabac table bytes
578 FUN_CHECK(ret = mpp_buffer_write(reg_ctx->cabac_buf, 0,
579 (void *)rkv_cabac_table, sizeof(rkv_cabac_table)));
580 mpp_buffer_sync_end(reg_ctx->cabac_buf);
581
582 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align);
583 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
584 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
585
586 (void)cfg;
587 __RETURN:
588 return MPP_OK;
589 __FAILED:
590 rkv_h264d_deinit(hal);
591
592 return ret;
593 }
594 /*!
595 ***********************************************************************
596 * \brief
597 * deinit
598 ***********************************************************************
599 */
600 //extern "C"
rkv_h264d_deinit(void * hal)601 MPP_RET rkv_h264d_deinit(void *hal)
602 {
603 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
604 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx;
605
606 RK_U32 i = 0;
607 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
608 for (i = 0; i < loop; i++) {
609 MPP_FREE(reg_ctx->reg_buf[i].regs);
610 mpp_buffer_put(reg_ctx->reg_buf[i].spspps);
611 mpp_buffer_put(reg_ctx->reg_buf[i].rps);
612 mpp_buffer_put(reg_ctx->reg_buf[i].sclst);
613 }
614 mpp_buffer_put(reg_ctx->cabac_buf);
615 mpp_buffer_put(reg_ctx->errinfo_buf);
616 MPP_FREE(p_hal->reg_ctx);
617
618 return MPP_OK;
619 }
620 /*!
621 ***********************************************************************
622 * \brief
623 * generate register
624 ***********************************************************************
625 */
626 //extern "C"
rkv_h264d_gen_regs(void * hal,HalTaskInfo * task)627 MPP_RET rkv_h264d_gen_regs(void *hal, HalTaskInfo *task)
628 {
629 MPP_RET ret = MPP_ERR_UNKNOW;
630 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
631
632 INP_CHECK(ret, NULL == p_hal);
633
634 if (task->dec.flags.parse_err ||
635 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
636 goto __RETURN;
637 }
638 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx;
639 if (p_hal->fast_mode) {
640 RK_U32 i = 0;
641 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
642 if (!reg_ctx->reg_buf[i].valid) {
643 task->dec.reg_index = i;
644 reg_ctx->spspps_buf = reg_ctx->reg_buf[i].spspps;
645 reg_ctx->rps_buf = reg_ctx->reg_buf[i].rps;
646 reg_ctx->sclst_buf = reg_ctx->reg_buf[i].sclst;
647 reg_ctx->regs = reg_ctx->reg_buf[i].regs;
648 reg_ctx->reg_buf[i].valid = 1;
649 break;
650 }
651 }
652 }
653
654 prepare_spspps(p_hal, (RK_U64 *)®_ctx->spspps, sizeof(reg_ctx->spspps));
655 prepare_framerps(p_hal, (RK_U64 *)®_ctx->rps, sizeof(reg_ctx->rps));
656 prepare_scanlist(p_hal, (RK_U64 *)®_ctx->sclst, sizeof(reg_ctx->sclst));
657 set_registers(p_hal, reg_ctx->regs, task);
658
659 //!< copy datas
660 RK_U32 i = 0;
661 for (i = 0; i < 256; i++) {
662 mpp_buffer_write(reg_ctx->spspps_buf,
663 (sizeof(reg_ctx->spspps) * i), (void *)reg_ctx->spspps,
664 sizeof(reg_ctx->spspps));
665 }
666 reg_ctx->regs->sw42.pps_base = mpp_buffer_get_fd(reg_ctx->spspps_buf);
667
668 mpp_buffer_write(reg_ctx->rps_buf, 0,
669 (void *)reg_ctx->rps, sizeof(reg_ctx->rps));
670 reg_ctx->regs->sw43.rps_base = mpp_buffer_get_fd(reg_ctx->rps_buf);
671
672 mpp_buffer_write(reg_ctx->sclst_buf, 0,
673 (void *)reg_ctx->sclst, sizeof(reg_ctx->sclst));
674 reg_ctx->regs->sw75.errorinfo_base = mpp_buffer_get_fd(reg_ctx->errinfo_buf);
675 mpp_buffer_sync_end(reg_ctx->spspps_buf);
676 mpp_buffer_sync_end(reg_ctx->rps_buf);
677 mpp_buffer_sync_end(reg_ctx->sclst_buf);
678
679 __RETURN:
680 return ret = MPP_OK;
681 }
682 /*!
683 ***********************************************************************
684 * \brief h
685 * start hard
686 ***********************************************************************
687 */
688 //extern "C"
rkv_h264d_start(void * hal,HalTaskInfo * task)689 MPP_RET rkv_h264d_start(void *hal, HalTaskInfo *task)
690 {
691 MPP_RET ret = MPP_ERR_UNKNOW;
692 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
693
694 INP_CHECK(ret, NULL == p_hal);
695
696 if (task->dec.flags.parse_err ||
697 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
698 goto __RETURN;
699 }
700
701 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx;
702 RK_U32 *p_regs = p_hal->fast_mode ?
703 (RK_U32 *)reg_ctx->reg_buf[task->dec.reg_index].regs :
704 (RK_U32 *)reg_ctx->regs;
705
706 p_regs[64] = 0;
707 p_regs[65] = 0;
708 p_regs[66] = 0;
709 p_regs[67] = 0x000000ff; // disable fpga reset
710 p_regs[44] = 0xfffffff7; // 0xffff_ffff, debug enable
711 p_regs[77] = 0xffffffff; // 0xffff_dfff, debug enable
712
713 p_regs[1] |= 0x00000061; // run hardware, enable buf_empty_en
714
715 do {
716 MppDevRegWrCfg wr_cfg;
717 MppDevRegRdCfg rd_cfg;
718 RK_U32 reg_size = DEC_RKV_REGISTERS * sizeof(RK_U32);
719
720 wr_cfg.reg = p_regs;
721 wr_cfg.size = reg_size;
722 wr_cfg.offset = 0;
723
724 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_WR, &wr_cfg);
725 if (ret) {
726 mpp_err_f("set register write failed %d\n", ret);
727 break;
728 }
729
730 rd_cfg.reg = p_regs;
731 rd_cfg.size = reg_size;
732 rd_cfg.offset = 0;
733
734 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg);
735 if (ret) {
736 mpp_err_f("set register read failed %d\n", ret);
737 break;
738 }
739
740 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_SEND, NULL);
741 if (ret) {
742 mpp_err_f("send cmd failed %d\n", ret);
743 break;
744 }
745 } while (0);
746
747 (void)task;
748 __RETURN:
749 return ret = MPP_OK;
750 }
751 /*!
752 ***********************************************************************
753 * \brief
754 * wait hard
755 ***********************************************************************
756 */
757 //extern "C"
rkv_h264d_wait(void * hal,HalTaskInfo * task)758 MPP_RET rkv_h264d_wait(void *hal, HalTaskInfo *task)
759 {
760 MPP_RET ret = MPP_ERR_UNKNOW;
761 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
762
763 INP_CHECK(ret, NULL == p_hal);
764 H264dRkvRegCtx_t *reg_ctx = (H264dRkvRegCtx_t *)p_hal->reg_ctx;
765 H264dRkvRegs_t *p_regs = p_hal->fast_mode ?
766 reg_ctx->reg_buf[task->dec.reg_index].regs :
767 reg_ctx->regs;
768
769 if (task->dec.flags.parse_err ||
770 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
771 goto __SKIP_HARD;
772 }
773
774 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
775 if (ret)
776 mpp_err_f("poll cmd failed %d\n", ret);
777
778 __SKIP_HARD:
779 if (p_hal->dec_cb) {
780 DecCbHalDone param;
781
782 param.task = (void *)&task->dec;
783 param.regs = (RK_U32 *)p_regs;
784
785 if (p_regs->sw01.dec_error_sta
786 || (!p_regs->sw01.dec_rdy_sta)
787 || p_regs->sw01.dec_empty_sta
788 || p_regs->sw45.strmd_error_status
789 || p_regs->sw45.colmv_error_ref_picidx
790 || p_regs->sw76.strmd_detect_error_flag)
791 param.hard_err = 1;
792 else
793 param.hard_err = 0;
794
795 mpp_callback(p_hal->dec_cb, ¶m);
796 }
797 memset(&p_regs->sw01, 0, sizeof(RK_U32));
798 if (p_hal->fast_mode) {
799 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
800 }
801
802 (void)task;
803 __RETURN:
804 return ret = MPP_OK;
805 }
806 /*!
807 ***********************************************************************
808 * \brief
809 * reset
810 ***********************************************************************
811 */
812 //extern "C"
rkv_h264d_reset(void * hal)813 MPP_RET rkv_h264d_reset(void *hal)
814 {
815 MPP_RET ret = MPP_ERR_UNKNOW;
816 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
817
818 INP_CHECK(ret, NULL == p_hal);
819
820
821 __RETURN:
822 return ret = MPP_OK;
823 }
824 /*!
825 ***********************************************************************
826 * \brief
827 * flush
828 ***********************************************************************
829 */
830 //extern "C"
rkv_h264d_flush(void * hal)831 MPP_RET rkv_h264d_flush(void *hal)
832 {
833 MPP_RET ret = MPP_ERR_UNKNOW;
834 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
835
836 INP_CHECK(ret, NULL == p_hal);
837
838 __RETURN:
839 return ret = MPP_OK;
840 }
841 /*!
842 ***********************************************************************
843 * \brief
844 * control
845 ***********************************************************************
846 */
847 //extern "C"
rkv_h264d_control(void * hal,MpiCmd cmd_type,void * param)848 MPP_RET rkv_h264d_control(void *hal, MpiCmd cmd_type, void *param)
849 {
850 MPP_RET ret = MPP_ERR_UNKNOW;
851 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
852
853 INP_CHECK(ret, NULL == p_hal);
854
855 switch ((MpiCmd)cmd_type) {
856 case MPP_DEC_SET_FRAME_INFO: {
857 MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
858 RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
859 RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
860
861 mpp_log("control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
862 if (fmt == MPP_FMT_YUV422SP) {
863 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
864 }
865 if (imgwidth > 1920 || imgheight > 1088) {
866 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align_256_odds);
867 }
868 break;
869 }
870
871 default:
872 break;
873 }
874
875 __RETURN:
876 return ret = MPP_OK;
877 }
878
879 const MppHalApi hal_h264d_rkvdpu = {
880 .name = "h264d_rkvdpu",
881 .type = MPP_CTX_DEC,
882 .coding = MPP_VIDEO_CodingAVC,
883 .ctx_size = sizeof(H264dRkvRegCtx_t),
884 .flag = 0,
885 .init = rkv_h264d_init,
886 .deinit = rkv_h264d_deinit,
887 .reg_gen = rkv_h264d_gen_regs,
888 .start = rkv_h264d_start,
889 .wait = rkv_h264d_wait,
890 .reset = rkv_h264d_reset,
891 .flush = rkv_h264d_flush,
892 .control = rkv_h264d_control,
893 };
894