1 /*
2 * Copyright 2022 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_avs2d_vdpu382"
18
19 #include <string.h>
20 #include <stdio.h>
21
22 #include "mpp_log.h"
23 #include "mpp_mem.h"
24 #include "mpp_common.h"
25 #include "mpp_debug.h"
26 #include "mpp_bitput.h"
27
28 #include "avs2d_syntax.h"
29 #include "hal_avs2d_api.h"
30 #include "hal_avs2d_vdpu382.h"
31 #include "mpp_dec_cb_param.h"
32 #include "vdpu382_avs2d.h"
33 #include "rk_hdr_meta_com.h"
34
35 #define VDPU382_FAST_REG_SET_CNT (3)
36 #define MAX_REF_NUM (8)
37 #define AVS2_RKV_SHPH_SIZE (1408 / 8) /* bytes */
38 #define AVS2_RKV_SCALIST_SIZE (80 + 128) /* bytes */
39 #define VDPU382_TOTAL_REG_CNT (278)
40
41 #define AVS2_RKV_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SHPH_SIZE, SZ_4K))
42 #define AVS2_RKV_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SCALIST_SIZE, SZ_4K))
43 #define AVS2_RKV_STREAM_INFO_SET_SIZE (AVS2_RKV_SHPH_ALIGNED_SIZE + \
44 AVS2_RKV_SCALIST_ALIGNED_SIZE)
45 #define AVS2_ALL_TBL_BUF_SIZE(cnt) (AVS2_RKV_STREAM_INFO_SET_SIZE * (cnt))
46 #define AVS2_SHPH_OFFSET(pos) (AVS2_RKV_STREAM_INFO_SET_SIZE * (pos))
47 #define AVS2_SCALIST_OFFSET(pos) (AVS2_SHPH_OFFSET(pos) + AVS2_RKV_SHPH_ALIGNED_SIZE)
48
49 #define COLMV_COMPRESS_EN (1)
50 #define COLMV_BLOCK_SIZE (16)
51 #define COLMV_BYTES (16)
52
53 typedef struct avs2d_buf_t {
54 RK_U32 valid;
55 RK_U32 offset_shph;
56 RK_U32 offset_sclst;
57 Vdpu382Avs2dRegSet *regs;
58 } Avs2dVdpu382Buf_t;
59
60 typedef struct avs2d_reg_ctx_t {
61 Avs2dVdpu382Buf_t reg_buf[VDPU382_FAST_REG_SET_CNT];
62
63 RK_U32 shph_offset;
64 RK_U32 sclst_offset;
65
66 Vdpu382Avs2dRegSet *regs;
67
68 RK_U8 shph_dat[AVS2_RKV_SHPH_SIZE];
69 RK_U8 scalist_dat[AVS2_RKV_SCALIST_SIZE];
70
71 MppBuffer bufs;
72 RK_S32 bufs_fd;
73 void *bufs_ptr;
74
75 MppBuffer rcb_buf[VDPU382_FAST_REG_SET_CNT];
76 RK_S32 rcb_buf_size;
77 Vdpu382RcbInfo rcb_info[RCB_BUF_COUNT];
78 RK_U32 reg_out[VDPU382_TOTAL_REG_CNT];
79
80 } Avs2dVdpu382RegCtx_t;
81
avs2d_ver_align(RK_U32 val)82 static RK_U32 avs2d_ver_align(RK_U32 val)
83 {
84 return MPP_ALIGN(val, 16);
85 }
86
avs2d_hor_align(RK_U32 val)87 static RK_U32 avs2d_hor_align(RK_U32 val)
88 {
89
90 return MPP_ALIGN(val, 16);
91 }
92
avs2d_len_align(RK_U32 val)93 static RK_U32 avs2d_len_align(RK_U32 val)
94 {
95 return (2 * MPP_ALIGN(val, 16));
96 }
97
avs2d_hor_align_64(RK_U32 val)98 static RK_U32 avs2d_hor_align_64(RK_U32 val)
99 {
100 return MPP_ALIGN(val, 64);
101 }
102
prepare_header(Avs2dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)103 static MPP_RET prepare_header(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
104 {
105 RK_U32 i, j;
106 BitputCtx_t bp;
107 RK_U64 *bit_buf = (RK_U64 *)data;
108 Avs2dSyntax_t *syntax = &p_hal->syntax;
109 PicParams_Avs2d *pp = &syntax->pp;
110 AlfParams_Avs2d *alfp = &syntax->alfp;
111 RefParams_Avs2d *refp = &syntax->refp;
112 WqmParams_Avs2d *wqmp = &syntax->wqmp;
113
114 memset(data, 0, len);
115
116 mpp_set_bitput_ctx(&bp, bit_buf, len);
117 //!< sequence header syntax
118 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
119 mpp_put_bits(&bp, pp->pic_width_in_luma_samples, 16);
120 mpp_put_bits(&bp, pp->pic_height_in_luma_samples, 16);
121 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
122 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
123 mpp_put_bits(&bp, pp->lcu_size, 3);
124 mpp_put_bits(&bp, pp->progressive_sequence, 1);
125 mpp_put_bits(&bp, pp->field_coded_sequence, 1);
126 mpp_put_bits(&bp, pp->multi_hypothesis_skip_enable_flag, 1);
127 mpp_put_bits(&bp, pp->dual_hypothesis_prediction_enable_flag, 1);
128 mpp_put_bits(&bp, pp->weighted_skip_enable_flag, 1);
129 mpp_put_bits(&bp, pp->asymmetrc_motion_partitions_enable_flag, 1);
130 mpp_put_bits(&bp, pp->nonsquare_quadtree_transform_enable_flag, 1);
131 mpp_put_bits(&bp, pp->nonsquare_intra_prediction_enable_flag, 1);
132 mpp_put_bits(&bp, pp->secondary_transform_enable_flag, 1);
133 mpp_put_bits(&bp, pp->sample_adaptive_offset_enable_flag, 1);
134 mpp_put_bits(&bp, pp->adaptive_loop_filter_enable_flag, 1);
135 mpp_put_bits(&bp, pp->pmvr_enable_flag, 1);
136 mpp_put_bits(&bp, pp->cross_slice_loopfilter_enable_flag, 1);
137 //!< picture header syntax
138 mpp_put_bits(&bp, pp->picture_type, 3);
139 mpp_put_bits(&bp, refp->ref_pic_num, 3);
140 mpp_put_bits(&bp, pp->scene_reference_enable_flag, 1);
141 mpp_put_bits(&bp, pp->bottom_field_picture_flag, 1);
142 mpp_put_bits(&bp, pp->fixed_picture_qp, 1);
143 mpp_put_bits(&bp, pp->picture_qp, 7);
144 mpp_put_bits(&bp, pp->loop_filter_disable_flag, 1);
145 mpp_put_bits(&bp, pp->alpha_c_offset, 5);
146 mpp_put_bits(&bp, pp->beta_offset, 5);
147 //!< weight quant param
148 mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cb, 6);
149 mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cr, 6);
150 mpp_put_bits(&bp, wqmp->pic_weight_quant_enable_flag, 1);
151 //!< alf param
152 mpp_put_bits(&bp, alfp->enable_pic_alf_y, 1);
153 mpp_put_bits(&bp, alfp->enable_pic_alf_cb, 1);
154 mpp_put_bits(&bp, alfp->enable_pic_alf_cr, 1);
155
156 if (alfp->enable_pic_alf_y) {
157 RK_U32 alf_filter_num = alfp->alf_filter_num_minus1 + 1;
158 mpp_put_bits(&bp, alfp->alf_filter_num_minus1, 4);
159
160 for (i = 0; i < 16; i++)
161 mpp_put_bits(&bp, alfp->alf_coeff_idx_tab[i], 4);
162
163 for (i = 0; i < alf_filter_num; i++) {
164 for (j = 0; j < 9; j++) {
165 mpp_put_bits(&bp, alfp->alf_coeff_y[i][j], 7);
166 }
167 }
168 }
169
170 if (alfp->enable_pic_alf_cb) {
171 for (j = 0; j < 9; j++)
172 mpp_put_bits(&bp, alfp->alf_coeff_cb[j], 7);
173 }
174
175 if (alfp->enable_pic_alf_cr) {
176 for (j = 0; j < 9; j++)
177 mpp_put_bits(&bp, alfp->alf_coeff_cr[j], 7);
178 }
179
180 mpp_put_align(&bp, 128, 0);
181
182 return MPP_OK;
183 }
184
prepare_scalist(Avs2dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)185 static MPP_RET prepare_scalist(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
186 {
187 RK_U32 i, j;
188 RK_U32 size_id, block_size;
189 BitputCtx_t bp;
190 RK_U64 *bit_buf = (RK_U64 *)data;
191 Avs2dSyntax_t *syntax = &p_hal->syntax;
192 WqmParams_Avs2d *wqmp = &syntax->wqmp;
193
194 if (!wqmp->pic_weight_quant_enable_flag)
195 return MPP_OK;
196
197 memset(data, 0, len);
198
199 mpp_set_bitput_ctx(&bp, bit_buf, len);
200
201 for (size_id = 0; size_id < 2; size_id++) {
202 block_size = MPP_MIN(1 << (size_id + 2), 8);
203 for (i = 0; i < block_size; i++) {
204 for (j = 0 ; j < block_size; j++)
205 //!< row col reversed
206 mpp_put_bits(&bp, wqmp->wq_matrix[size_id][size_id * j + i], 8);
207 }
208 }
209
210 return MPP_OK;
211 }
212
get_frame_fd(Avs2dHalCtx_t * p_hal,RK_S32 idx)213 static RK_S32 get_frame_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
214 {
215 RK_S32 ret_fd = 0;
216 MppBuffer mbuffer = NULL;
217
218 mpp_buf_slot_get_prop(p_hal->frame_slots, idx, SLOT_BUFFER, &mbuffer);
219 ret_fd = mpp_buffer_get_fd(mbuffer);
220
221 return ret_fd;
222 }
223
get_packet_fd(Avs2dHalCtx_t * p_hal,RK_S32 idx)224 static RK_S32 get_packet_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
225 {
226 RK_S32 ret_fd = 0;
227 MppBuffer mbuffer = NULL;
228
229 mpp_buf_slot_get_prop(p_hal->packet_slots, idx, SLOT_BUFFER, &mbuffer);
230 ret_fd = mpp_buffer_get_fd(mbuffer);
231
232 return ret_fd;
233 }
234
init_common_regs(Vdpu382Avs2dRegSet * regs)235 static MPP_RET init_common_regs(Vdpu382Avs2dRegSet *regs)
236 {
237 Vdpu382RegCommon *common = ®s->common;
238
239 common->reg009.dec_mode = 3; // AVS2
240 common->reg015.rlc_mode = 0;
241
242 common->reg011.buf_empty_en = 1;
243 common->reg011.err_head_fill_e = 1;
244 common->reg011.err_colmv_fill_e = 1;
245
246 common->reg010.dec_e = 1;
247
248 common->reg013.h26x_error_mode = 0;
249 common->reg021.inter_error_prc_mode = 0;
250 common->reg021.error_deb_en = 0;
251 common->reg021.error_intra_mode = 0;
252
253 common->reg024.cabac_err_en_lowbits = 0xffffffdf;
254 common->reg025.cabac_err_en_highbits = 0x3dffffff;
255
256 common->reg026.inter_auto_gating_e = 1;
257 common->reg026.filterd_auto_gating_e = 1;
258 common->reg026.strmd_auto_gating_e = 1;
259 common->reg026.mcp_auto_gating_e = 1;
260 common->reg026.busifd_auto_gating_e = 1;
261 common->reg026.dec_ctrl_auto_gating_e = 1;
262 common->reg026.intra_auto_gating_e = 1;
263 common->reg026.mc_auto_gating_e = 1;
264 common->reg026.transd_auto_gating_e = 1;
265 common->reg026.sram_auto_gating_e = 1;
266 common->reg026.cru_auto_gating_e = 1;
267 common->reg026.reg_cfg_gating_en = 1;
268
269 common->reg032_timeout_threshold = 0x0fffffff;
270
271 common->reg011.dec_clkgate_e = 1;
272
273 common->reg013.stmerror_waitdecfifo_empty = 1;
274 common->reg012.colmv_compress_en = COLMV_COMPRESS_EN;
275 common->reg012.info_collect_en = 1;
276 common->reg012.error_info_en = 0;
277
278 return MPP_OK;
279 }
280
avs2d_refine_rcb_size(Vdpu382RcbInfo * rcb_info,Vdpu382Avs2dRegSet * hw_regs,RK_S32 width,RK_S32 height,void * dxva)281 static void avs2d_refine_rcb_size(Vdpu382RcbInfo *rcb_info,
282 Vdpu382Avs2dRegSet *hw_regs,
283 RK_S32 width, RK_S32 height, void *dxva)
284 {
285 (void) height;
286 Avs2dSyntax_t *syntax = dxva;
287 RK_U8 ctu_size = 1 << syntax->pp.lcu_size;
288 RK_U32 chroma_fmt_idc = syntax->pp.chroma_format_idc;
289 RK_U8 bit_depth = syntax->pp.bit_depth_chroma_minus8 + 8;
290 RK_U32 rcb_bits = 0;
291
292 width = MPP_ALIGN(width, ctu_size);
293
294 /* RCB_STRMD_ROW */
295 if (width >= 8192) {
296 RK_U32 factor = 64 / ctu_size;
297
298 rcb_bits = (MPP_ALIGN(width, ctu_size) + factor - 1) / factor * 24;
299 } else
300 rcb_bits = 0;
301 rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
302
303 /* RCB_TRANSD_ROW */
304 if (width >= 8192)
305 rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1);
306 else
307 rcb_bits = 0;
308 rcb_info[RCB_TRANSD_ROW].size = MPP_RCB_BYTES(rcb_bits);
309
310 /* RCB_TRANSD_COL */
311 rcb_info[RCB_TRANSD_COL].size = 0;
312
313 /* RCB_INTER_ROW */
314 rcb_bits = width * 21;
315 rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
316
317 /* RCB_INTER_COL */
318 rcb_info[RCB_INTER_COL].size = 0;
319
320 /* RCB_INTRA_ROW */
321 rcb_bits = width * ((chroma_fmt_idc ? 1 : 0) + 1) * 11;
322 rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
323
324 /* RCB_DBLK_ROW */
325 if (chroma_fmt_idc == 1 ) {
326 if (ctu_size == 32)
327 rcb_bits = width * ( 4 + 8 * bit_depth);
328 else
329 rcb_bits = width * ( 2 + 8 * bit_depth);
330 } else
331 rcb_bits = 0;
332 rcb_info[RCB_DBLK_ROW].size = MPP_RCB_BYTES(rcb_bits);
333
334 /* RCB_SAO_ROW */
335 if (chroma_fmt_idc == 1 || chroma_fmt_idc == 2) {
336 rcb_bits = width * (128 / ctu_size + 2 * bit_depth);
337 } else {
338 rcb_bits = width * (128 / ctu_size + 3 * bit_depth);
339 }
340 rcb_info[RCB_SAO_ROW].size = MPP_RCB_BYTES(rcb_bits);
341
342 /* RCB_FBC_ROW */
343 if (hw_regs->common.reg012.fbc_e)
344 rcb_bits = width * 4 * bit_depth;
345 else
346 rcb_bits = 0;
347 rcb_info[RCB_FBC_ROW].size = MPP_RCB_BYTES(rcb_bits);
348
349 /* RCB_FILT_COL */
350 rcb_info[RCB_FILT_COL].size = 0;
351 return;
352 }
353
hal_avs2d_rcb_info_update(void * hal,Vdpu382Avs2dRegSet * hw_regs)354 static void hal_avs2d_rcb_info_update(void *hal, Vdpu382Avs2dRegSet *hw_regs)
355 {
356 MPP_RET ret = MPP_OK;
357 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
358 Avs2dVdpu382RegCtx_t *reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
359 RK_S32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
360 RK_S32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
361 RK_S32 i = 0;
362 RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
363
364 reg_ctx->rcb_buf_size = vdpu382_get_rcb_buf_size(reg_ctx->rcb_info, width, height);
365 avs2d_refine_rcb_size(reg_ctx->rcb_info, hw_regs, width, height, (void *)&p_hal->syntax);
366
367 for (i = 0; i < loop; i++) {
368 MppBuffer rcb_buf = NULL;
369
370 if (reg_ctx->rcb_buf[i]) {
371 mpp_buffer_put(reg_ctx->rcb_buf[i]);
372 reg_ctx->rcb_buf[i] = NULL;
373 }
374
375 ret = mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size);
376
377 if (ret)
378 mpp_err_f("AVS2D mpp_buffer_group_get failed\n");
379
380 reg_ctx->rcb_buf[i] = rcb_buf;
381 }
382 }
383
fill_registers(Avs2dHalCtx_t * p_hal,Vdpu382Avs2dRegSet * p_regs,HalTaskInfo * task)384 static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu382Avs2dRegSet *p_regs, HalTaskInfo *task)
385 {
386 MPP_RET ret = MPP_OK;
387 RK_U32 i;
388 MppFrame mframe = NULL;
389 Avs2dSyntax_t *syntax = &p_hal->syntax;
390 PicParams_Avs2d *pp = &syntax->pp;
391 RefParams_Avs2d *refp = &syntax->refp;
392 HalDecTask *task_dec = &task->dec;
393 Vdpu382RegCommon *common = &p_regs->common;
394 RK_U32 is_fbc = 0;
395 HalBuf *mv_buf = NULL;
396
397 mpp_buf_slot_get_prop(p_hal->frame_slots, task_dec->output, SLOT_FRAME_PTR, &mframe);
398 is_fbc = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
399
400 //!< caculate the yuv_frame_size
401 {
402 RK_U32 hor_virstride = 0;
403 RK_U32 ver_virstride = 0;
404 RK_U32 y_virstride = 0;
405
406 hor_virstride = mpp_frame_get_hor_stride(mframe);
407 ver_virstride = mpp_frame_get_ver_stride(mframe);
408 y_virstride = hor_virstride * ver_virstride;
409 AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride);
410
411 if (is_fbc) {
412 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
413 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
414
415 common->reg012.fbc_e = 1;
416 common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
417 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
418 common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
419 } else {
420 common->reg012.fbc_e = 0;
421 common->reg018.y_hor_virstride = hor_virstride / 16;
422 common->reg019.uv_hor_virstride = hor_virstride / 16;
423 common->reg020_y_virstride.y_virstride = y_virstride / 16;
424 }
425 common->reg013.cur_pic_is_idr = (pp->picture_type == 0 || pp->picture_type == 4 || pp->picture_type == 5);
426 }
427
428 // set current
429 {
430 RK_S32 fd = -1;
431 p_regs->avs2d_param.reg65_cur_top_poc = mpp_frame_get_poc(mframe);
432 p_regs->avs2d_param.reg66_cur_bot_poc = 0;
433 fd = get_frame_fd(p_hal, task_dec->output);
434 mpp_assert(fd >= 0);
435 p_regs->common_addr.reg130_decout_base = fd;
436 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, task_dec->output);
437 p_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
438 AVS2D_HAL_TRACE("cur frame index %d, fd %d, colmv fd %d", task_dec->output, fd, p_regs->common_addr.reg131_colmv_cur_base);
439 }
440
441 // set reference
442 {
443 RK_U64 ref_flag = 0;
444 RK_S32 valid_slot = -1;
445 RK_U32 *ref_low = (RK_U32 *)&p_regs->avs2d_param.reg99;
446 RK_U32 *ref_hight = (RK_U32 *)&p_regs->avs2d_param.reg100;
447
448 AVS2D_HAL_TRACE("num of ref %d", refp->ref_pic_num);
449
450 for (i = 0; i < refp->ref_pic_num; i++) {
451 if (task_dec->refer[i] < 0)
452 continue;
453
454 valid_slot = i;
455 break;
456 }
457
458 for (i = 0; i < refp->ref_pic_num; i++) {
459 MppFrame frame_ref = NULL;
460
461 RK_S32 slot_idx = task_dec->refer[i] < 0 ? valid_slot : task_dec->refer[i];
462
463 if (slot_idx < 0) {
464 AVS2D_HAL_TRACE("missing ref, could not found valid ref");
465 return ret = MPP_ERR_UNKNOW;
466 }
467
468 mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &frame_ref);
469
470 if (frame_ref) {
471 RK_U32 frm_flag = 1 << 3;
472
473 if (pp->bottom_field_picture_flag)
474 frm_flag |= 1 << 2;
475
476 if (pp->field_coded_sequence)
477 frm_flag |= 1;
478
479 ref_flag |= frm_flag << (i * 8);
480
481 p_regs->avs2d_addr.ref_base[i] = get_frame_fd(p_hal, slot_idx);
482 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
483 p_regs->avs2d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
484
485 p_regs->avs2d_param.reg67_098_ref_poc[i] = mpp_frame_get_poc(frame_ref);
486
487 AVS2D_HAL_TRACE("ref_base[%d] index=%d, fd = %d, colmv %d, poc %d",
488 i, slot_idx, p_regs->avs2d_addr.ref_base[i],
489 p_regs->avs2d_addr.colmv_base[i], p_regs->avs2d_param.reg67_098_ref_poc[i]);
490 }
491 }
492
493 if (p_hal->syntax.refp.scene_ref_enable && p_hal->syntax.refp.scene_ref_slot_idx >= 0) {
494 MppFrame scene_ref = NULL;
495 RK_S32 replace_idx = p_hal->syntax.refp.scene_ref_replace_pos;
496 RK_S32 slot_idx = p_hal->syntax.refp.scene_ref_slot_idx;
497
498 mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &scene_ref);
499
500 if (scene_ref) {
501 p_regs->avs2d_addr.ref_base[replace_idx] = get_frame_fd(p_hal, slot_idx);
502 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
503 p_regs->avs2d_addr.colmv_base[replace_idx] = mpp_buffer_get_fd(mv_buf->buf[0]);
504 p_regs->avs2d_param.reg67_098_ref_poc[replace_idx] = mpp_frame_get_poc(scene_ref);
505 }
506 }
507
508 *ref_low = (RK_U32) (ref_flag & 0xffffffff);
509 *ref_hight = (RK_U32) ((ref_flag >> 32) & 0xffffffff);
510
511 p_regs->common_addr.reg132_error_ref_base = p_regs->avs2d_addr.ref_base[0];
512 }
513
514 // set rlc
515 {
516 p_regs->common_addr.reg128_rlc_base = get_packet_fd(p_hal, task_dec->input);
517 AVS2D_HAL_TRACE("packet fd %d from slot %d", p_regs->common_addr.reg128_rlc_base, task_dec->input);
518 p_regs->common_addr.reg129_rlcwrite_base = p_regs->common_addr.reg128_rlc_base;
519 common->reg016_str_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64;
520 }
521
522 if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) && p_hal->cfg->base.enable_hdr_meta)
523 fill_hdr_meta_to_frame(mframe, HDR_AVS2);
524
525 /* set scale down info */
526 if (mpp_frame_get_thumbnail_en(mframe)) {
527 p_regs->avs2d_addr.scale_down_luma_base = p_regs->common_addr.reg130_decout_base;
528 p_regs->avs2d_addr.scale_down_chorme_base = p_regs->common_addr.reg130_decout_base;
529 vdpu382_setup_down_scale(mframe, p_hal->dev, &p_regs->common);
530 } else {
531 p_regs->avs2d_addr.scale_down_luma_base = 0;
532 p_regs->avs2d_addr.scale_down_chorme_base = 0;
533 p_regs->common.reg012.scale_down_en = 0;
534 }
535
536 return ret;
537 }
538
hal_avs2d_vdpu382_deinit(void * hal)539 MPP_RET hal_avs2d_vdpu382_deinit(void *hal)
540 {
541 MPP_RET ret = MPP_OK;
542 RK_U32 i, loop;
543 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
544 Avs2dVdpu382RegCtx_t *reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
545
546 AVS2D_HAL_TRACE("In.");
547
548 INP_CHECK(ret, NULL == reg_ctx);
549
550 //!< malloc buffers
551 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
552 for (i = 0; i < loop; i++) {
553 if (reg_ctx->rcb_buf[i]) {
554 mpp_buffer_put(reg_ctx->rcb_buf[i]);
555 reg_ctx->rcb_buf[i] = NULL;
556 }
557
558 MPP_FREE(reg_ctx->reg_buf[i].regs);
559 }
560
561 if (reg_ctx->bufs) {
562 mpp_buffer_put(reg_ctx->bufs);
563 reg_ctx->bufs = NULL;
564 }
565
566 if (p_hal->cmv_bufs) {
567 hal_bufs_deinit(p_hal->cmv_bufs);
568 p_hal->cmv_bufs = NULL;
569 }
570
571 MPP_FREE(p_hal->reg_ctx);
572
573 __RETURN:
574 AVS2D_HAL_TRACE("Out. ret %d", ret);
575 return ret;
576 }
577
hal_avs2d_vdpu382_init(void * hal,MppHalCfg * cfg)578 MPP_RET hal_avs2d_vdpu382_init(void *hal, MppHalCfg *cfg)
579 {
580 MPP_RET ret = MPP_OK;
581 RK_U32 i, loop;
582 Avs2dVdpu382RegCtx_t *reg_ctx;
583 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
584
585 AVS2D_HAL_TRACE("In.");
586
587 INP_CHECK(ret, NULL == p_hal);
588
589 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Avs2dVdpu382RegCtx_t)));
590 reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
591
592 //!< malloc buffers
593 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
594 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs, AVS2_ALL_TBL_BUF_SIZE(loop)));
595 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
596 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
597
598 for (i = 0; i < loop; i++) {
599 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu382Avs2dRegSet, 1);
600 init_common_regs(reg_ctx->reg_buf[i].regs);
601 reg_ctx->reg_buf[i].offset_shph = AVS2_SHPH_OFFSET(i);
602 reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i);
603 }
604
605 if (!p_hal->fast_mode) {
606 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
607 reg_ctx->shph_offset = reg_ctx->reg_buf[0].offset_shph;
608 reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst;
609 }
610
611 if (MPP_FRAME_FMT_IS_FBC(cfg->cfg->base.out_fmt))
612 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align_64);
613 else
614 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
615
616 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
617 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
618 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
619
620 {
621 // report hw_info to parser
622 const MppSocInfo *info = mpp_get_soc_info();
623 const void *hw_info = NULL;
624
625 for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
626 if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
627 hw_info = info->dec_caps[i];
628 break;
629 }
630 }
631
632 mpp_assert(hw_info);
633 cfg->hw_info = hw_info;
634 p_hal->hw_info = hw_info;
635 }
636
637 __RETURN:
638 AVS2D_HAL_TRACE("Out. ret %d", ret);
639 (void)cfg;
640 return ret;
641 __FAILED:
642 hal_avs2d_vdpu382_deinit(p_hal);
643 AVS2D_HAL_TRACE("Out. ret %d", ret);
644 return ret;
645 }
646
set_up_colmv_buf(void * hal)647 static MPP_RET set_up_colmv_buf(void *hal)
648 {
649 MPP_RET ret = MPP_OK;
650 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
651 Avs2dSyntax_t *syntax = &p_hal->syntax;
652 PicParams_Avs2d *pp = &syntax->pp;
653 RK_U32 mv_size = 0;
654
655 RK_U32 ctu_size = 1 << (p_hal->syntax.pp.lcu_size);
656 RK_U32 segment_w = 64 * COLMV_BLOCK_SIZE * COLMV_BLOCK_SIZE / ctu_size;
657 RK_U32 segment_h = ctu_size;
658 RK_U32 pic_w_align = MPP_ALIGN(pp->pic_width_in_luma_samples, segment_w);
659 RK_U32 pic_h_align = MPP_ALIGN(pp->pic_height_in_luma_samples, segment_h);
660 RK_U32 seg_cnt_w = pic_w_align / segment_w;
661 RK_U32 seg_cnt_h = pic_h_align / segment_h;
662 RK_U32 seg_head_line_size = MPP_ALIGN(seg_cnt_w, 16);
663 RK_U32 seg_head_size = seg_head_line_size * seg_cnt_h;
664 RK_U32 seg_payload_size = seg_cnt_w * seg_cnt_h * 64 * COLMV_BYTES;
665
666 if (COLMV_COMPRESS_EN)
667 mv_size = seg_payload_size + seg_head_size;
668 else
669 mv_size = (MPP_ALIGN(p_hal->syntax.pp.pic_width_in_luma_samples, 64) *
670 MPP_ALIGN(p_hal->syntax.pp.pic_height_in_luma_samples, 64)) >> 5;
671
672 // colmv frame size align to 128byte
673 if ((mv_size / 8) % 2 == 1) {
674 mv_size += 8;
675 }
676
677 if (pp->field_coded_sequence)
678 mv_size *= 2;
679 AVS2D_HAL_TRACE("mv_size %d", mv_size);
680
681 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
682 size_t size = mv_size;
683
684 if (p_hal->cmv_bufs) {
685 hal_bufs_deinit(p_hal->cmv_bufs);
686 p_hal->cmv_bufs = NULL;
687 }
688
689 hal_bufs_init(&p_hal->cmv_bufs);
690 if (p_hal->cmv_bufs == NULL) {
691 mpp_err_f("colmv bufs init fail");
692 ret = MPP_ERR_INIT;
693 goto __RETURN;
694 }
695
696 p_hal->mv_size = mv_size;
697 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
698 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
699 }
700
701 __RETURN:
702 return ret;
703 }
704
hal_avs2d_vdpu382_gen_regs(void * hal,HalTaskInfo * task)705 MPP_RET hal_avs2d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
706 {
707 MPP_RET ret = MPP_OK;
708 Avs2dVdpu382RegCtx_t *reg_ctx;
709 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
710 Vdpu382Avs2dRegSet *regs = NULL;
711
712 AVS2D_HAL_TRACE("In.");
713
714 INP_CHECK(ret, NULL == p_hal);
715
716 if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
717 ret = MPP_NOK;
718 goto __RETURN;
719 }
720
721 ret = set_up_colmv_buf(p_hal);
722 if (ret)
723 goto __RETURN;
724
725 reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
726
727 if (p_hal->fast_mode) {
728 RK_U32 i = 0;
729
730 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
731 if (!reg_ctx->reg_buf[i].valid) {
732 task->dec.reg_index = i;
733 regs = reg_ctx->reg_buf[i].regs;
734 reg_ctx->shph_offset = reg_ctx->reg_buf[i].offset_shph;
735 reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst;
736 reg_ctx->regs = reg_ctx->reg_buf[i].regs;
737 reg_ctx->reg_buf[i].valid = 1;
738 break;
739 }
740 }
741
742 mpp_assert(regs);
743 }
744
745 regs = reg_ctx->regs;
746
747 prepare_header(p_hal, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
748 prepare_scalist(p_hal, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
749
750 ret = fill_registers(p_hal, regs, task);
751
752 if (ret)
753 goto __RETURN;
754
755 {
756 memcpy(reg_ctx->bufs_ptr + reg_ctx->shph_offset, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
757 memcpy(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
758 regs->common.reg012.scanlist_addr_valid_en = 1;
759
760 MppDevRegOffsetCfg trans_cfg;
761 trans_cfg.reg_idx = 161;
762 trans_cfg.offset = reg_ctx->shph_offset;
763 regs->avs2d_addr.head_base = reg_ctx->bufs_fd;
764 mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
765
766 regs->avs2d_param.reg105.head_len = AVS2_RKV_SHPH_SIZE / 16;
767 regs->avs2d_param.reg105.head_len -= (regs->avs2d_param.reg105.head_len > 0) ? 1 : 0;
768
769 trans_cfg.reg_idx = 180;
770 trans_cfg.offset = reg_ctx->sclst_offset;
771 regs->avs2d_addr.scanlist_addr = reg_ctx->bufs_fd;
772 mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
773 }
774
775 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
776 FILE *fp_shph = NULL;
777 char name[50];
778 snprintf(name, sizeof(name), "/data/tmp/rkv_shph_%03d.bin", p_hal->frame_no);
779 fp_shph = fopen(name, "wb");
780 fwrite(reg_ctx->bufs_ptr + reg_ctx->shph_offset, 1, sizeof(reg_ctx->shph_dat), fp_shph);
781 fclose(fp_shph);
782 }
783
784 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
785 FILE *fp_scalist = NULL;
786 char name[50];
787 snprintf(name, sizeof(name), "/data/tmp/rkv_scalist_%03d.bin", p_hal->frame_no);
788 fp_scalist = fopen(name, "wb");
789 fwrite(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, 1, sizeof(reg_ctx->scalist_dat), fp_scalist);
790 fclose(fp_scalist);
791 }
792
793 // set rcb
794 {
795 hal_avs2d_rcb_info_update(p_hal, regs);
796 vdpu382_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ?
797 reg_ctx->rcb_buf[task->dec.reg_index] : reg_ctx->rcb_buf[0],
798 reg_ctx->rcb_info);
799
800 }
801
802 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
803 FILE *fp_rcb = NULL;
804 char name[50];
805 void *base = NULL;
806 snprintf(name, sizeof(name), "/data/tmp/rkv_rcb_%03d.bin", p_hal->frame_no);
807 fp_rcb = fopen(name, "wb");
808 base = mpp_buffer_get_ptr(reg_ctx->rcb_buf[0]);
809 fwrite(base, 1, reg_ctx->rcb_buf_size, fp_rcb);
810 fclose(fp_rcb);
811
812 }
813
814 vdpu382_setup_statistic(®s->common, ®s->statistic);
815 /* enable reference frame usage feedback */
816 regs->statistic.reg265.perf_cnt0_sel = 42;
817
818 __RETURN:
819 AVS2D_HAL_TRACE("Out. ret %d", ret);
820 return ret;
821 }
822
hal_avs2d_vdpu382_dump_reg_write(void * hal,Vdpu382Avs2dRegSet * regs)823 static MPP_RET hal_avs2d_vdpu382_dump_reg_write(void *hal, Vdpu382Avs2dRegSet *regs)
824 {
825 MPP_RET ret = MPP_OK;
826 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
827 FILE *fp_reg = NULL;
828 RK_U32 i = 0;
829 char name[50];
830 snprintf(name, sizeof(name), "/data/tmp/rkv_reg_write_%03d.txt", p_hal->frame_no);
831 fp_reg = fopen(name , "w+");
832
833 fprintf(fp_reg, "********Frame num %d\n", p_hal->frame_no);
834 for (i = 0; i < 8; i++)
835 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i, 0);
836
837 for (i = 0; i < sizeof(Vdpu382RegCommon) / sizeof(RK_U32); i++)
838 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_COMMON_REGS / sizeof(RK_U32)),
839 ((RK_U32 *)®s->common)[i]);
840
841 for (i = 0; i < 63 - 32; i++)
842 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 33, 0);
843
844 for (i = 0; i < sizeof(Vdpu382RegAvs2dParam) / sizeof(RK_U32); i++)
845 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_PARAMS_REGS / sizeof(RK_U32)),
846 ((RK_U32 *)®s->avs2d_param)[i]);
847
848 for (i = 0; i < 127 - 112; i++)
849 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 113, 0);
850
851 for (i = 0; i < sizeof(Vdpu382RegCommonAddr) / sizeof(RK_U32); i++)
852 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_COMMON_ADDR_REGS / sizeof(RK_U32)),
853 ((RK_U32 *)®s->common_addr)[i]);
854
855 for (i = 0; i < 159 - 142; i++)
856 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 143, 0);
857
858
859 for (i = 0; i < sizeof(Vdpu382RegAvs2dAddr) / sizeof(RK_U32); i++ )
860 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_ADDR_REGS / sizeof(RK_U32)),
861 ((RK_U32 *)®s->avs2d_addr)[i]);
862
863 for (i = 0; i < 223 - 197; i++)
864 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 198, 0);
865
866 for (i = 0; i < sizeof(Vdpu382RegIrqStatus) / sizeof(RK_U32); i++ )
867 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_INTERRUPT_REGS / sizeof(RK_U32)),
868 ((RK_U32 *)®s->irq_status)[i]);
869
870 for (i = 0; i < 255 - 237; i++)
871 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 238, 0);
872
873 for (i = 0; i < sizeof(Vdpu382RegStatistic) / sizeof(RK_U32); i++ )
874 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_STATISTIC_REGS / sizeof(RK_U32)),
875 ((RK_U32 *)®s->statistic)[i]);
876
877 fclose(fp_reg);
878 return ret;
879 }
880
hal_avs2d_vdpu382_dump_stream(void * hal,HalTaskInfo * task)881 static MPP_RET hal_avs2d_vdpu382_dump_stream(void *hal, HalTaskInfo *task)
882 {
883 MPP_RET ret = MPP_OK;
884 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
885
886 FILE *fp_stream = NULL;
887 char name[50];
888 MppBuffer buffer = NULL;
889 void *base = NULL;
890 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &buffer);
891 base = mpp_buffer_get_ptr(buffer);
892 snprintf(name, sizeof(name), "/data/tmp/rkv_stream_in_%03d.bin", p_hal->frame_no);
893 fp_stream = fopen(name, "wb");
894 fwrite(base, 1, mpp_packet_get_length(task->dec.input_packet), fp_stream);
895 fclose(fp_stream);
896
897 return ret;
898 }
899
hal_avs2d_vdpu382_start(void * hal,HalTaskInfo * task)900 MPP_RET hal_avs2d_vdpu382_start(void *hal, HalTaskInfo *task)
901 {
902 MPP_RET ret = MPP_OK;
903 Vdpu382Avs2dRegSet *regs = NULL;
904 Avs2dVdpu382RegCtx_t *reg_ctx;
905 MppDev dev = NULL;
906 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
907
908 AVS2D_HAL_TRACE("In.");
909 INP_CHECK(ret, NULL == p_hal);
910
911 if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
912 ret = MPP_NOK;
913 goto __RETURN;
914 }
915
916 reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
917 regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
918 dev = p_hal->dev;
919
920 p_hal->frame_no++;
921
922 do {
923 MppDevRegWrCfg wr_cfg;
924 MppDevRegRdCfg rd_cfg;
925
926 wr_cfg.reg = ®s->common;
927 wr_cfg.size = sizeof(regs->common);
928 wr_cfg.offset = OFFSET_COMMON_REGS;
929
930 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
931
932 if (ret) {
933 mpp_err_f("set register write failed %d\n", ret);
934 break;
935 }
936
937 wr_cfg.reg = ®s->avs2d_param;
938 wr_cfg.size = sizeof(regs->avs2d_param);
939 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
940
941 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
942
943 if (ret) {
944 mpp_err_f("set register write failed %d\n", ret);
945 break;
946 }
947
948 wr_cfg.reg = ®s->common_addr;
949 wr_cfg.size = sizeof(regs->common_addr);
950 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
951
952 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
953
954 if (ret) {
955 mpp_err_f("set register write failed %d\n", ret);
956 break;
957 }
958
959 wr_cfg.reg = ®s->avs2d_addr;
960 wr_cfg.size = sizeof(regs->avs2d_addr);
961 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
962
963 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
964
965 if (ret) {
966 mpp_err_f("set register write failed %d\n", ret);
967 break;
968 }
969
970 wr_cfg.reg = ®s->statistic;
971 wr_cfg.size = sizeof(regs->statistic);
972 wr_cfg.offset = OFFSET_STATISTIC_REGS;
973 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
974
975 if (ret) {
976 mpp_err_f("set register write failed %d\n", ret);
977 break;
978 }
979
980 rd_cfg.reg = ®s->irq_status;
981 rd_cfg.size = sizeof(regs->irq_status);
982 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
983 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
984
985 if (ret) {
986 mpp_err_f("set register read failed %d\n", ret);
987 break;
988 }
989
990 rd_cfg.reg = ®s->avs2d_param;
991 rd_cfg.size = sizeof(regs->avs2d_param);
992 rd_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
993 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
994
995 if (ret) {
996 mpp_err_f("set register read failed %d\n", ret);
997 break;
998 }
999
1000 rd_cfg.reg = ®s->statistic;
1001 rd_cfg.size = sizeof(regs->statistic);
1002 rd_cfg.offset = OFFSET_STATISTIC_REGS;
1003 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
1004
1005 if (ret) {
1006 mpp_err_f("set register write failed %d\n", ret);
1007 break;
1008 }
1009
1010 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
1011 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out));
1012 rd_cfg.reg = reg_ctx->reg_out;
1013 rd_cfg.size = sizeof(reg_ctx->reg_out);
1014 rd_cfg.offset = 0;
1015 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
1016 }
1017
1018 // rcb info for sram
1019 vdpu382_set_rcbinfo(dev, reg_ctx->rcb_info);
1020
1021 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN)
1022 hal_avs2d_vdpu382_dump_stream(hal, task);
1023
1024 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG)
1025 hal_avs2d_vdpu382_dump_reg_write(hal, regs);
1026
1027 // send request to hardware
1028 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
1029 if (ret) {
1030 mpp_err_f("send cmd failed %d\n", ret);
1031 break;
1032 }
1033
1034 } while (0);
1035
1036 __RETURN:
1037 AVS2D_HAL_TRACE("Out.");
1038 return ret;
1039 }
1040
1041
fetch_data(RK_U32 fmt,RK_U8 * line,RK_U32 num)1042 static RK_U8 fetch_data(RK_U32 fmt, RK_U8 *line, RK_U32 num)
1043 {
1044 RK_U32 offset = 0;
1045 RK_U32 value = 0;
1046
1047 if (fmt == MPP_FMT_YUV420SP_10BIT) {
1048 offset = (num * 2) & 7;
1049 value = (line[num * 10 / 8] >> offset) |
1050 (line[num * 10 / 8 + 1] << (8 - offset));
1051
1052 value = (value & 0x3ff) >> 2;
1053 } else if (fmt == MPP_FMT_YUV420SP) {
1054 value = line[num];
1055 }
1056
1057 return value;
1058 }
1059
hal_avs2d_vdpu382_dump_yuv(void * hal,HalTaskInfo * task)1060 static MPP_RET hal_avs2d_vdpu382_dump_yuv(void *hal, HalTaskInfo *task)
1061 {
1062 MPP_RET ret = MPP_OK;
1063 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
1064
1065 MppFrameFormat fmt = MPP_FMT_YUV420SP;
1066 RK_U32 vir_w = 0;
1067 RK_U32 vir_h = 0;
1068 RK_U32 i = 0;
1069 RK_U32 j = 0;
1070 FILE *fp_stream = NULL;
1071 char name[50];
1072 MppBuffer buffer = NULL;
1073 MppFrame frame;
1074 void *base = NULL;
1075
1076 ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_FRAME_PTR, &frame);
1077
1078 if (ret != MPP_OK || frame == NULL)
1079 mpp_log_f("failed to get frame slot %d", task->dec.output);
1080
1081 ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_BUFFER, &buffer);
1082
1083 if (ret != MPP_OK || buffer == NULL)
1084 mpp_log_f("failed to get frame buffer slot %d", task->dec.output);
1085
1086 AVS2D_HAL_TRACE("frame slot %d, fd %d\n", task->dec.output, mpp_buffer_get_fd(buffer));
1087 base = mpp_buffer_get_ptr(buffer);
1088 vir_w = mpp_frame_get_hor_stride(frame);
1089 vir_h = mpp_frame_get_ver_stride(frame);
1090 fmt = mpp_frame_get_fmt(frame);
1091 snprintf(name, sizeof(name), "/data/tmp/rkv_out_%dx%d_nv12_%03d.yuv", vir_w, vir_h,
1092 p_hal->frame_no);
1093 fp_stream = fopen(name, "wb");
1094 /* if format is fbc, write fbc header first */
1095 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1096 RK_U32 header_size = 0;
1097
1098 header_size = vir_w * vir_h / 16;
1099 fwrite(base, 1, header_size, fp_stream);
1100 base += header_size;
1101 }
1102
1103 if (fmt != MPP_FMT_YUV420SP_10BIT) {
1104 fwrite(base, 1, vir_w * vir_h * 3 / 2, fp_stream);
1105 } else {
1106 RK_U8 tmp = 0;
1107 for (i = 0; i < vir_h; i++) {
1108 for (j = 0; j < vir_w; j++) {
1109 tmp = fetch_data(fmt, base, j);
1110 fwrite(&tmp, 1, 1, fp_stream);
1111 }
1112 base += vir_w;
1113 }
1114
1115 for (i = 0; i < vir_h / 2; i++) {
1116 for (j = 0; j < vir_w; j++) {
1117 tmp = fetch_data(fmt, base, j);
1118 fwrite(&tmp, 1, 1, fp_stream);
1119 }
1120 base += vir_w;
1121 }
1122 }
1123 fclose(fp_stream);
1124
1125 return ret;
1126 }
1127
hal_avs2d_vdpu382_wait(void * hal,HalTaskInfo * task)1128 MPP_RET hal_avs2d_vdpu382_wait(void *hal, HalTaskInfo *task)
1129 {
1130 MPP_RET ret = MPP_OK;
1131 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
1132 Avs2dVdpu382RegCtx_t *reg_ctx;
1133 Vdpu382Avs2dRegSet *p_regs;
1134
1135 INP_CHECK(ret, NULL == p_hal);
1136 reg_ctx = (Avs2dVdpu382RegCtx_t *)p_hal->reg_ctx;
1137 p_regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
1138
1139 if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
1140 AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "found task error.\n");
1141 ret = MPP_NOK;
1142 goto __RETURN;
1143 } else {
1144 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1145 if (ret)
1146 mpp_err_f("poll cmd failed %d\n", ret);
1147 }
1148
1149 if (avs2d_hal_debug & AVS2D_HAL_DBG_OUT)
1150 hal_avs2d_vdpu382_dump_yuv(hal, task);
1151
1152 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
1153 FILE *fp_reg = NULL;
1154 RK_U32 i = 0;
1155 char name[50];
1156 snprintf(name, sizeof(name), "/data/tmp/rkv_reg_read_%03d.txt", p_hal->frame_no);
1157 fp_reg = fopen(name , "w+");
1158
1159 for (i = 0; i < 278; i++)
1160 fprintf(fp_reg, "%08x\n", reg_ctx->reg_out[i]);
1161
1162 fclose(fp_reg);
1163 }
1164
1165 AVS2D_HAL_TRACE("read reg[224] 0x%08x\n", p_regs->irq_status.reg224);
1166
1167 if (p_hal->dec_cb) {
1168 DecCbHalDone param;
1169
1170 param.task = (void *)&task->dec;
1171 param.regs = (RK_U32 *)p_regs;
1172
1173 if (p_regs->irq_status.reg224.dec_error_sta ||
1174 (!p_regs->irq_status.reg224.dec_rdy_sta) ||
1175 p_regs->irq_status.reg224.buf_empty_sta ||
1176 p_regs->irq_status.reg226.strmd_error_status ||
1177 p_regs->irq_status.reg227.colmv_error_ref_picidx ||
1178 p_regs->irq_status.reg226.strmd_detect_error_flag)
1179 param.hard_err = 1;
1180 else
1181 param.hard_err = 0;
1182
1183 task->dec.flags.ref_used = p_regs->statistic.reg265.link_perf_cnt0;
1184
1185 if (task->dec.flags.ref_miss) {
1186 RK_U32 ref_hw_usage = p_regs->statistic.reg265.link_perf_cnt0;
1187
1188 AVS2D_HAL_TRACE("hal frame %d ref miss %x hard_err %d hw_usage %x", p_hal->frame_no,
1189 task->dec.flags.ref_miss, param.hard_err, ref_hw_usage);
1190 }
1191
1192 AVS2D_HAL_TRACE("hal frame %d hard_err= %d", p_hal->frame_no, param.hard_err);
1193
1194 mpp_callback(p_hal->dec_cb, ¶m);
1195 }
1196
1197 memset(&p_regs->irq_status.reg224, 0, sizeof(RK_U32));
1198
1199 if (p_hal->fast_mode)
1200 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
1201
1202 __RETURN:
1203 AVS2D_HAL_TRACE("Out. ret %d", ret);
1204 return ret;
1205 }
1206