1 /*
2 * Copyright 2021 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_avs2d_rkv"
18
19 #include <string.h>
20 #include <stdio.h>
21
22 #include "mpp_log.h"
23 #include "mpp_mem.h"
24 #include "mpp_common.h"
25 #include "mpp_debug.h"
26 #include "mpp_bitput.h"
27
28 #include "avs2d_syntax.h"
29 #include "hal_avs2d_api.h"
30 #include "hal_avs2d_rkv.h"
31 #include "mpp_dec_cb_param.h"
32 #include "vdpu34x_avs2d.h"
33
34 #define VDPU34X_FAST_REG_SET_CNT (3)
35 #define MAX_REF_NUM (8)
36 #define AVS2_RKV_SHPH_SIZE (1408 / 8) /* bytes */
37 #define AVS2_RKV_SCALIST_SIZE (80 + 128) /* bytes */
38 #define VDPU34x_TOTAL_REG_CNT (278)
39
40 #define AVS2_RKV_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SHPH_SIZE, SZ_4K))
41 #define AVS2_RKV_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SCALIST_SIZE, SZ_4K))
42 #define AVS2_RKV_STREAM_INFO_SET_SIZE (AVS2_RKV_SHPH_ALIGNED_SIZE + \
43 AVS2_RKV_SCALIST_ALIGNED_SIZE)
44 #define AVS2_ALL_TBL_BUF_SIZE(cnt) (AVS2_RKV_STREAM_INFO_SET_SIZE * (cnt))
45 #define AVS2_SHPH_OFFSET(pos) (AVS2_RKV_STREAM_INFO_SET_SIZE * (pos))
46 #define AVS2_SCALIST_OFFSET(pos) (AVS2_SHPH_OFFSET(pos) + AVS2_RKV_SHPH_ALIGNED_SIZE)
47
48 #define COLMV_COMPRESS_EN (1)
49 #define COLMV_BLOCK_SIZE (16)
50 #define COLMV_BYTES (16)
51
52 typedef struct avs2d_buf_t {
53 RK_U32 valid;
54 RK_U32 offset_shph;
55 RK_U32 offset_sclst;
56 Vdpu34xAvs2dRegSet *regs;
57 } Avs2dRkvBuf_t;
58
59 typedef struct avs2d_reg_ctx_t {
60 Avs2dRkvBuf_t reg_buf[VDPU34X_FAST_REG_SET_CNT];
61
62 RK_U32 shph_offset;
63 RK_U32 sclst_offset;
64
65 Vdpu34xAvs2dRegSet *regs;
66
67 RK_U8 shph_dat[AVS2_RKV_SHPH_SIZE];
68 RK_U8 scalist_dat[AVS2_RKV_SCALIST_SIZE];
69
70 MppBuffer bufs;
71 RK_S32 bufs_fd;
72 void *bufs_ptr;
73
74 MppBuffer rcb_buf[VDPU34X_FAST_REG_SET_CNT];
75 RK_S32 rcb_buf_size;
76 Vdpu34xRcbInfo rcb_info[RCB_BUF_COUNT];
77 RK_U32 reg_out[VDPU34x_TOTAL_REG_CNT];
78
79 } Avs2dRkvRegCtx_t;
80
81 MPP_RET hal_avs2d_rkv_deinit(void *hal);
avs2d_ver_align(RK_U32 val)82 static RK_U32 avs2d_ver_align(RK_U32 val)
83 {
84 return MPP_ALIGN(val, 16);
85 }
86
avs2d_hor_align(RK_U32 val)87 static RK_U32 avs2d_hor_align(RK_U32 val)
88 {
89
90 return MPP_ALIGN(val, 16);
91 }
92
avs2d_len_align(RK_U32 val)93 static RK_U32 avs2d_len_align(RK_U32 val)
94 {
95 return (2 * MPP_ALIGN(val, 16));
96 }
97
avs2d_hor_align_64(RK_U32 val)98 static RK_U32 avs2d_hor_align_64(RK_U32 val)
99 {
100 return MPP_ALIGN(val, 64);
101 }
102
prepare_header(Avs2dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)103 static MPP_RET prepare_header(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
104 {
105 RK_U32 i, j;
106 BitputCtx_t bp;
107 RK_U64 *bit_buf = (RK_U64 *)data;
108 Avs2dSyntax_t *syntax = &p_hal->syntax;
109 PicParams_Avs2d *pp = &syntax->pp;
110 AlfParams_Avs2d *alfp = &syntax->alfp;
111 RefParams_Avs2d *refp = &syntax->refp;
112 WqmParams_Avs2d *wqmp = &syntax->wqmp;
113
114 memset(data, 0, len);
115
116 mpp_set_bitput_ctx(&bp, bit_buf, len);
117 //!< sequence header syntax
118 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
119 mpp_put_bits(&bp, pp->pic_width_in_luma_samples, 16);
120 mpp_put_bits(&bp, pp->pic_height_in_luma_samples, 16);
121 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
122 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
123 mpp_put_bits(&bp, pp->lcu_size, 3);
124 mpp_put_bits(&bp, pp->progressive_sequence, 1);
125 mpp_put_bits(&bp, pp->field_coded_sequence, 1);
126 mpp_put_bits(&bp, pp->multi_hypothesis_skip_enable_flag, 1);
127 mpp_put_bits(&bp, pp->dual_hypothesis_prediction_enable_flag, 1);
128 mpp_put_bits(&bp, pp->weighted_skip_enable_flag, 1);
129 mpp_put_bits(&bp, pp->asymmetrc_motion_partitions_enable_flag, 1);
130 mpp_put_bits(&bp, pp->nonsquare_quadtree_transform_enable_flag, 1);
131 mpp_put_bits(&bp, pp->nonsquare_intra_prediction_enable_flag, 1);
132 mpp_put_bits(&bp, pp->secondary_transform_enable_flag, 1);
133 mpp_put_bits(&bp, pp->sample_adaptive_offset_enable_flag, 1);
134 mpp_put_bits(&bp, pp->adaptive_loop_filter_enable_flag, 1);
135 mpp_put_bits(&bp, pp->pmvr_enable_flag, 1);
136 mpp_put_bits(&bp, pp->cross_slice_loopfilter_enable_flag, 1);
137 //!< picture header syntax
138 mpp_put_bits(&bp, pp->picture_type, 3);
139 mpp_put_bits(&bp, refp->ref_pic_num, 3);
140 mpp_put_bits(&bp, pp->scene_reference_enable_flag, 1);
141 mpp_put_bits(&bp, pp->bottom_field_picture_flag, 1);
142 mpp_put_bits(&bp, pp->fixed_picture_qp, 1);
143 mpp_put_bits(&bp, pp->picture_qp, 7);
144 mpp_put_bits(&bp, pp->loop_filter_disable_flag, 1);
145 mpp_put_bits(&bp, pp->alpha_c_offset, 5);
146 mpp_put_bits(&bp, pp->beta_offset, 5);
147 //!< weight quant param
148 mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cb, 6);
149 mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cr, 6);
150 mpp_put_bits(&bp, wqmp->pic_weight_quant_enable_flag, 1);
151 //!< alf param
152 mpp_put_bits(&bp, alfp->enable_pic_alf_y, 1);
153 mpp_put_bits(&bp, alfp->enable_pic_alf_cb, 1);
154 mpp_put_bits(&bp, alfp->enable_pic_alf_cr, 1);
155
156 if (alfp->enable_pic_alf_y) {
157 RK_U32 alf_filter_num = alfp->alf_filter_num_minus1 + 1;
158 mpp_put_bits(&bp, alfp->alf_filter_num_minus1, 4);
159
160 for (i = 0; i < 16; i++)
161 mpp_put_bits(&bp, alfp->alf_coeff_idx_tab[i], 4);
162
163 for (i = 0; i < alf_filter_num; i++) {
164 for (j = 0; j < 9; j++) {
165 mpp_put_bits(&bp, alfp->alf_coeff_y[i][j], 7);
166 }
167 }
168 }
169
170 if (alfp->enable_pic_alf_cb) {
171 for (j = 0; j < 9; j++)
172 mpp_put_bits(&bp, alfp->alf_coeff_cb[j], 7);
173 }
174
175 if (alfp->enable_pic_alf_cr) {
176 for (j = 0; j < 9; j++)
177 mpp_put_bits(&bp, alfp->alf_coeff_cr[j], 7);
178 }
179
180 mpp_put_align(&bp, 128, 0);
181
182 return MPP_OK;
183 }
184
prepare_scalist(Avs2dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)185 static MPP_RET prepare_scalist(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
186 {
187 RK_U32 i, j;
188 RK_U32 size_id, block_size;
189 BitputCtx_t bp;
190 RK_U64 *bit_buf = (RK_U64 *)data;
191 Avs2dSyntax_t *syntax = &p_hal->syntax;
192 WqmParams_Avs2d *wqmp = &syntax->wqmp;
193
194 if (!wqmp->pic_weight_quant_enable_flag)
195 return MPP_OK;
196
197 memset(data, 0, len);
198
199 mpp_set_bitput_ctx(&bp, bit_buf, len);
200
201 for (size_id = 0; size_id < 2; size_id++) {
202 block_size = MPP_MIN(1 << (size_id + 2), 8);
203 for (i = 0; i < block_size; i++) {
204 for (j = 0 ; j < block_size; j++)
205 //!< row col reversed
206 mpp_put_bits(&bp, wqmp->wq_matrix[size_id][size_id * j + i], 8);
207 }
208 }
209
210 return MPP_OK;
211 }
212
get_frame_fd(Avs2dHalCtx_t * p_hal,RK_S32 idx)213 static RK_S32 get_frame_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
214 {
215 RK_S32 ret_fd = 0;
216 MppBuffer mbuffer = NULL;
217
218 mpp_buf_slot_get_prop(p_hal->frame_slots, idx, SLOT_BUFFER, &mbuffer);
219 ret_fd = mpp_buffer_get_fd(mbuffer);
220
221 return ret_fd;
222 }
223
get_packet_fd(Avs2dHalCtx_t * p_hal,RK_S32 idx)224 static RK_S32 get_packet_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
225 {
226 RK_S32 ret_fd = 0;
227 MppBuffer mbuffer = NULL;
228
229 mpp_buf_slot_get_prop(p_hal->packet_slots, idx, SLOT_BUFFER, &mbuffer);
230 ret_fd = mpp_buffer_get_fd(mbuffer);
231
232 return ret_fd;
233 }
234
init_common_regs(Vdpu34xAvs2dRegSet * regs)235 static MPP_RET init_common_regs(Vdpu34xAvs2dRegSet *regs)
236 {
237 Vdpu34xRegCommon *common = ®s->common;
238
239 common->reg009.dec_mode = 3; // AVS2
240 common->reg015.rlc_mode = 0;
241
242 common->reg011.buf_empty_en = 1;
243 common->reg011.dec_timeout_e = 1;
244
245 common->reg010.dec_e = 1;
246
247 common->reg013.h26x_error_mode = 0;
248 common->reg013.colmv_error_mode = 0;
249 common->reg013.h26x_streamd_error_mode = 0;
250 common->reg021.inter_error_prc_mode = 0;
251 common->reg021.error_deb_en = 0;
252 common->reg021.error_intra_mode = 0;
253
254 if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) {
255 common->reg024.cabac_err_en_lowbits = 0;
256 common->reg025.cabac_err_en_highbits = 0;
257 common->reg026.swreg_block_gating_e = 0xfffef;
258 } else {
259 common->reg024.cabac_err_en_lowbits = 0xffffffdf;
260 common->reg025.cabac_err_en_highbits = 0x3dffffff;
261 common->reg026.swreg_block_gating_e = 0xfffff;
262 }
263
264 common->reg026.reg_cfg_gating_en = 1;
265 common->reg032_timeout_threshold = 0x3fffff;
266
267 common->reg011.dec_clkgate_e = 1;
268 common->reg011.dec_e_strmd_clkgate_dis = 0;
269 common->reg011.dec_timeout_e = 1;
270
271 common->reg013.timeout_mode = 1;
272 common->reg013.stmerror_waitdecfifo_empty = 1;
273 common->reg012.colmv_compress_en = COLMV_COMPRESS_EN;
274 common->reg012.wr_ddr_align_en = 1;
275 common->reg012.info_collect_en = 1;
276 common->reg012.error_info_en = 0;
277
278 return MPP_OK;
279 }
280
281 //TODO calc rcb buffer size;
282 /*
283 static void avs2d_refine_rcb_size(Vdpu34xRcbInfo *rcb_info,
284 Vdpu34xAvs2dRegSet *hw_regs,
285 RK_S32 width, RK_S32 height, void *dxva)
286 {
287 (void) rcb_info;
288 (void) hw_regs;
289 (void) width;
290 (void) height;
291 (void) dxva;
292 return;
293 }
294 */
295
hal_avs2d_rcb_info_update(void * hal,Vdpu34xAvs2dRegSet * hw_regs)296 static void hal_avs2d_rcb_info_update(void *hal, Vdpu34xAvs2dRegSet *hw_regs)
297 {
298 MPP_RET ret = MPP_OK;
299 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
300 Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
301 RK_S32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
302 RK_S32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
303 RK_S32 i = 0;
304 RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
305
306 (void) hw_regs;
307
308 reg_ctx->rcb_buf_size = vdpu34x_get_rcb_buf_size(reg_ctx->rcb_info, width, height);
309 //avs2d_refine_rcb_size(reg_ctx->rcb_info, hw_regs, width, height, (void *)&p_hal->syntax);
310
311 for (i = 0; i < loop; i++) {
312 MppBuffer rcb_buf = NULL;
313
314 if (reg_ctx->rcb_buf[i]) {
315 mpp_buffer_put(reg_ctx->rcb_buf[i]);
316 reg_ctx->rcb_buf[i] = NULL;
317 }
318
319 ret = mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size);
320
321 if (ret)
322 mpp_err_f("AVS2D mpp_buffer_group_get failed\n");
323
324 reg_ctx->rcb_buf[i] = rcb_buf;
325 }
326 }
327
fill_registers(Avs2dHalCtx_t * p_hal,Vdpu34xAvs2dRegSet * p_regs,HalTaskInfo * task)328 static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu34xAvs2dRegSet *p_regs, HalTaskInfo *task)
329 {
330 MPP_RET ret = MPP_OK;
331 RK_U32 i;
332 MppFrame mframe = NULL;
333 Avs2dSyntax_t *syntax = &p_hal->syntax;
334 PicParams_Avs2d *pp = &syntax->pp;
335 RefParams_Avs2d *refp = &syntax->refp;
336 HalDecTask *task_dec = &task->dec;
337 Vdpu34xRegCommon *common = &p_regs->common;
338 RK_U32 is_fbc = 0;
339 HalBuf *mv_buf = NULL;
340
341 mpp_buf_slot_get_prop(p_hal->frame_slots, task_dec->output, SLOT_FRAME_PTR, &mframe);
342 is_fbc = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
343
344 //!< caculate the yuv_frame_size
345 {
346 RK_U32 hor_virstride = 0;
347 RK_U32 ver_virstride = 0;
348 RK_U32 y_virstride = 0;
349
350 hor_virstride = mpp_frame_get_hor_stride(mframe);
351 ver_virstride = mpp_frame_get_ver_stride(mframe);
352 y_virstride = hor_virstride * ver_virstride;
353 AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride);
354
355 if (is_fbc) {
356 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
357 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
358
359 common->reg012.fbc_e = 1;
360 common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
361 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
362 common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
363 } else {
364 common->reg012.fbc_e = 0;
365 common->reg018.y_hor_virstride = hor_virstride / 16;
366 common->reg019.uv_hor_virstride = hor_virstride / 16;
367 common->reg020_y_virstride.y_virstride = y_virstride / 16;
368 }
369 common->reg013.cur_pic_is_idr = (pp->picture_type == 0 || pp->picture_type == 4 || pp->picture_type == 5);
370 }
371
372 // set current
373 {
374 RK_S32 fd = -1;
375 p_regs->avs2d_param.reg65_cur_top_poc = mpp_frame_get_poc(mframe);
376 p_regs->avs2d_param.reg66_cur_bot_poc = 0;
377 fd = get_frame_fd(p_hal, task_dec->output);
378 mpp_assert(fd >= 0);
379 p_regs->common_addr.reg130_decout_base = fd;
380 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, task_dec->output);
381 p_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
382 AVS2D_HAL_TRACE("cur frame index %d, fd %d, colmv fd %d", task_dec->output, fd, p_regs->common_addr.reg131_colmv_cur_base);
383 }
384
385 // set reference
386 {
387 RK_U64 ref_flag = 0;
388 RK_S32 valid_slot = -1;
389 RK_U32 *ref_low = (RK_U32 *)&p_regs->avs2d_param.reg99;
390 RK_U32 *ref_hight = (RK_U32 *)&p_regs->avs2d_param.reg100;
391 RK_U32 err_ref_base = 0;
392
393 AVS2D_HAL_TRACE("num of ref %d", refp->ref_pic_num);
394
395 for (i = 0; i < refp->ref_pic_num; i++) {
396 if (task_dec->refer[i] < 0)
397 continue;
398
399 valid_slot = i;
400 break;
401 }
402
403 for (i = 0; i < refp->ref_pic_num; i++) {
404 MppFrame frame_ref = NULL;
405
406 RK_S32 slot_idx = task_dec->refer[i] < 0 ? task_dec->refer[valid_slot] : task_dec->refer[i];
407
408 if (slot_idx < 0) {
409 AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "missing ref, could not found valid ref");
410 task->dec.flags.ref_err = 1;
411 return ret = MPP_ERR_UNKNOW;
412 }
413
414 mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &frame_ref);
415
416 if (frame_ref) {
417 RK_U32 frm_flag = 1 << 3;
418
419 if (pp->bottom_field_picture_flag)
420 frm_flag |= 1 << 2;
421
422 if (pp->field_coded_sequence)
423 frm_flag |= 1;
424
425 ref_flag |= frm_flag << (i * 8);
426
427 p_regs->avs2d_addr.ref_base[i] = get_frame_fd(p_hal, slot_idx);
428 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
429 p_regs->avs2d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
430
431 p_regs->avs2d_param.reg67_098_ref_poc[i] = mpp_frame_get_poc(frame_ref);
432
433 if (!err_ref_base && !mpp_frame_get_errinfo(frame_ref))
434 err_ref_base = p_regs->avs2d_addr.ref_base[i];
435
436 AVS2D_HAL_TRACE("ref_base[%d] index=%d, fd = %d, colmv %d, poc %d",
437 i, slot_idx, p_regs->avs2d_addr.ref_base[i],
438 p_regs->avs2d_addr.colmv_base[i], p_regs->avs2d_param.reg67_098_ref_poc[i]);
439 }
440 }
441
442 if (p_hal->syntax.refp.scene_ref_enable && p_hal->syntax.refp.scene_ref_slot_idx >= 0) {
443 MppFrame scene_ref = NULL;
444 RK_S32 slot_idx = p_hal->syntax.refp.scene_ref_slot_idx;
445 RK_S32 replace_idx = p_hal->syntax.refp.scene_ref_replace_pos;
446
447 mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &scene_ref);
448
449 if (scene_ref) {
450 p_regs->avs2d_addr.ref_base[replace_idx] = get_frame_fd(p_hal, slot_idx);
451 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
452 p_regs->avs2d_addr.colmv_base[replace_idx] = mpp_buffer_get_fd(mv_buf->buf[0]);
453 p_regs->avs2d_param.reg67_098_ref_poc[replace_idx] = mpp_frame_get_poc(scene_ref);
454 }
455 }
456
457 *ref_low = (RK_U32) (ref_flag & 0xffffffff);
458 *ref_hight = (RK_U32) ((ref_flag >> 32) & 0xffffffff);
459
460 p_regs->common_addr.reg132_error_ref_base = err_ref_base;
461 }
462
463 // set rlc
464 {
465 p_regs->common_addr.reg128_rlc_base = get_packet_fd(p_hal, task_dec->input);
466 AVS2D_HAL_TRACE("packet fd %d from slot %d", p_regs->common_addr.reg128_rlc_base, task_dec->input);
467 p_regs->common_addr.reg129_rlcwrite_base = p_regs->common_addr.reg128_rlc_base;
468 common->reg016_str_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64;
469 }
470
471 return ret;
472 }
473
hal_avs2d_rkv_deinit(void * hal)474 MPP_RET hal_avs2d_rkv_deinit(void *hal)
475 {
476 MPP_RET ret = MPP_OK;
477 RK_U32 i, loop;
478 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
479 Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
480
481 AVS2D_HAL_TRACE("In.");
482
483 INP_CHECK(ret, NULL == reg_ctx);
484
485 //!< malloc buffers
486 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
487 for (i = 0; i < loop; i++) {
488 if (reg_ctx->rcb_buf[i]) {
489 mpp_buffer_put(reg_ctx->rcb_buf[i]);
490 reg_ctx->rcb_buf[i] = NULL;
491 }
492
493 MPP_FREE(reg_ctx->reg_buf[i].regs);
494 }
495
496 if (reg_ctx->bufs) {
497 mpp_buffer_put(reg_ctx->bufs);
498 reg_ctx->bufs = NULL;
499 }
500
501 if (p_hal->cmv_bufs) {
502 hal_bufs_deinit(p_hal->cmv_bufs);
503 p_hal->cmv_bufs = NULL;
504 }
505
506 MPP_FREE(p_hal->reg_ctx);
507
508 __RETURN:
509 AVS2D_HAL_TRACE("Out. ret %d", ret);
510 return ret;
511 }
512
hal_avs2d_rkv_init(void * hal,MppHalCfg * cfg)513 MPP_RET hal_avs2d_rkv_init(void *hal, MppHalCfg *cfg)
514 {
515 MPP_RET ret = MPP_OK;
516 RK_U32 i, loop;
517 Avs2dRkvRegCtx_t *reg_ctx;
518 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
519
520 AVS2D_HAL_TRACE("In.");
521
522 INP_CHECK(ret, NULL == p_hal);
523
524 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Avs2dRkvRegCtx_t)));
525 reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
526
527 //!< malloc buffers
528 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
529 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs, AVS2_ALL_TBL_BUF_SIZE(loop)));
530 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
531 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
532
533 for (i = 0; i < loop; i++) {
534 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu34xAvs2dRegSet, 1);
535 init_common_regs(reg_ctx->reg_buf[i].regs);
536 reg_ctx->reg_buf[i].offset_shph = AVS2_SHPH_OFFSET(i);
537 reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i);
538 }
539
540 if (!p_hal->fast_mode) {
541 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
542 reg_ctx->shph_offset = reg_ctx->reg_buf[0].offset_shph;
543 reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst;
544 }
545
546 if (MPP_FRAME_FMT_IS_FBC(cfg->cfg->base.out_fmt))
547 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align_64);
548 else
549 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
550
551 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
552 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
553
554 __RETURN:
555 AVS2D_HAL_TRACE("Out. ret %d", ret);
556 (void)cfg;
557 return ret;
558 __FAILED:
559 hal_avs2d_rkv_deinit(p_hal);
560 AVS2D_HAL_TRACE("Out. ret %d", ret);
561 return ret;
562 }
563
set_up_colmv_buf(void * hal)564 static MPP_RET set_up_colmv_buf(void *hal)
565 {
566 MPP_RET ret = MPP_OK;
567 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
568 Avs2dSyntax_t *syntax = &p_hal->syntax;
569 PicParams_Avs2d *pp = &syntax->pp;
570 RK_U32 mv_size = 0;
571 RK_U32 ctu_size = 1 << (p_hal->syntax.pp.lcu_size);
572 RK_U32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
573 RK_U32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
574
575 mv_size = vdpu34x_get_colmv_size(width, height, ctu_size, COLMV_BYTES,
576 COLMV_BLOCK_SIZE, COLMV_COMPRESS_EN);
577 if (pp->field_coded_sequence)
578 mv_size *= 2;
579 AVS2D_HAL_TRACE("mv_size %d", mv_size);
580
581 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
582 size_t size = mv_size;
583
584 if (p_hal->cmv_bufs) {
585 hal_bufs_deinit(p_hal->cmv_bufs);
586 p_hal->cmv_bufs = NULL;
587 }
588
589 hal_bufs_init(&p_hal->cmv_bufs);
590 if (p_hal->cmv_bufs == NULL) {
591 mpp_err_f("colmv bufs init fail");
592 ret = MPP_ERR_INIT;
593 goto __RETURN;
594 }
595
596 p_hal->mv_size = mv_size;
597 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
598 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
599 }
600
601 __RETURN:
602 return ret;
603 }
604
hal_avs2d_rkv_gen_regs(void * hal,HalTaskInfo * task)605 MPP_RET hal_avs2d_rkv_gen_regs(void *hal, HalTaskInfo *task)
606 {
607 MPP_RET ret = MPP_OK;
608 Avs2dRkvRegCtx_t *reg_ctx;
609 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
610 Vdpu34xAvs2dRegSet *regs = NULL;
611
612 AVS2D_HAL_TRACE("In.");
613
614 INP_CHECK(ret, NULL == p_hal);
615
616 if ((task->dec.flags.parse_err || task->dec.flags.ref_err) &&
617 !p_hal->cfg->base.disable_error) {
618 ret = MPP_NOK;
619 goto __RETURN;
620 }
621
622 ret = set_up_colmv_buf(p_hal);
623 if (ret)
624 goto __RETURN;
625
626 reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
627
628 if (p_hal->fast_mode) {
629 RK_U32 i = 0;
630
631 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
632 if (!reg_ctx->reg_buf[i].valid) {
633 task->dec.reg_index = i;
634 regs = reg_ctx->reg_buf[i].regs;
635 reg_ctx->shph_offset = reg_ctx->reg_buf[i].offset_shph;
636 reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst;
637 reg_ctx->regs = reg_ctx->reg_buf[i].regs;
638 reg_ctx->reg_buf[i].valid = 1;
639 break;
640 }
641 }
642
643 mpp_assert(regs);
644 }
645
646 regs = reg_ctx->regs;
647
648 prepare_header(p_hal, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
649 prepare_scalist(p_hal, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
650
651 ret = fill_registers(p_hal, regs, task);
652
653 if (ret)
654 goto __RETURN;
655
656 {
657 memcpy(reg_ctx->bufs_ptr + reg_ctx->shph_offset, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
658 memcpy(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
659 regs->common.reg012.scanlist_addr_valid_en = 1;
660
661 regs->avs2d_addr.head_base = reg_ctx->bufs_fd;
662 mpp_dev_set_reg_offset(p_hal->dev, 161, reg_ctx->shph_offset);
663
664 regs->avs2d_param.reg105.head_len = AVS2_RKV_SHPH_SIZE / 16;
665 regs->avs2d_param.reg105.head_len -= (regs->avs2d_param.reg105.head_len > 0) ? 1 : 0;
666
667 regs->avs2d_addr.scanlist_addr = reg_ctx->bufs_fd;
668 mpp_dev_set_reg_offset(p_hal->dev, 180, reg_ctx->sclst_offset);
669 }
670
671 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
672 FILE *fp_shph = NULL;
673 char name[50];
674 snprintf(name, sizeof(name), "/data/tmp/rkv_shph_%03d.bin", p_hal->frame_no);
675 fp_shph = fopen(name, "wb");
676 fwrite(reg_ctx->bufs_ptr + reg_ctx->shph_offset, 1, sizeof(reg_ctx->shph_dat), fp_shph);
677 fclose(fp_shph);
678 }
679
680 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
681 FILE *fp_scalist = NULL;
682 char name[50];
683 snprintf(name, sizeof(name), "/data/tmp/rkv_scalist_%03d.bin", p_hal->frame_no);
684 fp_scalist = fopen(name, "wb");
685 fwrite(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, 1, sizeof(reg_ctx->scalist_dat), fp_scalist);
686 fclose(fp_scalist);
687 }
688
689 // set rcb
690 {
691 hal_avs2d_rcb_info_update(p_hal, regs);
692 vdpu34x_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ?
693 reg_ctx->rcb_buf[task->dec.reg_index] : reg_ctx->rcb_buf[0],
694 reg_ctx->rcb_info);
695
696 }
697
698 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
699 FILE *fp_rcb = NULL;
700 char name[50];
701 void *base = NULL;
702 snprintf(name, sizeof(name), "/data/tmp/rkv_rcb_%03d.bin", p_hal->frame_no);
703 fp_rcb = fopen(name, "wb");
704 base = mpp_buffer_get_ptr(reg_ctx->rcb_buf[0]);
705 fwrite(base, 1, reg_ctx->rcb_buf_size, fp_rcb);
706 fclose(fp_rcb);
707
708 }
709
710 vdpu34x_setup_statistic(®s->common, ®s->statistic);
711 mpp_buffer_sync_end(reg_ctx->bufs);
712
713 /* enable reference frame usage feedback */
714 regs->statistic.reg265.perf_cnt0_sel = 42;
715 regs->statistic.reg266_perf_cnt0 = 0;
716
717 __RETURN:
718 AVS2D_HAL_TRACE("Out. ret %d", ret);
719 return ret;
720 }
721
hal_avs2d_rkv_dump_reg_write(void * hal,Vdpu34xAvs2dRegSet * regs)722 static MPP_RET hal_avs2d_rkv_dump_reg_write(void *hal, Vdpu34xAvs2dRegSet *regs)
723 {
724 MPP_RET ret = MPP_OK;
725 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
726 FILE *fp_reg = NULL;
727 RK_U32 i = 0;
728 char name[50];
729 snprintf(name, sizeof(name), "/data/tmp/rkv_reg_write_%03d.txt", p_hal->frame_no);
730 fp_reg = fopen(name , "w+");
731
732 fprintf(fp_reg, "********Frame num %d\n", p_hal->frame_no);
733 for (i = 0; i < 8; i++)
734 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i, 0);
735
736 for (i = 0; i < sizeof(Vdpu34xRegCommon) / sizeof(RK_U32); i++)
737 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_COMMON_REGS / sizeof(RK_U32)),
738 ((RK_U32 *)®s->common)[i]);
739
740 for (i = 0; i < 63 - 32; i++)
741 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 33, 0);
742
743 for (i = 0; i < sizeof(Vdpu34xRegAvs2dParam) / sizeof(RK_U32); i++)
744 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_PARAMS_REGS / sizeof(RK_U32)),
745 ((RK_U32 *)®s->avs2d_param)[i]);
746
747 for (i = 0; i < 127 - 112; i++)
748 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 113, 0);
749
750 for (i = 0; i < sizeof(Vdpu34xRegCommonAddr) / sizeof(RK_U32); i++)
751 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_COMMON_ADDR_REGS / sizeof(RK_U32)),
752 ((RK_U32 *)®s->common_addr)[i]);
753
754 for (i = 0; i < 159 - 142; i++)
755 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 143, 0);
756
757
758 for (i = 0; i < sizeof(Vdpu34xRegAvs2dAddr) / sizeof(RK_U32); i++ )
759 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_ADDR_REGS / sizeof(RK_U32)),
760 ((RK_U32 *)®s->avs2d_addr)[i]);
761
762 for (i = 0; i < 223 - 197; i++)
763 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 198, 0);
764
765 for (i = 0; i < sizeof(Vdpu34xRegIrqStatus) / sizeof(RK_U32); i++ )
766 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_INTERRUPT_REGS / sizeof(RK_U32)),
767 ((RK_U32 *)®s->irq_status)[i]);
768
769 for (i = 0; i < 255 - 237; i++)
770 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 238, 0);
771
772 for (i = 0; i < sizeof(Vdpu34xRegStatistic) / sizeof(RK_U32); i++ )
773 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_STATISTIC_REGS / sizeof(RK_U32)),
774 ((RK_U32 *)®s->statistic)[i]);
775
776 fclose(fp_reg);
777 return ret;
778 }
779
hal_avs2d_rkv_dump_stream(void * hal,HalTaskInfo * task)780 static MPP_RET hal_avs2d_rkv_dump_stream(void *hal, HalTaskInfo *task)
781 {
782 MPP_RET ret = MPP_OK;
783 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
784
785 FILE *fp_stream = NULL;
786 char name[50];
787 MppBuffer buffer = NULL;
788 void *base = NULL;
789 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &buffer);
790 base = mpp_buffer_get_ptr(buffer);
791 snprintf(name, sizeof(name), "/data/tmp/rkv_stream_in_%03d.bin", p_hal->frame_no);
792 fp_stream = fopen(name, "wb");
793 fwrite(base, 1, mpp_packet_get_length(task->dec.input_packet), fp_stream);
794 fclose(fp_stream);
795
796 return ret;
797 }
798
hal_avs2d_rkv_start(void * hal,HalTaskInfo * task)799 MPP_RET hal_avs2d_rkv_start(void *hal, HalTaskInfo *task)
800 {
801 MPP_RET ret = MPP_OK;
802 Vdpu34xAvs2dRegSet *regs = NULL;
803 Avs2dRkvRegCtx_t *reg_ctx;
804 MppDev dev = NULL;
805 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
806
807 AVS2D_HAL_TRACE("In.");
808 INP_CHECK(ret, NULL == p_hal);
809
810 if ((task->dec.flags.parse_err || task->dec.flags.ref_err) &&
811 !p_hal->cfg->base.disable_error) {
812 ret = MPP_NOK;
813 goto __RETURN;
814 }
815
816 reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
817 regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
818 dev = p_hal->dev;
819
820 p_hal->frame_no++;
821
822 do {
823 MppDevRegWrCfg wr_cfg;
824 MppDevRegRdCfg rd_cfg;
825
826 wr_cfg.reg = ®s->common;
827 wr_cfg.size = sizeof(regs->common);
828 wr_cfg.offset = OFFSET_COMMON_REGS;
829
830 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
831
832 if (ret) {
833 mpp_err_f("set register write failed %d\n", ret);
834 break;
835 }
836
837 wr_cfg.reg = ®s->avs2d_param;
838 wr_cfg.size = sizeof(regs->avs2d_param);
839 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
840
841 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
842
843 if (ret) {
844 mpp_err_f("set register write failed %d\n", ret);
845 break;
846 }
847
848 wr_cfg.reg = ®s->common_addr;
849 wr_cfg.size = sizeof(regs->common_addr);
850 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
851
852 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
853
854 if (ret) {
855 mpp_err_f("set register write failed %d\n", ret);
856 break;
857 }
858
859 wr_cfg.reg = ®s->avs2d_addr;
860 wr_cfg.size = sizeof(regs->avs2d_addr);
861 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
862
863 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
864
865 if (ret) {
866 mpp_err_f("set register write failed %d\n", ret);
867 break;
868 }
869
870 wr_cfg.reg = ®s->statistic;
871 wr_cfg.size = sizeof(regs->statistic);
872 wr_cfg.offset = OFFSET_STATISTIC_REGS;
873 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
874
875 if (ret) {
876 mpp_err_f("set register write failed %d\n", ret);
877 break;
878 }
879
880 rd_cfg.reg = ®s->irq_status;
881 rd_cfg.size = sizeof(regs->irq_status);
882 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
883 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
884
885 if (ret) {
886 mpp_err_f("set register read failed %d\n", ret);
887 break;
888 }
889
890 rd_cfg.reg = ®s->avs2d_param;
891 rd_cfg.size = sizeof(regs->avs2d_param);
892 rd_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
893 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
894
895 if (ret) {
896 mpp_err_f("set register read failed %d\n", ret);
897 break;
898 }
899
900 rd_cfg.reg = ®s->statistic;
901 rd_cfg.size = sizeof(regs->statistic);
902 rd_cfg.offset = OFFSET_STATISTIC_REGS;
903 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
904
905 if (ret) {
906 mpp_err_f("set register write failed %d\n", ret);
907 break;
908 }
909
910 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
911 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out));
912 rd_cfg.reg = reg_ctx->reg_out;
913 rd_cfg.size = sizeof(reg_ctx->reg_out);
914 rd_cfg.offset = 0;
915 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
916 }
917
918 // rcb info for sram
919 vdpu34x_set_rcbinfo(dev, reg_ctx->rcb_info);
920
921 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN)
922 hal_avs2d_rkv_dump_stream(hal, task);
923
924 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG)
925 hal_avs2d_rkv_dump_reg_write(hal, regs);
926
927 // send request to hardware
928 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
929 if (ret) {
930 mpp_err_f("send cmd failed %d\n", ret);
931 break;
932 }
933
934 } while (0);
935
936 __RETURN:
937 AVS2D_HAL_TRACE("Out.");
938 return ret;
939 }
940
941
fetch_data(RK_U32 fmt,RK_U8 * line,RK_U32 num)942 static RK_U8 fetch_data(RK_U32 fmt, RK_U8 *line, RK_U32 num)
943 {
944 RK_U32 offset = 0;
945 RK_U32 value = 0;
946
947 if (fmt == MPP_FMT_YUV420SP_10BIT) {
948 offset = (num * 2) & 7;
949 value = (line[num * 10 / 8] >> offset) |
950 (line[num * 10 / 8 + 1] << (8 - offset));
951
952 value = (value & 0x3ff) >> 2;
953 } else if (fmt == MPP_FMT_YUV420SP) {
954 value = line[num];
955 }
956
957 return value;
958 }
959
hal_avs2d_rkv_dump_yuv(void * hal,HalTaskInfo * task)960 static MPP_RET hal_avs2d_rkv_dump_yuv(void *hal, HalTaskInfo *task)
961 {
962 MPP_RET ret = MPP_OK;
963 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
964
965 MppFrameFormat fmt = MPP_FMT_YUV420SP;
966 RK_U32 vir_w = 0;
967 RK_U32 vir_h = 0;
968 RK_U32 i = 0;
969 RK_U32 j = 0;
970 FILE *fp_stream = NULL;
971 char name[50];
972 MppBuffer buffer = NULL;
973 MppFrame frame;
974 void *base = NULL;
975
976 ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_FRAME_PTR, &frame);
977
978 if (ret != MPP_OK || frame == NULL)
979 mpp_log_f("failed to get frame slot %d", task->dec.output);
980
981 ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_BUFFER, &buffer);
982
983 if (ret != MPP_OK || buffer == NULL)
984 mpp_log_f("failed to get frame buffer slot %d", task->dec.output);
985
986 AVS2D_HAL_TRACE("frame slot %d, fd %d\n", task->dec.output, mpp_buffer_get_fd(buffer));
987 base = mpp_buffer_get_ptr(buffer);
988 vir_w = mpp_frame_get_hor_stride(frame);
989 vir_h = mpp_frame_get_ver_stride(frame);
990 fmt = mpp_frame_get_fmt(frame);
991 snprintf(name, sizeof(name), "/data/tmp/rkv_out_%dx%d_nv12_%03d.yuv", vir_w, vir_h,
992 p_hal->frame_no);
993 fp_stream = fopen(name, "wb");
994 /* if format is fbc, write fbc header first */
995 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
996 RK_U32 header_size = 0;
997
998 header_size = vir_w * vir_h / 16;
999 fwrite(base, 1, header_size, fp_stream);
1000 base += header_size;
1001 }
1002
1003 if (fmt != MPP_FMT_YUV420SP_10BIT) {
1004 fwrite(base, 1, vir_w * vir_h * 3 / 2, fp_stream);
1005 } else {
1006 RK_U8 tmp = 0;
1007 for (i = 0; i < vir_h; i++) {
1008 for (j = 0; j < vir_w; j++) {
1009 tmp = fetch_data(fmt, base, j);
1010 fwrite(&tmp, 1, 1, fp_stream);
1011 }
1012 base += vir_w;
1013 }
1014
1015 for (i = 0; i < vir_h / 2; i++) {
1016 for (j = 0; j < vir_w; j++) {
1017 tmp = fetch_data(fmt, base, j);
1018 fwrite(&tmp, 1, 1, fp_stream);
1019 }
1020 base += vir_w;
1021 }
1022 }
1023 fclose(fp_stream);
1024
1025 return ret;
1026 }
1027
hal_avs2d_rkv_wait(void * hal,HalTaskInfo * task)1028 MPP_RET hal_avs2d_rkv_wait(void *hal, HalTaskInfo *task)
1029 {
1030 MPP_RET ret = MPP_OK;
1031 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
1032 Avs2dRkvRegCtx_t *reg_ctx;
1033 Vdpu34xAvs2dRegSet *p_regs;
1034
1035 INP_CHECK(ret, NULL == p_hal);
1036 reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
1037 p_regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
1038
1039 if ((task->dec.flags.parse_err || task->dec.flags.ref_err) &&
1040 !p_hal->cfg->base.disable_error) {
1041 AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "found task error.\n");
1042 ret = MPP_NOK;
1043 goto __RETURN;
1044 } else {
1045 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1046 if (ret)
1047 mpp_err_f("poll cmd failed %d\n", ret);
1048 }
1049
1050 if (avs2d_hal_debug & AVS2D_HAL_DBG_OUT)
1051 hal_avs2d_rkv_dump_yuv(hal, task);
1052
1053 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
1054 FILE *fp_reg = NULL;
1055 RK_U32 i = 0;
1056 char name[50];
1057 snprintf(name, sizeof(name), "/data/tmp/rkv_reg_read_%03d.txt", p_hal->frame_no);
1058 fp_reg = fopen(name , "w+");
1059
1060 for (i = 0; i < 278; i++)
1061 fprintf(fp_reg, "%08x\n", reg_ctx->reg_out[i]);
1062
1063 fclose(fp_reg);
1064 }
1065
1066 AVS2D_HAL_TRACE("read reg[224] 0x%08x\n", p_regs->irq_status.reg224);
1067
1068 if (p_hal->dec_cb) {
1069 DecCbHalDone param;
1070
1071 param.task = (void *)&task->dec;
1072 param.regs = (RK_U32 *)p_regs;
1073
1074 if (p_regs->irq_status.reg224.dec_error_sta ||
1075 (!p_regs->irq_status.reg224.dec_rdy_sta) ||
1076 p_regs->irq_status.reg224.buf_empty_sta ||
1077 p_regs->irq_status.reg226.strmd_error_status ||
1078 p_regs->irq_status.reg227.colmv_error_ref_picidx ||
1079 p_regs->irq_status.reg225.strmd_detect_error_flag)
1080 param.hard_err = 1;
1081 else
1082 param.hard_err = 0;
1083
1084 task->dec.flags.ref_used = p_regs->statistic.reg266_perf_cnt0;
1085 task->dec.flags.ref_info_valid = 1;
1086
1087 if (task->dec.flags.ref_miss) {
1088 RK_U32 ref_hw_usage = p_regs->statistic.reg266_perf_cnt0;
1089
1090 AVS2D_HAL_TRACE("hal frame %d ref miss %x hard_err %d hw_usage %x", p_hal->frame_no,
1091 task->dec.flags.ref_miss, param.hard_err, ref_hw_usage);
1092 }
1093
1094 AVS2D_HAL_TRACE("hal frame %d hard_err= %d", p_hal->frame_no, param.hard_err);
1095
1096 mpp_callback(p_hal->dec_cb, ¶m);
1097 }
1098
1099 memset(&p_regs->irq_status.reg224, 0, sizeof(RK_U32));
1100
1101 if (p_hal->fast_mode)
1102 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
1103
1104 __RETURN:
1105 AVS2D_HAL_TRACE("Out. ret %d", ret);
1106 return ret;
1107 }
1108
1109 const MppHalApi hal_avs2d_rkvdpu = {
1110 .name = "avs2d_rkvdpu",
1111 .type = MPP_CTX_DEC,
1112 .coding = MPP_VIDEO_CodingAVS2,
1113 .ctx_size = sizeof(Avs2dRkvRegCtx_t),
1114 .flag = 0,
1115 .init = hal_avs2d_rkv_init,
1116 .deinit = hal_avs2d_rkv_deinit,
1117 .reg_gen = hal_avs2d_rkv_gen_regs,
1118 .start = hal_avs2d_rkv_start,
1119 .wait = hal_avs2d_rkv_wait,
1120 .reset = NULL,
1121 .flush = NULL,
1122 .control = NULL,
1123 };
1124