1 /*
2 * Copyright 2021 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_avs2d_rkv"
18
19 #include <string.h>
20 #include <stdio.h>
21
22 #include "mpp_log.h"
23 #include "mpp_mem.h"
24 #include "mpp_common.h"
25 #include "mpp_debug.h"
26 #include "mpp_bitput.h"
27
28 #include "avs2d_syntax.h"
29 #include "hal_avs2d_api.h"
30 #include "hal_avs2d_rkv.h"
31 #include "mpp_dec_cb_param.h"
32 #include "vdpu34x_avs2d.h"
33 #include "rk_hdr_meta_com.h"
34
35 #define VDPU34X_FAST_REG_SET_CNT (3)
36 #define MAX_REF_NUM (8)
37 #define AVS2_RKV_SHPH_SIZE (1408 / 8) /* bytes */
38 #define AVS2_RKV_SCALIST_SIZE (80 + 128) /* bytes */
39 #define VDPU34x_TOTAL_REG_CNT (278)
40
41 #define AVS2_RKV_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SHPH_SIZE, SZ_4K))
42 #define AVS2_RKV_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SCALIST_SIZE, SZ_4K))
43 #define AVS2_RKV_STREAM_INFO_SET_SIZE (AVS2_RKV_SHPH_ALIGNED_SIZE + \
44 AVS2_RKV_SCALIST_ALIGNED_SIZE)
45 #define AVS2_ALL_TBL_BUF_SIZE(cnt) (AVS2_RKV_STREAM_INFO_SET_SIZE * (cnt))
46 #define AVS2_SHPH_OFFSET(pos) (AVS2_RKV_STREAM_INFO_SET_SIZE * (pos))
47 #define AVS2_SCALIST_OFFSET(pos) (AVS2_SHPH_OFFSET(pos) + AVS2_RKV_SHPH_ALIGNED_SIZE)
48
49 #define COLMV_COMPRESS_EN (1)
50 #define COLMV_BLOCK_SIZE (16)
51 #define COLMV_BYTES (16)
52
53 typedef struct avs2d_buf_t {
54 RK_U32 valid;
55 RK_U32 offset_shph;
56 RK_U32 offset_sclst;
57 Vdpu34xAvs2dRegSet *regs;
58 } Avs2dRkvBuf_t;
59
60 typedef struct avs2d_reg_ctx_t {
61 Avs2dRkvBuf_t reg_buf[VDPU34X_FAST_REG_SET_CNT];
62
63 RK_U32 shph_offset;
64 RK_U32 sclst_offset;
65
66 Vdpu34xAvs2dRegSet *regs;
67
68 RK_U8 shph_dat[AVS2_RKV_SHPH_SIZE];
69 RK_U8 scalist_dat[AVS2_RKV_SCALIST_SIZE];
70
71 MppBuffer bufs;
72 RK_S32 bufs_fd;
73 void *bufs_ptr;
74
75 MppBuffer rcb_buf[VDPU34X_FAST_REG_SET_CNT];
76 RK_S32 rcb_buf_size;
77 Vdpu34xRcbInfo rcb_info[RCB_BUF_COUNT];
78 RK_U32 reg_out[VDPU34x_TOTAL_REG_CNT];
79
80 } Avs2dRkvRegCtx_t;
81
avs2d_ver_align(RK_U32 val)82 static RK_U32 avs2d_ver_align(RK_U32 val)
83 {
84 return MPP_ALIGN(val, 16);
85 }
86
avs2d_hor_align(RK_U32 val)87 static RK_U32 avs2d_hor_align(RK_U32 val)
88 {
89
90 return MPP_ALIGN(val, 16);
91 }
92
avs2d_len_align(RK_U32 val)93 static RK_U32 avs2d_len_align(RK_U32 val)
94 {
95 return (2 * MPP_ALIGN(val, 16));
96 }
97
avs2d_hor_align_64(RK_U32 val)98 static RK_U32 avs2d_hor_align_64(RK_U32 val)
99 {
100 return MPP_ALIGN(val, 64);
101 }
102
prepare_header(Avs2dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)103 static MPP_RET prepare_header(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
104 {
105 RK_U32 i, j;
106 BitputCtx_t bp;
107 RK_U64 *bit_buf = (RK_U64 *)data;
108 Avs2dSyntax_t *syntax = &p_hal->syntax;
109 PicParams_Avs2d *pp = &syntax->pp;
110 AlfParams_Avs2d *alfp = &syntax->alfp;
111 RefParams_Avs2d *refp = &syntax->refp;
112 WqmParams_Avs2d *wqmp = &syntax->wqmp;
113
114 memset(data, 0, len);
115
116 mpp_set_bitput_ctx(&bp, bit_buf, len);
117 //!< sequence header syntax
118 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
119 mpp_put_bits(&bp, pp->pic_width_in_luma_samples, 16);
120 mpp_put_bits(&bp, pp->pic_height_in_luma_samples, 16);
121 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
122 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
123 mpp_put_bits(&bp, pp->lcu_size, 3);
124 mpp_put_bits(&bp, pp->progressive_sequence, 1);
125 mpp_put_bits(&bp, pp->field_coded_sequence, 1);
126 mpp_put_bits(&bp, pp->multi_hypothesis_skip_enable_flag, 1);
127 mpp_put_bits(&bp, pp->dual_hypothesis_prediction_enable_flag, 1);
128 mpp_put_bits(&bp, pp->weighted_skip_enable_flag, 1);
129 mpp_put_bits(&bp, pp->asymmetrc_motion_partitions_enable_flag, 1);
130 mpp_put_bits(&bp, pp->nonsquare_quadtree_transform_enable_flag, 1);
131 mpp_put_bits(&bp, pp->nonsquare_intra_prediction_enable_flag, 1);
132 mpp_put_bits(&bp, pp->secondary_transform_enable_flag, 1);
133 mpp_put_bits(&bp, pp->sample_adaptive_offset_enable_flag, 1);
134 mpp_put_bits(&bp, pp->adaptive_loop_filter_enable_flag, 1);
135 mpp_put_bits(&bp, pp->pmvr_enable_flag, 1);
136 mpp_put_bits(&bp, pp->cross_slice_loopfilter_enable_flag, 1);
137 //!< picture header syntax
138 mpp_put_bits(&bp, pp->picture_type, 3);
139 mpp_put_bits(&bp, refp->ref_pic_num, 3);
140 mpp_put_bits(&bp, pp->scene_reference_enable_flag, 1);
141 mpp_put_bits(&bp, pp->bottom_field_picture_flag, 1);
142 mpp_put_bits(&bp, pp->fixed_picture_qp, 1);
143 mpp_put_bits(&bp, pp->picture_qp, 7);
144 mpp_put_bits(&bp, pp->loop_filter_disable_flag, 1);
145 mpp_put_bits(&bp, pp->alpha_c_offset, 5);
146 mpp_put_bits(&bp, pp->beta_offset, 5);
147 //!< weight quant param
148 mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cb, 6);
149 mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cr, 6);
150 mpp_put_bits(&bp, wqmp->pic_weight_quant_enable_flag, 1);
151 //!< alf param
152 mpp_put_bits(&bp, alfp->enable_pic_alf_y, 1);
153 mpp_put_bits(&bp, alfp->enable_pic_alf_cb, 1);
154 mpp_put_bits(&bp, alfp->enable_pic_alf_cr, 1);
155
156 if (alfp->enable_pic_alf_y) {
157 RK_U32 alf_filter_num = alfp->alf_filter_num_minus1 + 1;
158 mpp_put_bits(&bp, alfp->alf_filter_num_minus1, 4);
159
160 for (i = 0; i < 16; i++)
161 mpp_put_bits(&bp, alfp->alf_coeff_idx_tab[i], 4);
162
163 for (i = 0; i < alf_filter_num; i++) {
164 for (j = 0; j < 9; j++) {
165 mpp_put_bits(&bp, alfp->alf_coeff_y[i][j], 7);
166 }
167 }
168 }
169
170 if (alfp->enable_pic_alf_cb) {
171 for (j = 0; j < 9; j++)
172 mpp_put_bits(&bp, alfp->alf_coeff_cb[j], 7);
173 }
174
175 if (alfp->enable_pic_alf_cr) {
176 for (j = 0; j < 9; j++)
177 mpp_put_bits(&bp, alfp->alf_coeff_cr[j], 7);
178 }
179
180 mpp_put_align(&bp, 128, 0);
181
182 return MPP_OK;
183 }
184
prepare_scalist(Avs2dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)185 static MPP_RET prepare_scalist(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
186 {
187 RK_U32 i, j;
188 RK_U32 size_id, block_size;
189 BitputCtx_t bp;
190 RK_U64 *bit_buf = (RK_U64 *)data;
191 Avs2dSyntax_t *syntax = &p_hal->syntax;
192 WqmParams_Avs2d *wqmp = &syntax->wqmp;
193
194 if (!wqmp->pic_weight_quant_enable_flag)
195 return MPP_OK;
196
197 memset(data, 0, len);
198
199 mpp_set_bitput_ctx(&bp, bit_buf, len);
200
201 for (size_id = 0; size_id < 2; size_id++) {
202 block_size = MPP_MIN(1 << (size_id + 2), 8);
203 for (i = 0; i < block_size; i++) {
204 for (j = 0 ; j < block_size; j++)
205 //!< row col reversed
206 mpp_put_bits(&bp, wqmp->wq_matrix[size_id][size_id * j + i], 8);
207 }
208 }
209
210 return MPP_OK;
211 }
212
get_frame_fd(Avs2dHalCtx_t * p_hal,RK_S32 idx)213 static RK_S32 get_frame_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
214 {
215 RK_S32 ret_fd = 0;
216 MppBuffer mbuffer = NULL;
217
218 mpp_buf_slot_get_prop(p_hal->frame_slots, idx, SLOT_BUFFER, &mbuffer);
219 ret_fd = mpp_buffer_get_fd(mbuffer);
220
221 return ret_fd;
222 }
223
get_packet_fd(Avs2dHalCtx_t * p_hal,RK_S32 idx)224 static RK_S32 get_packet_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
225 {
226 RK_S32 ret_fd = 0;
227 MppBuffer mbuffer = NULL;
228
229 mpp_buf_slot_get_prop(p_hal->packet_slots, idx, SLOT_BUFFER, &mbuffer);
230 ret_fd = mpp_buffer_get_fd(mbuffer);
231
232 return ret_fd;
233 }
234
init_common_regs(Vdpu34xAvs2dRegSet * regs)235 static MPP_RET init_common_regs(Vdpu34xAvs2dRegSet *regs)
236 {
237 Vdpu34xRegCommon *common = ®s->common;
238
239 common->reg009.dec_mode = 3; // AVS2
240 common->reg015.rlc_mode = 0;
241
242 common->reg011.buf_empty_en = 1;
243 common->reg011.dec_timeout_e = 1;
244
245 common->reg010.dec_e = 1;
246
247 common->reg013.h26x_error_mode = 0;
248 common->reg013.colmv_error_mode = 0;
249 common->reg013.h26x_streamd_error_mode = 0;
250 common->reg021.inter_error_prc_mode = 0;
251 common->reg021.error_deb_en = 0;
252 common->reg021.error_intra_mode = 0;
253
254 common->reg024.cabac_err_en_lowbits = 0xffffffdf;
255 common->reg025.cabac_err_en_highbits = 0x3dffffff;
256
257 common->reg026.swreg_block_gating_e =
258 (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) ? 0xfffef : 0xfffff;
259 common->reg026.reg_cfg_gating_en = 1;
260 common->reg032_timeout_threshold = 0x0fffffff;
261
262 common->reg011.dec_clkgate_e = 1;
263 common->reg011.dec_e_strmd_clkgate_dis = 0;
264 common->reg011.dec_timeout_e = 1;
265
266 common->reg013.timeout_mode = 1;
267 common->reg013.stmerror_waitdecfifo_empty = 1;
268 common->reg012.colmv_compress_en = COLMV_COMPRESS_EN;
269 common->reg012.wr_ddr_align_en = 1;
270 common->reg012.info_collect_en = 1;
271 common->reg012.error_info_en = 0;
272
273 return MPP_OK;
274 }
275
276 //TODO calc rcb buffer size;
277 /*
278 static void avs2d_refine_rcb_size(Vdpu34xRcbInfo *rcb_info,
279 Vdpu34xAvs2dRegSet *hw_regs,
280 RK_S32 width, RK_S32 height, void *dxva)
281 {
282 (void) rcb_info;
283 (void) hw_regs;
284 (void) width;
285 (void) height;
286 (void) dxva;
287 return;
288 }
289 */
290
hal_avs2d_rcb_info_update(void * hal,Vdpu34xAvs2dRegSet * hw_regs)291 static void hal_avs2d_rcb_info_update(void *hal, Vdpu34xAvs2dRegSet *hw_regs)
292 {
293 MPP_RET ret = MPP_OK;
294 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
295 Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
296 RK_S32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
297 RK_S32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
298 RK_S32 i = 0;
299 RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
300
301 (void) hw_regs;
302
303 reg_ctx->rcb_buf_size = vdpu34x_get_rcb_buf_size(reg_ctx->rcb_info, width, height);
304 //avs2d_refine_rcb_size(reg_ctx->rcb_info, hw_regs, width, height, (void *)&p_hal->syntax);
305
306 for (i = 0; i < loop; i++) {
307 MppBuffer rcb_buf = NULL;
308
309 if (reg_ctx->rcb_buf[i]) {
310 mpp_buffer_put(reg_ctx->rcb_buf[i]);
311 reg_ctx->rcb_buf[i] = NULL;
312 }
313
314 ret = mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size);
315
316 if (ret)
317 mpp_err_f("AVS2D mpp_buffer_group_get failed\n");
318
319 reg_ctx->rcb_buf[i] = rcb_buf;
320 }
321 }
322
fill_registers(Avs2dHalCtx_t * p_hal,Vdpu34xAvs2dRegSet * p_regs,HalTaskInfo * task)323 static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu34xAvs2dRegSet *p_regs, HalTaskInfo *task)
324 {
325 MPP_RET ret = MPP_OK;
326 RK_U32 i;
327 MppFrame mframe = NULL;
328 Avs2dSyntax_t *syntax = &p_hal->syntax;
329 PicParams_Avs2d *pp = &syntax->pp;
330 RefParams_Avs2d *refp = &syntax->refp;
331 HalDecTask *task_dec = &task->dec;
332 Vdpu34xRegCommon *common = &p_regs->common;
333 RK_U32 is_fbc = 0;
334 HalBuf *mv_buf = NULL;
335
336 mpp_buf_slot_get_prop(p_hal->frame_slots, task_dec->output, SLOT_FRAME_PTR, &mframe);
337 is_fbc = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
338
339 //!< caculate the yuv_frame_size
340 {
341 RK_U32 hor_virstride = 0;
342 RK_U32 ver_virstride = 0;
343 RK_U32 y_virstride = 0;
344
345 hor_virstride = mpp_frame_get_hor_stride(mframe);
346 ver_virstride = mpp_frame_get_ver_stride(mframe);
347 y_virstride = hor_virstride * ver_virstride;
348 AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride);
349
350 if (is_fbc) {
351 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
352 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
353
354 common->reg012.fbc_e = 1;
355 common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
356 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
357 common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
358 } else {
359 common->reg012.fbc_e = 0;
360 common->reg018.y_hor_virstride = hor_virstride / 16;
361 common->reg019.uv_hor_virstride = hor_virstride / 16;
362 common->reg020_y_virstride.y_virstride = y_virstride / 16;
363 }
364 common->reg013.cur_pic_is_idr = (pp->picture_type == 0 || pp->picture_type == 4 || pp->picture_type == 5);
365 }
366
367 // set current
368 {
369 RK_S32 fd = -1;
370 p_regs->avs2d_param.reg65_cur_top_poc = mpp_frame_get_poc(mframe);
371 p_regs->avs2d_param.reg66_cur_bot_poc = 0;
372 fd = get_frame_fd(p_hal, task_dec->output);
373 mpp_assert(fd >= 0);
374 p_regs->common_addr.reg130_decout_base = fd;
375 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, task_dec->output);
376 p_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
377 AVS2D_HAL_TRACE("cur frame index %d, fd %d, colmv fd %d", task_dec->output, fd, p_regs->common_addr.reg131_colmv_cur_base);
378 }
379
380 // set reference
381 {
382 RK_U64 ref_flag = 0;
383 RK_S32 valid_slot = -1;
384 RK_U32 *ref_low = (RK_U32 *)&p_regs->avs2d_param.reg99;
385 RK_U32 *ref_hight = (RK_U32 *)&p_regs->avs2d_param.reg100;
386
387 AVS2D_HAL_TRACE("num of ref %d", refp->ref_pic_num);
388
389 for (i = 0; i < refp->ref_pic_num; i++) {
390 if (task_dec->refer[i] < 0)
391 continue;
392
393 valid_slot = i;
394 break;
395 }
396
397 for (i = 0; i < refp->ref_pic_num; i++) {
398 MppFrame frame_ref = NULL;
399
400 RK_S32 slot_idx = task_dec->refer[i] < 0 ? valid_slot : task_dec->refer[i];
401
402 if (slot_idx < 0) {
403 AVS2D_HAL_TRACE("missing ref, could not found valid ref");
404 return ret = MPP_ERR_UNKNOW;
405 }
406
407 mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &frame_ref);
408
409 if (frame_ref) {
410 RK_U32 frm_flag = 1 << 3;
411
412 if (pp->bottom_field_picture_flag)
413 frm_flag |= 1 << 2;
414
415 if (pp->field_coded_sequence)
416 frm_flag |= 1;
417
418 ref_flag |= frm_flag << (i * 8);
419
420 p_regs->avs2d_addr.ref_base[i] = get_frame_fd(p_hal, slot_idx);
421 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
422 p_regs->avs2d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
423
424 p_regs->avs2d_param.reg67_098_ref_poc[i] = mpp_frame_get_poc(frame_ref);
425
426 AVS2D_HAL_TRACE("ref_base[%d] index=%d, fd = %d, colmv %d, poc %d",
427 i, slot_idx, p_regs->avs2d_addr.ref_base[i],
428 p_regs->avs2d_addr.colmv_base[i], p_regs->avs2d_param.reg67_098_ref_poc[i]);
429 }
430 }
431
432 if (p_hal->syntax.refp.scene_ref_enable && p_hal->syntax.refp.scene_ref_slot_idx >= 0) {
433 MppFrame scene_ref = NULL;
434 RK_S32 slot_idx = p_hal->syntax.refp.scene_ref_slot_idx;
435 RK_S32 replace_idx = p_hal->syntax.refp.scene_ref_replace_pos;
436
437 mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &scene_ref);
438
439 if (scene_ref) {
440 p_regs->avs2d_addr.ref_base[replace_idx] = get_frame_fd(p_hal, slot_idx);
441 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
442 p_regs->avs2d_addr.colmv_base[replace_idx] = mpp_buffer_get_fd(mv_buf->buf[0]);
443 p_regs->avs2d_param.reg67_098_ref_poc[replace_idx] = mpp_frame_get_poc(scene_ref);
444 }
445 }
446
447 *ref_low = (RK_U32) (ref_flag & 0xffffffff);
448 *ref_hight = (RK_U32) ((ref_flag >> 32) & 0xffffffff);
449
450 p_regs->common_addr.reg132_error_ref_base = p_regs->avs2d_addr.ref_base[0];
451 }
452
453 // set rlc
454 {
455 p_regs->common_addr.reg128_rlc_base = get_packet_fd(p_hal, task_dec->input);
456 AVS2D_HAL_TRACE("packet fd %d from slot %d", p_regs->common_addr.reg128_rlc_base, task_dec->input);
457 p_regs->common_addr.reg129_rlcwrite_base = p_regs->common_addr.reg128_rlc_base;
458 common->reg016_str_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64;
459 }
460 if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) && p_hal->cfg->base.enable_hdr_meta)
461 fill_hdr_meta_to_frame(mframe, HDR_AVS2);
462 return ret;
463 }
464
hal_avs2d_rkv_deinit(void * hal)465 MPP_RET hal_avs2d_rkv_deinit(void *hal)
466 {
467 MPP_RET ret = MPP_OK;
468 RK_U32 i, loop;
469 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
470 Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
471
472 AVS2D_HAL_TRACE("In.");
473
474 INP_CHECK(ret, NULL == reg_ctx);
475
476 //!< malloc buffers
477 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
478 for (i = 0; i < loop; i++) {
479 if (reg_ctx->rcb_buf[i]) {
480 mpp_buffer_put(reg_ctx->rcb_buf[i]);
481 reg_ctx->rcb_buf[i] = NULL;
482 }
483
484 MPP_FREE(reg_ctx->reg_buf[i].regs);
485 }
486
487 if (reg_ctx->bufs) {
488 mpp_buffer_put(reg_ctx->bufs);
489 reg_ctx->bufs = NULL;
490 }
491
492 if (p_hal->cmv_bufs) {
493 hal_bufs_deinit(p_hal->cmv_bufs);
494 p_hal->cmv_bufs = NULL;
495 }
496
497 MPP_FREE(p_hal->reg_ctx);
498
499 __RETURN:
500 AVS2D_HAL_TRACE("Out. ret %d", ret);
501 return ret;
502 }
503
hal_avs2d_rkv_init(void * hal,MppHalCfg * cfg)504 MPP_RET hal_avs2d_rkv_init(void *hal, MppHalCfg *cfg)
505 {
506 MPP_RET ret = MPP_OK;
507 RK_U32 i, loop;
508 Avs2dRkvRegCtx_t *reg_ctx;
509 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
510
511 AVS2D_HAL_TRACE("In.");
512
513 INP_CHECK(ret, NULL == p_hal);
514
515 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Avs2dRkvRegCtx_t)));
516 reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
517
518 //!< malloc buffers
519 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
520 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs, AVS2_ALL_TBL_BUF_SIZE(loop)));
521 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
522 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
523
524 for (i = 0; i < loop; i++) {
525 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu34xAvs2dRegSet, 1);
526 init_common_regs(reg_ctx->reg_buf[i].regs);
527 reg_ctx->reg_buf[i].offset_shph = AVS2_SHPH_OFFSET(i);
528 reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i);
529 }
530
531 if (!p_hal->fast_mode) {
532 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
533 reg_ctx->shph_offset = reg_ctx->reg_buf[0].offset_shph;
534 reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst;
535 }
536
537 if (MPP_FRAME_FMT_IS_FBC(cfg->cfg->base.out_fmt))
538 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align_64);
539 else
540 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, avs2d_hor_align);
541
542 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
543 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
544
545 {
546 // report hw_info to parser
547 const MppSocInfo *info = mpp_get_soc_info();
548 const void *hw_info = NULL;
549
550 for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
551 if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
552 hw_info = info->dec_caps[i];
553 break;
554 }
555 }
556
557 mpp_assert(hw_info);
558 cfg->hw_info = hw_info;
559 }
560
561 __RETURN:
562 AVS2D_HAL_TRACE("Out. ret %d", ret);
563 (void)cfg;
564 return ret;
565 __FAILED:
566 hal_avs2d_rkv_deinit(p_hal);
567 AVS2D_HAL_TRACE("Out. ret %d", ret);
568 return ret;
569 }
570
set_up_colmv_buf(void * hal)571 static MPP_RET set_up_colmv_buf(void *hal)
572 {
573 MPP_RET ret = MPP_OK;
574 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
575 Avs2dSyntax_t *syntax = &p_hal->syntax;
576 PicParams_Avs2d *pp = &syntax->pp;
577 RK_U32 mv_size = 0;
578
579 RK_U32 ctu_size = 1 << (p_hal->syntax.pp.lcu_size);
580 RK_U32 segment_w = 64 * COLMV_BLOCK_SIZE * COLMV_BLOCK_SIZE / ctu_size;
581 RK_U32 segment_h = ctu_size;
582 RK_U32 pic_w_align = MPP_ALIGN(pp->pic_width_in_luma_samples, segment_w);
583 RK_U32 pic_h_align = MPP_ALIGN(pp->pic_height_in_luma_samples, segment_h);
584 RK_U32 seg_cnt_w = pic_w_align / segment_w;
585 RK_U32 seg_cnt_h = pic_h_align / segment_h;
586 RK_U32 seg_head_line_size = MPP_ALIGN(seg_cnt_w, 16);
587 RK_U32 seg_head_size = seg_head_line_size * seg_cnt_h;
588 RK_U32 seg_payload_size = seg_cnt_w * seg_cnt_h * 64 * COLMV_BYTES;
589
590 if (COLMV_COMPRESS_EN)
591 mv_size = seg_payload_size + seg_head_size;
592 else
593 mv_size = (MPP_ALIGN(p_hal->syntax.pp.pic_width_in_luma_samples, 64) *
594 MPP_ALIGN(p_hal->syntax.pp.pic_height_in_luma_samples, 64)) >> 5;
595
596 // colmv frame size align to 128byte
597 if ((mv_size / 8) % 2 == 1) {
598 mv_size += 8;
599 }
600
601 if (pp->field_coded_sequence)
602 mv_size *= 2;
603 AVS2D_HAL_TRACE("mv_size %d", mv_size);
604
605 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
606 size_t size = mv_size;
607
608 if (p_hal->cmv_bufs) {
609 hal_bufs_deinit(p_hal->cmv_bufs);
610 p_hal->cmv_bufs = NULL;
611 }
612
613 hal_bufs_init(&p_hal->cmv_bufs);
614 if (p_hal->cmv_bufs == NULL) {
615 mpp_err_f("colmv bufs init fail");
616 ret = MPP_ERR_INIT;
617 goto __RETURN;
618 }
619
620 p_hal->mv_size = mv_size;
621 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
622 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
623 }
624
625 __RETURN:
626 return ret;
627 }
628
hal_avs2d_rkv_gen_regs(void * hal,HalTaskInfo * task)629 MPP_RET hal_avs2d_rkv_gen_regs(void *hal, HalTaskInfo *task)
630 {
631 MPP_RET ret = MPP_OK;
632 Avs2dRkvRegCtx_t *reg_ctx;
633 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
634 Vdpu34xAvs2dRegSet *regs = NULL;
635
636 AVS2D_HAL_TRACE("In.");
637
638 INP_CHECK(ret, NULL == p_hal);
639
640 if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
641 ret = MPP_NOK;
642 goto __RETURN;
643 }
644
645 ret = set_up_colmv_buf(p_hal);
646 if (ret)
647 goto __RETURN;
648
649 reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
650
651 if (p_hal->fast_mode) {
652 RK_U32 i = 0;
653
654 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
655 if (!reg_ctx->reg_buf[i].valid) {
656 task->dec.reg_index = i;
657 regs = reg_ctx->reg_buf[i].regs;
658 reg_ctx->shph_offset = reg_ctx->reg_buf[i].offset_shph;
659 reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst;
660 reg_ctx->regs = reg_ctx->reg_buf[i].regs;
661 reg_ctx->reg_buf[i].valid = 1;
662 break;
663 }
664 }
665
666 mpp_assert(regs);
667 }
668
669 regs = reg_ctx->regs;
670
671 prepare_header(p_hal, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
672 prepare_scalist(p_hal, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
673
674 ret = fill_registers(p_hal, regs, task);
675
676 if (ret)
677 goto __RETURN;
678
679 {
680 memcpy(reg_ctx->bufs_ptr + reg_ctx->shph_offset, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
681 memcpy(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
682 regs->common.reg012.scanlist_addr_valid_en = 1;
683
684 MppDevRegOffsetCfg trans_cfg;
685 trans_cfg.reg_idx = 161;
686 trans_cfg.offset = reg_ctx->shph_offset;
687 regs->avs2d_addr.head_base = reg_ctx->bufs_fd;
688 mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
689
690 regs->avs2d_param.reg105.head_len = AVS2_RKV_SHPH_SIZE / 16;
691 regs->avs2d_param.reg105.head_len -= (regs->avs2d_param.reg105.head_len > 0) ? 1 : 0;
692
693 trans_cfg.reg_idx = 180;
694 trans_cfg.offset = reg_ctx->sclst_offset;
695 regs->avs2d_addr.scanlist_addr = reg_ctx->bufs_fd;
696 mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
697 }
698
699 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
700 FILE *fp_shph = NULL;
701 char name[50];
702 snprintf(name, sizeof(name), "/data/tmp/rkv_shph_%03d.bin", p_hal->frame_no);
703 fp_shph = fopen(name, "wb");
704 fwrite(reg_ctx->bufs_ptr + reg_ctx->shph_offset, 1, sizeof(reg_ctx->shph_dat), fp_shph);
705 fclose(fp_shph);
706 }
707
708 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
709 FILE *fp_scalist = NULL;
710 char name[50];
711 snprintf(name, sizeof(name), "/data/tmp/rkv_scalist_%03d.bin", p_hal->frame_no);
712 fp_scalist = fopen(name, "wb");
713 fwrite(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, 1, sizeof(reg_ctx->scalist_dat), fp_scalist);
714 fclose(fp_scalist);
715 }
716
717 // set rcb
718 {
719 hal_avs2d_rcb_info_update(p_hal, regs);
720 vdpu34x_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ?
721 reg_ctx->rcb_buf[task->dec.reg_index] : reg_ctx->rcb_buf[0],
722 reg_ctx->rcb_info);
723
724 }
725
726 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {
727 FILE *fp_rcb = NULL;
728 char name[50];
729 void *base = NULL;
730 snprintf(name, sizeof(name), "/data/tmp/rkv_rcb_%03d.bin", p_hal->frame_no);
731 fp_rcb = fopen(name, "wb");
732 base = mpp_buffer_get_ptr(reg_ctx->rcb_buf[0]);
733 fwrite(base, 1, reg_ctx->rcb_buf_size, fp_rcb);
734 fclose(fp_rcb);
735
736 }
737
738 vdpu34x_setup_statistic(®s->common, ®s->statistic);
739 /* enable reference frame usage feedback */
740 regs->statistic.reg265.perf_cnt0_sel = 42;
741 regs->statistic.reg266_perf_cnt0 = 0;
742
743 __RETURN:
744 AVS2D_HAL_TRACE("Out. ret %d", ret);
745 return ret;
746 }
747
hal_avs2d_rkv_dump_reg_write(void * hal,Vdpu34xAvs2dRegSet * regs)748 static MPP_RET hal_avs2d_rkv_dump_reg_write(void *hal, Vdpu34xAvs2dRegSet *regs)
749 {
750 MPP_RET ret = MPP_OK;
751 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
752 FILE *fp_reg = NULL;
753 RK_U32 i = 0;
754 char name[50];
755 snprintf(name, sizeof(name), "/data/tmp/rkv_reg_write_%03d.txt", p_hal->frame_no);
756 fp_reg = fopen(name , "w+");
757
758 fprintf(fp_reg, "********Frame num %d\n", p_hal->frame_no);
759 for (i = 0; i < 8; i++)
760 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i, 0);
761
762 for (i = 0; i < sizeof(Vdpu34xRegCommon) / sizeof(RK_U32); i++)
763 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_COMMON_REGS / sizeof(RK_U32)),
764 ((RK_U32 *)®s->common)[i]);
765
766 for (i = 0; i < 63 - 32; i++)
767 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 33, 0);
768
769 for (i = 0; i < sizeof(Vdpu34xRegAvs2dParam) / sizeof(RK_U32); i++)
770 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_PARAMS_REGS / sizeof(RK_U32)),
771 ((RK_U32 *)®s->avs2d_param)[i]);
772
773 for (i = 0; i < 127 - 112; i++)
774 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 113, 0);
775
776 for (i = 0; i < sizeof(Vdpu34xRegCommonAddr) / sizeof(RK_U32); i++)
777 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_COMMON_ADDR_REGS / sizeof(RK_U32)),
778 ((RK_U32 *)®s->common_addr)[i]);
779
780 for (i = 0; i < 159 - 142; i++)
781 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 143, 0);
782
783
784 for (i = 0; i < sizeof(Vdpu34xRegAvs2dAddr) / sizeof(RK_U32); i++ )
785 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_ADDR_REGS / sizeof(RK_U32)),
786 ((RK_U32 *)®s->avs2d_addr)[i]);
787
788 for (i = 0; i < 223 - 197; i++)
789 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 198, 0);
790
791 for (i = 0; i < sizeof(Vdpu34xRegIrqStatus) / sizeof(RK_U32); i++ )
792 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_INTERRUPT_REGS / sizeof(RK_U32)),
793 ((RK_U32 *)®s->irq_status)[i]);
794
795 for (i = 0; i < 255 - 237; i++)
796 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", i + 238, 0);
797
798 for (i = 0; i < sizeof(Vdpu34xRegStatistic) / sizeof(RK_U32); i++ )
799 fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_STATISTIC_REGS / sizeof(RK_U32)),
800 ((RK_U32 *)®s->statistic)[i]);
801
802 fclose(fp_reg);
803 return ret;
804 }
805
hal_avs2d_rkv_dump_stream(void * hal,HalTaskInfo * task)806 static MPP_RET hal_avs2d_rkv_dump_stream(void *hal, HalTaskInfo *task)
807 {
808 MPP_RET ret = MPP_OK;
809 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
810
811 FILE *fp_stream = NULL;
812 char name[50];
813 MppBuffer buffer = NULL;
814 void *base = NULL;
815 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &buffer);
816 base = mpp_buffer_get_ptr(buffer);
817 snprintf(name, sizeof(name), "/data/tmp/rkv_stream_in_%03d.bin", p_hal->frame_no);
818 fp_stream = fopen(name, "wb");
819 fwrite(base, 1, mpp_packet_get_length(task->dec.input_packet), fp_stream);
820 fclose(fp_stream);
821
822 return ret;
823 }
824
hal_avs2d_rkv_start(void * hal,HalTaskInfo * task)825 MPP_RET hal_avs2d_rkv_start(void *hal, HalTaskInfo *task)
826 {
827 MPP_RET ret = MPP_OK;
828 Vdpu34xAvs2dRegSet *regs = NULL;
829 Avs2dRkvRegCtx_t *reg_ctx;
830 MppDev dev = NULL;
831 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
832
833 AVS2D_HAL_TRACE("In.");
834 INP_CHECK(ret, NULL == p_hal);
835
836 if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
837 ret = MPP_NOK;
838 goto __RETURN;
839 }
840
841 reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
842 regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
843 dev = p_hal->dev;
844
845 p_hal->frame_no++;
846
847 do {
848 MppDevRegWrCfg wr_cfg;
849 MppDevRegRdCfg rd_cfg;
850
851 wr_cfg.reg = ®s->common;
852 wr_cfg.size = sizeof(regs->common);
853 wr_cfg.offset = OFFSET_COMMON_REGS;
854
855 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
856
857 if (ret) {
858 mpp_err_f("set register write failed %d\n", ret);
859 break;
860 }
861
862 wr_cfg.reg = ®s->avs2d_param;
863 wr_cfg.size = sizeof(regs->avs2d_param);
864 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
865
866 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
867
868 if (ret) {
869 mpp_err_f("set register write failed %d\n", ret);
870 break;
871 }
872
873 wr_cfg.reg = ®s->common_addr;
874 wr_cfg.size = sizeof(regs->common_addr);
875 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
876
877 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
878
879 if (ret) {
880 mpp_err_f("set register write failed %d\n", ret);
881 break;
882 }
883
884 wr_cfg.reg = ®s->avs2d_addr;
885 wr_cfg.size = sizeof(regs->avs2d_addr);
886 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
887
888 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
889
890 if (ret) {
891 mpp_err_f("set register write failed %d\n", ret);
892 break;
893 }
894
895 wr_cfg.reg = ®s->statistic;
896 wr_cfg.size = sizeof(regs->statistic);
897 wr_cfg.offset = OFFSET_STATISTIC_REGS;
898 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
899
900 if (ret) {
901 mpp_err_f("set register write failed %d\n", ret);
902 break;
903 }
904
905 rd_cfg.reg = ®s->irq_status;
906 rd_cfg.size = sizeof(regs->irq_status);
907 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
908 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
909
910 if (ret) {
911 mpp_err_f("set register read failed %d\n", ret);
912 break;
913 }
914
915 rd_cfg.reg = ®s->avs2d_param;
916 rd_cfg.size = sizeof(regs->avs2d_param);
917 rd_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
918 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
919
920 if (ret) {
921 mpp_err_f("set register read failed %d\n", ret);
922 break;
923 }
924
925 rd_cfg.reg = ®s->statistic;
926 rd_cfg.size = sizeof(regs->statistic);
927 rd_cfg.offset = OFFSET_STATISTIC_REGS;
928 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
929
930 if (ret) {
931 mpp_err_f("set register write failed %d\n", ret);
932 break;
933 }
934
935 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
936 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out));
937 rd_cfg.reg = reg_ctx->reg_out;
938 rd_cfg.size = sizeof(reg_ctx->reg_out);
939 rd_cfg.offset = 0;
940 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
941 }
942
943 // rcb info for sram
944 vdpu34x_set_rcbinfo(dev, reg_ctx->rcb_info);
945
946 if (avs2d_hal_debug & AVS2D_HAL_DBG_IN)
947 hal_avs2d_rkv_dump_stream(hal, task);
948
949 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG)
950 hal_avs2d_rkv_dump_reg_write(hal, regs);
951
952 // send request to hardware
953 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
954 if (ret) {
955 mpp_err_f("send cmd failed %d\n", ret);
956 break;
957 }
958
959 } while (0);
960
961 __RETURN:
962 AVS2D_HAL_TRACE("Out.");
963 return ret;
964 }
965
966
fetch_data(RK_U32 fmt,RK_U8 * line,RK_U32 num)967 static RK_U8 fetch_data(RK_U32 fmt, RK_U8 *line, RK_U32 num)
968 {
969 RK_U32 offset = 0;
970 RK_U32 value = 0;
971
972 if (fmt == MPP_FMT_YUV420SP_10BIT) {
973 offset = (num * 2) & 7;
974 value = (line[num * 10 / 8] >> offset) |
975 (line[num * 10 / 8 + 1] << (8 - offset));
976
977 value = (value & 0x3ff) >> 2;
978 } else if (fmt == MPP_FMT_YUV420SP) {
979 value = line[num];
980 }
981
982 return value;
983 }
984
hal_avs2d_rkv_dump_yuv(void * hal,HalTaskInfo * task)985 static MPP_RET hal_avs2d_rkv_dump_yuv(void *hal, HalTaskInfo *task)
986 {
987 MPP_RET ret = MPP_OK;
988 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
989
990 MppFrameFormat fmt = MPP_FMT_YUV420SP;
991 RK_U32 vir_w = 0;
992 RK_U32 vir_h = 0;
993 RK_U32 i = 0;
994 RK_U32 j = 0;
995 FILE *fp_stream = NULL;
996 char name[50];
997 MppBuffer buffer = NULL;
998 MppFrame frame;
999 void *base = NULL;
1000
1001 ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_FRAME_PTR, &frame);
1002
1003 if (ret != MPP_OK || frame == NULL)
1004 mpp_log_f("failed to get frame slot %d", task->dec.output);
1005
1006 ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_BUFFER, &buffer);
1007
1008 if (ret != MPP_OK || buffer == NULL)
1009 mpp_log_f("failed to get frame buffer slot %d", task->dec.output);
1010
1011 AVS2D_HAL_TRACE("frame slot %d, fd %d\n", task->dec.output, mpp_buffer_get_fd(buffer));
1012 base = mpp_buffer_get_ptr(buffer);
1013 vir_w = mpp_frame_get_hor_stride(frame);
1014 vir_h = mpp_frame_get_ver_stride(frame);
1015 fmt = mpp_frame_get_fmt(frame);
1016 snprintf(name, sizeof(name), "/data/tmp/rkv_out_%dx%d_nv12_%03d.yuv", vir_w, vir_h,
1017 p_hal->frame_no);
1018 fp_stream = fopen(name, "wb");
1019 /* if format is fbc, write fbc header first */
1020 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1021 RK_U32 header_size = 0;
1022
1023 header_size = vir_w * vir_h / 16;
1024 fwrite(base, 1, header_size, fp_stream);
1025 base += header_size;
1026 }
1027
1028 if (fmt != MPP_FMT_YUV420SP_10BIT) {
1029 fwrite(base, 1, vir_w * vir_h * 3 / 2, fp_stream);
1030 } else {
1031 RK_U8 tmp = 0;
1032 for (i = 0; i < vir_h; i++) {
1033 for (j = 0; j < vir_w; j++) {
1034 tmp = fetch_data(fmt, base, j);
1035 fwrite(&tmp, 1, 1, fp_stream);
1036 }
1037 base += vir_w;
1038 }
1039
1040 for (i = 0; i < vir_h / 2; i++) {
1041 for (j = 0; j < vir_w; j++) {
1042 tmp = fetch_data(fmt, base, j);
1043 fwrite(&tmp, 1, 1, fp_stream);
1044 }
1045 base += vir_w;
1046 }
1047 }
1048 fclose(fp_stream);
1049
1050 return ret;
1051 }
1052
hal_avs2d_rkv_wait(void * hal,HalTaskInfo * task)1053 MPP_RET hal_avs2d_rkv_wait(void *hal, HalTaskInfo *task)
1054 {
1055 MPP_RET ret = MPP_OK;
1056 Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
1057 Avs2dRkvRegCtx_t *reg_ctx;
1058 Vdpu34xAvs2dRegSet *p_regs;
1059
1060 INP_CHECK(ret, NULL == p_hal);
1061 reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
1062 p_regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
1063
1064 if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
1065 AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "found task error.\n");
1066 ret = MPP_NOK;
1067 goto __RETURN;
1068 } else {
1069 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1070 if (ret)
1071 mpp_err_f("poll cmd failed %d\n", ret);
1072 }
1073
1074 if (avs2d_hal_debug & AVS2D_HAL_DBG_OUT)
1075 hal_avs2d_rkv_dump_yuv(hal, task);
1076
1077 if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
1078 FILE *fp_reg = NULL;
1079 RK_U32 i = 0;
1080 char name[50];
1081 snprintf(name, sizeof(name), "/data/tmp/rkv_reg_read_%03d.txt", p_hal->frame_no);
1082 fp_reg = fopen(name , "w+");
1083
1084 for (i = 0; i < 278; i++)
1085 fprintf(fp_reg, "%08x\n", reg_ctx->reg_out[i]);
1086
1087 fclose(fp_reg);
1088 }
1089
1090 AVS2D_HAL_TRACE("read reg[224] 0x%08x\n", p_regs->irq_status.reg224);
1091
1092 if (p_hal->dec_cb) {
1093 DecCbHalDone param;
1094
1095 param.task = (void *)&task->dec;
1096 param.regs = (RK_U32 *)p_regs;
1097
1098 if (p_regs->irq_status.reg224.dec_error_sta ||
1099 (!p_regs->irq_status.reg224.dec_rdy_sta) ||
1100 p_regs->irq_status.reg224.buf_empty_sta ||
1101 p_regs->irq_status.reg226.strmd_error_status ||
1102 p_regs->irq_status.reg227.colmv_error_ref_picidx ||
1103 p_regs->irq_status.reg225.strmd_detect_error_flag)
1104 param.hard_err = 1;
1105 else
1106 param.hard_err = 0;
1107
1108 task->dec.flags.ref_used = p_regs->statistic.reg266_perf_cnt0;
1109
1110 if (task->dec.flags.ref_miss) {
1111 RK_U32 ref_hw_usage = p_regs->statistic.reg266_perf_cnt0;
1112
1113 AVS2D_HAL_TRACE("hal frame %d ref miss %x hard_err %d hw_usage %x", p_hal->frame_no,
1114 task->dec.flags.ref_miss, param.hard_err, ref_hw_usage);
1115 }
1116
1117 AVS2D_HAL_TRACE("hal frame %d hard_err= %d", p_hal->frame_no, param.hard_err);
1118
1119 mpp_callback(p_hal->dec_cb, ¶m);
1120 }
1121
1122 memset(&p_regs->irq_status.reg224, 0, sizeof(RK_U32));
1123
1124 if (p_hal->fast_mode)
1125 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
1126
1127 __RETURN:
1128 AVS2D_HAL_TRACE("Out. ret %d", ret);
1129 return ret;
1130 }
1131