xref: /OK3568_Linux_fs/external/mpp/mpp/hal/vpu/h263d/hal_h263d_api.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1 /*
2  * Copyright 2016 Rockchip Electronics Co. LTD
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #include <string.h>
18 
19 #include "mpp_env.h"
20 #include "mpp_debug.h"
21 #include "mpp_platform.h"
22 
23 #include "mpp_hal.h"
24 #include "hal_h263d_base.h"
25 #include "hal_h263d_vdpu1.h"
26 #include "hal_h263d_vdpu2.h"
27 
28 RK_U32 h263d_hal_debug = 0;
29 
vpu_h263d_get_buffer_by_index(hal_h263_ctx * ctx,RK_S32 index,MppBuffer * buffer)30 void vpu_h263d_get_buffer_by_index(hal_h263_ctx *ctx, RK_S32 index,
31                                    MppBuffer *buffer)
32 {
33     if (index >= 0) {
34         mpp_buf_slot_get_prop(ctx->frm_slots, index, SLOT_BUFFER, buffer);
35         mpp_assert(*buffer);
36     }
37 }
38 
hal_h263d_gen_regs(void * hal,HalTaskInfo * task)39 static MPP_RET hal_h263d_gen_regs(void *hal, HalTaskInfo *task)
40 {
41     hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
42     return ctx->hal_api.reg_gen(hal, task);
43 }
44 
hal_h263d_start(void * hal,HalTaskInfo * task)45 static MPP_RET hal_h263d_start(void *hal, HalTaskInfo *task)
46 {
47     hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
48     return ctx->hal_api.start(hal, task);
49 }
50 
hal_h263d_wait(void * hal,HalTaskInfo * task)51 static MPP_RET hal_h263d_wait(void *hal, HalTaskInfo *task)
52 {
53     hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
54     return ctx->hal_api.wait(hal, task);
55 }
56 
hal_h263d_deinit(void * hal)57 static MPP_RET hal_h263d_deinit(void *hal)
58 {
59     hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
60     return ctx->hal_api.deinit(hal);
61 }
62 
hal_h263d_init(void * hal,MppHalCfg * cfg)63 static MPP_RET hal_h263d_init(void *hal, MppHalCfg *cfg)
64 {
65     MppHalApi *p_api = NULL;
66     hal_h263_ctx *p_hal = (hal_h263_ctx *)hal;
67     VpuHwMode hw_mode = MODE_NULL;
68     RK_U32 hw_flag = 0;
69 
70     mpp_env_get_u32("h263d_hal_debug", &h263d_hal_debug, 0);
71 
72     memset(p_hal, 0, sizeof(hal_h263_ctx));
73     p_api = &p_hal->hal_api;
74 
75     p_hal->frm_slots = cfg->frame_slots;
76     p_hal->pkt_slots = cfg->packet_slots;
77 
78     hw_flag = mpp_get_vcodec_type();
79     if (hw_flag & HAVE_VDPU2)
80         hw_mode = VDPU2_MODE;
81     if (hw_flag & HAVE_VDPU1)
82         hw_mode = VDPU1_MODE;
83 
84     switch (hw_mode) {
85     case VDPU2_MODE : {
86         mpp_log("the VDPU2_MODE is used currently!\n");
87         p_api->init    = hal_vpu2_h263d_init;
88         p_api->deinit  = hal_vpu2_h263d_deinit;
89         p_api->reg_gen = hal_vpu2_h263d_gen_regs;
90         p_api->start   = hal_vpu2_h263d_start;
91         p_api->wait    = hal_vpu2_h263d_wait;
92         p_api->reset   = NULL;
93         p_api->flush   = NULL;
94         p_api->control = NULL;
95     } break;
96     case VDPU1_MODE : {
97         mpp_log("the VDPU1_MODE is used currently!\n");
98         p_api->init    = hal_vpu1_h263d_init;
99         p_api->deinit  = hal_vpu1_h263d_deinit;
100         p_api->reg_gen = hal_vpu1_h263d_gen_regs;
101         p_api->start   = hal_vpu1_h263d_start;
102         p_api->wait    = hal_vpu1_h263d_wait;
103         p_api->reset   = NULL;
104         p_api->flush   = NULL;
105         p_api->control = NULL;
106     } break;
107     default : {
108         mpp_err("unknow vpu type:%d.", hw_mode);
109         return MPP_ERR_INIT;
110     } break;
111     }
112 
113     return p_api->init(hal, cfg);
114 }
115 
116 const MppHalApi hal_api_h263d = {
117     "h263d_vpu",
118     MPP_CTX_DEC,
119     MPP_VIDEO_CodingH263,
120     sizeof(hal_h263_ctx),
121     0,
122     hal_h263d_init,
123     hal_h263d_deinit,
124     hal_h263d_gen_regs,
125     hal_h263d_start,
126     hal_h263d_wait,
127     NULL,
128     NULL,
129     NULL,
130 };
131