1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 /* 23 * Base structures shared with the kernel. 24 */ 25 26 #ifndef _UAPI_BASE_KERNEL_H_ 27 #define _UAPI_BASE_KERNEL_H_ 28 29 #include <linux/types.h> 30 #include "mali_base_mem_priv.h" 31 #include "gpu/mali_kbase_gpu_id.h" 32 #include "gpu/mali_kbase_gpu_coherency.h" 33 34 #define BASE_MAX_COHERENT_GROUPS 16 35 36 #if defined(PAGE_MASK) && defined(PAGE_SHIFT) 37 #define LOCAL_PAGE_SHIFT PAGE_SHIFT 38 #define LOCAL_PAGE_LSB ~PAGE_MASK 39 #else 40 #ifndef OSU_CONFIG_CPU_PAGE_SIZE_LOG2 41 #define OSU_CONFIG_CPU_PAGE_SIZE_LOG2 12 42 #endif 43 44 #if defined(OSU_CONFIG_CPU_PAGE_SIZE_LOG2) 45 #define LOCAL_PAGE_SHIFT OSU_CONFIG_CPU_PAGE_SIZE_LOG2 46 #define LOCAL_PAGE_LSB ((1ul << OSU_CONFIG_CPU_PAGE_SIZE_LOG2) - 1) 47 #else 48 #error Failed to find page size 49 #endif 50 #endif 51 52 /* Physical memory group ID for normal usage. 53 */ 54 #define BASE_MEM_GROUP_DEFAULT (0) 55 56 /* Number of physical memory groups. 57 */ 58 #define BASE_MEM_GROUP_COUNT (16) 59 60 /** 61 * typedef base_mem_alloc_flags - Memory allocation, access/hint flags. 62 * 63 * A combination of MEM_PROT/MEM_HINT flags must be passed to each allocator 64 * in order to determine the best cache policy. Some combinations are 65 * of course invalid (e.g. MEM_PROT_CPU_WR | MEM_HINT_CPU_RD), 66 * which defines a write-only region on the CPU side, which is 67 * heavily read by the CPU... 68 * Other flags are only meaningful to a particular allocator. 69 * More flags can be added to this list, as long as they don't clash 70 * (see BASE_MEM_FLAGS_NR_BITS for the number of the first free bit). 71 */ 72 typedef __u32 base_mem_alloc_flags; 73 74 /* A mask for all the flags which are modifiable via the base_mem_set_flags 75 * interface. 76 */ 77 #define BASE_MEM_FLAGS_MODIFIABLE \ 78 (BASE_MEM_DONT_NEED | BASE_MEM_COHERENT_SYSTEM | \ 79 BASE_MEM_COHERENT_LOCAL) 80 81 /* A mask of all the flags that can be returned via the base_mem_get_flags() 82 * interface. 83 */ 84 #define BASE_MEM_FLAGS_QUERYABLE \ 85 (BASE_MEM_FLAGS_INPUT_MASK & ~(BASE_MEM_SAME_VA | \ 86 BASE_MEM_COHERENT_SYSTEM_REQUIRED | BASE_MEM_DONT_NEED | \ 87 BASE_MEM_IMPORT_SHARED | BASE_MEM_FLAGS_RESERVED | \ 88 BASEP_MEM_FLAGS_KERNEL_ONLY)) 89 90 /** 91 * enum base_mem_import_type - Memory types supported by @a base_mem_import 92 * 93 * @BASE_MEM_IMPORT_TYPE_INVALID: Invalid type 94 * @BASE_MEM_IMPORT_TYPE_UMM: UMM import. Handle type is a file descriptor (int) 95 * @BASE_MEM_IMPORT_TYPE_USER_BUFFER: User buffer import. Handle is a 96 * base_mem_import_user_buffer 97 * 98 * Each type defines what the supported handle type is. 99 * 100 * If any new type is added here ARM must be contacted 101 * to allocate a numeric value for it. 102 * Do not just add a new type without synchronizing with ARM 103 * as future releases from ARM might include other new types 104 * which could clash with your custom types. 105 */ 106 enum base_mem_import_type { 107 BASE_MEM_IMPORT_TYPE_INVALID = 0, 108 /* 109 * Import type with value 1 is deprecated. 110 */ 111 BASE_MEM_IMPORT_TYPE_UMM = 2, 112 BASE_MEM_IMPORT_TYPE_USER_BUFFER = 3 113 }; 114 115 /** 116 * struct base_mem_import_user_buffer - Handle of an imported user buffer 117 * 118 * @ptr: address of imported user buffer 119 * @length: length of imported user buffer in bytes 120 * 121 * This structure is used to represent a handle of an imported user buffer. 122 */ 123 124 struct base_mem_import_user_buffer { 125 __u64 ptr; 126 __u64 length; 127 }; 128 129 /* Mask to detect 4GB boundary alignment */ 130 #define BASE_MEM_MASK_4GB 0xfffff000UL 131 /* Mask to detect 4GB boundary (in page units) alignment */ 132 #define BASE_MEM_PFN_MASK_4GB (BASE_MEM_MASK_4GB >> LOCAL_PAGE_SHIFT) 133 134 /* Limit on the 'extension' parameter for an allocation with the 135 * BASE_MEM_TILER_ALIGN_TOP flag set 136 * 137 * This is the same as the maximum limit for a Buffer Descriptor's chunk size 138 */ 139 #define BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES_LOG2 \ 140 (21u - (LOCAL_PAGE_SHIFT)) 141 #define BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES \ 142 (1ull << (BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES_LOG2)) 143 144 /* Bit mask of cookies used for memory allocation setup */ 145 #define KBASE_COOKIE_MASK ~1UL /* bit 0 is reserved */ 146 147 /* Maximum size allowed in a single KBASE_IOCTL_MEM_ALLOC call */ 148 #define KBASE_MEM_ALLOC_MAX_SIZE ((8ull << 30) >> PAGE_SHIFT) /* 8 GB */ 149 150 /* 151 * struct base_fence - Cross-device synchronisation fence. 152 * 153 * A fence is used to signal when the GPU has finished accessing a resource that 154 * may be shared with other devices, and also to delay work done asynchronously 155 * by the GPU until other devices have finished accessing a shared resource. 156 */ 157 struct base_fence { 158 struct { 159 int fd; 160 int stream_fd; 161 } basep; 162 }; 163 164 /** 165 * struct base_mem_aliasing_info - Memory aliasing info 166 * 167 * @handle: Handle to alias, can be BASE_MEM_WRITE_ALLOC_PAGES_HANDLE 168 * @offset: Offset within the handle to start aliasing from, in pages. 169 * Not used with BASE_MEM_WRITE_ALLOC_PAGES_HANDLE. 170 * @length: Length to alias, in pages. For BASE_MEM_WRITE_ALLOC_PAGES_HANDLE 171 * specifies the number of times the special page is needed. 172 * 173 * Describes a memory handle to be aliased. 174 * A subset of the handle can be chosen for aliasing, given an offset and a 175 * length. 176 * A special handle BASE_MEM_WRITE_ALLOC_PAGES_HANDLE is used to represent a 177 * region where a special page is mapped with a write-alloc cache setup, 178 * typically used when the write result of the GPU isn't needed, but the GPU 179 * must write anyway. 180 * 181 * Offset and length are specified in pages. 182 * Offset must be within the size of the handle. 183 * Offset+length must not overrun the size of the handle. 184 */ 185 struct base_mem_aliasing_info { 186 struct base_mem_handle handle; 187 __u64 offset; 188 __u64 length; 189 }; 190 191 /* Maximum percentage of just-in-time memory allocation trimming to perform 192 * on free. 193 */ 194 #define BASE_JIT_MAX_TRIM_LEVEL (100) 195 196 /* Maximum number of concurrent just-in-time memory allocations. 197 */ 198 #define BASE_JIT_ALLOC_COUNT (255) 199 200 /** 201 * struct base_jit_alloc_info - Structure which describes a JIT allocation 202 * request. 203 * @gpu_alloc_addr: The GPU virtual address to write the JIT 204 * allocated GPU virtual address to. 205 * @va_pages: The minimum number of virtual pages required. 206 * @commit_pages: The minimum number of physical pages which 207 * should back the allocation. 208 * @extension: Granularity of physical pages to grow the 209 * allocation by during a fault. 210 * @id: Unique ID provided by the caller, this is used 211 * to pair allocation and free requests. 212 * Zero is not a valid value. 213 * @bin_id: The JIT allocation bin, used in conjunction with 214 * @max_allocations to limit the number of each 215 * type of JIT allocation. 216 * @max_allocations: The maximum number of allocations allowed within 217 * the bin specified by @bin_id. Should be the same 218 * for all allocations within the same bin. 219 * @flags: flags specifying the special requirements for 220 * the JIT allocation, see 221 * %BASE_JIT_ALLOC_VALID_FLAGS 222 * @padding: Expansion space - should be initialised to zero 223 * @usage_id: A hint about which allocation should be reused. 224 * The kernel should attempt to use a previous 225 * allocation with the same usage_id 226 * @heap_info_gpu_addr: Pointer to an object in GPU memory describing 227 * the actual usage of the region. 228 * 229 * Kbase version history: 230 * 11.20: added @heap_info_gpu_addr 231 */ 232 struct base_jit_alloc_info { 233 __u64 gpu_alloc_addr; 234 __u64 va_pages; 235 __u64 commit_pages; 236 __u64 extension; 237 __u8 id; 238 __u8 bin_id; 239 __u8 max_allocations; 240 __u8 flags; 241 __u8 padding[2]; 242 __u16 usage_id; 243 __u64 heap_info_gpu_addr; 244 }; 245 246 enum base_external_resource_access { 247 BASE_EXT_RES_ACCESS_SHARED, 248 BASE_EXT_RES_ACCESS_EXCLUSIVE 249 }; 250 251 struct base_external_resource { 252 __u64 ext_resource; 253 }; 254 255 /** 256 * BASE_EXT_RES_COUNT_MAX - The maximum number of external resources 257 * which can be mapped/unmapped in a single request. 258 */ 259 #define BASE_EXT_RES_COUNT_MAX 10 260 261 /** 262 * struct base_external_resource_list - Structure which describes a list of 263 * external resources. 264 * @count: The number of resources. 265 * @ext_res: Array of external resources which is 266 * sized at allocation time. 267 */ 268 struct base_external_resource_list { 269 __u64 count; 270 struct base_external_resource ext_res[1]; 271 }; 272 273 struct base_jd_debug_copy_buffer { 274 __u64 address; 275 __u64 size; 276 struct base_external_resource extres; 277 }; 278 279 #define GPU_MAX_JOB_SLOTS 16 280 281 /** 282 * DOC: User-side Base GPU Property Queries 283 * 284 * The User-side Base GPU Property Query interface encapsulates two 285 * sub-modules: 286 * 287 * - "Dynamic GPU Properties" 288 * - "Base Platform Config GPU Properties" 289 * 290 * Base only deals with properties that vary between different GPU 291 * implementations - the Dynamic GPU properties and the Platform Config 292 * properties. 293 * 294 * For properties that are constant for the GPU Architecture, refer to the 295 * GPU module. However, we will discuss their relevance here just to 296 * provide background information. 297 * 298 * About the GPU Properties in Base and GPU modules 299 * 300 * The compile-time properties (Platform Config, GPU Compile-time 301 * properties) are exposed as pre-processor macros. 302 * 303 * Complementing the compile-time properties are the Dynamic GPU 304 * Properties, which act as a conduit for the GPU Configuration 305 * Discovery. 306 * 307 * In general, the dynamic properties are present to verify that the platform 308 * has been configured correctly with the right set of Platform Config 309 * Compile-time Properties. 310 * 311 * As a consistent guide across the entire DDK, the choice for dynamic or 312 * compile-time should consider the following, in order: 313 * 1. Can the code be written so that it doesn't need to know the 314 * implementation limits at all? 315 * 2. If you need the limits, get the information from the Dynamic Property 316 * lookup. This should be done once as you fetch the context, and then cached 317 * as part of the context data structure, so it's cheap to access. 318 * 3. If there's a clear and arguable inefficiency in using Dynamic Properties, 319 * then use a Compile-Time Property (Platform Config, or GPU Compile-time 320 * property). Examples of where this might be sensible follow: 321 * - Part of a critical inner-loop 322 * - Frequent re-use throughout the driver, causing significant extra load 323 * instructions or control flow that would be worthwhile optimizing out. 324 * 325 * We cannot provide an exhaustive set of examples, neither can we provide a 326 * rule for every possible situation. Use common sense, and think about: what 327 * the rest of the driver will be doing; how the compiler might represent the 328 * value if it is a compile-time constant; whether an OEM shipping multiple 329 * devices would benefit much more from a single DDK binary, instead of 330 * insignificant micro-optimizations. 331 * 332 * Dynamic GPU Properties 333 * 334 * Dynamic GPU properties are presented in two sets: 335 * 1. the commonly used properties in @ref base_gpu_props, which have been 336 * unpacked from GPU register bitfields. 337 * 2. The full set of raw, unprocessed properties in gpu_raw_gpu_props 338 * (also a member of base_gpu_props). All of these are presented in 339 * the packed form, as presented by the GPU registers themselves. 340 * 341 * The raw properties in gpu_raw_gpu_props are necessary to 342 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device 343 * behaving differently?". In this case, all information about the 344 * configuration is potentially useful, but it does not need to be processed 345 * by the driver. Instead, the raw registers can be processed by the Mali 346 * Tools software on the host PC. 347 * 348 * The properties returned extend the GPU Configuration Discovery 349 * registers. For example, GPU clock speed is not specified in the GPU 350 * Architecture, but is necessary for OpenCL's clGetDeviceInfo() function. 351 * 352 * The GPU properties are obtained by a call to 353 * base_get_gpu_props(). This simply returns a pointer to a const 354 * base_gpu_props structure. It is constant for the life of a base 355 * context. Multiple calls to base_get_gpu_props() to a base context 356 * return the same pointer to a constant structure. This avoids cache pollution 357 * of the common data. 358 * 359 * This pointer must not be freed, because it does not point to the start of a 360 * region allocated by the memory allocator; instead, just close the @ref 361 * base_context. 362 * 363 * 364 * Kernel Operation 365 * 366 * During Base Context Create time, user-side makes a single kernel call: 367 * - A call to fill user memory with GPU information structures 368 * 369 * The kernel-side will fill the provided the entire processed base_gpu_props 370 * structure, because this information is required in both 371 * user and kernel side; it does not make sense to decode it twice. 372 * 373 * Coherency groups must be derived from the bitmasks, but this can be done 374 * kernel side, and just once at kernel startup: Coherency groups must already 375 * be known kernel-side, to support chains that specify a 'Only Coherent Group' 376 * SW requirement, or 'Only Coherent Group with Tiler' SW requirement. 377 * 378 * Coherency Group calculation 379 * 380 * Creation of the coherent group data is done at device-driver startup, and so 381 * is one-time. This will most likely involve a loop with CLZ, shifting, and 382 * bit clearing on the L2_PRESENT mask, depending on whether the 383 * system is L2 Coherent. The number of shader cores is done by a 384 * population count, since faulty cores may be disabled during production, 385 * producing a non-contiguous mask. 386 * 387 * The memory requirements for this algorithm can be determined either by a __u64 388 * population count on the L2_PRESENT mask (a LUT helper already is 389 * required for the above), or simple assumption that there can be no more than 390 * 16 coherent groups, since core groups are typically 4 cores. 391 */ 392 393 /* 394 * More information is possible - but associativity and bus width are not 395 * required by upper-level apis. 396 */ 397 struct mali_base_gpu_l2_cache_props { 398 __u8 log2_line_size; 399 __u8 log2_cache_size; 400 __u8 num_l2_slices; /* Number of L2C slices. 1 or higher */ 401 __u8 padding[5]; 402 }; 403 404 struct mali_base_gpu_tiler_props { 405 __u32 bin_size_bytes; /* Max is 4*2^15 */ 406 __u32 max_active_levels; /* Max is 2^15 */ 407 }; 408 409 /** 410 * struct mali_base_gpu_thread_props - GPU threading system details. 411 * @max_threads: Max. number of threads per core 412 * @max_workgroup_size: Max. number of threads per workgroup 413 * @max_barrier_size: Max. number of threads that can synchronize on a 414 * simple barrier 415 * @max_registers: Total size [1..65535] of the register file available 416 * per core. 417 * @max_task_queue: Max. tasks [1..255] which may be sent to a core 418 * before it becomes blocked. 419 * @max_thread_group_split: Max. allowed value [1..15] of the Thread Group Split 420 * field. 421 * @impl_tech: 0 = Not specified, 1 = Silicon, 2 = FPGA, 422 * 3 = SW Model/Emulation 423 * @padding: padding to align to 8-byte 424 * @tls_alloc: Number of threads per core that TLS must be 425 * allocated for 426 */ 427 struct mali_base_gpu_thread_props { 428 __u32 max_threads; 429 __u32 max_workgroup_size; 430 __u32 max_barrier_size; 431 __u16 max_registers; 432 __u8 max_task_queue; 433 __u8 max_thread_group_split; 434 __u8 impl_tech; 435 __u8 padding[3]; 436 __u32 tls_alloc; 437 }; 438 439 /** 440 * struct mali_base_gpu_coherent_group - descriptor for a coherent group 441 * @core_mask: Core restriction mask required for the group 442 * @num_cores: Number of cores in the group 443 * @padding: padding to align to 8-byte 444 * 445 * \c core_mask exposes all cores in that coherent group, and \c num_cores 446 * provides a cached population-count for that mask. 447 * 448 * @note Whilst all cores are exposed in the mask, not all may be available to 449 * the application, depending on the Kernel Power policy. 450 * 451 * @note if u64s must be 8-byte aligned, then this structure has 32-bits of 452 * wastage. 453 */ 454 struct mali_base_gpu_coherent_group { 455 __u64 core_mask; 456 __u16 num_cores; 457 __u16 padding[3]; 458 }; 459 460 /** 461 * struct mali_base_gpu_coherent_group_info - Coherency group information 462 * @num_groups: Number of coherent groups in the GPU. 463 * @num_core_groups: Number of core groups (coherent or not) in the GPU. 464 * Equivalent to the number of L2 Caches. 465 * The GPU Counter dumping writes 2048 bytes per core group, 466 * regardless of whether the core groups are coherent or not. 467 * Hence this member is needed to calculate how much memory 468 * is required for dumping. 469 * @note Do not use it to work out how many valid elements 470 * are in the group[] member. Use num_groups instead. 471 * @coherency: Coherency features of the memory, accessed by gpu_mem_features 472 * methods 473 * @padding: padding to align to 8-byte 474 * @group: Descriptors of coherent groups 475 * 476 * Note that the sizes of the members could be reduced. However, the \c group 477 * member might be 8-byte aligned to ensure the __u64 core_mask is 8-byte 478 * aligned, thus leading to wastage if the other members sizes were reduced. 479 * 480 * The groups are sorted by core mask. The core masks are non-repeating and do 481 * not intersect. 482 */ 483 struct mali_base_gpu_coherent_group_info { 484 __u32 num_groups; 485 __u32 num_core_groups; 486 __u32 coherency; 487 __u32 padding; 488 struct mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS]; 489 }; 490 491 #if MALI_USE_CSF 492 #include "csf/mali_base_csf_kernel.h" 493 #else 494 #include "jm/mali_base_jm_kernel.h" 495 #endif 496 497 /** 498 * struct gpu_raw_gpu_props - A complete description of the GPU's Hardware 499 * Configuration Discovery registers. 500 * @shader_present: Shader core present bitmap 501 * @tiler_present: Tiler core present bitmap 502 * @l2_present: Level 2 cache present bitmap 503 * @stack_present: Core stack present bitmap 504 * @l2_features: L2 features 505 * @core_features: Core features 506 * @mem_features: Mem features 507 * @mmu_features: Mmu features 508 * @as_present: Bitmap of address spaces present 509 * @js_present: Job slots present 510 * @js_features: Array of job slot features. 511 * @tiler_features: Tiler features 512 * @texture_features: TEXTURE_FEATURES_x registers, as exposed by the GPU 513 * @gpu_id: GPU and revision identifier 514 * @thread_max_threads: Maximum number of threads per core 515 * @thread_max_workgroup_size: Maximum number of threads per workgroup 516 * @thread_max_barrier_size: Maximum number of threads per barrier 517 * @thread_features: Thread features 518 * @coherency_mode: Note: This is the _selected_ coherency mode rather than the 519 * available modes as exposed in the coherency_features register 520 * @thread_tls_alloc: Number of threads per core that TLS must be allocated for 521 * @gpu_features: GPU features 522 * 523 * The information is presented inefficiently for access. For frequent access, 524 * the values should be better expressed in an unpacked form in the 525 * base_gpu_props structure. 526 * 527 * The raw properties in gpu_raw_gpu_props are necessary to 528 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device 529 * behaving differently?". In this case, all information about the 530 * configuration is potentially useful, but it does not need to be processed 531 * by the driver. Instead, the raw registers can be processed by the Mali 532 * Tools software on the host PC. 533 * 534 */ 535 struct gpu_raw_gpu_props { 536 __u64 shader_present; 537 __u64 tiler_present; 538 __u64 l2_present; 539 __u64 stack_present; 540 __u32 l2_features; 541 __u32 core_features; 542 __u32 mem_features; 543 __u32 mmu_features; 544 545 __u32 as_present; 546 547 __u32 js_present; 548 __u32 js_features[GPU_MAX_JOB_SLOTS]; 549 __u32 tiler_features; 550 __u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS]; 551 552 __u32 gpu_id; 553 554 __u32 thread_max_threads; 555 __u32 thread_max_workgroup_size; 556 __u32 thread_max_barrier_size; 557 __u32 thread_features; 558 559 /* 560 * Note: This is the _selected_ coherency mode rather than the 561 * available modes as exposed in the coherency_features register. 562 */ 563 __u32 coherency_mode; 564 565 __u32 thread_tls_alloc; 566 __u64 gpu_features; 567 }; 568 569 /** 570 * struct base_gpu_props - Return structure for base_get_gpu_props(). 571 * @core_props: Core props. 572 * @l2_props: L2 props. 573 * @unused_1: Keep for backwards compatibility. 574 * @tiler_props: Tiler props. 575 * @thread_props: Thread props. 576 * @raw_props: This member is large, likely to be 128 bytes. 577 * @coherency_info: This must be last member of the structure. 578 * 579 * NOTE: the raw_props member in this data structure contains the register 580 * values from which the value of the other members are derived. The derived 581 * members exist to allow for efficient access and/or shielding the details 582 * of the layout of the registers. 583 */ 584 struct base_gpu_props { 585 struct mali_base_gpu_core_props core_props; 586 struct mali_base_gpu_l2_cache_props l2_props; 587 __u64 unused_1; 588 struct mali_base_gpu_tiler_props tiler_props; 589 struct mali_base_gpu_thread_props thread_props; 590 struct gpu_raw_gpu_props raw_props; 591 struct mali_base_gpu_coherent_group_info coherency_info; 592 }; 593 594 #define BASE_MEM_GROUP_ID_GET(flags) \ 595 ((flags & BASE_MEM_GROUP_ID_MASK) >> BASEP_MEM_GROUP_ID_SHIFT) 596 597 #define BASE_MEM_GROUP_ID_SET(id) \ 598 (((base_mem_alloc_flags)((id < 0 || id >= BASE_MEM_GROUP_COUNT) ? \ 599 BASE_MEM_GROUP_DEFAULT : \ 600 id) \ 601 << BASEP_MEM_GROUP_ID_SHIFT) & \ 602 BASE_MEM_GROUP_ID_MASK) 603 604 #define BASE_CONTEXT_MMU_GROUP_ID_SET(group_id) \ 605 (BASEP_CONTEXT_MMU_GROUP_ID_MASK & \ 606 ((base_context_create_flags)(group_id) \ 607 << BASEP_CONTEXT_MMU_GROUP_ID_SHIFT)) 608 609 #define BASE_CONTEXT_MMU_GROUP_ID_GET(flags) \ 610 ((flags & BASEP_CONTEXT_MMU_GROUP_ID_MASK) >> \ 611 BASEP_CONTEXT_MMU_GROUP_ID_SHIFT) 612 613 /* 614 * A number of bit flags are defined for requesting cpu_gpu_timeinfo. These 615 * flags are also used, where applicable, for specifying which fields 616 * are valid following the request operation. 617 */ 618 619 /* For monotonic (counter) timefield */ 620 #define BASE_TIMEINFO_MONOTONIC_FLAG (1UL << 0) 621 /* For system wide timestamp */ 622 #define BASE_TIMEINFO_TIMESTAMP_FLAG (1UL << 1) 623 /* For GPU cycle counter */ 624 #define BASE_TIMEINFO_CYCLE_COUNTER_FLAG (1UL << 2) 625 /* Specify kernel GPU register timestamp */ 626 #define BASE_TIMEINFO_KERNEL_SOURCE_FLAG (1UL << 30) 627 /* Specify userspace cntvct_el0 timestamp source */ 628 #define BASE_TIMEINFO_USER_SOURCE_FLAG (1UL << 31) 629 630 #define BASE_TIMEREQUEST_ALLOWED_FLAGS (\ 631 BASE_TIMEINFO_MONOTONIC_FLAG | \ 632 BASE_TIMEINFO_TIMESTAMP_FLAG | \ 633 BASE_TIMEINFO_CYCLE_COUNTER_FLAG | \ 634 BASE_TIMEINFO_KERNEL_SOURCE_FLAG | \ 635 BASE_TIMEINFO_USER_SOURCE_FLAG) 636 637 /* Maximum number of source allocations allowed to create an alias allocation. 638 * This needs to be 4096 * 6 to allow cube map arrays with up to 4096 array 639 * layers, since each cube map in the array will have 6 faces. 640 */ 641 #define BASE_MEM_ALIAS_MAX_ENTS ((size_t)24576) 642 643 #endif /* _UAPI_BASE_KERNEL_H_ */ 644