1 /*
2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/debug.h>
10 #include <common/fdt_wrappers.h>
11 #include <drivers/io/io_storage.h>
12 #include <drivers/partition/partition.h>
13 #include <lib/object_pool.h>
14 #include <libfdt.h>
15 #include <tools_share/firmware_image_package.h>
16
17 #include <plat/arm/common/arm_fconf_getter.h>
18 #include <plat/arm/common/arm_fconf_io_storage.h>
19 #include <platform_def.h>
20
21 #if PSA_FWU_SUPPORT
22 /* metadata entry details */
23 static io_block_spec_t fwu_metadata_spec;
24 #endif /* PSA_FWU_SUPPORT */
25
26 io_block_spec_t fip_block_spec = {
27 /*
28 * - With ARM_GPT_SUPPORT and BL1: a fixed FIP offset within the GPT image is used.
29 * - With ARM_GPT_SUPPORT and BL2: the FIP offset is derived from
30 * the partition table entries at runtime.
31 * - Without ARM_GPT_SUPPORT: both BL1 and BL2 use the fixed FIP base address.
32 */
33 #if ARM_GPT_SUPPORT
34 #if IMAGE_BL1
35 .offset = PLAT_ARM_FLASH_IMAGE_BASE + PLAT_ARM_FIP_OFFSET_IN_GPT,
36 #endif /* IMAGE_BL1 */
37 #else
38 .offset = PLAT_ARM_FLASH_IMAGE_BASE,
39 #endif /* ARM_GPT_SUPPORT */
40 .length = PLAT_ARM_FLASH_IMAGE_MAX_SIZE
41 };
42
43 #if ARM_GPT_SUPPORT
44 static const io_block_spec_t gpt_spec = {
45 .offset = PLAT_ARM_FLASH_IMAGE_BASE,
46 /*
47 * PLAT_PARTITION_BLOCK_SIZE = 512
48 * PLAT_PARTITION_MAX_ENTRIES = 128
49 * each sector has 4 partition entries, and there are
50 * 2 reserved sectors i.e. protective MBR and primary
51 * GPT header hence length gets calculated as,
52 * length = PLAT_PARTITION_BLOCK_SIZE * (128/4 + 2)
53 */
54 .length = LBA(PLAT_PARTITION_MAX_ENTRIES / 4 + 2),
55 };
56
57 /*
58 * length will be assigned at runtime based on MBR header data.
59 * Backup GPT Header is present in Last LBA-1 and its entries
60 * are last 32 blocks starts at LBA-33, On runtime update these
61 * before device usage. Update offset to beginning LBA-33 and
62 * length to LBA-33.
63 */
64 static io_block_spec_t bkup_gpt_spec = {
65 .offset = PLAT_ARM_FLASH_IMAGE_BASE,
66 .length = 0,
67 };
68 #endif /* ARM_GPT_SUPPORT */
69
70 const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = {
71 [BL2_IMAGE_ID] = {UUID_TRUSTED_BOOT_FIRMWARE_BL2},
72 [TB_FW_CONFIG_ID] = {UUID_TB_FW_CONFIG},
73 [FW_CONFIG_ID] = {UUID_FW_CONFIG},
74 #if !ARM_IO_IN_DTB
75 [SCP_BL2_IMAGE_ID] = {UUID_SCP_FIRMWARE_SCP_BL2},
76 [BL31_IMAGE_ID] = {UUID_EL3_RUNTIME_FIRMWARE_BL31},
77 [BL32_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32},
78 [BL32_EXTRA1_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32_EXTRA1},
79 [BL32_EXTRA2_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32_EXTRA2},
80 [BL33_IMAGE_ID] = {UUID_NON_TRUSTED_FIRMWARE_BL33},
81 [HW_CONFIG_ID] = {UUID_HW_CONFIG},
82 [SOC_FW_CONFIG_ID] = {UUID_SOC_FW_CONFIG},
83 [TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG},
84 [NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG},
85 [RMM_IMAGE_ID] = {UUID_REALM_MONITOR_MGMT_FIRMWARE},
86 #if ETHOSN_NPU_TZMP1
87 [ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
88 #endif /* ETHOSN_NPU_TZMP1 */
89 #endif /* ARM_IO_IN_DTB */
90 #if TRUSTED_BOARD_BOOT
91 [TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT},
92 #if !ARM_IO_IN_DTB
93 [CCA_CONTENT_CERT_ID] = {UUID_CCA_CONTENT_CERT},
94 [CORE_SWD_KEY_CERT_ID] = {UUID_CORE_SWD_KEY_CERT},
95 [PLAT_KEY_CERT_ID] = {UUID_PLAT_KEY_CERT},
96 [TRUSTED_KEY_CERT_ID] = {UUID_TRUSTED_KEY_CERT},
97 [SCP_FW_KEY_CERT_ID] = {UUID_SCP_FW_KEY_CERT},
98 [SOC_FW_KEY_CERT_ID] = {UUID_SOC_FW_KEY_CERT},
99 [TRUSTED_OS_FW_KEY_CERT_ID] = {UUID_TRUSTED_OS_FW_KEY_CERT},
100 [NON_TRUSTED_FW_KEY_CERT_ID] = {UUID_NON_TRUSTED_FW_KEY_CERT},
101 [SCP_FW_CONTENT_CERT_ID] = {UUID_SCP_FW_CONTENT_CERT},
102 [SOC_FW_CONTENT_CERT_ID] = {UUID_SOC_FW_CONTENT_CERT},
103 [TRUSTED_OS_FW_CONTENT_CERT_ID] = {UUID_TRUSTED_OS_FW_CONTENT_CERT},
104 [NON_TRUSTED_FW_CONTENT_CERT_ID] = {UUID_NON_TRUSTED_FW_CONTENT_CERT},
105 #if defined(SPD_spmd)
106 [SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT},
107 [PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT},
108 #endif
109 #if ETHOSN_NPU_TZMP1
110 [ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
111 [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
112 #endif /* ETHOSN_NPU_TZMP1 */
113 #endif /* ARM_IO_IN_DTB */
114 #endif /* TRUSTED_BOARD_BOOT */
115 };
116
117 /* By default, ARM platforms load images from the FIP */
118 struct plat_io_policy policies[MAX_NUMBER_IDS] = {
119 #if ARM_GPT_SUPPORT
120 [GPT_IMAGE_ID] = {
121 &memmap_dev_handle,
122 (uintptr_t)&gpt_spec,
123 open_memmap
124 },
125 [BKUP_GPT_IMAGE_ID] = {
126 &memmap_dev_handle,
127 (uintptr_t)&bkup_gpt_spec,
128 open_memmap
129 },
130 #endif /* ARM_GPT_SUPPORT */
131 #if PSA_FWU_SUPPORT
132 [FWU_METADATA_IMAGE_ID] = {
133 &memmap_dev_handle,
134 /* filled runtime from partition information */
135 (uintptr_t)&fwu_metadata_spec,
136 open_memmap
137 },
138 [BKUP_FWU_METADATA_IMAGE_ID] = {
139 &memmap_dev_handle,
140 /* filled runtime from partition information */
141 (uintptr_t)&fwu_metadata_spec,
142 open_memmap
143 },
144 #endif /* PSA_FWU_SUPPORT */
145 [FIP_IMAGE_ID] = {
146 &memmap_dev_handle,
147 (uintptr_t)&fip_block_spec,
148 open_memmap
149 },
150 #if !defined(DECRYPTION_SUPPORT_none)
151 [ENC_IMAGE_ID] = {
152 &fip_dev_handle,
153 (uintptr_t)NULL,
154 open_fip
155 },
156 #endif
157 [BL2_IMAGE_ID] = {
158 &fip_dev_handle,
159 (uintptr_t)&arm_uuid_spec[BL2_IMAGE_ID],
160 open_fip
161 },
162 [TB_FW_CONFIG_ID] = {
163 &fip_dev_handle,
164 (uintptr_t)&arm_uuid_spec[TB_FW_CONFIG_ID],
165 open_fip
166 },
167 [FW_CONFIG_ID] = {
168 &fip_dev_handle,
169 (uintptr_t)&arm_uuid_spec[FW_CONFIG_ID],
170 open_fip
171 },
172 #if !ARM_IO_IN_DTB
173 [SCP_BL2_IMAGE_ID] = {
174 &fip_dev_handle,
175 (uintptr_t)&arm_uuid_spec[SCP_BL2_IMAGE_ID],
176 open_fip
177 },
178 #if ENCRYPT_BL31 && !defined(DECRYPTION_SUPPORT_none)
179 [BL31_IMAGE_ID] = {
180 &enc_dev_handle,
181 (uintptr_t)&arm_uuid_spec[BL31_IMAGE_ID],
182 open_enc_fip
183 },
184 #else
185 [BL31_IMAGE_ID] = {
186 &fip_dev_handle,
187 (uintptr_t)&arm_uuid_spec[BL31_IMAGE_ID],
188 open_fip
189 },
190 #endif
191 #if ENCRYPT_BL32 && !defined(DECRYPTION_SUPPORT_none)
192 [BL32_IMAGE_ID] = {
193 &enc_dev_handle,
194 (uintptr_t)&arm_uuid_spec[BL32_IMAGE_ID],
195 open_enc_fip
196 },
197 [BL32_EXTRA1_IMAGE_ID] = {
198 &enc_dev_handle,
199 (uintptr_t)&arm_uuid_spec[BL32_EXTRA1_IMAGE_ID],
200 open_enc_fip
201 },
202 [BL32_EXTRA2_IMAGE_ID] = {
203 &enc_dev_handle,
204 (uintptr_t)&arm_uuid_spec[BL32_EXTRA2_IMAGE_ID],
205 open_enc_fip
206 },
207 #else
208 [BL32_IMAGE_ID] = {
209 &fip_dev_handle,
210 (uintptr_t)&arm_uuid_spec[BL32_IMAGE_ID],
211 open_fip
212 },
213 [BL32_EXTRA1_IMAGE_ID] = {
214 &fip_dev_handle,
215 (uintptr_t)&arm_uuid_spec[BL32_EXTRA1_IMAGE_ID],
216 open_fip
217 },
218 [BL32_EXTRA2_IMAGE_ID] = {
219 &fip_dev_handle,
220 (uintptr_t)&arm_uuid_spec[BL32_EXTRA2_IMAGE_ID],
221 open_fip
222 },
223 #endif
224 [BL33_IMAGE_ID] = {
225 &fip_dev_handle,
226 (uintptr_t)&arm_uuid_spec[BL33_IMAGE_ID],
227 open_fip
228 },
229 [RMM_IMAGE_ID] = {
230 &fip_dev_handle,
231 (uintptr_t)&arm_uuid_spec[RMM_IMAGE_ID],
232 open_fip
233 },
234 [HW_CONFIG_ID] = {
235 &fip_dev_handle,
236 (uintptr_t)&arm_uuid_spec[HW_CONFIG_ID],
237 open_fip
238 },
239 [SOC_FW_CONFIG_ID] = {
240 &fip_dev_handle,
241 (uintptr_t)&arm_uuid_spec[SOC_FW_CONFIG_ID],
242 open_fip
243 },
244 [TOS_FW_CONFIG_ID] = {
245 &fip_dev_handle,
246 (uintptr_t)&arm_uuid_spec[TOS_FW_CONFIG_ID],
247 open_fip
248 },
249 [NT_FW_CONFIG_ID] = {
250 &fip_dev_handle,
251 (uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID],
252 open_fip
253 },
254 #if ETHOSN_NPU_TZMP1
255 [ETHOSN_NPU_FW_IMAGE_ID] = {
256 &fip_dev_handle,
257 (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_IMAGE_ID],
258 open_fip
259 },
260 #endif /* ETHOSN_NPU_TZMP1 */
261 #endif /* ARM_IO_IN_DTB */
262 #if TRUSTED_BOARD_BOOT
263 [TRUSTED_BOOT_FW_CERT_ID] = {
264 &fip_dev_handle,
265 (uintptr_t)&arm_uuid_spec[TRUSTED_BOOT_FW_CERT_ID],
266 open_fip
267 },
268 #if !ARM_IO_IN_DTB
269 [CCA_CONTENT_CERT_ID] = {
270 &fip_dev_handle,
271 (uintptr_t)&arm_uuid_spec[CCA_CONTENT_CERT_ID],
272 open_fip
273 },
274 [CORE_SWD_KEY_CERT_ID] = {
275 &fip_dev_handle,
276 (uintptr_t)&arm_uuid_spec[CORE_SWD_KEY_CERT_ID],
277 open_fip
278 },
279 [PLAT_KEY_CERT_ID] = {
280 &fip_dev_handle,
281 (uintptr_t)&arm_uuid_spec[PLAT_KEY_CERT_ID],
282 open_fip
283 },
284 [TRUSTED_KEY_CERT_ID] = {
285 &fip_dev_handle,
286 (uintptr_t)&arm_uuid_spec[TRUSTED_KEY_CERT_ID],
287 open_fip
288 },
289 [SCP_FW_KEY_CERT_ID] = {
290 &fip_dev_handle,
291 (uintptr_t)&arm_uuid_spec[SCP_FW_KEY_CERT_ID],
292 open_fip
293 },
294 [SOC_FW_KEY_CERT_ID] = {
295 &fip_dev_handle,
296 (uintptr_t)&arm_uuid_spec[SOC_FW_KEY_CERT_ID],
297 open_fip
298 },
299 [TRUSTED_OS_FW_KEY_CERT_ID] = {
300 &fip_dev_handle,
301 (uintptr_t)&arm_uuid_spec[TRUSTED_OS_FW_KEY_CERT_ID],
302 open_fip
303 },
304 [NON_TRUSTED_FW_KEY_CERT_ID] = {
305 &fip_dev_handle,
306 (uintptr_t)&arm_uuid_spec[NON_TRUSTED_FW_KEY_CERT_ID],
307 open_fip
308 },
309 [SCP_FW_CONTENT_CERT_ID] = {
310 &fip_dev_handle,
311 (uintptr_t)&arm_uuid_spec[SCP_FW_CONTENT_CERT_ID],
312 open_fip
313 },
314 [SOC_FW_CONTENT_CERT_ID] = {
315 &fip_dev_handle,
316 (uintptr_t)&arm_uuid_spec[SOC_FW_CONTENT_CERT_ID],
317 open_fip
318 },
319 [TRUSTED_OS_FW_CONTENT_CERT_ID] = {
320 &fip_dev_handle,
321 (uintptr_t)&arm_uuid_spec[TRUSTED_OS_FW_CONTENT_CERT_ID],
322 open_fip
323 },
324 [NON_TRUSTED_FW_CONTENT_CERT_ID] = {
325 &fip_dev_handle,
326 (uintptr_t)&arm_uuid_spec[NON_TRUSTED_FW_CONTENT_CERT_ID],
327 open_fip
328 },
329 #if defined(SPD_spmd)
330 [SIP_SP_CONTENT_CERT_ID] = {
331 &fip_dev_handle,
332 (uintptr_t)&arm_uuid_spec[SIP_SP_CONTENT_CERT_ID],
333 open_fip
334 },
335 [PLAT_SP_CONTENT_CERT_ID] = {
336 &fip_dev_handle,
337 (uintptr_t)&arm_uuid_spec[PLAT_SP_CONTENT_CERT_ID],
338 open_fip
339 },
340 #endif
341 #if ETHOSN_NPU_TZMP1
342 [ETHOSN_NPU_FW_KEY_CERT_ID] = {
343 &fip_dev_handle,
344 (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_KEY_CERT_ID],
345 open_fip
346 },
347 [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
348 &fip_dev_handle,
349 (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_CONTENT_CERT_ID],
350 open_fip
351 },
352 #endif /* ETHOSN_NPU_TZMP1 */
353 #endif /* ARM_IO_IN_DTB */
354 #endif /* TRUSTED_BOARD_BOOT */
355 };
356
357 #ifdef IMAGE_BL2
358
359 #define FCONF_ARM_IO_UUID_NUM_BASE U(10)
360
361 #if ETHOSN_NPU_TZMP1
362 #define FCONF_ARM_IO_UUID_NUM_NPU U(1)
363 #else
364 #define FCONF_ARM_IO_UUID_NUM_NPU U(0)
365 #endif /* ETHOSN_NPU_TZMP1 */
366
367 #if TRUSTED_BOARD_BOOT
368 #define FCONF_ARM_IO_UUID_NUM_TBB U(12)
369 #else
370 #define FCONF_ARM_IO_UUID_NUM_TBB U(0)
371 #endif /* TRUSTED_BOARD_BOOT */
372
373 #if TRUSTED_BOARD_BOOT && defined(SPD_spmd)
374 #define FCONF_ARM_IO_UUID_NUM_SPD U(2)
375 #else
376 #define FCONF_ARM_IO_UUID_NUM_SPD U(0)
377 #endif /* TRUSTED_BOARD_BOOT && defined(SPD_spmd) */
378
379 #if TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1
380 #define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(2)
381 #else
382 #define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(0)
383 #endif /* TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 */
384
385 #define FCONF_ARM_IO_UUID_NUMBER FCONF_ARM_IO_UUID_NUM_BASE + \
386 FCONF_ARM_IO_UUID_NUM_NPU + \
387 FCONF_ARM_IO_UUID_NUM_TBB + \
388 FCONF_ARM_IO_UUID_NUM_SPD + \
389 FCONF_ARM_IO_UUID_NUM_NPU_TBB
390
391 static io_uuid_spec_t fconf_arm_uuids[FCONF_ARM_IO_UUID_NUMBER];
392 static OBJECT_POOL_ARRAY(fconf_arm_uuids_pool, fconf_arm_uuids);
393
394 struct policies_load_info {
395 unsigned int image_id;
396 const char *name;
397 };
398
399 /* image id to property name table */
400 static const struct policies_load_info load_info[FCONF_ARM_IO_UUID_NUMBER] = {
401 {SCP_BL2_IMAGE_ID, "scp_bl2_uuid"},
402 {BL31_IMAGE_ID, "bl31_uuid"},
403 {BL32_IMAGE_ID, "bl32_uuid"},
404 {BL32_EXTRA1_IMAGE_ID, "bl32_extra1_uuid"},
405 {BL32_EXTRA2_IMAGE_ID, "bl32_extra2_uuid"},
406 {BL33_IMAGE_ID, "bl33_uuid"},
407 {HW_CONFIG_ID, "hw_cfg_uuid"},
408 {SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"},
409 {TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"},
410 {NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"},
411 #if ETHOSN_NPU_TZMP1
412 {ETHOSN_NPU_FW_IMAGE_ID, "ethosn_npu_fw_uuid"},
413 #endif /* ETHOSN_NPU_TZMP1 */
414 #if TRUSTED_BOARD_BOOT
415 {CCA_CONTENT_CERT_ID, "cca_cert_uuid"},
416 {CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"},
417 {PLAT_KEY_CERT_ID, "plat_cert_uuid"},
418 {TRUSTED_KEY_CERT_ID, "t_key_cert_uuid"},
419 {SCP_FW_KEY_CERT_ID, "scp_fw_key_uuid"},
420 {SOC_FW_KEY_CERT_ID, "soc_fw_key_uuid"},
421 {TRUSTED_OS_FW_KEY_CERT_ID, "tos_fw_key_cert_uuid"},
422 {NON_TRUSTED_FW_KEY_CERT_ID, "nt_fw_key_cert_uuid"},
423 {SCP_FW_CONTENT_CERT_ID, "scp_fw_content_cert_uuid"},
424 {SOC_FW_CONTENT_CERT_ID, "soc_fw_content_cert_uuid"},
425 {TRUSTED_OS_FW_CONTENT_CERT_ID, "tos_fw_content_cert_uuid"},
426 {NON_TRUSTED_FW_CONTENT_CERT_ID, "nt_fw_content_cert_uuid"},
427 #if defined(SPD_spmd)
428 {SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"},
429 {PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"},
430 #endif
431 #if ETHOSN_NPU_TZMP1
432 {ETHOSN_NPU_FW_KEY_CERT_ID, "ethosn_npu_fw_key_cert_uuid"},
433 {ETHOSN_NPU_FW_CONTENT_CERT_ID, "ethosn_npu_fw_content_cert_uuid"},
434 #endif /* ETHOSN_NPU_TZMP1 */
435 #endif /* TRUSTED_BOARD_BOOT */
436 };
437
fconf_populate_arm_io_policies(uintptr_t config)438 int fconf_populate_arm_io_policies(uintptr_t config)
439 {
440 int err, node;
441 unsigned int i;
442
443 union uuid_helper_t uuid_helper;
444 io_uuid_spec_t *uuid_ptr;
445
446 /* As libfdt uses void *, we can't avoid this cast */
447 const void *dtb = (void *)config;
448
449 /* Assert the node offset point to "arm,io-fip-handle" compatible property */
450 const char *compatible_str = "arm,io-fip-handle";
451 node = fdt_node_offset_by_compatible(dtb, -1, compatible_str);
452 if (node < 0) {
453 ERROR("FCONF: Can't find %s compatible in dtb\n", compatible_str);
454 return node;
455 }
456
457 /* Locate the uuid cells and read the value for all the load info uuid */
458 for (i = 0; i < FCONF_ARM_IO_UUID_NUMBER; i++) {
459 uuid_ptr = pool_alloc(&fconf_arm_uuids_pool);
460 err = fdtw_read_uuid(dtb, node, load_info[i].name, 16,
461 (uint8_t *)&uuid_helper);
462 if (err < 0) {
463 WARN("FCONF: Read cell failed for %s\n", load_info[i].name);
464 return err;
465 }
466
467 VERBOSE("FCONF: arm-io_policies.%s cell found with value = "
468 "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x\n",
469 load_info[i].name,
470 uuid_helper.uuid_struct.time_low[0], uuid_helper.uuid_struct.time_low[1],
471 uuid_helper.uuid_struct.time_low[2], uuid_helper.uuid_struct.time_low[3],
472 uuid_helper.uuid_struct.time_mid[0], uuid_helper.uuid_struct.time_mid[1],
473 uuid_helper.uuid_struct.time_hi_and_version[0],
474 uuid_helper.uuid_struct.time_hi_and_version[1],
475 uuid_helper.uuid_struct.clock_seq_hi_and_reserved,
476 uuid_helper.uuid_struct.clock_seq_low,
477 uuid_helper.uuid_struct.node[0], uuid_helper.uuid_struct.node[1],
478 uuid_helper.uuid_struct.node[2], uuid_helper.uuid_struct.node[3],
479 uuid_helper.uuid_struct.node[4], uuid_helper.uuid_struct.node[5]);
480
481 uuid_ptr->uuid = uuid_helper.uuid_struct;
482 policies[load_info[i].image_id].image_spec = (uintptr_t)uuid_ptr;
483 policies[load_info[i].image_id].dev_handle = &fip_dev_handle;
484 policies[load_info[i].image_id].check = open_fip;
485 }
486 return 0;
487 }
488
489 #if ARM_IO_IN_DTB
490 FCONF_REGISTER_POPULATOR(TB_FW, arm_io, fconf_populate_arm_io_policies);
491 #endif /* ARM_IO_IN_DTB */
492
493 #endif /* IMAGE_BL2 */
494