1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Based on arch/arm/kernel/setup.c
4 *
5 * Copyright (C) 1995-2001 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/export.h>
11 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/ioport.h>
14 #include <linux/delay.h>
15 #include <linux/initrd.h>
16 #include <linux/console.h>
17 #include <linux/cache.h>
18 #include <linux/screen_info.h>
19 #include <linux/init.h>
20 #include <linux/kexec.h>
21 #include <linux/root_dev.h>
22 #include <linux/cpu.h>
23 #include <linux/interrupt.h>
24 #include <linux/smp.h>
25 #include <linux/fs.h>
26 #include <linux/proc_fs.h>
27 #include <linux/memblock.h>
28 #include <linux/of_fdt.h>
29 #include <linux/efi.h>
30 #include <linux/psci.h>
31 #include <linux/sched/task.h>
32 #include <linux/mm.h>
33
34 #include <asm/acpi.h>
35 #include <asm/fixmap.h>
36 #include <asm/cpu.h>
37 #include <asm/cputype.h>
38 #include <asm/daifflags.h>
39 #include <asm/elf.h>
40 #include <asm/cpufeature.h>
41 #include <asm/cpu_ops.h>
42 #include <asm/kasan.h>
43 #include <asm/numa.h>
44 #include <asm/sections.h>
45 #include <asm/setup.h>
46 #include <asm/smp_plat.h>
47 #include <asm/cacheflush.h>
48 #include <asm/tlbflush.h>
49 #include <asm/traps.h>
50 #include <asm/efi.h>
51 #include <asm/xen/hypervisor.h>
52 #include <asm/mmu_context.h>
53
54 static int num_standard_resources;
55 static struct resource *standard_resources;
56
57 phys_addr_t __fdt_pointer __initdata;
58
59 /*
60 * Standard memory resources
61 */
62 static struct resource mem_res[] = {
63 {
64 .name = "Kernel code",
65 .start = 0,
66 .end = 0,
67 .flags = IORESOURCE_SYSTEM_RAM
68 },
69 {
70 .name = "Kernel data",
71 .start = 0,
72 .end = 0,
73 .flags = IORESOURCE_SYSTEM_RAM
74 }
75 };
76
77 #define kernel_code mem_res[0]
78 #define kernel_data mem_res[1]
79
80 /*
81 * The recorded values of x0 .. x3 upon kernel entry.
82 */
83 u64 __cacheline_aligned boot_args[4];
84
smp_setup_processor_id(void)85 void __init smp_setup_processor_id(void)
86 {
87 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
88 set_cpu_logical_map(0, mpidr);
89
90 /*
91 * clear __my_cpu_offset on boot CPU to avoid hang caused by
92 * using percpu variable early, for example, lockdep will
93 * access percpu variable inside lock_release
94 */
95 set_my_cpu_offset(0);
96 pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n",
97 (unsigned long)mpidr, read_cpuid_id());
98 }
99
arch_match_cpu_phys_id(int cpu,u64 phys_id)100 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
101 {
102 return phys_id == cpu_logical_map(cpu);
103 }
104
105 struct mpidr_hash mpidr_hash;
106 /**
107 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
108 * level in order to build a linear index from an
109 * MPIDR value. Resulting algorithm is a collision
110 * free hash carried out through shifting and ORing
111 */
smp_build_mpidr_hash(void)112 static void __init smp_build_mpidr_hash(void)
113 {
114 u32 i, affinity, fs[4], bits[4], ls;
115 u64 mask = 0;
116 /*
117 * Pre-scan the list of MPIDRS and filter out bits that do
118 * not contribute to affinity levels, ie they never toggle.
119 */
120 for_each_possible_cpu(i)
121 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
122 pr_debug("mask of set bits %#llx\n", mask);
123 /*
124 * Find and stash the last and first bit set at all affinity levels to
125 * check how many bits are required to represent them.
126 */
127 for (i = 0; i < 4; i++) {
128 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
129 /*
130 * Find the MSB bit and LSB bits position
131 * to determine how many bits are required
132 * to express the affinity level.
133 */
134 ls = fls(affinity);
135 fs[i] = affinity ? ffs(affinity) - 1 : 0;
136 bits[i] = ls - fs[i];
137 }
138 /*
139 * An index can be created from the MPIDR_EL1 by isolating the
140 * significant bits at each affinity level and by shifting
141 * them in order to compress the 32 bits values space to a
142 * compressed set of values. This is equivalent to hashing
143 * the MPIDR_EL1 through shifting and ORing. It is a collision free
144 * hash though not minimal since some levels might contain a number
145 * of CPUs that is not an exact power of 2 and their bit
146 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
147 */
148 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
149 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
150 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
151 (bits[1] + bits[0]);
152 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
153 fs[3] - (bits[2] + bits[1] + bits[0]);
154 mpidr_hash.mask = mask;
155 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
156 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
157 mpidr_hash.shift_aff[0],
158 mpidr_hash.shift_aff[1],
159 mpidr_hash.shift_aff[2],
160 mpidr_hash.shift_aff[3],
161 mpidr_hash.mask,
162 mpidr_hash.bits);
163 /*
164 * 4x is an arbitrary value used to warn on a hash table much bigger
165 * than expected on most systems.
166 */
167 if (mpidr_hash_size() > 4 * num_possible_cpus())
168 pr_warn("Large number of MPIDR hash buckets detected\n");
169 }
170
171 static void *early_fdt_ptr __initdata;
172
get_early_fdt_ptr(void)173 void __init *get_early_fdt_ptr(void)
174 {
175 return early_fdt_ptr;
176 }
177
early_fdt_map(u64 dt_phys)178 asmlinkage void __init early_fdt_map(u64 dt_phys)
179 {
180 int fdt_size;
181
182 early_fixmap_init();
183 early_fdt_ptr = fixmap_remap_fdt(dt_phys, &fdt_size, PAGE_KERNEL);
184 }
185
setup_machine_fdt(phys_addr_t dt_phys)186 static void __init setup_machine_fdt(phys_addr_t dt_phys)
187 {
188 int size;
189 void *dt_virt = fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL);
190 const char *name;
191
192 if (dt_virt)
193 memblock_reserve(dt_phys, size);
194
195 if (!dt_virt || !early_init_dt_scan(dt_virt)) {
196 pr_crit("\n"
197 "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
198 "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
199 "\nPlease check your bootloader.",
200 &dt_phys, dt_virt);
201
202 while (true)
203 cpu_relax();
204 }
205
206 /* Early fixups are done, map the FDT as read-only now */
207 fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL_RO);
208
209 name = of_flat_dt_get_machine_name();
210 if (!name)
211 return;
212
213 pr_info("Machine model: %s\n", name);
214 dump_stack_set_arch_desc("%s (DT)", name);
215 }
216
request_standard_resources(void)217 static void __init request_standard_resources(void)
218 {
219 struct memblock_region *region;
220 struct resource *res;
221 unsigned long i = 0;
222 size_t res_size;
223
224 kernel_code.start = __pa_symbol(_text);
225 kernel_code.end = __pa_symbol(__init_begin - 1);
226 kernel_data.start = __pa_symbol(_sdata);
227 kernel_data.end = __pa_symbol(_end - 1);
228
229 num_standard_resources = memblock.memory.cnt;
230 res_size = num_standard_resources * sizeof(*standard_resources);
231 standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES);
232 if (!standard_resources)
233 panic("%s: Failed to allocate %zu bytes\n", __func__, res_size);
234
235 for_each_mem_region(region) {
236 res = &standard_resources[i++];
237 if (memblock_is_nomap(region)) {
238 res->name = "reserved";
239 res->flags = IORESOURCE_MEM;
240 } else {
241 res->name = "System RAM";
242 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
243 }
244 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
245 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
246
247 request_resource(&iomem_resource, res);
248
249 if (kernel_code.start >= res->start &&
250 kernel_code.end <= res->end)
251 request_resource(res, &kernel_code);
252 if (kernel_data.start >= res->start &&
253 kernel_data.end <= res->end)
254 request_resource(res, &kernel_data);
255 #ifdef CONFIG_KEXEC_CORE
256 /* Userspace will find "Crash kernel" region in /proc/iomem. */
257 if (crashk_res.end && crashk_res.start >= res->start &&
258 crashk_res.end <= res->end)
259 request_resource(res, &crashk_res);
260 #endif
261 }
262 }
263
reserve_memblock_reserved_regions(void)264 static int __init reserve_memblock_reserved_regions(void)
265 {
266 u64 i, j;
267
268 for (i = 0; i < num_standard_resources; ++i) {
269 struct resource *mem = &standard_resources[i];
270 phys_addr_t r_start, r_end, mem_size = resource_size(mem);
271
272 if (!memblock_is_region_reserved(mem->start, mem_size))
273 continue;
274
275 for_each_reserved_mem_range(j, &r_start, &r_end) {
276 resource_size_t start, end;
277
278 start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start);
279 end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end);
280
281 if (start > mem->end || end < mem->start)
282 continue;
283
284 reserve_region_with_split(mem, start, end, "reserved");
285 }
286 }
287
288 return 0;
289 }
290 arch_initcall(reserve_memblock_reserved_regions);
291
292 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
293
cpu_logical_map(unsigned int cpu)294 u64 cpu_logical_map(unsigned int cpu)
295 {
296 return __cpu_logical_map[cpu];
297 }
298
setup_arch(char ** cmdline_p)299 void __init __no_sanitize_address setup_arch(char **cmdline_p)
300 {
301 init_mm.start_code = (unsigned long) _text;
302 init_mm.end_code = (unsigned long) _etext;
303 init_mm.end_data = (unsigned long) _edata;
304 init_mm.brk = (unsigned long) _end;
305
306 *cmdline_p = boot_command_line;
307
308 /*
309 * If know now we are going to need KPTI then use non-global
310 * mappings from the start, avoiding the cost of rewriting
311 * everything later.
312 */
313 arm64_use_ng_mappings = kaslr_requires_kpti();
314
315 early_fixmap_init();
316 early_ioremap_init();
317
318 setup_machine_fdt(__fdt_pointer);
319
320 /*
321 * Initialise the static keys early as they may be enabled by the
322 * cpufeature code and early parameters.
323 */
324 jump_label_init();
325 parse_early_param();
326
327 /*
328 * Unmask asynchronous aborts and fiq after bringing up possible
329 * earlycon. (Report possible System Errors once we can report this
330 * occurred).
331 */
332 local_daif_restore(DAIF_PROCCTX_NOIRQ);
333
334 /*
335 * TTBR0 is only used for the identity mapping at this stage. Make it
336 * point to zero page to avoid speculatively fetching new entries.
337 */
338 cpu_uninstall_idmap();
339
340 xen_early_init();
341 efi_init();
342
343 if (!efi_enabled(EFI_BOOT) && ((u64)_text % MIN_KIMG_ALIGN) != 0)
344 pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
345
346 arm64_memblock_init();
347
348 paging_init();
349
350 acpi_table_upgrade();
351
352 /* Parse the ACPI tables for possible boot-time configuration */
353 acpi_boot_table_init();
354
355 if (acpi_disabled)
356 unflatten_device_tree();
357
358 bootmem_init();
359
360 kasan_init();
361
362 request_standard_resources();
363
364 early_ioremap_reset();
365
366 if (acpi_disabled)
367 psci_dt_init();
368 else
369 psci_acpi_init();
370
371 init_bootcpu_ops();
372 smp_init_cpus();
373 smp_build_mpidr_hash();
374
375 /* Init percpu seeds for random tags after cpus are set up. */
376 kasan_init_sw_tags();
377
378 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
379 /*
380 * Make sure init_thread_info.ttbr0 always generates translation
381 * faults in case uaccess_enable() is inadvertently called by the init
382 * thread.
383 */
384 init_task.thread_info.ttbr0 = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
385 #endif
386
387 if (boot_args[1] || boot_args[2] || boot_args[3]) {
388 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
389 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
390 "This indicates a broken bootloader or old kernel\n",
391 boot_args[1], boot_args[2], boot_args[3]);
392 }
393 }
394
cpu_can_disable(unsigned int cpu)395 static inline bool cpu_can_disable(unsigned int cpu)
396 {
397 #ifdef CONFIG_HOTPLUG_CPU
398 const struct cpu_operations *ops = get_cpu_ops(cpu);
399
400 if (ops && ops->cpu_can_disable)
401 return ops->cpu_can_disable(cpu);
402 #endif
403 return false;
404 }
405
topology_init(void)406 static int __init topology_init(void)
407 {
408 int i;
409
410 for_each_online_node(i)
411 register_one_node(i);
412
413 for_each_possible_cpu(i) {
414 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
415 cpu->hotpluggable = cpu_can_disable(i);
416 register_cpu(cpu, i);
417 }
418
419 return 0;
420 }
421 subsys_initcall(topology_init);
422
dump_kernel_offset(void)423 static void dump_kernel_offset(void)
424 {
425 const unsigned long offset = kaslr_offset();
426
427 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) {
428 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n",
429 offset, KIMAGE_VADDR);
430 pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET);
431 } else {
432 pr_emerg("Kernel Offset: disabled\n");
433 }
434 }
435
arm64_panic_block_dump(struct notifier_block * self,unsigned long v,void * p)436 static int arm64_panic_block_dump(struct notifier_block *self,
437 unsigned long v, void *p)
438 {
439 dump_kernel_offset();
440 dump_cpu_features();
441 dump_mem_limit();
442 return 0;
443 }
444
445 static struct notifier_block arm64_panic_block = {
446 .notifier_call = arm64_panic_block_dump
447 };
448
register_arm64_panic_block(void)449 static int __init register_arm64_panic_block(void)
450 {
451 atomic_notifier_chain_register(&panic_notifier_list,
452 &arm64_panic_block);
453 return 0;
454 }
455 device_initcall(register_arm64_panic_block);
456