1 /* 2 * Driver for Rockchip TSP Controller 3 * 4 * Copyright (C) 2012-2016 ROCKCHIP, Inc. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _RK_TSP_H 17 #define _RK_TSP_H 18 19 #include <linux/types.h> 20 21 #define _SBF(s, v) ((v) << (s)) 22 23 #define TSP_GCFG 0x0000 24 #define TSOUT_ON BIT(3) 25 #define PVR_ON BIT(2) 26 #define PTI1_ON BIT(1) 27 #define PTI0_ON BIT(0) 28 29 #define PVR_CTRL 0x0004 30 #define PVR_BURST_INCR4 _SBF(4, 0x00) 31 #define PVR_BURST_INCR8 _SBF(4, 0x01) 32 #define PVR_BURST_INCR16 _SBF(4, 0x02) 33 #define PVR_SOURCE_NO_PID_FILTER_PTI0 _SBF(2, 0x00) 34 #define PVR_SOURCE_PID_FILTER_PTI0 _SBF(2, 0x01) 35 #define PVR_SOURCE_NO_PID_FILTER_PTI1 _SBF(2, 0x02) 36 #define PVR_SOURCE_PID_FILTER_PTI1 _SBF(2, 0x03) 37 #define PVR_STOP BIT(1) 38 #define PVR_START BIT(0) 39 40 #define PVR_LEN 0x0008 41 #define PVR_ADDR 0x000c 42 #define PVR_INT_STS 0x0010 43 #define PVR_INT_ENA 0x0014 44 #define TSOUT_CTRL 0x0018 45 46 #define PVR_TOP_ADDR 0x001c 47 #define PVR_WRITE_ADDR 0x0020 48 49 #define PTI0_CTRL 0x0100 50 #define TS_ERROR_NOT_OUTPUT _SBF(19, 0x00) 51 #define TS_ERROR_SET_INDICATOR _SBF(19, 0x01) 52 #define TS_ERROR_NOT_CARE _SBF(19, 0x02) 53 #define TS_CLK_PHASE_SEL BIT(18) 54 #define DEMUX_BURST_INCR4 _SBF(16, 0x00) 55 #define DEMUX_BURST_INCR8 _SBF(16, 0x01) 56 #define DEMUX_BURST_INCR16 _SBF(16, 0x02) 57 #define SYNC_BYPASS BIT(15) 58 #define CW_BYTEORDER BIT(14) 59 #define CM_ON BIT(13) 60 #define SERIAL_SYNC_VALID_MODE _SBF(11, 0x00) 61 #define PARALLEL_SYNC_VALID_MODE _SBF(11, 0x01) 62 #define PARALLEL_SYNC_BURST_MODE _SBF(11, 0x02) 63 #define PARALLEL_NOSYNC_VALID_MODE _SBF(11, 0x03) 64 #define TSI_BIT_ORDER BIT(10) 65 /* 0: memory, 1: hsadc */ 66 #define TSI_SEL BIT(9) 67 #define OUT_BYTESWAP BIT(8) 68 #define IN_BYTESWAP BIT(7) 69 #define SOFT_CLEAR BIT(0) 70 71 #define PTI0_LLP_CFG 0x0104 72 #define PTI0_LLP_BASE 0x0108 73 #define PTI0_LLP_WRITE 0x010c 74 #define PTI0_LLP_READ 0x0110 75 #define PTI0_PID_STS0 0x0114 76 #define PTI0_PID_STS1 0x0118 77 #define PTI0_PID_STS2 0x011c 78 #define PTI0_PID_STS3 0x0120 79 #define PTI0_PID_INT_ENA0 0x0124 80 #define PTI0_PID_INT_ENA1 0x0128 81 #define PTI0_PID_INT_ENA2 0x012c 82 #define PTI0_PID_INT_ENA3 0x0130 83 #define PTI0_PCR_INT_STS 0x0134 84 #define PTI0_PCR_INT_ENA 0x0138 85 #define PTI0_PCR0_CTRL 0x013c 86 #define PTI0_PCR0_H 0x015c 87 #define PTI0_PCR0_L 0x0160 88 #define PTI0_DMA_STS 0x019c 89 #define PTI0_DMA_ENA 0x01a0 90 #define PTI0_DATA_FLAG0 0x01a4 91 #define PTI0_DATA_FLAG1 0x01a8 92 #define PTI0_LIST_FLAG 0x01ac 93 #define PTI0_DST_STS0 0x01b0 94 #define PTI0_DST_STS1 0x01b4 95 #define PTI0_DST_ENA0 0x01b8 96 #define PTI0_DST_ENA1 0x01bc 97 #define PTI0_ECW0_H 0x0200 98 #define PTI0_ECW0_L 0x0204 99 #define PTI0_OCW0_H 0x0208 100 #define PTI0_OCW0_L 0x020c 101 #define PTI0_PID0_CTRL 0x0300 102 #define PTI0_PID0_BASE 0x0400 103 #define PTI0_PID0_TOP 0x0404 104 #define PTI0_PID0_WRITE 0x0408 105 #define PTI0_PID0_READ 0x040c 106 #define PTI0_LIST0_BASE 0x0800 107 #define PTI0_LIST0_TOP 0x0804 108 #define PTI0_LIST0_WRITE 0x0808 109 #define PTI0_LIST0_READ 0x080c 110 #define PTI0_PID0_CFG 0x0900 111 #define PTI0_PID0_FILT_0 0x0904 112 #define PTI0_PID0_FILT_1 0x0908 113 #define PTI0_PID0_FILT_2 0x090c 114 #define PTI0_PID0_FILT_3 0x0910 115 116 #define MMU_DTE_ADDR 0x08800 117 #define MMU_STATUS 0x08804 118 #define MMU_COMMAND 0x08808 119 #define MMU_PAGE_FAULT_ADDR 0x0880c 120 #define MMU_ZAP_ONE_LINE 0x08810 121 #define MMU_INT_RAWSTAT 0x08814 122 #define MMU_INT_CLEAR 0x08818 123 #define MMU_INT_MASK 0x0881c 124 #define MMU_INT_STATUS 0x08820 125 #define MMU_AUTO_GATING 0x08824 126 #define MMU_MISS_CNT 0x08828 127 #define MMU_BURST_CNT 0x0882c 128 129 #define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb)) 130 131 enum soc_type { 132 RK312X, 133 RK3228, 134 RK3328, 135 }; 136 137 enum grf_fields { 138 TSP_IO_GROUP_SEL, 139 TSP_VALID, 140 TSP_FAIL, 141 TSP_CLK, 142 TSP_SYNCM0, 143 TSP_D0, 144 TSP_D1, 145 TSP_D2, 146 TSP_D3, 147 TSP_D4, 148 TSP_D5M0, 149 TSP_D6M0, 150 TSP_D7M0, 151 TSP_SYNCM1, 152 TSP_D5M1, 153 TSP_D6M1, 154 TSP_D7M1, 155 MAX_FIELDS, 156 }; 157 158 enum tsp_filter_type { 159 TSP_SECTION_FILTER = 1, 160 TSP_PES_FILTER = 2, 161 TSP_ES_FILTER = 4, 162 TSP_TS_FILTER = 8, 163 }; 164 165 struct rockchip_tsp_plat_data { 166 const u32 *grf_reg_fields; 167 enum soc_type soc_type; 168 }; 169 170 struct tsp_ctx { 171 int pid; 172 int index; 173 uint filter_type; /*bit 0~3: section, pes, es, ts*/ 174 u8 *base; 175 u8 *top; 176 u8 *write; 177 u8 *read; 178 u8 *buf; 179 u32 buf_len; 180 dma_addr_t dma_buf; 181 u8 filter_byte[TSP_DMX_FILTER_SIZE]; 182 u8 filter_mask[TSP_DMX_FILTER_SIZE]; 183 void (*get_data_callback)(const u8 *buf, size_t count, u16 pid); 184 struct list_head pid_list; 185 }; 186 187 struct tsp_dev { 188 struct device *dev; 189 void __iomem *ioaddr; 190 struct regmap *grf; 191 struct clk *tsp_clk; 192 struct clk *tsp_aclk; 193 struct clk *tsp_hclk; 194 int tsp_irq; 195 int serial_parallel_mode; 196 struct list_head pid_list; 197 /* lock for list operate */ 198 spinlock_t list_lock; 199 200 int is_open; 201 202 /* timer */ 203 struct timer_list timer; 204 205 /* ts workque */ 206 struct work_struct ts_work; 207 struct workqueue_struct *ts_queue; 208 /* mutex for feed buf to dvb-core */ 209 struct mutex ts_mutex; 210 211 /* section workque */ 212 struct work_struct sec_work; 213 struct workqueue_struct *sec_queue; 214 215 int tsp_start_descram; 216 217 struct rockchip_tsp_channel_info channel_info[64]; 218 unsigned long channel_release_timeout[64]; 219 const struct rockchip_tsp_plat_data *pdata; 220 }; 221 222 #define TSP_CMD_IO_OPEN _IO('o', 120) 223 #define TSP_CMD_IO_CLOSE _IO('o', 121) 224 #define TSP_CMD_SET_PCR_PID _IOW('o', 122, ca_descr_t) 225 #define TSP_CMD_GET_PCR_VAL _IOR('o', 123, ca_descr_t) 226 #define TSP_CMD_SET_DESCAM_PID _IOW('o', 124, ca_descr_t) 227 #define TSP_CMD_SET_LIVE_STATUS _IOW('o', 125, ca_descr_t) 228 #define TSP_CMD_RESET_REGS _IOW('o', 126, ca_descr_t) 229 230 #endif 231