1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
5 */
6
7 #ifndef __LINUX_MTD_SPI_NOR_H
8 #define __LINUX_MTD_SPI_NOR_H
9
10 #include <linux/bitops.h>
11 #include <linux/mtd/cfi.h>
12 #include <linux/mtd/mtd.h>
13
14 /*
15 * Manufacturer IDs
16 *
17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
18 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
19 */
20 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
21 #define SNOR_MFR_GIGADEVICE 0xc8
22 #define SNOR_MFR_INTEL CFI_MFR_INTEL
23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
25 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
26 #define SNOR_MFR_SPANSION CFI_MFR_AMD
27 #define SNOR_MFR_SST CFI_MFR_SST
28 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
29 #define SNOR_MFR_NORMEM CFI_MFR_NORMEM
30
31 /*
32 * Note on opcode nomenclature: some opcodes have a format like
33 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
34 * of I/O lines used for the opcode, address, and data (respectively). The
35 * FUNCTION has an optional suffix of '4', to represent an opcode which
36 * requires a 4-byte (32-bit) address.
37 */
38
39 /* Flash opcodes. */
40 #define SPINOR_OP_WREN 0x06 /* Write enable */
41 #define SPINOR_OP_RDSR 0x05 /* Read status register */
42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
43 #define SPINOR_OP_WRCR 0x31 /* Write configure register 1 byte */
44 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
45 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
46 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
47 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
48 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
49 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
50 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
51 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
52 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
53 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
54 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
55 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
56 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
57 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
58 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
59 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
60 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
61 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
62 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
63 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
64 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
65 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
66 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
67 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
68 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
69 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
70 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
71
72 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
73 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
74 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
75 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
76 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
77 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
78 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
79 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
80 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
81 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
82 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
83 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
84 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
85 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
86 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
87 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
88 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
89
90 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
91 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
92 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
93 #define SPINOR_OP_READ_1_4_4_DTR 0xed
94
95 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
96 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
97 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
98
99 /* Used for SST flashes only. */
100 #define SPINOR_OP_BP 0x02 /* Byte program */
101 #define SPINOR_OP_WRDI 0x04 /* Write disable */
102 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
103
104 /* Used for SST26* flashes only. */
105 #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
106 #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
107
108 /* Used for S3AN flashes only */
109 #define SPINOR_OP_XSE 0x50 /* Sector erase */
110 #define SPINOR_OP_XPP 0x82 /* Page program */
111 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
112
113 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
114 #define XSR_RDY BIT(7) /* Ready */
115
116 /* Used for Macronix and Winbond flashes. */
117 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
118 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
119
120 /* Used for Spansion flashes only. */
121 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
122 #define SPINOR_OP_BRRD 0x16 /* Bank register read */
123 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
124
125 /* Used for Micron flashes only. */
126 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
127 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
128
129 /* Status Register bits. */
130 #define SR_WIP BIT(0) /* Write in progress */
131 #define SR_WEL BIT(1) /* Write enable latch */
132 /* meaning of other SR_* bits may differ between vendors */
133 #define SR_BP0 BIT(2) /* Block protect 0 */
134 #define SR_BP1 BIT(3) /* Block protect 1 */
135 #define SR_BP2 BIT(4) /* Block protect 2 */
136 #define SR_TB BIT(5) /* Top/Bottom protect */
137 #define SR_SRWD BIT(7) /* SR write protect */
138 /* Spansion/Cypress specific status bits */
139 #define SR_E_ERR BIT(5)
140 #define SR_P_ERR BIT(6)
141
142 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
143
144 /* Enhanced Volatile Configuration Register bits */
145 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
146
147 #define SR_QUAD_EN_NORMEM BIT(2) /* NORMEM Quad I/O */
148
149 /* Flag Status Register bits */
150 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
151 #define FSR_E_ERR BIT(5) /* Erase operation status */
152 #define FSR_P_ERR BIT(4) /* Program operation status */
153 #define FSR_PT_ERR BIT(1) /* Protection error bit */
154
155 /* Configuration Register bits. */
156 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
157
158 /* Status Register 2 bits. */
159 #define SR2_QUAD_EN_BIT7 BIT(7)
160
161 /* Supported SPI protocols */
162 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
163 #define SNOR_PROTO_INST_SHIFT 16
164 #define SNOR_PROTO_INST(_nbits) \
165 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
166 SNOR_PROTO_INST_MASK)
167
168 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
169 #define SNOR_PROTO_ADDR_SHIFT 8
170 #define SNOR_PROTO_ADDR(_nbits) \
171 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
172 SNOR_PROTO_ADDR_MASK)
173
174 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
175 #define SNOR_PROTO_DATA_SHIFT 0
176 #define SNOR_PROTO_DATA(_nbits) \
177 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
178 SNOR_PROTO_DATA_MASK)
179
180 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
181
182 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
183 (SNOR_PROTO_INST(_inst_nbits) | \
184 SNOR_PROTO_ADDR(_addr_nbits) | \
185 SNOR_PROTO_DATA(_data_nbits))
186 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
187 (SNOR_PROTO_IS_DTR | \
188 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
189
190 enum spi_nor_protocol {
191 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
192 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
193 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
194 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
195 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
196 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
197 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
198 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
199 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
200 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
201
202 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
203 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
204 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
205 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
206 };
207
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)208 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
209 {
210 return !!(proto & SNOR_PROTO_IS_DTR);
211 }
212
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)213 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
214 {
215 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
216 SNOR_PROTO_INST_SHIFT;
217 }
218
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)219 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
220 {
221 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
222 SNOR_PROTO_ADDR_SHIFT;
223 }
224
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)225 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
226 {
227 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
228 SNOR_PROTO_DATA_SHIFT;
229 }
230
spi_nor_get_protocol_width(enum spi_nor_protocol proto)231 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
232 {
233 return spi_nor_get_protocol_data_nbits(proto);
234 }
235
236 #define SPI_NOR_MAX_CMD_SIZE 8
237 enum spi_nor_ops {
238 SPI_NOR_OPS_READ = 0,
239 SPI_NOR_OPS_WRITE,
240 SPI_NOR_OPS_ERASE,
241 SPI_NOR_OPS_LOCK,
242 SPI_NOR_OPS_UNLOCK,
243 };
244
245 enum spi_nor_option_flags {
246 SNOR_F_USE_FSR = BIT(0),
247 SNOR_F_HAS_SR_TB = BIT(1),
248 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
249 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
250 SNOR_F_READY_XSR_RDY = BIT(4),
251 SNOR_F_USE_CLSR = BIT(5),
252 SNOR_F_BROKEN_RESET = BIT(6),
253 };
254
255 /**
256 * struct flash_info - Forward declaration of a structure used internally by
257 * spi_nor_scan()
258 */
259 struct flash_info;
260
261 /* TODO: Remove, once all users of spi_flash interface are moved to MTD */
262 #define spi_flash spi_nor
263
264 /**
265 * struct spi_nor - Structure for defining a the SPI NOR layer
266 * @mtd: point to a mtd_info structure
267 * @lock: the lock for the read/write/erase/lock/unlock operations
268 * @dev: point to a spi device, or a spi nor controller device.
269 * @info: spi-nor part JDEC MFR id and other info
270 * @page_size: the page size of the SPI NOR
271 * @addr_width: number of address bytes
272 * @erase_opcode: the opcode for erasing a sector
273 * @read_opcode: the read opcode
274 * @read_dummy: the dummy needed by the read operation
275 * @program_opcode: the program opcode
276 * @bank_read_cmd: Bank read cmd
277 * @bank_write_cmd: Bank write cmd
278 * @bank_curr: Current flash bank
279 * @sst_write_second: used by the SST write operation
280 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
281 * @read_proto: the SPI protocol for read operations
282 * @write_proto: the SPI protocol for write operations
283 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
284 * @cmd_buf: used by the write_reg
285 * @prepare: [OPTIONAL] do some preparations for the
286 * read/write/erase/lock/unlock operations
287 * @unprepare: [OPTIONAL] do some post work after the
288 * read/write/erase/lock/unlock operations
289 * @read_reg: [DRIVER-SPECIFIC] read out the register
290 * @write_reg: [DRIVER-SPECIFIC] write data to the register
291 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
292 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
293 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
294 * at the offset @offs; if not provided by the driver,
295 * spi-nor will send the erase opcode via write_reg()
296 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
297 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
298 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
299 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
300 * completely locked
301 * @priv: the private data
302 */
303 struct spi_nor {
304 struct mtd_info mtd;
305 struct udevice *dev;
306 struct spi_slave *spi;
307 const struct flash_info *info;
308 u32 page_size;
309 u8 addr_width;
310 u8 erase_opcode;
311 u8 read_opcode;
312 u8 read_dummy;
313 u8 program_opcode;
314 #ifdef CONFIG_SPI_FLASH_BAR
315 u8 bank_read_cmd;
316 u8 bank_write_cmd;
317 u8 bank_curr;
318 #endif
319 enum spi_nor_protocol read_proto;
320 enum spi_nor_protocol write_proto;
321 enum spi_nor_protocol reg_proto;
322 bool sst_write_second;
323 u32 flags;
324 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
325
326 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
327 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
328 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
329 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
330
331 ssize_t (*read)(struct spi_nor *nor, loff_t from,
332 size_t len, u_char *read_buf);
333 ssize_t (*write)(struct spi_nor *nor, loff_t to,
334 size_t len, const u_char *write_buf);
335 int (*erase)(struct spi_nor *nor, loff_t offs);
336
337 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
338 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
339 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
340 int (*quad_enable)(struct spi_nor *nor);
341
342 void *priv;
343 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
344 const char *name;
345 u32 size;
346 u32 sector_size;
347 u32 erase_size;
348 };
349
spi_nor_set_flash_node(struct spi_nor * nor,const struct device_node * np)350 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
351 const struct device_node *np)
352 {
353 mtd_set_of_node(&nor->mtd, np);
354 }
355
356 static inline const struct
spi_nor_get_flash_node(struct spi_nor * nor)357 device_node *spi_nor_get_flash_node(struct spi_nor *nor)
358 {
359 return mtd_get_of_node(&nor->mtd);
360 }
361
362 /**
363 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
364 * supported by the SPI controller (bus master).
365 * @mask: the bitmask listing all the supported hw capabilies
366 */
367 struct spi_nor_hwcaps {
368 u32 mask;
369 };
370
371 /*
372 *(Fast) Read capabilities.
373 * MUST be ordered by priority: the higher bit position, the higher priority.
374 * As a matter of performances, it is relevant to use Octo SPI protocols first,
375 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
376 * (Slow) Read.
377 */
378 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
379 #define SNOR_HWCAPS_READ BIT(0)
380 #define SNOR_HWCAPS_READ_FAST BIT(1)
381 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
382
383 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
384 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
385 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
386 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
387 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
388
389 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
390 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
391 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
392 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
393 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
394
395 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
396 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
397 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
398 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
399 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
400
401 /*
402 * Page Program capabilities.
403 * MUST be ordered by priority: the higher bit position, the higher priority.
404 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
405 * legacy SPI 1-1-1 protocol.
406 * Note that Dual Page Programs are not supported because there is no existing
407 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
408 * implements such commands.
409 */
410 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
411 #define SNOR_HWCAPS_PP BIT(16)
412
413 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
414 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
415 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
416 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
417
418 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
419 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
420 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
421 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
422
423 /**
424 * spi_nor_scan() - scan the SPI NOR
425 * @nor: the spi_nor structure
426 *
427 * The drivers can use this function to scan the SPI NOR.
428 * In the scanning, it will try to get all the necessary information to
429 * fill the mtd_info{} and the spi_nor{}.
430 *
431 * Return: 0 for success, others for failure.
432 */
433 int spi_nor_scan(struct spi_nor *nor);
434
435 #endif
436