1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __HAL_JPEGE_VPU720_REG_H__ 7 #define __HAL_JPEGE_VPU720_REG_H__ 8 9 #include "rk_type.h" 10 11 typedef struct JpegeVpu720BaseReg_t { 12 // 0x0000, IP version 13 RK_U32 reg000_version; 14 // 0x0004, Start Command 15 struct { 16 // Number of new nodes added to link table 17 RK_U32 lkt_num : 8; 18 /** 19 * @brief VEPU command 20 * 0 -- N/A 21 * 1 -- One-frame encoding by register configuration 22 * 2 -- Multi-frame encoding start with link table mode 23 * 3 -- Multi-frame encoding update (with link table mode) 24 * 4 -- link table encoding force pause 25 * 5 -- continue link table encoder when link table stop 26 * 6 -- safe_clr 27 * 7 -- force_clr 28 */ 29 RK_U32 vepu_cmd : 4; 30 RK_U32 : 20; 31 } reg001_enc_strt; 32 33 /*reserved 0x8 ~ 0xC*/ 34 RK_U32 reg002_003[2]; 35 36 // 0x0010, Interrupt Enable 37 struct { 38 // One frame encoding finish interrupt enable 39 RK_U32 fenc_done_en : 1; 40 // Link table one node finish interrupt enable 41 RK_U32 lkt_node_done_en : 1; 42 // Safe clear finish interrupt enable 43 RK_U32 sclr_done_en : 1; 44 // One slice of video encoding finish interrupt enable 45 RK_U32 vslc_done_en : 1; 46 // Video bit stream buffer overflow interrupt enable 47 RK_U32 vbsb_oflw_en : 1; 48 // Video bit stream buffer write section interrupt enable 49 RK_U32 vbsb_sct_en : 1; 50 // Frame encoding error interrupt enable 51 RK_U32 fenc_err_en : 1; 52 // Watch dog (timeout) interrupt enable 53 RK_U32 wdg_en : 1; 54 // Link table operation error interrupt enable 55 RK_U32 lkt_oerr_en : 1; 56 // Link table encoding error stop interrupt enable 57 RK_U32 lkt_estp_en : 1; 58 // Link cmd force pause interrupt enable 59 RK_U32 lkt_fstp_en : 1; 60 // Link table note stop interrupt enable 61 RK_U32 lkt_note_stp_en : 1; 62 RK_U32 lkt_data_error_en : 1; 63 RK_U32 : 19; 64 } reg004_int_en; 65 66 // 0x0014, Interrupt Mask 67 struct { 68 RK_U32 fenc_done_msk : 1; 69 RK_U32 lkt_node_done_msk : 1; 70 RK_U32 sclr_done_msk : 1; 71 RK_U32 vslc_done_msk : 1; 72 RK_U32 vbsb_oflw_msk : 1; 73 RK_U32 vbsb_sct_msk : 1; 74 RK_U32 fenc_err_msk : 1; 75 RK_U32 wdg_msk : 1; 76 RK_U32 lkt_oerr_msk : 1; 77 RK_U32 lkt_estp_msk : 1; 78 RK_U32 lkt_fstp_msk : 1; 79 RK_U32 lkt_note_stp_msk : 1; 80 RK_U32 lkt_data_error_msk : 1; 81 RK_U32 : 19; 82 } reg005_int_msk; 83 84 // 0x0018, Interrupt Clear 85 struct { 86 RK_U32 fenc_done_clr : 1; 87 RK_U32 lkt_node_done_clr : 1; 88 RK_U32 sclr_done_clr : 1; 89 RK_U32 vslc_done_clr : 1; 90 RK_U32 vbsb_oflw_clr : 1; 91 RK_U32 vbsb_sct_clr : 1; 92 RK_U32 fenc_err_clr : 1; 93 RK_U32 wdg_clr : 1; 94 RK_U32 lkt_oerr_clr : 1; 95 RK_U32 lkt_estp_clr : 1; 96 RK_U32 lkt_fstp_clr : 1; 97 RK_U32 lkt_note_stp_clr : 1; 98 RK_U32 lkt_data_error_clr : 1; 99 RK_U32 : 19; 100 } reg006_int_clr; 101 102 // 0x001c, Interrupt State; 103 struct { 104 RK_U32 fenc_done_state : 1; 105 RK_U32 lkt_node_done_state : 1; 106 RK_U32 sclr_done_state : 1; 107 RK_U32 vslc_done_state : 1; 108 RK_U32 vbsb_oflw_state : 1; 109 RK_U32 vbsb_sct_state : 1; 110 RK_U32 fenc_err_state : 1; 111 RK_U32 wdg_state : 1; 112 RK_U32 lkt_oerr_state : 1; 113 RK_U32 lkt_estp_state : 1; 114 RK_U32 lkt_fstp_state : 1; 115 RK_U32 lkt_note_stp_state : 1; 116 RK_U32 lkt_data_error_state : 1; 117 RK_U32 : 19; 118 } reg007_int_state; 119 120 // 0x0020, Clock and RST CTRL 121 struct { 122 // Encoder auto reset core clock domain when frame finished 123 RK_U32 resetn_hw_en : 1; 124 // Encoder SRAM auto clock gating enable 125 RK_U32 sram_ckg_en : 1; 126 // Auto clock gating enable 127 RK_U32 cke : 1; 128 RK_U32 : 29; 129 } reg008_cru_ctrl; 130 131 // 0x0024, Fast link table cfg buffer addr, 128 byte aligned 132 RK_U32 reg009_lkt_base_addr; 133 134 // 0x0028, Link table node operation configuration 135 struct { 136 // Only the ejpeg with the same core ID can use this node 137 RK_U32 core_id : 4; 138 // The enable of lkt error stop next frame 139 RK_U32 lkt_err_stop_en : 1; 140 // The enable of lkt frame stop when the frame end 141 RK_U32 lkt_node_stop_en : 1; 142 RK_U32 : 10; 143 /** 144 * @brief Data swap for link table read channel. 145 * bit[3] -- swap 64 bits in 128 bits 146 * bit[2] -- swap 32 bits in 64 bits; 147 * bit[1] -- swap 16 bits in 32 bits; 148 * bit[0] -- swap 8 bits in 16 bits; 149 */ 150 RK_U32 lktr_bus_edin : 4; 151 /** 152 * @brief 153 * Data swap for link table write channel. 154 * bit[3] -- swap 64 bits in 128 bits 155 * bit[2] -- swap 32 bits in 64 bits; 156 * bit[1] -- swap 16 bits in 32 bits; 157 * bit[0] -- swap 8 bits in 16 bits; 158 */ 159 RK_U32 lktw_bus_edin : 4; 160 RK_U32 : 8; 161 } reg010_node_ocfg; 162 163 // 0x002c, watch dog configure register 164 RK_U32 reg011_wdg_jpeg; 165 166 // reserved, 0x0030 167 RK_U32 reg012; 168 169 // 0x0034, low delay esc operation configuration. Bit[0-30] : read ecs num. 170 RK_U32 reg013_low_delay_ecs_ocfg; 171 // 0x0038, low delay packet operation configuration. Bit[0-30] : read packet num. 172 RK_U32 reg014_low_delay_packet_ocfg; 173 174 // reserved, 0x003c 175 RK_U32 reg015; 176 177 // 0x0040, Address of JPEG Q table buffer, 128 byte aligned 178 RK_U32 reg016_adr_qtbl; 179 // 0x0044, Top address of JPEG Bit stream buffer, 16 byte aligned 180 RK_U32 reg017_adr_bsbt; 181 // 0x0048, Bottom address of JPEG bit stream buffer, 16 byte aligned 182 RK_U32 reg018_adr_bsbb; 183 // 0x004c, Read Address of JPEG bit stream buffer, 1 byte aligned 184 RK_U32 reg019_adr_bsbr; 185 // 0x0050, Start address of JPEG bit stream buffer, 1 byte aligned 186 RK_U32 reg020_adr_bsbs; 187 // 0x0054, Base address of ECS length buffer, 8 byte align 188 RK_U32 reg021_adr_ecs_len; 189 // 0x0058, Base address of the 1st storage area for video source buffer 190 RK_U32 reg022_adr_src0; 191 // 0x005c, Base address of the 2nd storage area for video source buffer 192 RK_U32 reg023_adr_src1; 193 // 0x0060, Base address of the 3rd storage area for video source buffer 194 RK_U32 reg024_adr_src2; 195 196 // reserved, 0x0064 197 RK_U32 reg025; 198 199 // 0x0068, rk jpeg encoder axi performance ctrl0 description 200 struct { 201 RK_U32 perf_work_e : 1; 202 RK_U32 perf_clr_e : 1; 203 RK_U32 perf_frm_type : 1; 204 RK_U32 cnt_type : 1; 205 RK_U32 rd_latency_id : 4; 206 RK_U32 rd_latency_thr : 12; 207 RK_U32 : 12; 208 } reg026_axi_perf_ctrl0; 209 210 // 0x006c, rk jpeg encoder axi performance ctrl1 description 211 struct { 212 RK_U32 addr_align_type : 2; 213 RK_U32 ar_cnt_id_type : 1; 214 RK_U32 aw_cnt_id_type : 1; 215 RK_U32 ar_count_id : 4; 216 RK_U32 aw_count_id : 4; 217 RK_U32 rd_total_bytes_mode : 1; 218 RK_U32 : 19; 219 } reg027_axi_perf_ctrl1; 220 221 // 0x0070, reserved 222 RK_U32 reg028; 223 224 // 0x0074, picture size 225 struct { 226 // Ceil(encoding picture height / 8) -1 227 RK_U32 pic_wd8_m1 : 13; 228 RK_U32 : 3; 229 // Ceil(encoding picture height / 8) -1 230 RK_U32 pic_hd8_m1 : 13; 231 RK_U32 : 3; 232 } reg029_sw_enc_rsl; 233 234 // 0x0078, JPEG source filling pixels for align 235 struct { 236 RK_U32 pic_wfill_jpeg : 6; 237 RK_U32 : 10; 238 RK_U32 pic_hfill_jpeg : 6; 239 RK_U32 : 10; 240 } reg030_sw_src_fill; 241 242 /* reserved 0x7c */ 243 RK_U32 reg031; 244 245 // 0x0080, JPEG source format 246 struct { 247 RK_U32 : 1; 248 RK_U32 rbuv_swap_jpeg : 1; 249 /** 250 * @brief srouce color format 251 * 4'h0: tile400 252 * 4'h1: tile420 253 * 4'h2: tile422 254 * 4'h3: tile444 255 * 4'h4: YUV422SP 256 * 4'h5: YUV422P 257 * 4'h6: YUV420SP 258 * 4'h7: YUV420P 259 * 4'h8: YUYV422 260 * 4'h9: UYVY422 261 * 4'ha: YUV400 262 * 4'hc: YUV444SP 263 * 4'hd: YUV444P 264 * Others: Reserved 265 */ 266 RK_U32 src_fmt : 4; 267 /** 268 * @brief color format of output from preprocess 269 * 2'h0: YUV400; 270 * 2'h1: YUV420; 271 * 2'h2: YUV422; 272 * 2'h3: YUV444; 273 * 274 */ 275 RK_U32 out_fmt : 2; 276 RK_U32 : 1; 277 RK_U32 src_range_trns_en : 1; 278 RK_U32 src_range_trns_sel : 1; 279 /** 280 * @brief Chroma downsample mode 281 * 0 -- Average 282 * 1 -- Drop 283 */ 284 RK_U32 chroma_ds_mode : 1; 285 // Chroma value will be force to some value 286 RK_U32 chroma_force_en : 1; 287 RK_U32 : 2; 288 // 1 00 src mirror image 289 RK_U32 src_mirr_jpeg : 1; 290 RK_U32 u_force_value : 8; 291 RK_U32 v_force_value : 8; 292 } reg032_sw_src_fmt; 293 294 // 0x0084, encoding picture offset 295 struct { 296 RK_U32 pic_ofst_x : 16; 297 RK_U32 pic_ofst_y : 16; 298 } reg033_sw_pic_ofst; 299 300 // 0x0088, JPEG source stride0 301 struct { 302 RK_U32 src_strd_0 : 20; 303 RK_U32 : 12; 304 } reg034_sw_src_strd_0; 305 306 // 0x008c, JPEG source stride1 307 struct { 308 RK_U32 src_strd_1 : 19; 309 RK_U32 : 13; 310 } reg035_sw_src_strd_1; 311 312 // 0x0090, JPEG common config 313 struct { 314 /* the number of MCU in the restart interval */ 315 RK_U32 rst_intv : 16; 316 RK_U32 : 9; 317 /** 318 * @brief JPEG encoder output mode 319 * 1'b0: frame by frame, without interrupt at any ECS; 320 * 1'b1: low latency mode, with interrupt per ECS, flush all the 321 * bit stream after each ECS finished. 322 */ 323 RK_U32 out_mode : 1; 324 /* the number of the fisrt RSTm */ 325 RK_U32 rst_m : 3; 326 /** 327 * @brief Indicate if the current ECS is the last ECS of the whole picture. 328 * If it is the last ecs, add EOI. 329 */ 330 RK_U32 pic_last_ecs : 1; 331 /** 332 * @brief reload Q table or not 333 * 0 -- load Q table for current task 334 * 1 -- no need to load Q table 335 */ 336 RK_U32 jpeg_qtble_noload : 1; 337 RK_U32 : 1; 338 } reg036_sw_jpeg_enc_cfg; 339 340 // 0x0094, Low dealy packet size config 341 RK_U32 reg037_bsp_size_jpeg; 342 343 // 0x0098, Bit stream output padding config 344 struct { 345 RK_U32 uvc_partition0_len : 12; 346 RK_U32 uvc_partition_len : 12; 347 RK_U32 uvc_skip_len : 6; 348 RK_U32 : 2; 349 } reg038_sw_uvc_cfg; 350 351 // 0x009c, Y Quantify rounding 352 struct { 353 /* bias for Y at quantization */ 354 RK_U32 bias_y : 15; 355 RK_U32 : 17; 356 } reg039_sw_jpeg_y_cfg; 357 358 // 0x00a0, U Quantify rounding 359 struct { 360 361 /* bias for U at quantization */ 362 RK_U32 bias_u : 15; 363 RK_U32 : 17; 364 } reg040_sw_jpeg_u_cfg; 365 366 // 0x00a4, V Quantify rounding 367 struct { 368 /* bias for V at quantization */ 369 RK_U32 bias_v : 15; 370 RK_U32 : 17; 371 } reg041_sw_jpeg_v_cfg; 372 373 // 0x00a8, Data bus endian 374 struct { 375 /** 376 * @brief Data swap for jpeg bit stream write channel 377 * [3]: Swap 64 bits in 128 bits 378 * [2]: Swap 32 bits in 64 bits 379 * [1]: Swap 16 bits in 32 bits 380 * [0]: Swap 8 bits in 16 bits 381 */ 382 RK_U32 jbsw_bus_edin : 4; 383 // Data swap for video source loading channel. 384 RK_U32 vsl_bus_edin : 4; 385 // Data swap for lkt state write channel 386 RK_U32 ecs_len_edin : 4; 387 // Data swap for qtbl read channel 388 RK_U32 sw_qtbl_edin : 4; 389 } reg042_dbus_endn; 390 391 } JpegeVpu720BaseReg; 392 393 typedef struct JpegeVpu720StatusReg_t { 394 // 0x00c0, Low 32 bits of JPEG header bits length. 395 RK_U32 st_bsl_l32_jpeg_head_bits; 396 // 0x00c4, High 32 bits of JPEG header bits length 397 RK_U32 st_bsl_h32_jpeg_head_bits; 398 399 // 0x00c8, Y and U source range 400 struct { 401 RK_U32 y_max_value : 8; 402 RK_U32 y_min_value : 8; 403 RK_U32 u_max_value : 8; 404 RK_U32 u_min_vlaue : 8; 405 } st_vsp_value0; 406 407 // 0x00cc, V source range and total_ecs_num_minus 408 struct { 409 RK_U32 v_max_value : 8; 410 RK_U32 v_min_vlaue : 8; 411 RK_U32 total_ecs_num_minus1 : 8; 412 } st_vsp_value1; 413 414 // 0x00d0, bit[0-15] 415 RK_U32 st_perf_rd_max_latency_num0; 416 // 0x00d4 417 RK_U32 st_perf_rd_latency_samp_num; 418 // 0x00d8 419 RK_U32 st_perf_rd_latency_acc_sum; 420 // 0x00dc 421 RK_U32 st_perf_rd_axi_total_byte; 422 // 0x00e0 423 RK_U32 st_perf_wr_axi_total_byte; 424 // 0x00e4 425 RK_U32 st_perf_working_cnt; 426 427 RK_U32 sw_reserved_00e8_00ec[2]; 428 429 // 0x00f0 430 struct { 431 RK_U32 vsp_work_flag : 1; 432 RK_U32 jpeg_core_work_flag : 1; 433 RK_U32 dma_wr_work_flag : 1; 434 RK_U32 dma_work_flag : 1; 435 } st_wdg; 436 437 // 0x00f4 438 RK_U32 st_ppl_pos; 439 // 0x00f8 440 RK_U32 st_core_pos; 441 442 // 0x00fc, Bus status 443 struct { 444 RK_U32 ejpeg_arready : 1; 445 RK_U32 ejpeg_cfg_arvalid : 1; 446 RK_U32 ejpeg_cfg_arvalid_type : 1; 447 RK_U32 ejpeg_cfg_arready : 1; 448 RK_U32 ejpeg_vsp_arvalid : 1; 449 RK_U32 ejpeg_vsp_arready : 1; 450 RK_U32 rkejpeg_arvalid : 1; 451 RK_U32 ejpeg_cfg_ar_cnt : 2; 452 RK_U32 rkejpeg_arready : 1; 453 RK_U32 rkejpeg_ravlid : 1; 454 RK_U32 rkejpeg_rid : 4; 455 RK_U32 rkejpeg_rresp : 2; 456 RK_U32 rkejpeg_rready : 1; 457 RK_U32 axi_wr_state_cs : 1; 458 RK_U32 ejpeg_strmd_awvalid : 1; 459 RK_U32 ejpeg_strmd_awtype : 1; 460 RK_U32 ejpeg_strmd_awready : 1; 461 RK_U32 ejpeg_strmd_wvalid : 1; 462 RK_U32 ejpeg_strmd_wready : 1; 463 RK_U32 ejpeg_cfg_awvalid : 1; 464 RK_U32 ejpeg_cfg_awready : 1; 465 RK_U32 rkejpeg_awvalid : 1; 466 RK_U32 rkejpeg_awid : 1; 467 RK_U32 rkejpeg_wvalid : 1; 468 RK_U32 rkejpeg_wready : 1; 469 RK_U32 ejpeg_freeze_flag : 1; 470 RK_U32 : 1; 471 } st_bus; 472 473 // 0x0100, vsp_dbg_status 474 RK_U32 dbg_ppl; 475 // 0x0104, jpeg core dbg status 476 RK_U32 dbg_jpeg_core; 477 // reserved, 0x0108 478 RK_U32 sw_reserved_0108; 479 // 0x010c, The bit stream write address status 480 RK_U32 st_adr_jbsbw; 481 // 0x0110, ECS length buffer write address status 482 RK_U32 st_adr_ecs_len; 483 // 0x0114, the 1st storage aread for video source buffer read address status 484 RK_U32 st_adr_src0_jpeg; 485 // 0x0118, the 2nd storage aread for video source buffer read address status 486 RK_U32 st_adr_src1_jpeg; 487 // 0x011c, the 3rd storage aread for video source buffer read address status 488 RK_U32 st_adr_src2_jpeg; 489 490 // 0x0120, low delay packet num status 491 struct { 492 RK_U32 bs_packet_num : 16; 493 RK_U32 bs_packet_lst : 1; 494 } st_low_delay_packet_num; 495 496 // 0x0124, low delay ecs_len num status 497 struct { 498 RK_U32 ecs_len_num : 16; 499 RK_U32 ecs_len_lst : 1; 500 } st_ecs_len_num; 501 502 // 0x0128, JPEG common status 503 struct { 504 /** 505 * @brief 506 * 0: idle 507 * 1: cru open 508 * 2: lkt cfg load 509 * 3: qtbl_cfg_load 510 * 4:enc 511 * 5:frame end 512 * 6:cru_close 513 * 7:lkt_error_stop 514 * 8:lkt_force_stop 515 * 9:lkt_node_stop 516 */ 517 RK_U32 jpeg_enc_state : 4; 518 RK_U32 lkt_mode_en : 1; 519 } st_enc; 520 521 // 0x012c, Link table num 522 struct { 523 RK_U32 lkt_cfg_num : 8; 524 RK_U32 lkt_done_num : 8; 525 RK_U32 lkt_int_num : 8; 526 RK_U32 lkt_cfg_load_num : 8; 527 } st_lkt_num; 528 529 // 0x0130, link table cfg info 530 struct { 531 RK_U32 lkt_core_id : 4; 532 RK_U32 : 4; 533 RK_U32 lkt_stop_flag : 1; 534 RK_U32 lkt_node_int : 1; 535 RK_U32 lkt_task_id : 12; 536 RK_U32 : 10; 537 } st_lkt_info; 538 539 //0x0134, next read addr for lkt_cfg 540 RK_U32 st_lkt_cfg_next_addr; 541 //0x0138, lkt state buffer write addr 542 RK_U32 st_lkt_waddr; 543 } JpegeVpu720StatusReg; 544 545 546 #define JPEGE_VPU720_REG_BASE_INT_STATE (0x1c) 547 #define JPEGE_VPU720_REG_STATUS_OFFSET (0xc0) 548 549 typedef struct JpegeVpu720RegSet_t { 550 JpegeVpu720BaseReg reg_base; 551 JpegeVpu720StatusReg reg_st; 552 RK_U32 int_state; 553 } JpegeVpu720Reg; 554 555 #endif /* __HAL_JPEGE_VPU720_REG_H__ */