1 /*
2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <malloc.h>
14 #include <memalign.h>
15 #include <miiphy.h>
16 #include <net.h>
17 #include <netdev.h>
18 #include "fec_mxc.h"
19
20 #include <asm/io.h>
21 #include <linux/errno.h>
22 #include <linux/compiler.h>
23
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/mach-imx/sys_proto.h>
27 #include <asm-generic/gpio.h>
28
29 #include "fec_mxc.h"
30 #include <eth_phy.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 /*
35 * Timeout the transfer after 5 mS. This is usually a bit more, since
36 * the code in the tightloops this timeout is used in adds some overhead.
37 */
38 #define FEC_XFER_TIMEOUT 5000
39
40 /*
41 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
42 * 64-byte alignment in the DMA RX FEC buffer.
43 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
44 * satisfies the alignment on other SoCs (32-bytes)
45 */
46 #define FEC_DMA_RX_MINALIGN 64
47
48 #ifndef CONFIG_MII
49 #error "CONFIG_MII has to be defined!"
50 #endif
51
52 #ifndef CONFIG_FEC_XCV_TYPE
53 #define CONFIG_FEC_XCV_TYPE MII100
54 #endif
55
56 /*
57 * The i.MX28 operates with packets in big endian. We need to swap them before
58 * sending and after receiving.
59 */
60 #ifdef CONFIG_MX28
61 #define CONFIG_FEC_MXC_SWAP_PACKET
62 #endif
63
64 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
65
66 /* Check various alignment issues at compile time */
67 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
68 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
69 #endif
70
71 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
72 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
73 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
74 #endif
75
76 #undef DEBUG
77
78 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet(uint32_t * packet,int length)79 static void swap_packet(uint32_t *packet, int length)
80 {
81 int i;
82
83 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
84 packet[i] = __swab32(packet[i]);
85 }
86 #endif
87
88 /* MII-interface related functions */
fec_mdio_read(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr)89 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
90 uint8_t regaddr)
91 {
92 uint32_t reg; /* convenient holder for the PHY register */
93 uint32_t phy; /* convenient holder for the PHY */
94 uint32_t start;
95 int val;
96
97 /*
98 * reading from any PHY's register is done by properly
99 * programming the FEC's MII data register.
100 */
101 writel(FEC_IEVENT_MII, ð->ievent);
102 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
103 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
104
105 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
106 phy | reg, ð->mii_data);
107
108 /* wait for the related interrupt */
109 start = get_timer(0);
110 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
111 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
112 printf("Read MDIO failed...\n");
113 return -1;
114 }
115 }
116
117 /* clear mii interrupt bit */
118 writel(FEC_IEVENT_MII, ð->ievent);
119
120 /* it's now safe to read the PHY's register */
121 val = (unsigned short)readl(ð->mii_data);
122 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
123 regaddr, val);
124 return val;
125 }
126
fec_mii_setspeed(struct ethernet_regs * eth)127 static void fec_mii_setspeed(struct ethernet_regs *eth)
128 {
129 /*
130 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
131 * and do not drop the Preamble.
132 *
133 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
134 * MII_SPEED) register that defines the MDIO output hold time. Earlier
135 * versions are RAZ there, so just ignore the difference and write the
136 * register always.
137 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
138 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
139 * output.
140 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
141 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
142 * holdtime cannot result in a value greater than 3.
143 */
144 u32 pclk = imx_get_fecclk();
145 u32 speed = DIV_ROUND_UP(pclk, 5000000);
146 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
147 #ifdef FEC_QUIRK_ENET_MAC
148 speed--;
149 #endif
150 writel(speed << 1 | hold << 8, ð->mii_speed);
151 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
152 }
153
fec_mdio_write(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr,uint16_t data)154 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
155 uint8_t regaddr, uint16_t data)
156 {
157 uint32_t reg; /* convenient holder for the PHY register */
158 uint32_t phy; /* convenient holder for the PHY */
159 uint32_t start;
160
161 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
162 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
163
164 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
165 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
166
167 /* wait for the MII interrupt */
168 start = get_timer(0);
169 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
170 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
171 printf("Write MDIO failed...\n");
172 return -1;
173 }
174 }
175
176 /* clear MII interrupt bit */
177 writel(FEC_IEVENT_MII, ð->ievent);
178 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
179 regaddr, data);
180
181 return 0;
182 }
183
fec_phy_read(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr)184 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
185 int regaddr)
186 {
187 return fec_mdio_read(bus->priv, phyaddr, regaddr);
188 }
189
fec_phy_write(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr,u16 data)190 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
191 int regaddr, u16 data)
192 {
193 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
194 }
195
196 #ifndef CONFIG_PHYLIB
miiphy_restart_aneg(struct eth_device * dev)197 static int miiphy_restart_aneg(struct eth_device *dev)
198 {
199 int ret = 0;
200 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
201 struct fec_priv *fec = (struct fec_priv *)dev->priv;
202 struct ethernet_regs *eth = fec->bus->priv;
203
204 /*
205 * Wake up from sleep if necessary
206 * Reset PHY, then delay 300ns
207 */
208 #ifdef CONFIG_MX27
209 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
210 #endif
211 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
212 udelay(1000);
213
214 /* Set the auto-negotiation advertisement register bits */
215 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
216 LPA_100FULL | LPA_100HALF | LPA_10FULL |
217 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
218 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
219 BMCR_ANENABLE | BMCR_ANRESTART);
220
221 if (fec->mii_postcall)
222 ret = fec->mii_postcall(fec->phy_id);
223
224 #endif
225 return ret;
226 }
227
228 #ifndef CONFIG_FEC_FIXED_SPEED
miiphy_wait_aneg(struct eth_device * dev)229 static int miiphy_wait_aneg(struct eth_device *dev)
230 {
231 uint32_t start;
232 int status;
233 struct fec_priv *fec = (struct fec_priv *)dev->priv;
234 struct ethernet_regs *eth = fec->bus->priv;
235
236 /* Wait for AN completion */
237 start = get_timer(0);
238 do {
239 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
240 printf("%s: Autonegotiation timeout\n", dev->name);
241 return -1;
242 }
243
244 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
245 if (status < 0) {
246 printf("%s: Autonegotiation failed. status: %d\n",
247 dev->name, status);
248 return -1;
249 }
250 } while (!(status & BMSR_LSTATUS));
251
252 return 0;
253 }
254 #endif /* CONFIG_FEC_FIXED_SPEED */
255 #endif
256
fec_rx_task_enable(struct fec_priv * fec)257 static int fec_rx_task_enable(struct fec_priv *fec)
258 {
259 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
260 return 0;
261 }
262
fec_rx_task_disable(struct fec_priv * fec)263 static int fec_rx_task_disable(struct fec_priv *fec)
264 {
265 return 0;
266 }
267
fec_tx_task_enable(struct fec_priv * fec)268 static int fec_tx_task_enable(struct fec_priv *fec)
269 {
270 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
271 return 0;
272 }
273
fec_tx_task_disable(struct fec_priv * fec)274 static int fec_tx_task_disable(struct fec_priv *fec)
275 {
276 return 0;
277 }
278
279 /**
280 * Initialize receive task's buffer descriptors
281 * @param[in] fec all we know about the device yet
282 * @param[in] count receive buffer count to be allocated
283 * @param[in] dsize desired size of each receive buffer
284 * @return 0 on success
285 *
286 * Init all RX descriptors to default values.
287 */
fec_rbd_init(struct fec_priv * fec,int count,int dsize)288 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
289 {
290 uint32_t size;
291 uint8_t *data;
292 int i;
293
294 /*
295 * Reload the RX descriptors with default values and wipe
296 * the RX buffers.
297 */
298 size = roundup(dsize, ARCH_DMA_MINALIGN);
299 for (i = 0; i < count; i++) {
300 data = (uint8_t *)fec->rbd_base[i].data_pointer;
301 memset(data, 0, dsize);
302 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
303
304 fec->rbd_base[i].status = FEC_RBD_EMPTY;
305 fec->rbd_base[i].data_length = 0;
306 }
307
308 /* Mark the last RBD to close the ring. */
309 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
310 fec->rbd_index = 0;
311
312 flush_dcache_range((unsigned)fec->rbd_base,
313 (unsigned)fec->rbd_base + size);
314 }
315
316 /**
317 * Initialize transmit task's buffer descriptors
318 * @param[in] fec all we know about the device yet
319 *
320 * Transmit buffers are created externally. We only have to init the BDs here.\n
321 * Note: There is a race condition in the hardware. When only one BD is in
322 * use it must be marked with the WRAP bit to use it for every transmitt.
323 * This bit in combination with the READY bit results into double transmit
324 * of each data buffer. It seems the state machine checks READY earlier then
325 * resetting it after the first transfer.
326 * Using two BDs solves this issue.
327 */
fec_tbd_init(struct fec_priv * fec)328 static void fec_tbd_init(struct fec_priv *fec)
329 {
330 unsigned addr = (unsigned)fec->tbd_base;
331 unsigned size = roundup(2 * sizeof(struct fec_bd),
332 ARCH_DMA_MINALIGN);
333
334 memset(fec->tbd_base, 0, size);
335 fec->tbd_base[0].status = 0;
336 fec->tbd_base[1].status = FEC_TBD_WRAP;
337 fec->tbd_index = 0;
338 flush_dcache_range(addr, addr + size);
339 }
340
341 /**
342 * Mark the given read buffer descriptor as free
343 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
344 * @param[in] prbd buffer descriptor to mark free again
345 */
fec_rbd_clean(int last,struct fec_bd * prbd)346 static void fec_rbd_clean(int last, struct fec_bd *prbd)
347 {
348 unsigned short flags = FEC_RBD_EMPTY;
349 if (last)
350 flags |= FEC_RBD_WRAP;
351 writew(flags, &prbd->status);
352 writew(0, &prbd->data_length);
353 }
354
fec_get_hwaddr(int dev_id,unsigned char * mac)355 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
356 {
357 imx_get_mac_from_fuse(dev_id, mac);
358 return !is_valid_ethaddr(mac);
359 }
360
361 #ifdef CONFIG_DM_ETH
fecmxc_set_hwaddr(struct udevice * dev)362 static int fecmxc_set_hwaddr(struct udevice *dev)
363 #else
364 static int fec_set_hwaddr(struct eth_device *dev)
365 #endif
366 {
367 #ifdef CONFIG_DM_ETH
368 struct fec_priv *fec = dev_get_priv(dev);
369 struct eth_pdata *pdata = dev_get_platdata(dev);
370 uchar *mac = pdata->enetaddr;
371 #else
372 uchar *mac = dev->enetaddr;
373 struct fec_priv *fec = (struct fec_priv *)dev->priv;
374 #endif
375
376 writel(0, &fec->eth->iaddr1);
377 writel(0, &fec->eth->iaddr2);
378 writel(0, &fec->eth->gaddr1);
379 writel(0, &fec->eth->gaddr2);
380
381 /* Set physical address */
382 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
383 &fec->eth->paddr1);
384 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
385
386 return 0;
387 }
388
389 /* Do initial configuration of the FEC registers */
fec_reg_setup(struct fec_priv * fec)390 static void fec_reg_setup(struct fec_priv *fec)
391 {
392 uint32_t rcntrl;
393
394 /* Set interrupt mask register */
395 writel(0x00000000, &fec->eth->imask);
396
397 /* Clear FEC-Lite interrupt event register(IEVENT) */
398 writel(0xffffffff, &fec->eth->ievent);
399
400 /* Set FEC-Lite receive control register(R_CNTRL): */
401
402 /* Start with frame length = 1518, common for all modes. */
403 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
404 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
405 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
406 if (fec->xcv_type == RGMII)
407 rcntrl |= FEC_RCNTRL_RGMII;
408 else if (fec->xcv_type == RMII)
409 rcntrl |= FEC_RCNTRL_RMII;
410
411 writel(rcntrl, &fec->eth->r_cntrl);
412 }
413
414 /**
415 * Start the FEC engine
416 * @param[in] dev Our device to handle
417 */
418 #ifdef CONFIG_DM_ETH
fec_open(struct udevice * dev)419 static int fec_open(struct udevice *dev)
420 #else
421 static int fec_open(struct eth_device *edev)
422 #endif
423 {
424 #ifdef CONFIG_DM_ETH
425 struct fec_priv *fec = dev_get_priv(dev);
426 #else
427 struct fec_priv *fec = (struct fec_priv *)edev->priv;
428 #endif
429 int speed;
430 uint32_t addr, size;
431 int i;
432
433 debug("fec_open: fec_open(dev)\n");
434 /* full-duplex, heartbeat disabled */
435 writel(1 << 2, &fec->eth->x_cntrl);
436 fec->rbd_index = 0;
437
438 /* Invalidate all descriptors */
439 for (i = 0; i < FEC_RBD_NUM - 1; i++)
440 fec_rbd_clean(0, &fec->rbd_base[i]);
441 fec_rbd_clean(1, &fec->rbd_base[i]);
442
443 /* Flush the descriptors into RAM */
444 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
445 ARCH_DMA_MINALIGN);
446 addr = (uint32_t)fec->rbd_base;
447 flush_dcache_range(addr, addr + size);
448
449 #ifdef FEC_QUIRK_ENET_MAC
450 /* Enable ENET HW endian SWAP */
451 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
452 &fec->eth->ecntrl);
453 /* Enable ENET store and forward mode */
454 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
455 &fec->eth->x_wmrk);
456 #endif
457 /* Enable FEC-Lite controller */
458 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
459 &fec->eth->ecntrl);
460
461 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
462 udelay(100);
463
464 /* setup the MII gasket for RMII mode */
465 /* disable the gasket */
466 writew(0, &fec->eth->miigsk_enr);
467
468 /* wait for the gasket to be disabled */
469 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
470 udelay(2);
471
472 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
473 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
474
475 /* re-enable the gasket */
476 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
477
478 /* wait until MII gasket is ready */
479 int max_loops = 10;
480 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
481 if (--max_loops <= 0) {
482 printf("WAIT for MII Gasket ready timed out\n");
483 break;
484 }
485 }
486 #endif
487
488 #ifdef CONFIG_PHYLIB
489 {
490 /* Start up the PHY */
491 int ret = phy_startup(fec->phydev);
492
493 if (ret) {
494 printf("Could not initialize PHY %s\n",
495 fec->phydev->dev->name);
496 return ret;
497 }
498 speed = fec->phydev->speed;
499 }
500 #elif CONFIG_FEC_FIXED_SPEED
501 speed = CONFIG_FEC_FIXED_SPEED;
502 #else
503 miiphy_wait_aneg(edev);
504 speed = miiphy_speed(edev->name, fec->phy_id);
505 miiphy_duplex(edev->name, fec->phy_id);
506 #endif
507
508 #ifdef FEC_QUIRK_ENET_MAC
509 {
510 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
511 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
512 if (speed == _1000BASET)
513 ecr |= FEC_ECNTRL_SPEED;
514 else if (speed != _100BASET)
515 rcr |= FEC_RCNTRL_RMII_10T;
516 writel(ecr, &fec->eth->ecntrl);
517 writel(rcr, &fec->eth->r_cntrl);
518 }
519 #endif
520 debug("%s:Speed=%i\n", __func__, speed);
521
522 /* Enable SmartDMA receive task */
523 fec_rx_task_enable(fec);
524
525 udelay(100000);
526 return 0;
527 }
528
529 #ifdef CONFIG_DM_ETH
fecmxc_init(struct udevice * dev)530 static int fecmxc_init(struct udevice *dev)
531 #else
532 static int fec_init(struct eth_device *dev, bd_t *bd)
533 #endif
534 {
535 #ifdef CONFIG_DM_ETH
536 struct fec_priv *fec = dev_get_priv(dev);
537 #else
538 struct fec_priv *fec = (struct fec_priv *)dev->priv;
539 #endif
540 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
541 int i;
542
543 /* Initialize MAC address */
544 #ifdef CONFIG_DM_ETH
545 fecmxc_set_hwaddr(dev);
546 #else
547 fec_set_hwaddr(dev);
548 #endif
549
550 /* Setup transmit descriptors, there are two in total. */
551 fec_tbd_init(fec);
552
553 /* Setup receive descriptors. */
554 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
555
556 fec_reg_setup(fec);
557
558 if (fec->xcv_type != SEVENWIRE)
559 fec_mii_setspeed(fec->bus->priv);
560
561 /* Set Opcode/Pause Duration Register */
562 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
563 writel(0x2, &fec->eth->x_wmrk);
564
565 /* Set multicast address filter */
566 writel(0x00000000, &fec->eth->gaddr1);
567 writel(0x00000000, &fec->eth->gaddr2);
568
569 /* Do not access reserved register for i.MX6UL */
570 if (!is_mx6ul() && !is_mx6ull()) {
571 /* clear MIB RAM */
572 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
573 writel(0, i);
574
575 /* FIFO receive start register */
576 writel(0x520, &fec->eth->r_fstart);
577 }
578
579 /* size and address of each buffer */
580 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
581 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
582 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
583
584 #ifndef CONFIG_PHYLIB
585 if (fec->xcv_type != SEVENWIRE)
586 miiphy_restart_aneg(dev);
587 #endif
588 fec_open(dev);
589 return 0;
590 }
591
592 /**
593 * Halt the FEC engine
594 * @param[in] dev Our device to handle
595 */
596 #ifdef CONFIG_DM_ETH
fecmxc_halt(struct udevice * dev)597 static void fecmxc_halt(struct udevice *dev)
598 #else
599 static void fec_halt(struct eth_device *dev)
600 #endif
601 {
602 #ifdef CONFIG_DM_ETH
603 struct fec_priv *fec = dev_get_priv(dev);
604 #else
605 struct fec_priv *fec = (struct fec_priv *)dev->priv;
606 #endif
607 int counter = 0xffff;
608
609 /* issue graceful stop command to the FEC transmitter if necessary */
610 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
611 &fec->eth->x_cntrl);
612
613 debug("eth_halt: wait for stop regs\n");
614 /* wait for graceful stop to register */
615 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
616 udelay(1);
617
618 /* Disable SmartDMA tasks */
619 fec_tx_task_disable(fec);
620 fec_rx_task_disable(fec);
621
622 /*
623 * Disable the Ethernet Controller
624 * Note: this will also reset the BD index counter!
625 */
626 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
627 &fec->eth->ecntrl);
628 fec->rbd_index = 0;
629 fec->tbd_index = 0;
630 debug("eth_halt: done\n");
631 }
632
633 /**
634 * Transmit one frame
635 * @param[in] dev Our ethernet device to handle
636 * @param[in] packet Pointer to the data to be transmitted
637 * @param[in] length Data count in bytes
638 * @return 0 on success
639 */
640 #ifdef CONFIG_DM_ETH
fecmxc_send(struct udevice * dev,void * packet,int length)641 static int fecmxc_send(struct udevice *dev, void *packet, int length)
642 #else
643 static int fec_send(struct eth_device *dev, void *packet, int length)
644 #endif
645 {
646 unsigned int status;
647 uint32_t size, end;
648 uint32_t addr;
649 int timeout = FEC_XFER_TIMEOUT;
650 int ret = 0;
651
652 /*
653 * This routine transmits one frame. This routine only accepts
654 * 6-byte Ethernet addresses.
655 */
656 #ifdef CONFIG_DM_ETH
657 struct fec_priv *fec = dev_get_priv(dev);
658 #else
659 struct fec_priv *fec = (struct fec_priv *)dev->priv;
660 #endif
661
662 /*
663 * Check for valid length of data.
664 */
665 if ((length > 1500) || (length <= 0)) {
666 printf("Payload (%d) too large\n", length);
667 return -1;
668 }
669
670 /*
671 * Setup the transmit buffer. We are always using the first buffer for
672 * transmission, the second will be empty and only used to stop the DMA
673 * engine. We also flush the packet to RAM here to avoid cache trouble.
674 */
675 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
676 swap_packet((uint32_t *)packet, length);
677 #endif
678
679 addr = (uint32_t)packet;
680 end = roundup(addr + length, ARCH_DMA_MINALIGN);
681 addr &= ~(ARCH_DMA_MINALIGN - 1);
682 flush_dcache_range(addr, end);
683
684 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
685 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
686
687 /*
688 * update BD's status now
689 * This block:
690 * - is always the last in a chain (means no chain)
691 * - should transmitt the CRC
692 * - might be the last BD in the list, so the address counter should
693 * wrap (-> keep the WRAP flag)
694 */
695 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
696 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
697 writew(status, &fec->tbd_base[fec->tbd_index].status);
698
699 /*
700 * Flush data cache. This code flushes both TX descriptors to RAM.
701 * After this code, the descriptors will be safely in RAM and we
702 * can start DMA.
703 */
704 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
705 addr = (uint32_t)fec->tbd_base;
706 flush_dcache_range(addr, addr + size);
707
708 /*
709 * Below we read the DMA descriptor's last four bytes back from the
710 * DRAM. This is important in order to make sure that all WRITE
711 * operations on the bus that were triggered by previous cache FLUSH
712 * have completed.
713 *
714 * Otherwise, on MX28, it is possible to observe a corruption of the
715 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
716 * for the bus structure of MX28. The scenario is as follows:
717 *
718 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
719 * to DRAM due to flush_dcache_range()
720 * 2) ARM core writes the FEC registers via AHB_ARB2
721 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
722 *
723 * Note that 2) does sometimes finish before 1) due to reordering of
724 * WRITE accesses on the AHB bus, therefore triggering 3) before the
725 * DMA descriptor is fully written into DRAM. This results in occasional
726 * corruption of the DMA descriptor.
727 */
728 readl(addr + size - 4);
729
730 /* Enable SmartDMA transmit task */
731 fec_tx_task_enable(fec);
732
733 /*
734 * Wait until frame is sent. On each turn of the wait cycle, we must
735 * invalidate data cache to see what's really in RAM. Also, we need
736 * barrier here.
737 */
738 while (--timeout) {
739 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
740 break;
741 }
742
743 if (!timeout) {
744 ret = -EINVAL;
745 goto out;
746 }
747
748 /*
749 * The TDAR bit is cleared when the descriptors are all out from TX
750 * but on mx6solox we noticed that the READY bit is still not cleared
751 * right after TDAR.
752 * These are two distinct signals, and in IC simulation, we found that
753 * TDAR always gets cleared prior than the READY bit of last BD becomes
754 * cleared.
755 * In mx6solox, we use a later version of FEC IP. It looks like that
756 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
757 * version.
758 *
759 * Fix this by polling the READY bit of BD after the TDAR polling,
760 * which covers the mx6solox case and does not harm the other SoCs.
761 */
762 timeout = FEC_XFER_TIMEOUT;
763 while (--timeout) {
764 invalidate_dcache_range(addr, addr + size);
765 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
766 FEC_TBD_READY))
767 break;
768 }
769
770 if (!timeout)
771 ret = -EINVAL;
772
773 out:
774 debug("fec_send: status 0x%x index %d ret %i\n",
775 readw(&fec->tbd_base[fec->tbd_index].status),
776 fec->tbd_index, ret);
777 /* for next transmission use the other buffer */
778 if (fec->tbd_index)
779 fec->tbd_index = 0;
780 else
781 fec->tbd_index = 1;
782
783 return ret;
784 }
785
786 /**
787 * Pull one frame from the card
788 * @param[in] dev Our ethernet device to handle
789 * @return Length of packet read
790 */
791 #ifdef CONFIG_DM_ETH
fecmxc_recv(struct udevice * dev,int flags,uchar ** packetp)792 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
793 #else
794 static int fec_recv(struct eth_device *dev)
795 #endif
796 {
797 #ifdef CONFIG_DM_ETH
798 struct fec_priv *fec = dev_get_priv(dev);
799 #else
800 struct fec_priv *fec = (struct fec_priv *)dev->priv;
801 #endif
802 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
803 unsigned long ievent;
804 int frame_length, len = 0;
805 uint16_t bd_status;
806 uint32_t addr, size, end;
807 int i;
808 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
809
810 /* Check if any critical events have happened */
811 ievent = readl(&fec->eth->ievent);
812 writel(ievent, &fec->eth->ievent);
813 debug("fec_recv: ievent 0x%lx\n", ievent);
814 if (ievent & FEC_IEVENT_BABR) {
815 #ifdef CONFIG_DM_ETH
816 fecmxc_halt(dev);
817 fecmxc_init(dev);
818 #else
819 fec_halt(dev);
820 fec_init(dev, fec->bd);
821 #endif
822 printf("some error: 0x%08lx\n", ievent);
823 return 0;
824 }
825 if (ievent & FEC_IEVENT_HBERR) {
826 /* Heartbeat error */
827 writel(0x00000001 | readl(&fec->eth->x_cntrl),
828 &fec->eth->x_cntrl);
829 }
830 if (ievent & FEC_IEVENT_GRA) {
831 /* Graceful stop complete */
832 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
833 #ifdef CONFIG_DM_ETH
834 fecmxc_halt(dev);
835 #else
836 fec_halt(dev);
837 #endif
838 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
839 &fec->eth->x_cntrl);
840 #ifdef CONFIG_DM_ETH
841 fecmxc_init(dev);
842 #else
843 fec_init(dev, fec->bd);
844 #endif
845 }
846 }
847
848 /*
849 * Read the buffer status. Before the status can be read, the data cache
850 * must be invalidated, because the data in RAM might have been changed
851 * by DMA. The descriptors are properly aligned to cachelines so there's
852 * no need to worry they'd overlap.
853 *
854 * WARNING: By invalidating the descriptor here, we also invalidate
855 * the descriptors surrounding this one. Therefore we can NOT change the
856 * contents of this descriptor nor the surrounding ones. The problem is
857 * that in order to mark the descriptor as processed, we need to change
858 * the descriptor. The solution is to mark the whole cache line when all
859 * descriptors in the cache line are processed.
860 */
861 addr = (uint32_t)rbd;
862 addr &= ~(ARCH_DMA_MINALIGN - 1);
863 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
864 invalidate_dcache_range(addr, addr + size);
865
866 bd_status = readw(&rbd->status);
867 debug("fec_recv: status 0x%x\n", bd_status);
868
869 if (!(bd_status & FEC_RBD_EMPTY)) {
870 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
871 ((readw(&rbd->data_length) - 4) > 14)) {
872 /* Get buffer address and size */
873 addr = readl(&rbd->data_pointer);
874 frame_length = readw(&rbd->data_length) - 4;
875 /* Invalidate data cache over the buffer */
876 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
877 addr &= ~(ARCH_DMA_MINALIGN - 1);
878 invalidate_dcache_range(addr, end);
879
880 /* Fill the buffer and pass it to upper layers */
881 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
882 swap_packet((uint32_t *)addr, frame_length);
883 #endif
884 memcpy(buff, (char *)addr, frame_length);
885 net_process_received_packet(buff, frame_length);
886 len = frame_length;
887 } else {
888 if (bd_status & FEC_RBD_ERR)
889 printf("error frame: 0x%08x 0x%08x\n",
890 addr, bd_status);
891 }
892
893 /*
894 * Free the current buffer, restart the engine and move forward
895 * to the next buffer. Here we check if the whole cacheline of
896 * descriptors was already processed and if so, we mark it free
897 * as whole.
898 */
899 size = RXDESC_PER_CACHELINE - 1;
900 if ((fec->rbd_index & size) == size) {
901 i = fec->rbd_index - size;
902 addr = (uint32_t)&fec->rbd_base[i];
903 for (; i <= fec->rbd_index ; i++) {
904 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
905 &fec->rbd_base[i]);
906 }
907 flush_dcache_range(addr,
908 addr + ARCH_DMA_MINALIGN);
909 }
910
911 fec_rx_task_enable(fec);
912 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
913 }
914 debug("fec_recv: stop\n");
915
916 return len;
917 }
918
fec_set_dev_name(char * dest,int dev_id)919 static void fec_set_dev_name(char *dest, int dev_id)
920 {
921 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
922 }
923
fec_alloc_descs(struct fec_priv * fec)924 static int fec_alloc_descs(struct fec_priv *fec)
925 {
926 unsigned int size;
927 int i;
928 uint8_t *data;
929
930 /* Allocate TX descriptors. */
931 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
932 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
933 if (!fec->tbd_base)
934 goto err_tx;
935
936 /* Allocate RX descriptors. */
937 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
938 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
939 if (!fec->rbd_base)
940 goto err_rx;
941
942 memset(fec->rbd_base, 0, size);
943
944 /* Allocate RX buffers. */
945
946 /* Maximum RX buffer size. */
947 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
948 for (i = 0; i < FEC_RBD_NUM; i++) {
949 data = memalign(FEC_DMA_RX_MINALIGN, size);
950 if (!data) {
951 printf("%s: error allocating rxbuf %d\n", __func__, i);
952 goto err_ring;
953 }
954
955 memset(data, 0, size);
956
957 fec->rbd_base[i].data_pointer = (uint32_t)data;
958 fec->rbd_base[i].status = FEC_RBD_EMPTY;
959 fec->rbd_base[i].data_length = 0;
960 /* Flush the buffer to memory. */
961 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
962 }
963
964 /* Mark the last RBD to close the ring. */
965 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
966
967 fec->rbd_index = 0;
968 fec->tbd_index = 0;
969
970 return 0;
971
972 err_ring:
973 for (; i >= 0; i--)
974 free((void *)fec->rbd_base[i].data_pointer);
975 free(fec->rbd_base);
976 err_rx:
977 free(fec->tbd_base);
978 err_tx:
979 return -ENOMEM;
980 }
981
fec_free_descs(struct fec_priv * fec)982 static void fec_free_descs(struct fec_priv *fec)
983 {
984 int i;
985
986 for (i = 0; i < FEC_RBD_NUM; i++)
987 free((void *)fec->rbd_base[i].data_pointer);
988 free(fec->rbd_base);
989 free(fec->tbd_base);
990 }
991
992 #ifdef CONFIG_DM_ETH
fec_get_miibus(struct udevice * dev,int dev_id)993 struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id)
994 #else
995 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
996 #endif
997 {
998 #ifdef CONFIG_DM_ETH
999 struct fec_priv *priv = dev_get_priv(dev);
1000 struct ethernet_regs *eth = priv->eth;
1001 #else
1002 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1003 #endif
1004 struct mii_dev *bus;
1005 int ret;
1006
1007 bus = mdio_alloc();
1008 if (!bus) {
1009 printf("mdio_alloc failed\n");
1010 return NULL;
1011 }
1012 bus->read = fec_phy_read;
1013 bus->write = fec_phy_write;
1014 bus->priv = eth;
1015 fec_set_dev_name(bus->name, dev_id);
1016
1017 ret = mdio_register(bus);
1018 if (ret) {
1019 printf("mdio_register failed\n");
1020 free(bus);
1021 return NULL;
1022 }
1023 fec_mii_setspeed(eth);
1024 return bus;
1025 }
1026
1027 #ifndef CONFIG_DM_ETH
1028 #ifdef CONFIG_PHYLIB
fec_probe(bd_t * bd,int dev_id,uint32_t base_addr,struct mii_dev * bus,struct phy_device * phydev)1029 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1030 struct mii_dev *bus, struct phy_device *phydev)
1031 #else
1032 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1033 struct mii_dev *bus, int phy_id)
1034 #endif
1035 {
1036 struct eth_device *edev;
1037 struct fec_priv *fec;
1038 unsigned char ethaddr[6];
1039 char mac[16];
1040 uint32_t start;
1041 int ret = 0;
1042
1043 /* create and fill edev struct */
1044 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1045 if (!edev) {
1046 puts("fec_mxc: not enough malloc memory for eth_device\n");
1047 ret = -ENOMEM;
1048 goto err1;
1049 }
1050
1051 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1052 if (!fec) {
1053 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1054 ret = -ENOMEM;
1055 goto err2;
1056 }
1057
1058 memset(edev, 0, sizeof(*edev));
1059 memset(fec, 0, sizeof(*fec));
1060
1061 ret = fec_alloc_descs(fec);
1062 if (ret)
1063 goto err3;
1064
1065 edev->priv = fec;
1066 edev->init = fec_init;
1067 edev->send = fec_send;
1068 edev->recv = fec_recv;
1069 edev->halt = fec_halt;
1070 edev->write_hwaddr = fec_set_hwaddr;
1071
1072 fec->eth = (struct ethernet_regs *)base_addr;
1073 fec->bd = bd;
1074
1075 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1076
1077 /* Reset chip. */
1078 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1079 start = get_timer(0);
1080 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1081 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1082 printf("FEC MXC: Timeout resetting chip\n");
1083 goto err4;
1084 }
1085 udelay(10);
1086 }
1087
1088 fec_reg_setup(fec);
1089 fec_set_dev_name(edev->name, dev_id);
1090 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1091 fec->bus = bus;
1092 fec_mii_setspeed(bus->priv);
1093 #ifdef CONFIG_PHYLIB
1094 fec->phydev = phydev;
1095 phy_connect_dev(phydev, edev);
1096 /* Configure phy */
1097 phy_config(phydev);
1098 #else
1099 fec->phy_id = phy_id;
1100 #endif
1101 eth_register(edev);
1102 /* only support one eth device, the index number pointed by dev_id */
1103 edev->index = fec->dev_id;
1104
1105 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1106 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1107 memcpy(edev->enetaddr, ethaddr, 6);
1108 if (fec->dev_id)
1109 sprintf(mac, "eth%daddr", fec->dev_id);
1110 else
1111 strcpy(mac, "ethaddr");
1112 if (!env_get(mac))
1113 eth_env_set_enetaddr(mac, ethaddr);
1114 }
1115 return ret;
1116 err4:
1117 fec_free_descs(fec);
1118 err3:
1119 free(fec);
1120 err2:
1121 free(edev);
1122 err1:
1123 return ret;
1124 }
1125
fecmxc_initialize_multi(bd_t * bd,int dev_id,int phy_id,uint32_t addr)1126 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1127 {
1128 uint32_t base_mii;
1129 struct mii_dev *bus = NULL;
1130 #ifdef CONFIG_PHYLIB
1131 struct phy_device *phydev = NULL;
1132 #endif
1133 int ret;
1134
1135 #ifdef CONFIG_MX28
1136 /*
1137 * The i.MX28 has two ethernet interfaces, but they are not equal.
1138 * Only the first one can access the MDIO bus.
1139 */
1140 base_mii = MXS_ENET0_BASE;
1141 #else
1142 base_mii = addr;
1143 #endif
1144 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1145 bus = fec_get_miibus(base_mii, dev_id);
1146 if (!bus)
1147 return -ENOMEM;
1148 #ifdef CONFIG_PHYLIB
1149 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1150 if (!phydev) {
1151 mdio_unregister(bus);
1152 free(bus);
1153 return -ENOMEM;
1154 }
1155 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1156 #else
1157 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1158 #endif
1159 if (ret) {
1160 #ifdef CONFIG_PHYLIB
1161 free(phydev);
1162 #endif
1163 mdio_unregister(bus);
1164 free(bus);
1165 }
1166 return ret;
1167 }
1168
1169 #ifdef CONFIG_FEC_MXC_PHYADDR
fecmxc_initialize(bd_t * bd)1170 int fecmxc_initialize(bd_t *bd)
1171 {
1172 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1173 IMX_FEC_BASE);
1174 }
1175 #endif
1176
1177 #ifndef CONFIG_PHYLIB
fecmxc_register_mii_postcall(struct eth_device * dev,int (* cb)(int))1178 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1179 {
1180 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1181 fec->mii_postcall = cb;
1182 return 0;
1183 }
1184 #endif
1185
1186 #else
1187
fecmxc_read_rom_hwaddr(struct udevice * dev)1188 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1189 {
1190 struct fec_priv *priv = dev_get_priv(dev);
1191 struct eth_pdata *pdata = dev_get_platdata(dev);
1192
1193 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1194 }
1195
1196 static const struct eth_ops fecmxc_ops = {
1197 .start = fecmxc_init,
1198 .send = fecmxc_send,
1199 .recv = fecmxc_recv,
1200 .stop = fecmxc_halt,
1201 .write_hwaddr = fecmxc_set_hwaddr,
1202 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1203 };
1204
fec_phy_init(struct fec_priv * priv,struct udevice * dev)1205 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1206 {
1207 struct phy_device *phydev;
1208 int mask = 0xffffffff;
1209
1210 #ifdef CONFIG_PHYLIB
1211 mask = 1 << CONFIG_FEC_MXC_PHYADDR;
1212 #endif
1213
1214 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
1215 if (!phydev)
1216 return -ENODEV;
1217
1218 phy_connect_dev(phydev, dev);
1219
1220 priv->phydev = phydev;
1221 phy_config(phydev);
1222
1223 return 0;
1224 }
1225
fecmxc_probe(struct udevice * dev)1226 static int fecmxc_probe(struct udevice *dev)
1227 {
1228 struct eth_pdata *pdata = dev_get_platdata(dev);
1229 struct fec_priv *priv = dev_get_priv(dev);
1230 struct mii_dev *bus = NULL;
1231 int dev_id = -1;
1232 uint32_t start;
1233 int ret;
1234
1235 ret = fec_alloc_descs(priv);
1236 if (ret)
1237 return ret;
1238
1239 /* Reset chip. */
1240 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1241 &priv->eth->ecntrl);
1242 start = get_timer(0);
1243 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1244 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1245 printf("FEC MXC: Timeout reseting chip\n");
1246 goto err_timeout;
1247 }
1248 udelay(10);
1249 }
1250
1251 fec_reg_setup(priv);
1252
1253 priv->dev_id = dev->seq;
1254
1255 #ifdef CONFIG_DM_ETH_PHY
1256 bus = eth_phy_get_mdio_bus(dev);
1257 #endif
1258
1259 if (!bus) {
1260 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1261 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1262 #else
1263 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
1264 #endif
1265 }
1266 if (!bus) {
1267 ret = -ENOMEM;
1268 goto err_mii;
1269 }
1270
1271 #ifdef CONFIG_DM_ETH_PHY
1272 eth_phy_set_mdio_bus(dev, bus);
1273 #endif
1274
1275 priv->bus = bus;
1276 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1277 priv->interface = pdata->phy_interface;
1278 ret = fec_phy_init(priv, dev);
1279 if (ret)
1280 goto err_phy;
1281
1282 return 0;
1283
1284 err_timeout:
1285 free(priv->phydev);
1286 err_phy:
1287 mdio_unregister(bus);
1288 free(bus);
1289 err_mii:
1290 fec_free_descs(priv);
1291 return ret;
1292 }
1293
fecmxc_remove(struct udevice * dev)1294 static int fecmxc_remove(struct udevice *dev)
1295 {
1296 struct fec_priv *priv = dev_get_priv(dev);
1297
1298 free(priv->phydev);
1299 fec_free_descs(priv);
1300 mdio_unregister(priv->bus);
1301 mdio_free(priv->bus);
1302
1303 return 0;
1304 }
1305
fecmxc_ofdata_to_platdata(struct udevice * dev)1306 static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1307 {
1308 struct eth_pdata *pdata = dev_get_platdata(dev);
1309 struct fec_priv *priv = dev_get_priv(dev);
1310 const char *phy_mode;
1311
1312 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1313 priv->eth = (struct ethernet_regs *)pdata->iobase;
1314
1315 pdata->phy_interface = -1;
1316 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1317 NULL);
1318 if (phy_mode)
1319 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1320 if (pdata->phy_interface == -1) {
1321 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1322 return -EINVAL;
1323 }
1324
1325 /* TODO
1326 * Need to get the reset-gpio and related properties from DT
1327 * and implemet the enet reset code on .probe call
1328 */
1329
1330 return 0;
1331 }
1332
1333 static const struct udevice_id fecmxc_ids[] = {
1334 { .compatible = "fsl,imx6q-fec" },
1335 { }
1336 };
1337
1338 U_BOOT_DRIVER(fecmxc_gem) = {
1339 .name = "fecmxc",
1340 .id = UCLASS_ETH,
1341 .of_match = fecmxc_ids,
1342 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1343 .probe = fecmxc_probe,
1344 .remove = fecmxc_remove,
1345 .ops = &fecmxc_ops,
1346 .priv_auto_alloc_size = sizeof(struct fec_priv),
1347 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1348 };
1349 #endif
1350