1 /*
2 * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <errno.h>
8 #include <stdint.h>
9 #include <stdio.h>
10 #include <common/debug.h>
11 #include <drivers/delay_timer.h>
12 #include <lib/mmio.h>
13 #include <lib/mmio_poll.h>
14 #include <lib/utils_def.h>
15
16 #include <lib/mtk_init/mtk_init.h>
17 #include <lpm/mt_lp_api.h>
18 #include <mt_spm_reg.h>
19 #include <mtk_mmap_pool.h>
20 #include <soc_temp_lvts.h>
21 #include <soc_temp_lvts_interface.h>
22 #include <thermal_lvts.h>
23
24 enum mt8189_lvts_domain {
25 MT8189_AP_DOMAIN,
26 MT8189_MCU_DOMAIN,
27 MT8189_NUM_DOMAIN
28 };
29
30 enum mt8189_lvts_controller_enum {
31 MT8189_LVTS_MCU_CTRL0,
32 MT8189_LVTS_MCU_CTRL1,
33 MT8189_LVTS_MCU_CTRL2,
34 MT8189_LVTS_AP_CTRL0,
35 MT8189_LVTS_GPU_CTRL0,
36 MT8189_LVTS_CTRL_NUM
37 };
38
39 #define THERMAL_CSRAM_BASE_MAP_ADDR (THERMAL_CSRAM_BASE & ~(PAGE_SIZE - 1))
40 static const mmap_region_t thermal_mmap[] MTK_MMAP_SECTION = {
41 MAP_REGION_FLAT(THERM_CTRL_AP_BASE, THERM_AP_REG_SIZE,
42 MT_DEVICE | MT_RW | MT_SECURE),
43 MAP_REGION_FLAT(THERM_CTRL_MCU_BASE, THERM_MCU_REG_SIZE,
44 MT_DEVICE | MT_RW | MT_SECURE),
45 MAP_REGION_FLAT(THERMAL_CSRAM_BASE_MAP_ADDR, PAGE_SIZE,
46 MT_DEVICE | MT_RW | MT_SECURE),
47 MAP_REGION_FLAT(INFRACFG_BASE, PAGE_SIZE,
48 MT_DEVICE | MT_RW | MT_SECURE),
49 {0}
50 };
51 DECLARE_MTK_MMAP_REGIONS(thermal_mmap);
52
disable_hw_reboot_interrupt(struct lvts_data * lvts_data,unsigned int tc_id)53 void disable_hw_reboot_interrupt(struct lvts_data *lvts_data,
54 unsigned int tc_id)
55 {
56 uint32_t temp;
57 uintptr_t base;
58
59 base = GET_BASE_ADDR(lvts_data, tc_id);
60
61 /* LVTS thermal controller has two interrupts for thermal HW reboot
62 * One is for AP SW and the other is for RGU
63 * The interrupt of AP SW can turn off by a bit of a register, but
64 * the other for RGU cannot.
65 * To prevent rebooting device accidentally, we are going to add
66 * a huge offset to LVTS and make LVTS always report extremely low
67 * temperature.
68 */
69
70 /* After adding the huge offset 0x3FFF, LVTS alawys adds the
71 * offset to MSR_RAW.
72 * When MSR_RAW is larger, SW will convert lower temperature/
73 */
74 mmio_setbits_32(LVTSPROTCTL_0 + base, 0x3FFF);
75
76 /* Disable the interrupt of AP SW */
77 temp = mmio_read_32(LVTSMONINT_0 + base);
78
79 temp = temp & ~(STAGE3_INT_EN);
80
81 if (lvts_data->enable_dump_log) {
82 temp = temp & ~(HIGH_OFFSET3_INT_EN |
83 HIGH_OFFSET2_INT_EN |
84 HIGH_OFFSET1_INT_EN |
85 HIGH_OFFSET0_INT_EN);
86
87 temp = temp & ~(LOW_OFFSET3_INT_EN |
88 LOW_OFFSET2_INT_EN |
89 LOW_OFFSET1_INT_EN |
90 LOW_OFFSET0_INT_EN);
91 }
92
93 mmio_write_32(LVTSMONINT_0 + base, temp);
94 dmbsy();
95 }
96
enable_hw_reboot_interrupt(struct lvts_data * lvts_data,unsigned int tc_id)97 void enable_hw_reboot_interrupt(struct lvts_data *lvts_data,
98 unsigned int tc_id)
99 {
100 uint32_t temp;
101 uintptr_t base;
102
103 base = GET_BASE_ADDR(lvts_data, tc_id);
104
105 /* Enable the interrupt of AP SW */
106 temp = mmio_read_32(LVTSMONINT_0 + base);
107
108 if (lvts_data->enable_dump_log) {
109 temp = temp | HIGH_OFFSET3_INT_EN |
110 HIGH_OFFSET2_INT_EN |
111 HIGH_OFFSET1_INT_EN |
112 HIGH_OFFSET0_INT_EN;
113
114 temp = temp | LOW_OFFSET3_INT_EN |
115 LOW_OFFSET2_INT_EN |
116 LOW_OFFSET1_INT_EN |
117 LOW_OFFSET0_INT_EN;
118 } else {
119 temp = temp | STAGE3_INT_EN;
120 }
121
122 mmio_write_32(LVTSMONINT_0 + base, temp);
123
124 /* Clear the offset */
125 mmio_clrbits_32(LVTSPROTCTL_0 + base, PROTOFFSET);
126
127 dmbsy();
128 }
129
set_tc_hw_reboot_threshold(struct lvts_data * lvts_data,int trip_point,unsigned int tc_id)130 void set_tc_hw_reboot_threshold(struct lvts_data *lvts_data, int trip_point,
131 unsigned int tc_id)
132 {
133 struct tc_settings *tc = lvts_data->tc;
134 unsigned int msr_raw, cur_msr_raw, d_index, i;
135 uint32_t temp, config;
136 uintptr_t base;
137 struct platform_ops *ops = &lvts_data->ops;
138
139 msr_raw = 0;
140 base = GET_BASE_ADDR(lvts_data, tc_id);
141 d_index = get_dominator_index(lvts_data, tc_id);
142
143 disable_hw_reboot_interrupt(lvts_data, tc_id);
144
145 if (tc_id < MT8189_LVTS_CTRL_NUM) {
146 temp = mmio_read_32(LVTSPROTCTL_0 + base);
147 if (d_index == ALL_SENSING_POINTS) {
148 /* Maximum of 4 sensing points */
149 config = (0x1 << 16);
150 mmio_write_32(LVTSPROTCTL_0 + base, config | temp);
151 msr_raw = 0;
152 for (i = 0; i < tc[tc_id].num_sensor; i++) {
153 cur_msr_raw = ops->lvts_temp_to_raw(
154 &(tc[tc_id].coeff), i, trip_point);
155 if (msr_raw < cur_msr_raw)
156 msr_raw = cur_msr_raw;
157 }
158 } else {
159 /* Select protection sensor */
160 config = ((d_index << 2) + 0x2) << 16;
161 mmio_write_32(LVTSPROTCTL_0 + base, config | temp);
162 msr_raw = ops->lvts_temp_to_raw(
163 &(tc[tc_id].coeff), d_index, trip_point);
164 }
165 } else {
166 INFO("Error: tc_id %d over %d\n", tc_id, MT8189_LVTS_CTRL_NUM);
167 }
168
169 if (lvts_data->enable_dump_log) {
170 /* high offset INT */
171 mmio_write_32(LVTSOFFSETH_0 + base, msr_raw);
172
173 /*
174 * lowoffset INT
175 * set a big msr_raw = 0xffff(very low temperature)
176 * to let lowoffset INT not be triggered
177 */
178 mmio_write_32(LVTSOFFSETL_0 + base, 0xffff);
179 } else {
180 mmio_write_32(LVTSPROTTC_0 + base, msr_raw);
181 }
182
183 dmbsy();
184
185 enable_hw_reboot_interrupt(lvts_data, tc_id);
186 }
187
188 #define LVTS_COEFF_A_X_1000 (-250460)
189 #define LVTS_COEFF_B_X_1000 (250460)
190
lvts_raw_to_temp_v1(const struct formula_coeff * co,uint32_t sensor_id,uint32_t msr_raw)191 static int lvts_raw_to_temp_v1(const struct formula_coeff *co,
192 uint32_t sensor_id, uint32_t msr_raw)
193 {
194 /* This function returns degree mC
195 * temp[i] = a * MSR_RAW/16384 + GOLDEN_TEMP/2 + b
196 * a = -250.46
197 * b = 250.46
198 */
199 (void)sensor_id;
200 int temp_mC = 0;
201 int temp1 = 0;
202 int golden_temp = co ? (int)co->golden_temp : DEFAULT_EFUSE_GOLDEN_TEMP;
203
204 temp1 = ((int)LVTS_COEFF_A_X_1000 * ((int)msr_raw)) >> 14;
205
206 temp_mC = temp1 + golden_temp * 500 + LVTS_COEFF_B_X_1000;
207
208 return temp_mC;
209 }
210
lvts_temp_to_raw_v1(const struct formula_coeff * co,uint32_t sensor_id,int temp)211 static uint32_t lvts_temp_to_raw_v1(const struct formula_coeff *co,
212 uint32_t sensor_id, int temp)
213 {
214 /* MSR_RAW = ((temp[i] - GOLDEN_TEMP/2 - b) * 16384) / a
215 * a = -250.46
216 * b = 250.46
217 */
218 (void)sensor_id;
219 uint32_t msr_raw = 0;
220 int golden_temp = co ? (int)co->golden_temp : DEFAULT_EFUSE_GOLDEN_TEMP;
221
222 msr_raw = (uint32_t)(
223 ((long long)(
224 (golden_temp * 500) + LVTS_COEFF_B_X_1000 - temp) << 14) /
225 (-1 * LVTS_COEFF_A_X_1000));
226 msr_raw = msr_raw & 0xFFFF;
227
228 return msr_raw;
229 }
230
mt8189_get_calibration_data(struct lvts_data * lvts_data)231 static void mt8189_get_calibration_data(struct lvts_data *lvts_data)
232 {
233 lvts_data->efuse[0] = mmio_read_32(EFUSEC_BASE + 0x01A4);
234 lvts_data->efuse[1] = mmio_read_32(EFUSEC_BASE + 0x01A8);
235 lvts_data->efuse[2] = mmio_read_32(EFUSEC_BASE + 0x01AC);
236 lvts_data->efuse[3] = mmio_read_32(EFUSEC_BASE + 0x01B0);
237 lvts_data->efuse[4] = mmio_read_32(EFUSEC_BASE + 0x01B4);
238 lvts_data->efuse[5] = mmio_read_32(EFUSEC_BASE + 0x01B8);
239 lvts_data->efuse[6] = mmio_read_32(EFUSEC_BASE + 0x01BC);
240 lvts_data->efuse[7] = mmio_read_32(EFUSEC_BASE + 0x01C0);
241 lvts_data->efuse[8] = mmio_read_32(EFUSEC_BASE + 0x01C4);
242 lvts_data->efuse[9] = mmio_read_32(EFUSEC_BASE + 0x01C8);
243 lvts_data->efuse[10] = mmio_read_32(EFUSEC_BASE + 0x01CC);
244 lvts_data->efuse[11] = mmio_read_32(EFUSEC_BASE + 0x01D0);
245 lvts_data->efuse[12] = mmio_read_32(EFUSEC_BASE + 0x01D4);
246 lvts_data->efuse[13] = mmio_read_32(EFUSEC_BASE + 0x01D8);
247 lvts_data->efuse[14] = mmio_read_32(EFUSEC_BASE + 0x01DC);
248
249 lvts_data->efuse[15] = mmio_read_32(EFUSEC_BASE + 0x01E0);
250 lvts_data->efuse[16] = mmio_read_32(EFUSEC_BASE + 0x01E4);
251 lvts_data->efuse[17] = mmio_read_32(EFUSEC_BASE + 0x01E8);
252 lvts_data->efuse[18] = mmio_read_32(EFUSEC_BASE + 0x01EC);
253 lvts_data->efuse[19] = mmio_read_32(EFUSEC_BASE + 0x01F0);
254 lvts_data->efuse[20] = mmio_read_32(EFUSEC_BASE + 0x01F4);
255 lvts_data->efuse[21] = mmio_read_32(EFUSEC_BASE + 0x01F8);
256 lvts_data->efuse[22] = mmio_read_32(EFUSEC_BASE + 0x01FC);
257 }
258
init_controller_v1(struct lvts_data * lvts_data)259 static void init_controller_v1(struct lvts_data *lvts_data)
260 {
261 unsigned int i;
262 uintptr_t base;
263 struct tc_settings *tc = lvts_data->tc;
264
265 assert(lvts_data->num_tc <= MT8189_LVTS_CTRL_NUM);
266 lvts_write_all_device(lvts_data, SET_DEVICE_LOW_POWER_SINGLE_MODE_V1);
267 for (i = 0; i < lvts_data->num_tc; i++) {
268 if (tc[i].ctrl_on_off == CTRL_OFF)
269 continue;
270
271 base = GET_BASE_ADDR(lvts_data, i);
272
273 mmio_write_32(LVTSTSSEL_0 + base, 0x13121110);
274 mmio_write_32(LVTSCALSCALE_0 + base, SET_CALC_SCALE_RULES);
275 dmbsy();
276
277 set_polling_speed(lvts_data, i);
278 set_hw_filter(lvts_data, i);
279 }
280 }
281
mt8189_device_enable_and_init(struct lvts_data * lvts_data)282 static void mt8189_device_enable_and_init(struct lvts_data *lvts_data)
283 {
284 unsigned int i;
285 struct tc_settings *tc = lvts_data->tc;
286
287 assert(lvts_data->num_tc <= MT8189_LVTS_CTRL_NUM);
288 for (i = 0; i < lvts_data->num_tc; i++) {
289 if (tc[i].ctrl_on_off == CTRL_OFF)
290 continue;
291
292 lvts_write_device(lvts_data, 0xC1030300, i);
293 lvts_write_device(lvts_data, 0xC10307A6, i);
294 lvts_write_device(lvts_data, 0xC1030500, i);
295 lvts_write_device(lvts_data, 0xC1030420, i);
296 lvts_write_device(lvts_data, 0xC1030A8C, i);
297 lvts_write_device(lvts_data, 0xC1030CFC, i);
298 lvts_write_device(lvts_data, 0xC103098D, i);
299 lvts_write_device(lvts_data, 0xC10308F1, i);
300 }
301 }
302
mt8189_device_read_count_rc_n(struct lvts_data * lvts_data)303 static int mt8189_device_read_count_rc_n(struct lvts_data *lvts_data)
304 {
305 /* Resistor-Capacitor Calibration */
306 /* count_RC_N: count RC now */
307 struct tc_settings *tc = lvts_data->tc;
308 struct sensor_cal_data *cal_data = &lvts_data->cal_data;
309 unsigned int i, j, s_index;
310 uintptr_t base;
311 int ret;
312 uint32_t temp, data, rc_data;
313 uint32_t refine_data_idx[4] = {0};
314 uint32_t count_rc_delta = 0;
315
316 lvts_write_all_device(lvts_data, SET_LVTS_MANUAL_RCK_V1);
317 if (lvts_data->init_done == true) {
318 lvts_write_all_device(lvts_data, SET_SENSOR_NO_RCK_V1);
319 lvts_write_all_device(lvts_data,
320 SET_DEVICE_LOW_POWER_SINGLE_MODE_V1);
321 return 0;
322 }
323
324 assert(lvts_data->num_tc <= MT8189_LVTS_CTRL_NUM);
325 for (i = 0; i < lvts_data->num_tc; i++) {
326 if (tc[i].ctrl_on_off == CTRL_OFF)
327 continue;
328
329 base = GET_BASE_ADDR(lvts_data, i);
330 lvts_write_device(lvts_data, SET_LVTS_MANUAL_RCK_OPERATION_8189,
331 i);
332
333 for (j = 0; j < tc[i].num_sensor; j++) {
334 if (j >= ALL_SENSING_POINTS)
335 break;
336
337 if (tc[i].sensor_on_off[j] != SEN_ON)
338 continue;
339
340 refine_data_idx[j] = 0xff;
341 s_index = tc[i].sensor_map[j];
342
343 lvts_write_device(lvts_data, SELECT_SENSOR_RCK_V1(j),
344 i);
345 lvts_write_device(lvts_data,
346 SET_DEVICE_SINGLE_MODE_8189, i);
347 lvts_write_device(lvts_data, SET_TS_DIV_EN_8189, i);
348 lvts_write_device(lvts_data, SET_VCO_RST_8189, i);
349 lvts_write_device(lvts_data, SET_TS_DIV_EN_8189, i);
350 udelay(20);
351
352 lvts_write_device(lvts_data, KICK_OFF_RCK_COUNTING_V1,
353 i);
354
355 ret = mmio_read_32_poll_timeout(
356 LVTS_CONFIG_0 + base,
357 temp,
358 ((temp & DEVICE_SENSING_STATUS) == 0),
359 20);
360 if (ret)
361 INFO("Error: %d DEVICE_SENSING_STATUS timeout\n"
362 , i);
363
364 lvts_write_device(lvts_data, SET_TS_DIS_8189, i);
365
366 /* wait for sensor 0*/
367 udelay(50 * (j == 0));
368
369 data = lvts_read_device(lvts_data, 0x00, i);
370 /* wait 5us buffer */
371 udelay(5);
372
373 rc_data = (data & GENMASK(23, 0));
374
375 if (rc_data == 0) {
376 refine_data_idx[j] = s_index;
377 } else {
378 if (cal_data->count_rc[i] > rc_data)
379 count_rc_delta = (cal_data->count_rc[i]
380 * 1000) / rc_data;
381 else
382 count_rc_delta = (rc_data * 1000)
383 / cal_data->count_rc[i];
384
385 if (count_rc_delta > 1061) {
386 refine_data_idx[j] = s_index;
387 }
388 }
389
390 ret = mmio_read_32_poll_timeout(
391 LVTS_CONFIG_0 + base,
392 temp,
393 ((temp & DEVICE_ACCESS_STARTUS) == 0),
394 20);
395 if (ret)
396 INFO("Error: %d DEVICE_ACCESS_START timeout\n",
397 i);
398
399 if (s_index < MT8189_NUM_TS) {
400 if (refine_data_idx[j] != 0xff) {
401 cal_data->count_rc_now[s_index] =
402 cal_data->count_rc[i];
403 } else {
404 cal_data->count_rc_now[s_index] =
405 rc_data & GENMASK(23, 0);
406 }
407 }
408
409 /* count data here that want to set to efuse later */
410 cal_data->efuse_data[s_index] = (uint32_t)(((
411 (unsigned long long)
412 cal_data->count_rc_now[s_index]) *
413 cal_data->count_r[s_index]) >> 14);
414 lvts_write_device(lvts_data,
415 (0x10 | SELECT_SENSOR_RCK_V1(j)), i);
416 }
417
418 /* Recover Setting for Normal Access on
419 * temperature fetch
420 */
421 lvts_write_device(lvts_data, SET_SENSOR_NO_RCK_V1, i);
422 lvts_write_device(lvts_data,
423 SET_DEVICE_LOW_POWER_SINGLE_MODE_V1, i);
424 }
425
426 return 0;
427 }
428
mt8189_lvts_reset(struct lvts_data * lvts_data)429 static void mt8189_lvts_reset(struct lvts_data *lvts_data)
430 {
431 unsigned int i;
432 uint32_t temp;
433
434 for (i = 0; i < lvts_data->num_domain; i++) {
435 if (i < MT8189_NUM_DOMAIN) {
436 temp = (uint32_t)BIT(
437 lvts_data->domain[i].reset_set_bitnum);
438 mmio_write_32((lvts_data->domain[i].reset_base +
439 lvts_data->domain[i].reset_set_offset),
440 temp);
441
442 udelay(1);
443
444 temp = (uint32_t)BIT(
445 lvts_data->domain[i].reset_clr_bitnum);
446 mmio_write_32((lvts_data->domain[i].reset_base +
447 lvts_data->domain[i].reset_clr_offset),
448 temp);
449 }
450 }
451
452 }
453
mt8189_device_identification(struct lvts_data * lvts_data)454 static void mt8189_device_identification(struct lvts_data *lvts_data)
455 {
456 unsigned int i;
457 uintptr_t base;
458 uint32_t data, lvts_dev_id;
459 struct tc_settings *tc = lvts_data->tc;
460
461 assert(lvts_data->num_tc <= MT8189_LVTS_CTRL_NUM);
462 for (i = 0; i < lvts_data->num_tc; i++) {
463 if (tc[i].ctrl_on_off == CTRL_OFF)
464 continue;
465
466 base = GET_BASE_ADDR(lvts_data, i);
467
468 mmio_write_32(LVTSCLKEN_0 + base, ENABLE_LVTS_CTRL_CLK);
469 }
470
471 lvts_write_all_device(lvts_data, RESET_ALL_DEVICES);
472 lvts_write_all_device(lvts_data, READ_BACK_DEVICE_ID);
473
474 for (i = 0; i < lvts_data->num_tc; i++) {
475 if (tc[i].ctrl_on_off == CTRL_OFF)
476 continue;
477
478 base = GET_BASE_ADDR(lvts_data, i);
479 /* Check LVTS device ID */
480 data = mmio_read_32(LVTS_ID_0 + base) & GENMASK(7, 0);
481
482 lvts_dev_id = 0x81 + i;
483
484 if (data != lvts_dev_id) {
485 INFO("LVTS_TC_%d, Device ID should be 0x%x, but 0x%x\n",
486 i, lvts_dev_id, data);
487 }
488 }
489 }
490
mt8189_efuse_to_cal_data(struct lvts_data * lvts_data)491 static void mt8189_efuse_to_cal_data(struct lvts_data *lvts_data)
492 {
493 struct sensor_cal_data *cal_data = &lvts_data->cal_data;
494 struct tc_settings *tc = lvts_data->tc;
495 unsigned int i;
496
497 cal_data->golden_temp = GET_CAL_BITMASK(lvts_data, 0, 7, 0);
498
499 assert(lvts_data->num_tc <= MT8189_LVTS_CTRL_NUM);
500 for (i = 0; i < lvts_data->num_tc; i++)
501 tc[i].coeff.golden_temp = cal_data->golden_temp;
502
503 cal_data->count_r[MT8189_TS1_0] = GET_CAL_BITMASK(lvts_data, 1, 23, 0);
504 cal_data->count_r[MT8189_TS1_1] = GET_CAL_BITMASK(lvts_data, 2, 23, 0);
505 cal_data->count_r[MT8189_TS1_2] = GET_CAL_BITMASK(lvts_data, 3, 23, 0);
506 cal_data->count_r[MT8189_TS1_3] = GET_CAL_BITMASK(lvts_data, 4, 23, 0);
507
508 cal_data->count_r[MT8189_TS2_0] = GET_CAL_BITMASK(lvts_data, 6, 23, 0);
509 cal_data->count_r[MT8189_TS2_1] = GET_CAL_BITMASK(lvts_data, 7, 23, 0);
510 cal_data->count_r[MT8189_TS2_2] = GET_CAL_BITMASK(lvts_data, 8, 23, 0);
511 cal_data->count_r[MT8189_TS2_3] = GET_CAL_BITMASK(lvts_data, 9, 23, 0);
512
513 cal_data->count_r[MT8189_TS3_0] = GET_CAL_BITMASK(lvts_data, 11, 23, 0);
514 cal_data->count_r[MT8189_TS3_1] = GET_CAL_BITMASK(lvts_data, 12, 23, 0);
515 cal_data->count_r[MT8189_TS3_2] = GET_CAL_BITMASK(lvts_data, 13, 23, 0);
516 cal_data->count_r[MT8189_TS3_3] = GET_CAL_BITMASK(lvts_data, 14, 23, 0);
517
518 cal_data->count_r[MT8189_TS4_0] = GET_CAL_BITMASK(lvts_data, 16, 23, 0);
519 cal_data->count_r[MT8189_TS4_1] = GET_CAL_BITMASK(lvts_data, 17, 23, 0);
520 cal_data->count_r[MT8189_TS4_2] = GET_CAL_BITMASK(lvts_data, 18, 23, 0);
521 cal_data->count_r[MT8189_TS4_3] = GET_CAL_BITMASK(lvts_data, 19, 23, 0);
522
523 cal_data->count_r[MT8189_TS5_0] = GET_CAL_BITMASK(lvts_data, 21, 23, 0);
524 cal_data->count_r[MT8189_TS5_1] = GET_CAL_BITMASK(lvts_data, 22, 23, 0);
525
526 cal_data->count_rc[MT8189_LVTS_MCU_CTRL0] =
527 GET_CAL_BITMASK(lvts_data, 0, 31, 8);
528 cal_data->count_rc[MT8189_LVTS_MCU_CTRL1] =
529 GET_CAL_BITMASK(lvts_data, 5, 23, 0);
530 cal_data->count_rc[MT8189_LVTS_MCU_CTRL2] =
531 GET_CAL_BITMASK(lvts_data, 10, 23, 0);
532
533 cal_data->count_rc[MT8189_LVTS_AP_CTRL0] =
534 GET_CAL_BITMASK(lvts_data, 15, 23, 0);
535 cal_data->count_rc[MT8189_LVTS_GPU_CTRL0] =
536 GET_CAL_BITMASK(lvts_data, 20, 23, 0);
537 }
538
mt8189_check_cal_data(struct lvts_data * lvts_data)539 static void mt8189_check_cal_data(struct lvts_data *lvts_data)
540 {
541 struct sensor_cal_data *cal_data = &lvts_data->cal_data;
542 struct tc_settings *tc = lvts_data->tc;
543 unsigned int i, j;
544 bool efuse_calibrated = false;
545
546 assert(lvts_data->num_sensor <= MT8189_NUM_TS);
547 assert(lvts_data->num_tc <= MT8189_LVTS_CTRL_NUM);
548 if ((cal_data->golden_temp != 0) || (cal_data->golden_temp_ht != 0)) {
549 efuse_calibrated = true;
550 } else {
551 for (i = 0; i < lvts_data->num_sensor; i++) {
552 if (cal_data->count_r[i] != 0) {
553 efuse_calibrated = true;
554 break;
555 }
556 }
557 if (!efuse_calibrated) {
558 for (j = 0; j < lvts_data->num_tc; j++) {
559 if (cal_data->count_rc[j] != 0) {
560 efuse_calibrated = true;
561 break;
562 }
563 }
564 }
565 }
566
567 if (!efuse_calibrated) {
568 /* It means all efuse data are equal to 0 */
569 INFO("[lvts_cal] This sample is not calibrated, fake !!\n");
570 for (i = 0; i < lvts_data->num_sensor; i++)
571 cal_data->count_r[i] = cal_data->default_count_r;
572
573 for (i = 0; i < lvts_data->num_tc; i++)
574 cal_data->count_rc[i] = cal_data->default_count_rc;
575
576 cal_data->golden_temp = cal_data->default_golden_temp;
577
578 for (i = 0; i < lvts_data->num_tc; i++)
579 tc[i].coeff.golden_temp = cal_data->default_golden_temp;
580 }
581 }
582
mt8189_update_coef_data(struct lvts_data * lvts_data)583 static void mt8189_update_coef_data(struct lvts_data *lvts_data)
584 {
585 struct sensor_cal_data *cal_data = &lvts_data->cal_data;
586 struct tc_settings *tc = lvts_data->tc;
587 unsigned int i, j, s_index;
588
589 for (i = 0; i < lvts_data->num_tc; i++) {
590 if (tc[i].ctrl_on_off == CTRL_OFF)
591 continue;
592
593 for (j = 0; j < tc[i].num_sensor; j++) {
594 if (tc[i].sensor_on_off[j] != SEN_ON)
595 continue;
596
597 s_index = tc[i].sensor_map[j];
598 tc[i].coeff.a[j] = COF_A_OFS + (COF_A_CONST_OFS *
599 (int)(cal_data->count_r[s_index])
600 / COF_A_COUNT_R_GLD);
601 }
602 }
603 }
604
605 static struct power_domain mt8189_domain_settings[MT8189_NUM_DOMAIN] = {
606 [MT8189_AP_DOMAIN] = {
607 .base = THERM_CTRL_AP_BASE,
608 .reset_base = INFRACFG_BASE,
609 .reset_set_offset = THERM_AP_RESET_SET_OFFSET,
610 .reset_clr_offset = THERM_AP_RESET_CLR_OFFSET,
611 .reset_set_bitnum = THERM_AP_RESET_SET_BITNUM,
612 .reset_clr_bitnum = THERM_AP_RESET_CLR_BITNUM,
613 },
614 [MT8189_MCU_DOMAIN] = {
615 .base = THERM_CTRL_MCU_BASE,
616 .reset_base = INFRACFG_BASE,
617 .reset_set_offset = THERM_MCU_RESET_SET_OFFSET,
618 .reset_clr_offset = THERM_MCU_RESET_CLR_OFFSET,
619 .reset_set_bitnum = THERM_MCU_RESET_SET_BITNUM,
620 .reset_clr_bitnum = THERM_MCU_RESET_CLR_BITNUM,
621 },
622 };
623
624 static struct tc_settings mt8189_tc_settings[MT8189_LVTS_CTRL_NUM] = {
625 [MT8189_LVTS_MCU_CTRL0] = {
626 .domain_index = MT8189_MCU_DOMAIN,
627 .addr_offset = 0x0,
628 .num_sensor = 4,
629 .sensor_map = {MT8189_TS1_0, MT8189_TS1_1, MT8189_TS1_2,
630 MT8189_TS1_3},
631 .ctrl_on_off = CTRL_ON,
632 .sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
633 .tc_speed = SET_TC_SPEED_IN_US(10, 2460, 10, 10),
634 .hw_filter = LVTS_FILTER_1,
635 .dominator_sensing_point = ALL_SENSING_POINTS,
636 .hw_reboot_trip_point = THERMAL_REBOOT_TEMPERATURE,
637 .irq_bit = BIT(1),
638 .coeff = {
639 .cali_mode = CALI_NT,
640 },
641 },
642 [MT8189_LVTS_MCU_CTRL1] = {
643 .domain_index = MT8189_MCU_DOMAIN,
644 .addr_offset = 0x100,
645 .num_sensor = 4,
646 .sensor_map = {MT8189_TS2_0, MT8189_TS2_1, MT8189_TS2_2,
647 MT8189_TS2_3},
648 .ctrl_on_off = CTRL_ON,
649 .sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
650 .tc_speed = SET_TC_SPEED_IN_US(10, 2460, 10, 10),
651 .hw_filter = LVTS_FILTER_1,
652 .dominator_sensing_point = ALL_SENSING_POINTS,
653 .hw_reboot_trip_point = THERMAL_REBOOT_TEMPERATURE,
654 .irq_bit = BIT(2),
655 .coeff = {
656 .cali_mode = CALI_NT,
657 },
658 },
659 [MT8189_LVTS_MCU_CTRL2] = {
660 .domain_index = MT8189_MCU_DOMAIN,
661 .addr_offset = 0x200,
662 .num_sensor = 4,
663 .sensor_map = {MT8189_TS3_0, MT8189_TS3_1, MT8189_TS3_2,
664 MT8189_TS3_3},
665 .ctrl_on_off = CTRL_ON,
666 .sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
667 .tc_speed = SET_TC_SPEED_IN_US(10, 4490, 10, 10),
668 .hw_filter = LVTS_FILTER_1,
669 .dominator_sensing_point = ALL_SENSING_POINTS,
670 .hw_reboot_trip_point = THERMAL_REBOOT_TEMPERATURE,
671 .irq_bit = BIT(3),
672 .coeff = {
673 .cali_mode = CALI_NT,
674 },
675 },
676 [MT8189_LVTS_AP_CTRL0] = {
677 .domain_index = MT8189_AP_DOMAIN,
678 .addr_offset = 0x0,
679 .num_sensor = 4,
680 .sensor_map = {MT8189_TS4_0, MT8189_TS4_1, MT8189_TS4_2,
681 MT8189_TS4_3},
682 .ctrl_on_off = CTRL_ON,
683 .sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
684 .tc_speed = SET_TC_SPEED_IN_US(10, 2100, 10, 10),
685 .hw_filter = LVTS_FILTER_1,
686 .dominator_sensing_point = ALL_SENSING_POINTS,
687 .hw_reboot_trip_point = THERMAL_REBOOT_TEMPERATURE,
688 .irq_bit = BIT(1),
689 .coeff = {
690 .cali_mode = CALI_NT,
691 },
692 },
693 [MT8189_LVTS_GPU_CTRL0] = {
694 .domain_index = MT8189_AP_DOMAIN,
695 .addr_offset = 0x100,
696 .num_sensor = 2,
697 .sensor_map = {MT8189_TS5_0, MT8189_TS5_1},
698 .ctrl_on_off = CTRL_ON,
699 .sensor_on_off = {SEN_ON, SEN_ON},
700 .tc_speed = SET_TC_SPEED_IN_US(10, 1380, 10, 10),
701 .hw_filter = LVTS_FILTER_1,
702 .dominator_sensing_point = ALL_SENSING_POINTS,
703 .hw_reboot_trip_point = THERMAL_REBOOT_TEMPERATURE,
704 .irq_bit = BIT(2),
705 .coeff = {
706 .cali_mode = CALI_NT,
707 },
708 },
709 };
710
711 static struct sensor_data mt8189_sensor_data[MT8189_NUM_TS];
712 static uint32_t mt8189_efuse[NUM_EFUSE_ADDR];
713 static uint32_t count_r[MT8189_NUM_TS];
714 static uint32_t count_rc[MT8189_LVTS_CTRL_NUM];
715 static uint32_t count_rc_now[MT8189_NUM_TS];
716 static uint32_t efuse_data[MT8189_NUM_TS];
717 static uint32_t irq_bitmap[MT8189_NUM_DOMAIN];
718
719 struct lvts_data lvts_data_instance = {
720 .num_domain = MT8189_NUM_DOMAIN,
721 .domain = mt8189_domain_settings,
722 .num_tc = MT8189_LVTS_CTRL_NUM,
723 .tc = mt8189_tc_settings,
724 .num_sensor = MT8189_NUM_TS,
725 .sen_data = mt8189_sensor_data,
726 .ops = {
727 .lvts_reset = mt8189_lvts_reset,
728 .device_identification = mt8189_device_identification,
729 .get_calibration_data = mt8189_get_calibration_data,
730 .efuse_to_cal_data = mt8189_efuse_to_cal_data,
731 .device_enable_and_init = mt8189_device_enable_and_init,
732 .device_enable_auto_rck = NULL,
733 .device_read_count_rc_n = mt8189_device_read_count_rc_n,
734 .set_cal_data = set_calibration_data_v1,
735 .init_controller = init_controller_v1,
736 .lvts_temp_to_raw = lvts_temp_to_raw_v1,
737 .lvts_raw_to_temp = lvts_raw_to_temp_v1,
738 .check_cal_data = mt8189_check_cal_data,
739 .update_coef_data = mt8189_update_coef_data,
740 },
741 .feature_bitmap = 0,
742 .num_efuse_addr = NUM_EFUSE_ADDR,
743 .efuse = mt8189_efuse,
744 .cal_data = {
745 .default_golden_temp = DEFAULT_EFUSE_GOLDEN_TEMP,
746 .default_golden_temp_ht = DEFAULT_EFUSE_GOLDEN_TEMP_HT,
747 .default_count_r = DEFAULT_EFUSE_COUNT,
748 .default_count_rc = DEFAULT_EFUSE_COUNT_RC,
749
750 .count_r = count_r,
751 .count_rc = count_rc,
752 .count_rc_now = count_rc_now,
753 .efuse_data = efuse_data,
754 },
755 .irq_bitmap = irq_bitmap,
756 .enable_dump_log = 0,
757 };
758
thermal_clock_open(void)759 void thermal_clock_open(void)
760 {
761 mmio_setbits_32(THERM_MODULE_SW_CG_0_CLR, BIT(THERM_BIT));
762 dmbsy();
763 }
764
thermal_clock_close(void)765 void thermal_clock_close(void)
766 {
767 mmio_setbits_32(THERM_MODULE_SW_CG_0_SET, BIT(THERM_BIT));
768 dmbsy();
769 }
770