1 /*
2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef ARCH_HELPERS_H
8 #define ARCH_HELPERS_H
9
10 #include <cdefs.h>
11 #include <stdbool.h>
12 #include <stdint.h>
13 #include <string.h>
14
15 #include <arch.h>
16 #include <lib/extensions/sysreg128.h>
17
18 /**********************************************************************
19 * Macros which create inline functions to read or write CPU system
20 * registers
21 *********************************************************************/
22
23 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
24 static inline u_register_t read_ ## _name(void) \
25 { \
26 u_register_t v; \
27 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
28 return v; \
29 }
30
31 #define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \
32 static inline u_register_t read_ ## _name(void) \
33 { \
34 u_register_t v; \
35 __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \
36 return v; \
37 }
38
39 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
40 static inline void write_ ## _name(u_register_t v) \
41 { \
42 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
43 }
44
45 #define SYSREG_WRITE_CONST(reg_name, v) \
46 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
47
48 /* Define read function for system register */
49 #define DEFINE_SYSREG_READ_FUNC(_name) \
50 _DEFINE_SYSREG_READ_FUNC(_name, _name)
51
52 /* Define read & write function for system register */
53 #define DEFINE_SYSREG_RW_FUNCS(_name) \
54 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
55 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
56
57 /* Define read & write function for renamed system register */
58 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
59 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
60 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
61
62 /* Define read function for renamed system register */
63 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
64 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
65
66 /* Define write function for renamed system register */
67 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
68 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
69
70 /* Define read function for ID register (w/o volatile qualifier) */
71 #define DEFINE_IDREG_READ_FUNC(_name) \
72 _DEFINE_SYSREG_READ_FUNC_NV(_name, _name)
73
74 /* Define read function for renamed ID register (w/o volatile qualifier) */
75 #define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \
76 _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name)
77
78 /**********************************************************************
79 * Macros to create inline functions for system instructions
80 *********************************************************************/
81
82 /* Define function for simple system instruction */
83 #define DEFINE_SYSOP_FUNC(_op) \
84 static inline void _op(void) \
85 { \
86 __asm__ (#_op); \
87 }
88
89 /* Define function for system instruction with register parameter */
90 #define DEFINE_SYSOP_PARAM_FUNC(_op) \
91 static inline void _op(uint64_t v) \
92 { \
93 __asm__ (#_op " %0" : : "r" (v)); \
94 }
95
96 /* Define function for system instruction with type specifier */
97 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
98 static inline void _op ## _type(void) \
99 { \
100 __asm__ (#_op " " #_type : : : "memory"); \
101 }
102
103 /* Define function for system instruction with register parameter */
104 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
105 static inline void _op ## _type(uint64_t v) \
106 { \
107 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
108 }
109
110 /*******************************************************************************
111 * TLB maintenance accessor prototypes
112 ******************************************************************************/
113
114 #if ERRATA_A57_813419 || ERRATA_A76_1286807
115 /*
116 * Define function for TLBI instruction with type specifier that implements
117 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
118 * Cortex-A76.
119 */
120 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\
121 static inline void tlbi ## _type(void) \
122 { \
123 __asm__("tlbi " #_type "\n" \
124 "dsb ish\n" \
125 "tlbi " #_type); \
126 }
127
128 /*
129 * Define function for TLBI instruction with register parameter that implements
130 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
131 * Cortex-A76.
132 */
133 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \
134 static inline void tlbi ## _type(uint64_t v) \
135 { \
136 __asm__("tlbi " #_type ", %0\n" \
137 "dsb ish\n" \
138 "tlbi " #_type ", %0" : : "r" (v)); \
139 }
140 #endif /* ERRATA_A57_813419 */
141
142 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
143 /*
144 * Define function for DC instruction with register parameter that enables
145 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
146 */
147 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
148 static inline void dc ## _name(uint64_t v) \
149 { \
150 __asm__("dc " #_type ", %0" : : "r" (v)); \
151 }
152 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
153
154 #if ERRATA_A57_813419
DEFINE_SYSOP_TYPE_FUNC(tlbi,alle1)155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
158 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
159 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
160 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
161 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
162 #elif ERRATA_A76_1286807
163 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1)
164 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is)
165 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2)
166 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is)
167 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
168 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
169 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1)
170 #else
171 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
172 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
173 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
174 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
175 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
176 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
177 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
178 #endif
179
180 #if ERRATA_A57_813419
181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
184 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
185 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
186 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
187 #elif ERRATA_A76_1286807
188 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is)
189 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is)
190 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is)
191 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is)
192 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
193 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
194 #else
195 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
196 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
197 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
198 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
199 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
200 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
201 #endif
202
203 /*******************************************************************************
204 * Cache maintenance accessor prototypes
205 ******************************************************************************/
206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
207 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
208 #if ERRATA_A53_827319
209 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
210 #else
211 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
212 #endif
213 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
214 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
215 #else
216 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
217 #endif
218 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
219 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
220 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
221 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
222 #else
223 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
224 #endif
225 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
226
227 /*******************************************************************************
228 * Address translation accessor prototypes
229 ******************************************************************************/
230 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
231 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
232 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
233 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
234 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
235 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
236 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
237
238 /*******************************************************************************
239 * Strip Pointer Authentication Code
240 ******************************************************************************/
241 static inline u_register_t xpaci(u_register_t arg)
242 {
243 __asm__ (".arch armv8.3-a\n"
244 "xpaci %0\n"
245 : "+r" (arg));
246
247 return arg;
248 }
249
250 void flush_dcache_range(uintptr_t addr, size_t size);
251 void flush_dcache_to_popa_range(uintptr_t addr, size_t size);
252 void flush_dcache_to_popa_range_mte2(uintptr_t addr, size_t size);
253 void clean_dcache_range(uintptr_t addr, size_t size);
254 void inv_dcache_range(uintptr_t addr, size_t size);
255 bool is_dcache_enabled(void);
256
257 void dcsw_op_louis(u_register_t op_type);
258 void dcsw_op_all(u_register_t op_type);
259
260 void disable_mmu_el1(void);
261 void disable_mmu_el3(void);
262 void disable_mpu_el2(void);
263 void disable_mmu_icache_el1(void);
264 void disable_mmu_icache_el3(void);
265 void disable_mpu_icache_el2(void);
266
267 /*******************************************************************************
268 * Misc. accessor prototypes
269 ******************************************************************************/
270
271 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
272 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
273
274
275 #if ENABLE_FEAT_D128 && !IMAGE_BL32
276 /* Don't use mrrs/msrr read/write implementation with tspd,
277 * While using SPD=tspd, tspd compiles with current arch_helpers
278 * thus trying to use mrrs/msrr read/write from Secure-world.
279 * SCR_EL3.D128en is set only for Non-Secure world, which may cause
280 * panic while using mrrs/msrr from tspd secure world.
281 */
282 DECLARE_SYSREG128_RW_FUNCS(par_el1)
283
DECLARE_SYSREG128_RW_FUNCS(ttbr0_el1)284 DECLARE_SYSREG128_RW_FUNCS(ttbr0_el1)
285 DECLARE_SYSREG128_RW_FUNCS(ttbr1_el1)
286
287 DECLARE_SYSREG128_RW_FUNCS(ttbr0_el2)
288 DECLARE_SYSREG128_RW_FUNCS(ttbr1_el2)
289 DECLARE_SYSREG128_RW_FUNCS(vttbr_el2)
290
291 /* FEAT_THE Registers */
292 DECLARE_SYSREG128_RW_FUNCS(rcwmask_el1)
293 DECLARE_SYSREG128_RW_FUNCS(rcwsmask_el1)
294 #else
295 DEFINE_SYSREG_RW_FUNCS(par_el1)
296
297 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
298 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
299
300 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
301 DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2)
302 DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
303
304 /* FEAT_THE Registers */
305 DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1)
306 DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1)
307
308 #endif /* ENABLE_FEAT_D128 && !IMAGE_BL32 */
309
310 DEFINE_IDREG_READ_FUNC(id_pfr0_el1)
311 DEFINE_IDREG_READ_FUNC(id_pfr1_el1)
312 DEFINE_RENAME_IDREG_READ_FUNC(id_pfr2_el1, ID_PFR2_EL1)
313 DEFINE_IDREG_READ_FUNC(id_afr0_el1)
314 DEFINE_IDREG_READ_FUNC(id_dfr0_el1)
315 DEFINE_RENAME_IDREG_READ_FUNC(id_dfr1_el1, ID_DFR1_EL1)
316 DEFINE_IDREG_READ_FUNC(id_mmfr0_el1)
317 DEFINE_IDREG_READ_FUNC(id_mmfr1_el1)
318 DEFINE_IDREG_READ_FUNC(id_mmfr2_el1)
319 DEFINE_IDREG_READ_FUNC(id_mmfr3_el1)
320 DEFINE_IDREG_READ_FUNC(id_mmfr4_el1)
321 DEFINE_IDREG_READ_FUNC(id_mmfr5_el1)
322 DEFINE_IDREG_READ_FUNC(id_isar0_el1)
323 DEFINE_IDREG_READ_FUNC(id_isar1_el1)
324 DEFINE_IDREG_READ_FUNC(id_isar2_el1)
325 DEFINE_IDREG_READ_FUNC(id_isar3_el1)
326 DEFINE_IDREG_READ_FUNC(id_isar4_el1)
327 DEFINE_IDREG_READ_FUNC(id_isar5_el1)
328 DEFINE_RENAME_IDREG_READ_FUNC(id_isar6_el1, ID_ISAR6_EL1)
329 DEFINE_IDREG_READ_FUNC(mvfr0_el1)
330 DEFINE_IDREG_READ_FUNC(mvfr1_el1)
331 DEFINE_IDREG_READ_FUNC(mvfr2_el1)
332
333 DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1)
334 DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1)
335 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
336 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar3_el1, ID_AA64ISAR3_EL1)
337 DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1)
338 DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1)
339 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1)
340 DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1)
341 DEFINE_IDREG_READ_FUNC(id_aa64dfr1_el1)
342 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64zfr0_el1, ID_AA64ZFR0_EL1)
343 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64fpfr0_el1, ID_AA64FPFR0_EL1)
344 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64dfr2_el1, ID_AA64DFR2_EL1)
345 DEFINE_IDREG_READ_FUNC(id_aa64afr0_el1)
346 DEFINE_IDREG_READ_FUNC(id_aa64afr1_el1)
347 DEFINE_RENAME_IDREG_READ_FUNC(gmid_el1, GMID_EL1)
348
349 DEFINE_SYSREG_READ_FUNC(CurrentEl)
350 DEFINE_SYSREG_READ_FUNC(ctr_el0)
351 DEFINE_SYSREG_RW_FUNCS(daif)
352 DEFINE_SYSREG_RW_FUNCS(spsr_el1)
353 DEFINE_SYSREG_RW_FUNCS(spsr_el2)
354 DEFINE_SYSREG_RW_FUNCS(spsr_el3)
355 DEFINE_SYSREG_RW_FUNCS(elr_el1)
356 DEFINE_SYSREG_RW_FUNCS(elr_el2)
357 DEFINE_SYSREG_RW_FUNCS(elr_el3)
358 DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
359 DEFINE_SYSREG_RW_FUNCS(mdccint_el1)
360 DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
361 DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
362 DEFINE_SYSREG_RW_FUNCS(sp_el1)
363 DEFINE_SYSREG_RW_FUNCS(sp_el2)
364 DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1)
365
366 DEFINE_SYSOP_FUNC(wfi)
367 DEFINE_SYSOP_FUNC(wfe)
368 DEFINE_SYSOP_FUNC(sev)
369 DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
370 DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
371 DEFINE_SYSOP_TYPE_FUNC(dmb, st)
372 DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
373 DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
374 DEFINE_SYSOP_TYPE_FUNC(dsb, osh)
375 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
376 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
377 DEFINE_SYSOP_TYPE_FUNC(dsb, oshst)
378 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
379 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
380 DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
381 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
382 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
383 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
384 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
385 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
386 DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
387 DEFINE_SYSOP_FUNC(isb)
388
389 static inline void enable_irq(void)
390 {
391 /*
392 * The compiler memory barrier will prevent the compiler from
393 * scheduling non-volatile memory access after the write to the
394 * register.
395 *
396 * This could happen if some initialization code issues non-volatile
397 * accesses to an area used by an interrupt handler, in the assumption
398 * that it is safe as the interrupts are disabled at the time it does
399 * that (according to program order). However, non-volatile accesses
400 * are not necessarily in program order relatively with volatile inline
401 * assembly statements (and volatile accesses).
402 */
403 COMPILER_BARRIER();
404 write_daifclr(DAIF_IRQ_BIT);
405 isb();
406 }
407
enable_fiq(void)408 static inline void enable_fiq(void)
409 {
410 COMPILER_BARRIER();
411 write_daifclr(DAIF_FIQ_BIT);
412 isb();
413 }
414
enable_serror(void)415 static inline void enable_serror(void)
416 {
417 COMPILER_BARRIER();
418 write_daifclr(DAIF_ABT_BIT);
419 isb();
420 }
421
enable_debug_exceptions(void)422 static inline void enable_debug_exceptions(void)
423 {
424 COMPILER_BARRIER();
425 write_daifclr(DAIF_DBG_BIT);
426 isb();
427 }
428
disable_irq(void)429 static inline void disable_irq(void)
430 {
431 COMPILER_BARRIER();
432 write_daifset(DAIF_IRQ_BIT);
433 isb();
434 }
435
disable_fiq(void)436 static inline void disable_fiq(void)
437 {
438 COMPILER_BARRIER();
439 write_daifset(DAIF_FIQ_BIT);
440 isb();
441 }
442
disable_serror(void)443 static inline void disable_serror(void)
444 {
445 COMPILER_BARRIER();
446 write_daifset(DAIF_ABT_BIT);
447 isb();
448 }
449
disable_debug_exceptions(void)450 static inline void disable_debug_exceptions(void)
451 {
452 COMPILER_BARRIER();
453 write_daifset(DAIF_DBG_BIT);
454 isb();
455 }
456
457 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
458 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
459
460 /*******************************************************************************
461 * System register accessor prototypes
462 ******************************************************************************/
463 DEFINE_IDREG_READ_FUNC(midr_el1)
464 DEFINE_SYSREG_READ_FUNC(mpidr_el1)
465 DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1)
466 DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1)
467
468 DEFINE_SYSREG_RW_FUNCS(scr_el3)
469 DEFINE_SYSREG_RW_FUNCS(hcr_el2)
470
471 DEFINE_SYSREG_RW_FUNCS(vbar_el1)
472 DEFINE_SYSREG_RW_FUNCS(vbar_el2)
473 DEFINE_SYSREG_RW_FUNCS(vbar_el3)
474
475 DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
476 DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
477 DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
478
479 DEFINE_SYSREG_RW_FUNCS(actlr_el1)
480 DEFINE_SYSREG_RW_FUNCS(actlr_el2)
481 DEFINE_SYSREG_RW_FUNCS(actlr_el3)
482
483 DEFINE_SYSREG_RW_FUNCS(esr_el1)
484 DEFINE_SYSREG_RW_FUNCS(esr_el2)
485 DEFINE_SYSREG_RW_FUNCS(esr_el3)
486
487 DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
488 DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
489 DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
490
491 DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
492 DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
493 DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
494
495 DEFINE_SYSREG_RW_FUNCS(far_el1)
496 DEFINE_SYSREG_RW_FUNCS(far_el2)
497 DEFINE_SYSREG_RW_FUNCS(far_el3)
498
499 DEFINE_SYSREG_RW_FUNCS(mair_el1)
500 DEFINE_SYSREG_RW_FUNCS(mair_el2)
501 DEFINE_SYSREG_RW_FUNCS(mair_el3)
502
503 DEFINE_SYSREG_RW_FUNCS(amair_el1)
504 DEFINE_SYSREG_RW_FUNCS(amair_el2)
505 DEFINE_SYSREG_RW_FUNCS(amair_el3)
506
507 DEFINE_SYSREG_READ_FUNC(rvbar_el1)
508 DEFINE_SYSREG_READ_FUNC(rvbar_el2)
509 DEFINE_SYSREG_READ_FUNC(rvbar_el3)
510
511 DEFINE_SYSREG_RW_FUNCS(rmr_el1)
512 DEFINE_SYSREG_RW_FUNCS(rmr_el2)
513 DEFINE_SYSREG_RW_FUNCS(rmr_el3)
514
515 DEFINE_SYSREG_RW_FUNCS(tcr_el1)
516 DEFINE_SYSREG_RW_FUNCS(tcr_el2)
517 DEFINE_SYSREG_RW_FUNCS(tcr_el3)
518
519 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
520
521 DEFINE_SYSREG_RW_FUNCS(cptr_el2)
522 DEFINE_SYSREG_RW_FUNCS(cptr_el3)
523
524 DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
525 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
526 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
527 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
528 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
529 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
530 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
531 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
532 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
533 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
534 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
535 DEFINE_SYSREG_READ_FUNC(cntpct_el0)
536 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
537 DEFINE_SYSREG_RW_FUNCS(cntv_ctl_el0)
538 DEFINE_SYSREG_RW_FUNCS(cntv_cval_el0)
539 DEFINE_SYSREG_RW_FUNCS(cntkctl_el1)
540
541 DEFINE_SYSREG_RW_FUNCS(vtcr_el2)
542
543 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
544 CNTP_CTL_ENABLE_MASK)
545 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
546 CNTP_CTL_IMASK_MASK)
547 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
548 CNTP_CTL_ISTATUS_MASK)
549
550 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
551 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
552
553 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
554 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
555
556 DEFINE_SYSREG_RW_FUNCS(tpidr_el0)
557 DEFINE_SYSREG_RW_FUNCS(tpidr_el1)
558 DEFINE_SYSREG_RW_FUNCS(tpidr_el2)
559 DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
560
561 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
562
563 DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
564 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
565
566 DEFINE_SYSREG_RW_FUNCS(hacr_el2)
567 DEFINE_SYSREG_RW_FUNCS(hpfar_el2)
568
569 DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2)
570 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2)
571 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2)
572
573 DEFINE_SYSREG_READ_FUNC(isr_el1)
574
575 DEFINE_SYSREG_RW_FUNCS(mdscr_el1)
576 DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
577 DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
578 DEFINE_SYSREG_RW_FUNCS(hstr_el2)
579 DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
580
581 DEFINE_SYSREG_RW_FUNCS(csselr_el1)
582 DEFINE_SYSREG_RW_FUNCS(tpidrro_el0)
583 DEFINE_SYSREG_RW_FUNCS(contextidr_el1)
584 DEFINE_SYSREG_RW_FUNCS(spsr_abt)
585 DEFINE_SYSREG_RW_FUNCS(spsr_und)
586 DEFINE_SYSREG_RW_FUNCS(spsr_irq)
587 DEFINE_SYSREG_RW_FUNCS(spsr_fiq)
588 DEFINE_SYSREG_RW_FUNCS(dacr32_el2)
589 DEFINE_SYSREG_RW_FUNCS(ifsr32_el2)
590
591 /* GICv5 System Registers */
592 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr0_el3, ICC_PPI_DOMAINR0_EL3)
593 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr1_el3, ICC_PPI_DOMAINR1_EL3)
594 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr2_el3, ICC_PPI_DOMAINR2_EL3)
595 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr3_el3, ICC_PPI_DOMAINR3_EL3)
596
597 /* GICv3 System Registers */
598
599 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
600 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
601 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
602 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
603 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
604 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
605 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
606 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
607 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
608 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
609 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
610 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
611 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
612 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
613 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
614 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
615 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R)
616
617 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
618 DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
619 DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0)
620 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0)
621 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
622 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
623 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
624 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
625 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr00_el0, AMEVCNTR00_EL0);
626 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr01_el0, AMEVCNTR01_EL0);
627 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr02_el0, AMEVCNTR02_EL0);
628 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr03_el0, AMEVCNTR03_EL0);
629
630 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr10_el0, AMEVCNTR10_EL0);
631 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr11_el0, AMEVCNTR11_EL0);
632 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr12_el0, AMEVCNTR12_EL0);
633 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr13_el0, AMEVCNTR13_EL0);
634 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr14_el0, AMEVCNTR14_EL0);
635 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr15_el0, AMEVCNTR15_EL0);
636 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr16_el0, AMEVCNTR16_EL0);
637 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr17_el0, AMEVCNTR17_EL0);
638 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr18_el0, AMEVCNTR18_EL0);
639 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr19_el0, AMEVCNTR19_EL0);
640 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1a_el0, AMEVCNTR1A_EL0);
641 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1b_el0, AMEVCNTR1B_EL0);
642 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1c_el0, AMEVCNTR1C_EL0);
643 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1d_el0, AMEVCNTR1D_EL0);
644 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1e_el0, AMEVCNTR1E_EL0);
645 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1f_el0, AMEVCNTR1F_EL0);
646
DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1,PMBLIMITR_EL1)647 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
648
649 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
650 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
651
652 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
653 DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3)
654 DEFINE_RENAME_SYSREG_RW_FUNCS(svcr, SVCR)
655
656 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
657 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
658
659 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
660 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
661 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
662 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
663 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
664 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
665
666 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
667 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1)
668 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0)
669
670 /* Armv8.1 VHE Registers */
671 DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
672
673 /* Armv8.2 ID Registers */
674 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
675
676 /* Armv8.2 RAS Registers */
677 DEFINE_RENAME_SYSREG_RW_FUNCS(disr_el1, DISR_EL1)
678 DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2)
679 DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2)
680
681 /* Armv8.2 MPAM Registers */
682 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
683 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
684 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
685 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
686 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm0_el2, MPAMVPM0_EL2)
687 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm1_el2, MPAMVPM1_EL2)
688 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm2_el2, MPAMVPM2_EL2)
689 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm3_el2, MPAMVPM3_EL2)
690 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm4_el2, MPAMVPM4_EL2)
691 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm5_el2, MPAMVPM5_EL2)
692 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm6_el2, MPAMVPM6_EL2)
693 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm7_el2, MPAMVPM7_EL2)
694 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpmv_el2, MPAMVPMV_EL2)
695
696 /* Armv8.3 Pointer Authentication Registers */
697 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
698 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
699
700 /* Armv8.4 Data Independent Timing Register */
701 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
702
703 /* Armv8.4 FEAT_TRF Register */
704 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
705 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
706 DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
707
708 /* Armv8.5 MTE Registers */
709 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
710 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
711 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
712 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
713 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2)
714
715 /* Armv8.5 FEAT_RNG Registers */
716 DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
717 DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)
718
719 /* Armv8.6 FEAT_FGT Registers */
720 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
721 DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2)
722 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
723 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2)
724 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2)
725 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2)
726
727 /* ARMv8.6 FEAT_ECV Register */
728 DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2)
729
730 /* FEAT_HCX Register */
731 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
732
733 /* Armv8.9 system registers */
734 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1)
735
736 /* Armv8.9 FEAT_FGT2 Registers */
737 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr2_el2, HDFGRTR2_EL2)
738 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr2_el2, HDFGWTR2_EL2)
739 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr2_el2, HFGITR2_EL2)
740 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr2_el2, HFGRTR2_EL2)
741 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr2_el2, HFGWTR2_EL2)
742
743 /* FEAT_TCR2 Register */
744 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el1, TCR2_EL1)
745 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2)
746
747 /* FEAT_SxPIE Registers */
748 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el1, PIRE0_EL1)
749 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2)
750 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el1, PIR_EL1)
751 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2)
752 DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2)
753
754 /* FEAT_SxPOE Registers */
755 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el1, POR_EL1)
756 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2)
757 DEFINE_RENAME_SYSREG_RW_FUNCS(s2por_el1, S2POR_EL1)
758
759 /* FEAT_GCS Registers */
760 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
761 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
762 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
763 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1)
764 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
765 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
766
767 /* FEAT_SCTLR2 Registers */
768 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
769 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)
770 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el3, SCTLR2_EL3)
771
772 /* FEAT_LS64_ACCDATA Registers */
773 DEFINE_RENAME_SYSREG_RW_FUNCS(accdata_el1, ACCDATA_EL1)
774
775 /* DynamIQ Control registers */
776 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
777 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcr_el1, CLUSTERPMCR_EL1)
778 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcntenset_el1, CLUSTERPMCNTENSET_EL1)
779 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmccntr_el1, CLUSTERPMCCNTR_EL1)
780 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsset_el1, CLUSTERPMOVSSET_EL1)
781 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsclr_el1, CLUSTERPMOVSCLR_EL1)
782 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmselr_el1, CLUSTERPMSELR_EL1)
783 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevcntr_el1, CLUSTERPMXEVCNTR_EL1)
784 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevtyper_el1, CLUSTERPMXEVTYPER_EL1)
785 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmmdcr_el3, CLUSTERPMMDCR_EL3)
786
787 /* CPU Power/Performance Management registers */
788 DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3)
789 DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3)
790
791 /* Armv9.1 FEAT_BRBE Registers */
792 DEFINE_RENAME_SYSREG_RW_FUNCS(brbcr_el2, BRBCR_EL2)
793
794 /* Armv9.2 RME Registers */
795 DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3)
796 DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3)
797
798 DEFINE_RENAME_SYSREG_RW_FUNCS(fpmr, FPMR)
799
800 /* FEAT_MEC Registers */
801 DEFINE_RENAME_SYSREG_READ_FUNC(mecidr_el2, MECIDR_EL2)
802
803 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr4_el1, ID_AA64MMFR4_EL1)
804
805 /* FEAT_FGWTE3 Registers */
806 DEFINE_RENAME_SYSREG_RW_FUNCS(fgwte3_el3, FGWTE3_EL3)
807
808 /* Armv9.3 MPAM_PE_BW_CTRL Registers */
809 DEFINE_RENAME_SYSREG_RW_FUNCS(mpambw2_el2, MPAMBW2_EL2)
810 DEFINE_RENAME_SYSREG_RW_FUNCS(mpambw3_el3, MPAMBW3_EL3)
811
812 #define IS_IN_EL(x) \
813 (GET_EL(read_CurrentEl()) == MODE_EL##x)
814
815 #define IS_IN_EL1() IS_IN_EL(1)
816 #define IS_IN_EL2() IS_IN_EL(2)
817 #define IS_IN_EL3() IS_IN_EL(3)
818
819 static inline unsigned int get_current_el(void)
820 {
821 return GET_EL(read_CurrentEl());
822 }
823
get_current_el_maybe_constant(void)824 static inline unsigned int get_current_el_maybe_constant(void)
825 {
826 #if defined(IMAGE_AT_EL1)
827 return 1;
828 #elif defined(IMAGE_AT_EL2)
829 return 2; /* no use-case in TF-A */
830 #elif defined(IMAGE_AT_EL3)
831 return 3;
832 #else
833 /*
834 * If we do not know which exception level this is being built for
835 * (e.g. built for library), fall back to run-time detection.
836 */
837 return get_current_el();
838 #endif
839 }
840
841 /*
842 * Check if an EL is implemented from AA64PFR0 register fields.
843 */
el_implemented(unsigned int el)844 static inline uint64_t el_implemented(unsigned int el)
845 {
846 if (el > 3U) {
847 return EL_IMPL_NONE;
848 } else {
849 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
850
851 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
852 }
853 }
854
855 /*
856 * Read number of break points available.
857 */
read_brps_id_field(void)858 static inline unsigned int read_brps_id_field(void)
859 {
860 return EXTRACT(ID_AA64DFR1_BRP, read_id_aa64dfr1_el1());
861 }
862
863 /*
864 * TLBI PAALLOS instruction
865 * (TLB Invalidate GPT Information by PA, All Entries, Outer Shareable)
866 */
tlbipaallos(void)867 static inline void tlbipaallos(void)
868 {
869 __asm__("sys #6, c8, c1, #4");
870 }
871
872 /*
873 * TLBI RPALOS instructions
874 * (TLB Range Invalidate GPT Information by PA, Last level, Outer Shareable)
875 *
876 * command SIZE, bits [47:44] field:
877 * 0b0000 4KB
878 * 0b0001 16KB
879 * 0b0010 64KB
880 * 0b0011 2MB
881 * 0b0100 32MB
882 * 0b0101 512MB
883 * 0b0110 1GB
884 * 0b0111 16GB
885 * 0b1000 64GB
886 * 0b1001 512GB
887 */
888 #define TLBI_SZ_4K 0UL
889 #define TLBI_SZ_16K 1UL
890 #define TLBI_SZ_64K 2UL
891 #define TLBI_SZ_2M 3UL
892 #define TLBI_SZ_32M 4UL
893 #define TLBI_SZ_512M 5UL
894 #define TLBI_SZ_1G 6UL
895 #define TLBI_SZ_16G 7UL
896 #define TLBI_SZ_64G 8UL
897 #define TLBI_SZ_512G 9UL
898
899 #define TLBI_ADDR_SHIFT U(12)
900 #define TLBI_SIZE_SHIFT U(44)
901
902 #define TLBIRPALOS(_addr, _size) \
903 { \
904 u_register_t arg = ((_addr) >> TLBI_ADDR_SHIFT) | \
905 ((_size) << TLBI_SIZE_SHIFT); \
906 __asm__("sys #6, c8, c4, #7, %0" : : "r" (arg)); \
907 }
908
909 /* Note: addr must be aligned to 4KB */
tlbirpalos_4k(uintptr_t addr)910 static inline void tlbirpalos_4k(uintptr_t addr)
911 {
912 TLBIRPALOS(addr, TLBI_SZ_4K);
913 }
914
915 /* Note: addr must be aligned to 16KB */
tlbirpalos_16k(uintptr_t addr)916 static inline void tlbirpalos_16k(uintptr_t addr)
917 {
918 TLBIRPALOS(addr, TLBI_SZ_16K);
919 }
920
921 /* Note: addr must be aligned to 64KB */
tlbirpalos_64k(uintptr_t addr)922 static inline void tlbirpalos_64k(uintptr_t addr)
923 {
924 TLBIRPALOS(addr, TLBI_SZ_64K);
925 }
926
927 /* Note: addr must be aligned to 2MB */
tlbirpalos_2m(uintptr_t addr)928 static inline void tlbirpalos_2m(uintptr_t addr)
929 {
930 TLBIRPALOS(addr, TLBI_SZ_2M);
931 }
932
933 /* Note: addr must be aligned to 32MB */
tlbirpalos_32m(uintptr_t addr)934 static inline void tlbirpalos_32m(uintptr_t addr)
935 {
936 TLBIRPALOS(addr, TLBI_SZ_32M);
937 }
938
939 /* Note: addr must be aligned to 512MB */
tlbirpalos_512m(uintptr_t addr)940 static inline void tlbirpalos_512m(uintptr_t addr)
941 {
942 TLBIRPALOS(addr, TLBI_SZ_512M);
943 }
944
945 /* Previously defined accessor functions with incomplete register names */
946
947 #define read_current_el() read_CurrentEl()
948
949 #define dsb() dsbsy()
950
951 #define read_midr() read_midr_el1()
952
953 #define read_mpidr() read_mpidr_el1()
954
955 #define read_scr() read_scr_el3()
956 #define write_scr(_v) write_scr_el3(_v)
957
958 #define read_hcr() read_hcr_el2()
959 #define write_hcr(_v) write_hcr_el2(_v)
960
961 #define read_cpacr() read_cpacr_el1()
962 #define write_cpacr(_v) write_cpacr_el1(_v)
963
964 #define read_clusterpwrdn() read_clusterpwrdn_el1()
965 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
966
967 #define read_clusterpmcr() read_clusterpmcr_el1()
968 #define write_clusterpmcr(_v) write_clusterpmcr_el1(_v)
969
970 #define read_clusterpmcntenset() read_clusterpmcntenset_el1()
971 #define write_clusterpmcntenset(_v) write_clusterpmcntenset_el1(_v)
972
973 #define read_clusterpmccntr() read_clusterpmccntr_el1()
974 #define write_clusterpmccntr(_v) write_clusterpmccntr_el1(_v)
975
976 #define read_clusterpmovsset() read_clusterpmovsset_el1()
977 #define write_clusterpmovsset(_v) write_clusterpmovsset_el1(_v)
978
979 #define read_clusterpmovsclr() read_clusterpmovsclr_el1()
980 #define write_clusterpmovsclr(_v) write_clusterpmovsclr_el1(_v)
981
982 #define read_clusterpmselr() read_clusterpmselr_el1()
983 #define write_clusterpmselr(_v) write_clusterpmselr_el1(_v)
984
985 #define read_clusterpmxevcntr() read_clusterpmxevcntr_el1()
986 #define write_clusterpmxevcntr(_v) write_clusterpmxevcntr_el1(_v)
987
988 #define read_clusterpmxevtyper() read_clusterpmxevtyper_el1()
989 #define write_clusterpmxevtyper(_v) write_clusterpmxevtyper_el1(_v)
990
991 #define read_clusterpmmdcr() read_clusterpmmdcr_el3()
992 #define write_clusterpmmdcr(_v) write_clusterpmmdcr_el3(_v)
993
994 #if ERRATA_SPECULATIVE_AT
995 /*
996 * Assuming SCTLR.M bit is already enabled
997 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits
998 * 2. Execute AT instruction for lower EL1/0
999 * 3. Disable page table walk by setting TCR_EL1.EPDx bits
1000 */
1001 #define AT(_at_inst, _va) \
1002 { \
1003 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
1004 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \
1005 isb(); \
1006 _at_inst(_va); \
1007 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \
1008 isb(); \
1009 }
1010 #else
1011 #define AT(_at_inst, _va) _at_inst(_va)
1012 #endif
1013
1014 #endif /* ARCH_HELPERS_H */
1015