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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 //============================================================================== 95 // [mvideo_context.h] 96 // Date: 20081203 97 // Descriptions: structure pool 98 //============================================================================== 99 #ifndef MVIDEO_CONTEXT_H 100 #define MVIDEO_CONTEXT_H 101 102 #include "MsCommon.h" 103 #ifdef MSOS_TYPE_LINUX_KERNEL 104 #include "drvCMAPool_v2.h" 105 #else 106 #include "drvCMAPool.h" 107 #endif 108 #include "mhal_xc_chip_config.h" 109 110 #include "ULog.h" 111 #include "UFO.h" 112 113 //============================================================================== 114 //============================================================================== 115 #ifdef MVIDEO_CONTEXT_C 116 #define INTERFACE 117 #else 118 #define INTERFACE extern 119 #endif 120 #if (defined ANDROID) && (defined TV_OS) 121 #include <cutils/log.h> 122 #define printf LOGD 123 #ifndef LOGD // android 4.1 rename LOGx to ALOGx 124 #define LOGD ALOGD 125 #endif 126 #endif 127 #define XC_CONTEXT_ENABLE 1 128 129 130 #if 0//(defined ANDROID) //add for dbg convenience 131 #include <cutils/log.h> 132 #define printf LOGD 133 #endif 134 135 #if defined ANDROID 136 #include <sys/mman.h> 137 #include <cutils/ashmem.h> 138 #include <cutils/log.h> 139 140 #define printf ALOGD 141 #endif 142 143 #ifdef CONFIG_MS_DEBUG_XC_LOG 144 #ifndef MS_DEBUG 145 #define MS_DEBUG 146 #endif 147 #endif 148 //#define MS_DEBUG 1 149 150 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB //when the app layer ewindow is sub xc change to device_id1 151 INTERFACE void *g_pDevice0Instance; //instance pointer,for recording sc0 152 INTERFACE void *g_pDevice1Instance; //instance pointer,for recording sc1 153 154 #if (defined CONFIG_MLOG) 155 #define CHECK_DEVICE0_INSTANCE()\ 156 do{\ 157 if (g_pDevice0Instance == NULL)\ 158 {\ 159 ULOGD("XC_ERR","[utopia error]function %s line %d instance pointer for device 0 should not be null\n",__FUNCTION__,__LINE__);\ 160 }\ 161 }while(0) 162 #define CHECK_DEVICE1_INSTANCE()\ 163 do{\ 164 if (g_pDevice1Instance == NULL)\ 165 {\ 166 ULOGD("XC_ERR","[utopia error]function %s line %d instance pointer for device 1 should not be null\n",__FUNCTION__,__LINE__);\ 167 }\ 168 }while(0) 169 #else 170 #define CHECK_DEVICE0_INSTANCE()\ 171 do{\ 172 if (g_pDevice0Instance == NULL)\ 173 {\ 174 printf("[utopia error]function %s line %d instance pointer for device 0 should not be null\n",__FUNCTION__,__LINE__);\ 175 }\ 176 }while(0) 177 #define CHECK_DEVICE1_INSTANCE()\ 178 do{\ 179 if (g_pDevice1Instance == NULL)\ 180 {\ 181 printf("[utopia error]function %s line %d instance pointer for device 1 should not be null\n",__FUNCTION__,__LINE__);\ 182 }\ 183 }while(0) 184 #endif 185 #define USE_OTHER_SC_AS_SUB_WINDOW()\ 186 do \ 187 { \ 188 if(pXCArgs->eWindow == SUB_WINDOW) \ 189 { \ 190 CHECK_DEVICE1_INSTANCE();\ 191 pInstance = g_pDevice1Instance;\ 192 pXCArgs->eWindow = MAIN_WINDOW; \ 193 } \ 194 }while(0) 195 #else 196 #define USE_OTHER_SC_AS_SUB_WINDOW() \ 197 do \ 198 { \ 199 }while(0) 200 #endif 201 #ifdef MS_DEBUG 202 #if (defined CONFIG_MLOG) 203 #define XC_LOG_TRACE(_dbgSwitch_, _fmt, _args...) \ 204 { \ 205 if( (_dbgSwitch_ & _u16XCDbgSwitch_InternalUseOnly) != 0 ) \ 206 { \ 207 if (_dbgSwitch_ & XC_DBGLEVEL_SETTIMING) \ 208 { \ 209 ULOGD("XC_LPLL","[%s,%5d] ",__FUNCTION__,__LINE__); \ 210 ULOGD("XC_LPLL",_fmt, ##_args); \ 211 } \ 212 else if (_dbgSwitch_ & XC_DBGLEVEL_SETWINDOW) \ 213 { \ 214 ULOGD("XC_SETWINDOW","[%s,%5d] ",__FUNCTION__,__LINE__); \ 215 ULOGD("XC_SETWINDOW",_fmt, ##_args); \ 216 } \ 217 else if (_dbgSwitch_ & XC_DBGLEVEL_MUX) \ 218 { \ 219 ULOGD("XC_MUX","[%s,%5d] ",__FUNCTION__,__LINE__); \ 220 ULOGD("XC_MUX",_fmt, ##_args); \ 221 } \ 222 else if (_dbgSwitch_ & XC_DGBLEVEL_CROPCALC) \ 223 { \ 224 ULOGD("XC_CROP","[%s,%5d] ",__FUNCTION__,__LINE__); \ 225 ULOGD("XC_CROP",_fmt, ##_args); \ 226 } \ 227 else if (_dbgSwitch_ & XC_DBGLEVEL_AUTOGEOMETRY) \ 228 { \ 229 ULOGD("XC_AUTOGEO","[%s,%5d] ",__FUNCTION__,__LINE__); \ 230 ULOGD("XC_AUTOGEO",_fmt, ##_args); \ 231 } \ 232 else if (_dbgSwitch_ & XC_DBGLEVEL_SETTIMING_ISR) \ 233 { \ 234 ULOGD("XC_LPLL_ISR","[%s,%5d] ",__FUNCTION__,__LINE__); \ 235 ULOGD("XC_LPLL_ISR",_fmt, ##_args); \ 236 } \ 237 else if (_dbgSwitch_ & XC_DBGLEVEL_FUNCTION_TRACE) \ 238 { \ 239 ULOGD("XC_FUN_TRACE","[%s,%5d] ",__FUNCTION__,__LINE__); \ 240 ULOGD("XC_FUN_TRACE",_fmt, ##_args); \ 241 } \ 242 else if (_dbgSwitch_ & XC_DBGLEVEL_PARAMETER_TRACE) \ 243 { \ 244 ULOGD("XC_PARA_TRACE","[%s,%5d] ",__FUNCTION__,__LINE__); \ 245 ULOGD("XC_PARA_TRACE",_fmt, ##_args); \ 246 } \ 247 } \ 248 } 249 #else 250 #define XC_LOG_TRACE(_dbgSwitch_, _fmt, _args...) \ 251 { \ 252 if( (_dbgSwitch_ & _u16XCDbgSwitch_InternalUseOnly) != 0 ) \ 253 { \ 254 MDrv_XC_ShowTrace_Header(_dbgSwitch_); \ 255 printf("[%s,%5d] ",__FUNCTION__,__LINE__); \ 256 printf(_fmt, ##_args); \ 257 } \ 258 } 259 #endif 260 #else 261 #define XC_LOG_TRACE(_dbgSwitch_, _fmt, _args...) 262 #endif 263 264 typedef struct 265 { 266 MS_U16 u16CMDCNT_IPM; 267 MS_U16 u16CMDCNT_IPS; 268 MS_U16 u16CMDCNT_OPM; 269 MS_U16 u16CMDCNT_OPS; 270 } XC_DS_CMDCNT; 271 272 ///< number of panel_info_ex supported by current XC 273 #define PANEL_INFO_EX_NUM 3 274 275 // default value for SC_IP pixel repetition (gsrcinfo.status2.u8IP_PixelRep) 276 #define INVALID_IP_PIXELREPTITION 0xFF 277 278 // default timeout value for wait output vsync 279 #define DEFAULT_OUTPUT_VSYNC_TIMEOUT 25 280 #define MAX_DIP_BUFF_CNT 8 281 282 #define BWR_MEM_CFG_NUM 8 283 #define BWR_BITPERPIX_CFG_NUM 3 284 285 #define BIT_PER_PIX_VAULE_16 16 286 #define BIT_PER_PIX_VAULE_20 20 287 #define BIT_PER_PIX_VAULE_24 24 288 289 #define IsVBY1(x) ( (((x)>= E_XC_PNL_LPLL_VBY1_10BIT_4LANE)&&((x)<= E_XC_PNL_LPLL_VBY1_8BIT_8LANE)) || ((x)== E_XC_PNL_LPLL_VBY1_10BIT_16LANE)||((x)== E_XC_PNL_LPLL_VBY1_8BIT_16LANE) ) 290 #define IsVBY1_16LANE(x) (((x)== E_XC_PNL_LPLL_VBY1_10BIT_16LANE)||((x)== E_XC_PNL_LPLL_VBY1_8BIT_16LANE)) 291 292 #ifdef PATCH_TCON_BRING_UP 293 static const char panelName_UD_VB1_8LANE_DRDEPI[20] = "UD_VB1_8LANE_DRDEPI"; 294 #define VSYNC_START_FOR_UD_VB1_8LANE_DRDEPI 1 295 #define VSYNC_END_FOR_UD_VB1_8LANE_DRDEPI 3 296 #endif 297 298 //kinds of BWR memory config type 299 typedef enum 300 { 301 E_XC_BWR_MEM_CONFIG_1, 302 E_XC_BWR_MEM_CONFIG_2, 303 E_XC_BWR_MEM_CONFIG_3, 304 E_XC_BWR_MEM_CONFIG_4, 305 E_XC_BWR_MEM_CONFIG_5, 306 E_XC_BWR_MEM_CONFIG_6, 307 E_XC_BWR_MEM_CONFIG_7, 308 E_XC_BWR_MEM_CONFIG_8, 309 E_XC_BWR_MEM_CONFIG_Max, 310 } E_XC_BWR_MEM_CONFIG; 311 312 //kinds of bitperpix config type 313 typedef enum 314 { 315 E_XC_BWR_MEM_CFG_BPP_16, 316 E_XC_BWR_MEM_CFG_BPP_20, 317 E_XC_BWR_MEM_CFG_BPP_24, 318 E_XC_BWR_MEM_CFG_BPP_MAX, 319 } E_XC_BWR_MEM_CFG_BPP_TYPE; 320 321 //BWR memory config index 322 typedef enum 323 { 324 E_XC_BWR_MME_CFG_INDEX_0, 325 E_XC_BWR_MME_CFG_INDEX_1, 326 E_XC_BWR_MME_CFG_INDEX_2, 327 E_XC_BWR_MME_CFG_INDEX_3, 328 E_XC_BWR_MME_CFG_INDEX_MAX, 329 } E_XC_BWR_MME_CFG_INDEX; 330 331 // for semaphore POOL 332 typedef enum 333 { 334 E_XC_POOL_ID_INTERNAL_REGISTER = 0, // for XC write register 335 E_XC_POOL_ID_INTERNAL_VARIABLE = 1, // for XC global variable 336 E_XC_POOL_ID_INTERNAL_MENULOAD = 2, // for menuload write register 337 E_XC_POOL_ID_INTERNAL_DS = 3, // for DS write register 338 339 340 E_XC_POOL_ID_NUM, 341 E_XC_POOL_ID_INTERNAL_REGISTER_1 = E_XC_POOL_ID_NUM, // for XC write register 342 E_XC_POOL_ID_INTERNAL_VARIABLE_1, // for XC global variable 343 E_XC_POOL_ID_INTERNAL_MENULOAD_1, // for menuload write register 344 E_XC_POOL_ID_INTERNAL_DS_1, // for DS write register 345 346 E_XC_POOL_ID_MAX, 347 } E_XC_POOL_ID; 348 typedef enum 349 { 350 E_XC_ID_REG = 0, // for XC write register 351 E_XC_ID_VAR = 1, // for XC global variable 352 E_XC_ID_MLD = 2, // for menuload write register 353 E_XC_ID_DS = 3, // for ds write register 354 } E_XC_POOL_ID_TYPE; 355 356 357 /// frame/field number stored in frame buffer 358 typedef enum 359 { 360 IMAGE_STORE_UNDEFINE = 0, 361 IMAGE_STORE_2_FIELDS = 1, 362 IMAGE_STORE_4_FIELDS, 363 IMAGE_STORE_6_FIELDS, 364 IMAGE_STORE_8_FIELDS, 365 IMAGE_STORE_10_FIELDS, 366 IMAGE_STORE_12_FIELDS, 367 IMAGE_STORE_14_FIELDS, 368 IMAGE_STORE_16_FIELDS, 369 IMAGE_STORE_18_FIELDS, 370 IMAGE_STORE_20_FIELDS, 371 372 IMAGE_STORE_2_FRAMES = 100, 373 IMAGE_STORE_3_FRAMES, 374 IMAGE_STORE_4_FRAMES, 375 IMAGE_STORE_5_FRAMES, 376 IMAGE_STORE_6_FRAMES, 377 IMAGE_STORE_7_FRAMES, 378 IMAGE_STORE_8_FRAMES, 379 IMAGE_STORE_9_FRAMES, 380 IMAGE_STORE_10_FRAMES, 381 IMAGE_STORE_11_FRAMES, 382 IMAGE_STORE_12_FRAMES, 383 IMAGE_STORE_13_FRAMES 384 } XC_FRAME_STORE_NUMBER; 385 386 // for ipm connect opm or frcm 387 typedef enum 388 { 389 E_XC_IPM_CONNETC_SUB_FRCM = 0, 390 E_XC_IPM_CONNETC_MAIN_FRCM, 391 E_XC_IPM_CONNETC_SUB_OPM, 392 E_XC_IPM_CONNETC_MAIN_OPM 393 } E_XC_IPM_CONNECT_ID; 394 395 // for frcm connect scm or frcm 396 typedef enum 397 { 398 E_XC_FRCMW_CONNETC_SUB_SCM = 0, 399 E_XC_FRCMW_CONNETC_MAIN_SCM, 400 E_XC_FRCMW_CONNETC_SUB_FRCM, 401 E_XC_FRCMW_CONNETC_MAIN_FRCM 402 } E_XC_FRCMW_CONNECT_ID; 403 404 // for memory scm->frcm or direct frcm 405 typedef enum 406 { 407 E_XC_SCM_TO_FRCM = 0, 408 E_XC_DIRECT_FRCM, 409 E_XC_STREAM_FLOW_MAX 410 } E_XC_STREAM_FLOW; 411 412 // Define store value 413 typedef enum 414 { 415 E_STORE_VALUE_AUTO_TUNE_AREA_TRIG = 0, //Generate TRAIN_TRIG_P from delayed line of Vsync(Setting the delay line for Auto tune area) 416 E_STORE_VALUE_DISP_AREA_TRIG, //Generate DISP_TRIG_P from delayed line of Vsync(Setting the delay line for Display area) 417 E_STORE_VALUE_IP_AUTO_TUNE_AREA_TRIG, // DI change to ip and add auto tune area trig for ip 418 E_STORE_VALUE_IP_DISP_AREA_TRIG, // DI change to ip and add display area trig for ip 419 E_STORE_VALUE_INIT_CMD_NUM, //BK20_90 init cmd number 420 E_STORE_VALUE_MAX 421 }EN_STORE_VALUE_TYPE; 422 423 // For XC bypass mode, check which module be bypassed 424 typedef enum 425 { 426 E_XC_BYPASS_HVSP = 0, 427 }E_XC_BYPASS_MODULE; 428 429 typedef enum { 430 E_XC_INSTANT_TYPE_XC = 0, 431 E_XC_INSTANT_TYPE_ACE, 432 E_XC_INSTANT_TYPE_GOP, 433 E_XC_INSTANT_TYPE_NUM, 434 } E_XC_INSTANT_TYPE; 435 436 typedef enum 437 { 438 pipeID_SC0_main, 439 pipeID_SC0_sub, 440 pipeID_SC1_main, 441 } SCALER_PIPE_ID; 442 443 typedef enum 444 { 445 E_XC_OPTEE_TIMER_TEE_DISABLE, 446 E_XC_OPTEE_TIMER_TEE_ENABLE, 447 E_XC_OPTEE_TIMER_TEE_RBASE_ABNORMAL, 448 E_XC_OPTEE_TIMER_TEE_CRASH, 449 }EN_XC_OPTEE_TIMER_STATUS; 450 451 typedef struct 452 { 453 MS_U32 u32DeviceID; 454 E_XC_INSTANT_TYPE eXCType; 455 } XC_INSTANT_ATTRIBUTE; 456 457 #define INIT_XC_INSTANT_ATTR(stXCInstantAttribute) \ 458 do {\ 459 memset(&(stXCInstantAttribute), 0, sizeof(stXCInstantAttribute)); \ 460 (stXCInstantAttribute).u32DeviceID = 0;\ 461 (stXCInstantAttribute).eXCType = E_XC_INSTANT_TYPE_XC;\ 462 } while(0) 463 464 ////===========================>>SW DB Buffer 465 typedef struct __attribute__((packed)) 466 { 467 MS_U16 u16H_CapStart; 468 MS_U16 u16H_CapSize; 469 MS_U16 u16V_CapStart; 470 MS_U16 u16V_CapSize; 471 472 MS_U16 u16H_DisStart; 473 MS_U16 u16H_DisEnd; 474 MS_U16 u16V_DisStart; 475 MS_U16 u16V_DisEnd; 476 477 MS_U32 u32H_PreScalingRatio; 478 MS_U32 u32V_PreScalingRatio; 479 MS_U32 u32H_PostScalingRatio; 480 MS_U32 u32V_PostScalingRatio; 481 482 MS_U16 u16VLen; 483 MS_U16 u16VWritelimit; 484 485 MS_U16 u16DNROffset; 486 MS_U16 u16DNRFetch; 487 MS_U16 u16OPMOffset; 488 MS_U16 u16OPMFetch; 489 MS_U16 u16LBOffset; 490 MS_U16 u16DispOffset; 491 MS_U16 u16AlignWidth; 492 493 MS_PHY u32WritelimitBase; 494 MS_PHY u32DNRBase0; 495 MS_PHY u32DNRBase1; 496 MS_PHY u32DNRBase2; 497 498 MS_PHY u32OPMBase0; 499 MS_PHY u32OPMBase1; 500 MS_PHY u32OPMBase2; 501 502 // add FRCM memory control 503 MS_PHY u32FRCM_WBase0; 504 MS_PHY u32FRCM_WBase1; 505 MS_PHY u32FRCM_WBase2; 506 MS_U16 u16FRCM_WOffset; 507 MS_U16 u16FRCM_WFetch; 508 509 MS_PHY u32FRCM_RBase0; 510 MS_PHY u32FRCM_RBase1; 511 MS_PHY u32FRCM_RBase2; 512 MS_U16 u16FRCM_ROffset; 513 MS_U16 u16FRCM_RFetch; 514 515 MS_PHY u32FRCMWritelimitBase; 516 MS_U16 u16VFRCMWritelimit; 517 MS_U16 u16FRCMVLen; 518 519 MS_U16 u16DualDNROffset; 520 MS_U16 u16DualDNRFetch; 521 MS_U16 u16DualOPMOffset; 522 MS_U16 u16DualOPMFetch; 523 MS_U16 u16DualLBOffset; 524 MS_U16 u16DualDispOffset; 525 MS_U16 u16DualAlignWidth; 526 527 MS_PHY u32DualWritelimitBase; 528 MS_PHY u32DualDNRBase0; 529 MS_PHY u32DualDNRBase1; 530 MS_PHY u32DualDNRBase2; 531 532 MS_PHY u32DualOPMBase0; 533 MS_PHY u32DualOPMBase1; 534 MS_PHY u32DualOPMBase2; 535 536 MS_BOOL bOpmLcntInv_En; 537 }SC_SWDB_INFO, *P_SC_SWDB_INFO; 538 539 typedef struct 540 { 541 // XC need below information do to frame lock 542 MS_U16 u16HStart; ///<DE H start 543 MS_U16 u16VStart; ///<DE V start 544 MS_U16 u16Width; ///<DE H width 545 MS_U16 u16Height; ///< DE V height 546 MS_U16 u16HTotal; ///<H total 547 MS_U16 u16VTotal; ///<V total 548 MS_U16 u16VFreq; ///<Panel output Vfreq 549 }XC_PANEL_TIMING, *PXC_PANEL_TIMING; 550 551 //xc BWR base addr 552 typedef struct 553 { 554 MS_PHY u32BWR_Miu_Left_DNRBase0; 555 MS_PHY u32BWR_Miu_Right_DNRBase0; 556 MS_PHY u32BWR_Miu_Left_DNRBase1; 557 MS_PHY u32BWR_Miu_Right_DNRBase1; 558 MS_PHY u32BWR_Miu_Left_OPMBase0; 559 MS_PHY u32BWR_Miu_Right_OPMBase0; 560 MS_PHY u32BWR_Miu_Left_OPMBase1; 561 MS_PHY u32BWR_Miu_Right_OPMBase1; 562 }XC_BWR_BaseAddr,*P_XC_BWR_BaseAddr; 563 564 //xc BWR memory map 565 typedef struct 566 { 567 MS_U16 u16BWR_MEM_CFG_VALUE; 568 E_XC_BWR_MEM_CFG_BPP_TYPE eBitPerPixelType; 569 }XC_BWR_MEM_CFG_MAP,*P_XC_BWR_MEM_CFG_MAP; 570 571 //xc dual mod cfg 572 typedef struct 573 { 574 MS_BOOL bEnableMiuDualMod; 575 MS_U32 u32LeftFactor; 576 MS_U32 u32RightFactor; 577 }XC_MIU_DualMod_Cfg,*P_XC_MIU_DualMod_Cfg; 578 579 580 typedef struct 581 { 582 //------------------------- 583 // customized pre scaling 584 //------------------------- 585 MS_BOOL bPreHCusScaling; ///<assign pre H customized scaling instead of using XC scaling 586 MS_U16 u16PreHCusScalingSrc; ///<pre H customized scaling src width 587 MS_U16 u16PreHCusScalingDst; ///<pre H customized scaling dst width 588 MS_BOOL bPreVCusScaling; ///<assign pre V manuel scaling instead of using XC scaling 589 MS_U16 u16PreVCusScalingSrc; ///<pre V customized scaling src height 590 MS_U16 u16PreVCusScalingDst; ///<pre V customized scaling dst height 591 592 MS_BOOL bAutoBestPreScaling; 593 594 //------------------------- 595 // memory format 596 //------------------------- 597 XC_FRAME_STORE_NUMBER eFrameStoreNumber; ///< the number of frame/field stored in frame bufffer 598 XC_FRAME_STORE_NUMBER eFRCMFrameStoreNumber; ///< the number of frame/field stored in frcm frame bufffer 599 600 MS_U16 u16LBOffset; ///<line buffer offset 601 MS_U16 u16OutputVFreqAfterFRC; 602 E_XC_SOURCE_TO_VE eSourceToVE; 603 XC_PANEL_TIMING stXCPanelDefaultTiming; 604 MS_BOOL bIPMemWriteRequestDisabled; 605 MirrorMode_t eMirrorMode; ///<For API to get current XC mirror type 606 XC_PANEL_INFO_EX stPanelInfoEx[PANEL_INFO_EX_NUM]; 607 MS_U8 u8IP_PixelRep; ///<For SC_ip set fir down sample divider 608 MS_BOOL bForceInterlaceInPMode; ///<Force InterlaceMode in IP1 when source is Progessive. 609 MS_BOOL bInFRCMode; 610 MS_BOOL bIsInitOSDC; 611 MS_XC_OSDC_TGEN_INFO stXCOSDCTIMING; 612 MS_XC_OSDC_CTRL_INFO stXCOSDC_CTRL; 613 MS_U16 u16OC_PreLplltype; 614 MS_U16 u16OC_Tgen_VTotal; 615 MS_U16 u16OC_Tgen_HTotal; 616 617 MS_U16 u16OP1_OutputVFreqAfterFRC; /// ***When FRC inside chip turn on the FRC featur, it will have XC_OP and FRC_OP 618 /// So, assign u16OP1_OutputVFreqAfterFRC for XC_OP 619 /// assign u16OutputVFreqAfterFRC for FRC_OP 620 /// ***But, non-FRC inside chip, this value will return u16OutputVFreqAfterFRC 621 622 //------------------------- 623 // SW DS 624 //------------------------- 625 MS_U16 u16VirtualBox_Width; 626 MS_U16 u16VirtualBox_Height; 627 628 //SUPPORT_BWD 629 //add BWR base addr control 630 XC_BWR_BaseAddr stBWRBase[BWR_BITPERPIX_CFG_NUM]; 631 //add BWR memory config map 632 XC_BWR_MEM_CFG_MAP stMemCfgMap[BWR_MEM_CFG_NUM]; 633 634 //UFO_XC_SUPPORT_DUAL_MIU 635 XC_MIU_DualMod_Cfg stMiuDualModCfg; 636 MS_PHY u32DualMiuDNRBase0; 637 MS_PHY u32DualMiuDNRBase1; 638 MS_PHY u32DualMiuDNRBase2; 639 MS_U16 u16DualMiuDNROffset; 640 MS_U16 u16DualMiuIPMFetch; 641 642 //CMA 643 MS_U32 u32PreCMAMemDualSCMSize; ///<CMA Dual SCM Size 644 MS_U8 u8CMADualHeapID; ///<CMA Dual Heap ID 645 MS_U8 u8PreCMADualHeapID; ///<CMA Dual Pre Heap ID 646 647 //MVOP/XC Handshake mode 648 MS_BOOL bMVOPHSKMode; 649 650 #ifdef UFO_XC_SET_DSINFO_V0 651 MS_U32 u32ApiDSInfo_Version; ///<Version of current structure. Please always set to "PANEL_INFO_EX_VERSION" as input 652 MS_U16 u16ApiDSInfo_Length; 653 //MVOP 654 MS_U32 u32MFCodecInfo; 655 XC_DS_HDRInfo stHDRInfo; 656 //XC 657 MS_BOOL bUpdate_DS_CMD; 658 MS_BOOL bEnableDNR; 659 #endif 660 661 //Scaler high accurate output Vfreq 662 MS_U32 u32HighAccurateOutputVFreqAfterFRC; 663 XC_CMA_CONFIG stXCConfigCMA[CMA_XC_MEM_NUM]; 664 } XC_InternalStatus2, *P_XC_InternalStatus2; 665 666 typedef struct 667 { 668 INPUT_SOURCE_TYPE_t enInputSourceType; ///< Input source type 669 MS_WINDOW_TYPE stDispWin; ///<Display window 670 } ST_XC_INTERNALSTATUS_NODELAY, *P_ST_XC_INTERNALSTATUS_NODELAY; 671 672 /// XC internal status 673 typedef struct __attribute__((packed)) 674 { 675 //---------------------- 676 // Customer setting 677 //---------------------- 678 INPUT_SOURCE_TYPE_t enInputSourceType; ///< Input source type 679 680 //---------------------- 681 // Window 682 //---------------------- 683 MS_WINDOW_TYPE stCapWin; ///<Capture window 684 MS_WINDOW_TYPE stDispWin; ///<Display window 685 MS_WINDOW_TYPE stCropWin; ///<Crop window 686 687 //---------------------- 688 // Timing 689 //---------------------- 690 MS_BOOL bInterlace; ///<Interlaced or Progressive 691 MS_BOOL bHDuplicate; ///<flag for vop horizontal duplicate, for MVD, YPbPr, indicate input double sampled or not 692 MS_U16 u16InputVFreq; ///<Input V Frequency, VFreqx10, for calculate output panel timing 693 MS_U16 u16InputVTotal; ///<Input Vertical total, for calculate output panel timing 694 MS_U16 u16DefaultHtotal; ///<Default Htotal for VGA/YPbPr input 695 MS_U16 u16DefaultPhase; ///<Default Phase for VGA/YPbPr input 696 697 698 699 //---------------------- 700 // customized post scaling 701 //---------------------- 702 MS_BOOL bHCusScaling; ///<assign H customized scaling instead of using XC scaling 703 MS_U16 u16HCusScalingSrc; ///<H customized scaling src width 704 MS_U16 u16HCusScalingDst; ///<H customized scaling dst width 705 MS_BOOL bVCusScaling; ///<assign V manuel scaling instead of using XC scaling 706 MS_U16 u16VCusScalingSrc; ///<V customized scaling src height 707 MS_U16 u16VCusScalingDst; ///<V customized scaling dst height 708 709 //-------------- 710 // 9 lattice 711 //-------------- 712 MS_BOOL bDisplayNineLattice; ///<used to indicate where to display in panel and where to put in frame buffer 713 714 //---------------------- 715 // XC internal setting 716 //---------------------- 717 718 /* scaling ratio */ 719 MS_U16 u16H_SizeAfterPreScaling; ///<Horizontal size after prescaling 720 MS_U16 u16V_SizeAfterPreScaling; ///<Vertical size after prescaling 721 MS_BOOL bPreV_ScalingDown; ///<define whether it's pre-Vertical scaling down 722 MS_BOOL bPreScalingRatioChanged; ///<True: PreScaling Ratio is different from with previous setWindow. False: PreScaling Ratio is same as previous one. 723 724 /* real crop win in memory */ 725 MS_WINDOW_TYPE ScaledCropWin; 726 727 /* others */ 728 MS_U32 u32Op2DclkSet; ///<OP to Dot clock set 729 730 /* Video screen status */ 731 MS_BOOL bBlackscreenEnabled; ///<Black screen status 732 MS_BOOL bBluescreenEnabled; ///<Blue screen status 733 MS_BOOL bAutoNoSignalEnabled; ///< Auto No signal enabled 734 MS_U16 u16VideoDark; ///<Video dark 735 736 MS_U16 u16V_Length; ///<for MDrv_Scaler_SetFetchNumberLimit(opm v lenth) 737 MS_U16 u16FRCMV_Length; ///<for MDrv_Scaler_SetFetchNumberLimit(FRCM v length) 738 MS_U16 u16BytePerWord; ///<BytePerWord in Scaler 739 MS_U16 u16OffsetPixelAlignment; ///<Pixel alignment of Offset (including IPM/OPM) 740 MS_U8 u8BitPerPixel; ///<Bits number Per Pixel 741 MS_DEINTERLACE_MODE eDeInterlaceMode; ///<De-interlace mode 742 MS_U8 u8DelayLines; ///<delay lines 743 MS_BOOL bMemFmt422; ///<whether memory format is 422, for easy usage 744 MS_IMAGE_STORE_FMT eMemory_FMT; ///<memory format 745 MS_BOOL bForceNRoff; ///<Force NR off 746 MS_BOOL bEn3DNR; ///<whether it's 3DNR enabled 747 MS_BOOL bUseYUVSpace; ///< color format before 3x3 matrix 748 MS_BOOL bMemYUVFmt; ///< memroy color format 749 MS_BOOL bForceRGBin; ///<Force set format in memory as RGB (only for RGB input source) 750 MS_BOOL bLinearMode; ///<Is current memory format LinearMode? 751 MS_BOOL bRWBankAuto; ///<accounding to framebuffer ,Auto adjust read/write bank mapping mode 752 753 // frame lock related 754 // only main can select FB/FBL because panel output timing depends on main window, sub will always use FB 755 MS_BOOL bFBL; ///<whether it's framebufferless case 756 MS_BOOL bR_FBL; ///<whether it's request framebufferless case, this variable is not reliable before load MADi mode. 757 MS_BOOL bFastFrameLock; ///<whether framelock is enabled or not 758 MS_BOOL bDoneFPLL; ///<whether the FPLL is done 759 MS_BOOL bEnableFPLL; ///<enable FPLL or not 760 MS_BOOL bFPLL_LOCK; ///<whether FPLL is locked (in specific threshold.) 761 762 // Capture_Memory 763 MS_PHY u32IPMBase0; ///<IPM base 0 764 MS_PHY u32IPMBase1; ///<IPM base 1 765 MS_PHY u32IPMBase2; ///<IPM base 2 766 MS_U16 u16IPMOffset; ///<IPM offset 767 MS_U16 u16IPMFetch; ///<IPM fetch 768 //CMA 769 MS_U32 u32PreCMAMemSCMSize[CMA_XC_MEM_NUM]; ///<CMA SCM Size 770 MS_U32 u32PreCMAMemFRCMSize[CMA_XC_MEM_NUM]; ///<CMA FRCM Size 771 MS_U8 u8CMAHeapID; ///<CMA Heap ID 772 MS_U8 u8PreCMAHeapID; ///<CMA Pre Heap ID 773 774 E_XC_STREAM_FLOW enPreStreamFlow; ///<memory scm->frcm or direct frcm 775 //------------------------------------------------------- 776 // To keep interface compatibility, please don't add any 777 // new members to XC_InternalStatus. 778 // Please add to XC_InternalStatus2. 779 //------------------------------------------------------- 780 XC_InternalStatus2 Status2; 781 ST_XC_INTERNALSTATUS_NODELAY stStatusnodelay; 782 #ifdef UFO_XC_FB_LEVEL 783 E_XC_FB_LEVEL eFBLevel; 784 #endif 785 }XC_InternalStatus, *P_XC_InternalStatus; 786 787 typedef struct __attribute__((packed)) 788 { 789 MS_U8 u8DIP_BufCnt; 790 MS_PHY u64DIP_YBuf[MAX_DIP_BUFF_CNT]; 791 MS_PHY u64DIP_CBuf[MAX_DIP_BUFF_CNT]; 792 } XC_DIP_BUFFER_INFO; 793 794 typedef enum 795 { 796 SCAN_AUTO = 0, 797 SCAN_PROGRESSIVE = SCAN_AUTO, 798 SCAN_INTERLACE = 1 799 }EN_VIDEO_SCAN_TYPE; 800 801 //SC 802 typedef struct __attribute__((packed)) 803 { 804 //---------------------- 805 // Customer setting 806 //---------------------- 807 INPUT_SOURCE_TYPE_t enInputSourceType; ///< Input source type 808 //---------------------- 809 // Source type for DIP 810 //---------------------- 811 SCALER_DIP_SOURCE_TYPE enDIPSourceType; ///<DIP input source type 812 //---------------------- 813 // Window 814 //---------------------- 815 MS_WINDOW_TYPE stCapWin; ///<Capture window 816 //---------------------- 817 // Timing 818 //---------------------- 819 MS_BOOL bInterlace; ///<Interlaced or Progressive 820 MS_BOOL bHDuplicate; ///<flag for vop horizontal duplicate, for MVD, YPbPr, indicate input double sampled or not 821 //---------------------- 822 // customized post scaling 823 //---------------------- 824 MS_BOOL bHCusScaling; ///<assign H customized scaling instead of using XC scaling 825 MS_U16 u16HCusScalingSrc; ///<H customized scaling src width 826 MS_U16 u16HCusScalingDst; ///<H customized scaling dst width 827 MS_BOOL bVCusScaling; ///<assign V manuel scaling instead of using XC scaling 828 MS_U16 u16VCusScalingSrc; ///<V customized scaling src height 829 MS_U16 u16VCusScalingDst; ///<V customized scaling dst height 830 //------------------------- 831 // customized pre scaling 832 //------------------------- 833 MS_BOOL bPreHCusScaling; ///<assign pre H customized scaling instead of using XC scaling 834 MS_U16 u16PreHCusScalingSrc; ///<pre H customized scaling src width 835 MS_U16 u16PreHCusScalingDst; ///<pre H customized scaling dst width 836 MS_BOOL bPreVCusScaling; ///<assign pre V manuel scaling instead of using XC scaling 837 MS_U16 u16PreVCusScalingSrc; ///<pre V customized scaling src height 838 MS_U16 u16PreVCusScalingDst; ///<pre V customized scaling dst height 839 //---------------------- 840 // XC internal setting 841 //---------------------- 842 /* scaling ratio */ 843 MS_U16 u16H_SizeAfterPreScaling; ///<Horizontal size after prescaling 844 MS_U16 u16V_SizeAfterPreScaling; ///<Vertical size after prescaling 845 846 MS_U8 u8DelayLines; ///<delay lines 847 MS_BOOL bMemFmt422; ///<whether memory format is 422, for easy usage 848 MS_BOOL bMemYUVFmt; ///< memroy color format 849 850 XC_DIP_BUFFER_INFO stBufInfo; 851 }XC_DIP_InternalStatus, *P_XC_DIP_InternalStatus; 852 853 typedef struct __attribute__((packed)) 854 { 855 MS_S32 s32MutexCnt; 856 MS_S32 s32CurThreadId; 857 MS_S32 s32ComMutex; 858 }XC_Mutex; 859 860 typedef struct __attribute__((packed)) 861 { 862 XC_InternalStatus StatusInfo[2]; 863 #ifndef UTOPIA_V2 864 XC_DIP_InternalStatus DIP_StatusInfo[3]; 865 #endif 866 }XC_Context_Shared; 867 868 typedef struct __attribute__((packed)) 869 { 870 XC_Mutex Mutex; 871 872 // FPLL related 873 MS_BOOL bEnableFPLLManualDebug; ///< if enabled, no set to phase limit, limitD5D6D7RK 874 }XC_Context; 875 876 typedef struct 877 { 878 MS_BOOL bTop; 879 MS_BOOL bBottom; 880 MS_BOOL bLeft; 881 MS_BOOL bRight; 882 MS_U8 u8TopBold; //0~3 883 MS_U8 u8BottomBold; //0~3 884 MS_U8 u8LeftBold; //0~3 885 MS_U8 u8RightBold; //0~3 886 } XC_OP1_PatGen_Border; 887 888 // Path 889 typedef struct __attribute__((packed)) s_Data_Path 890 { 891 892 ////////////////////////////// 893 // Path Type 894 ////////////////////////////// 895 E_PATH_TYPE e_PathType; 896 897 ////////////////////////////// 898 // Path Status 899 ////////////////////////////// 900 901 /* 902 Make the signal go through the path. If this flag is not enabled, 903 synchronous_event_handler and source_monitor are useless. 904 */ 905 #define DATA_PATH_ENABLE BIT(0) 906 907 /* 908 Used to identify a path is created or not. ( 1: path created ) 909 */ 910 #define DATA_PATH_USING BIT(1) 911 912 /* 913 Used to identify the priodic handler enabled or disabled 914 */ 915 #define ENABLE_PERIODIC_HANDLER BIT(2) 916 917 MS_U8 u8PathStatus; 918 919 ////////////////////////////// 920 // A path has a format like Src -> Dest 921 ////////////////////////////// 922 INPUT_SOURCE_TYPE_t src; 923 E_DEST_TYPE dest; 924 925 ////////////////////////////// 926 // thread for source. 927 ////////////////////////////// 928 void (*path_thread)(INPUT_SOURCE_TYPE_t src, MS_BOOL bRealTimeMonitorOnly); 929 #if !defined (__aarch64__) 930 MS_U32 u32AlignmentDummy0; 931 #endif 932 /////////////////////////////////////// 933 // Customize function. 934 // This will be executed automatically when synchronous event triggered. 935 /////////////////////////////////////// 936 void (* synchronous_event_handler )(INPUT_SOURCE_TYPE_t src, void* para); 937 #if !defined (__aarch64__) 938 MS_U32 u32AlignmentDummy1; 939 #endif 940 /////////////////////////////////////// 941 // Customize function. 942 // This will be executed automatically when destination on/off event triggered. 943 /////////////////////////////////////// 944 void (* dest_on_off_event_handler )(INPUT_SOURCE_TYPE_t src, void* para); 945 #if !defined (__aarch64__) 946 MS_U32 u32AlignmentDummy2; 947 #endif 948 /////////////////////////////////////// 949 // Customize function. 950 // This will be executed periodically after enabled destinatio period handler 951 /////////////////////////////////////// 952 void (* dest_periodic_handler )(INPUT_SOURCE_TYPE_t src, MS_BOOL bRealTimeMonitorOnly); 953 #if !defined (__aarch64__) 954 MS_U32 u32AlignmentDummy3; 955 #endif 956 }MUX_DATA_PATH; 957 958 959 // Path Collection 960 typedef struct __attribute__((packed)) s_Mux_InputSource_Attr 961 { 962 // The number of pathes which is used right now. 963 MS_U8 u8PathCount; 964 965 void (*input_source_to_input_port)(INPUT_SOURCE_TYPE_t src_ids , E_MUX_INPUTPORT* port_ids , MS_U8* u8port_count ); 966 #if !defined (__aarch64__) 967 MS_U32 u32AlignmentDummy; 968 #endif 969 970 // Pathes. 971 // Path array in MAPP_MUX is constructed [Sync path, Sync path, ..., Async path, Async path] 972 MUX_DATA_PATH Mux_DataPaths[MAX_DATA_PATH_SUPPORTED]; 973 974 // indicate how many times the src created 975 MS_U16 u16SrcCreateTime[INPUT_SOURCE_NUM]; 976 }InputSource_Mux_Attr; 977 978 #if (XC_CONTEXT_ENABLE) 979 #define gSrcInfo (pXCResourcePrivate->stdrvXC_MVideo._SCShared.StatusInfo) 980 #define gSrcInfo_1 (pXCResourcePrivate_1->stdrvXC_MVideo._SCShared.StatusInfo) 981 #ifndef UTOPIA_V2 982 #define g_DIPSrcInfo (pXCResourcePrivate->stdrvXC_MVideo._SCShared.DIP_StatusInfo) 983 #endif 984 #else 985 INTERFACE XC_InternalStatus gSrcInfo[2]; 986 INTERFACE XC_InternalStatus gSrcInfo_1[2]; 987 #ifndef UTOPIA_V2 988 INTERFACE XC_DIP_InternalStatus g_DIPSrcInfo[3]; 989 #endif 990 #endif 991 992 #define IsVMirrorMode(eWindow) ((MIRROR_V_ONLY == gSrcInfo[(eWindow)].Status2.eMirrorMode) || (MIRROR_HV == gSrcInfo[(eWindow)].Status2.eMirrorMode)) 993 #define IsHMirrorMode(eWindow) ((MIRROR_H_ONLY == gSrcInfo[(eWindow)].Status2.eMirrorMode) || (MIRROR_HV == gSrcInfo[(eWindow)].Status2.eMirrorMode)) 994 #define IS_4K2K_MODE(width, height) (((width) >= XC_4K2K_WIDTH_MIN) && ((height) >= XC_4K2K_HIGH_MIN)) 995 #define IS_4K1K_MODE(width, height) (((width) >= XC_4K2K_WIDTH_MIN) && ((height) >= XC_4K1K_HIGH_MIN) && ((height) < XC_4K2K_HIGH_MIN)) 996 #define IS_2K2K_MODE(width, height) (((width) >= XC_2K2K_WIDTH_MIN)&&((height) >= XC_2K2K_HIGH_MIN)) 997 #define IS_INPUT_4K2K(eWindow) ((gSrcInfo[eWindow].stCapWin.width > 3000) && (gSrcInfo[eWindow].stCapWin.height> 2000)) 998 #define IS_INPUT_4K1K(eWindow) ((gSrcInfo[eWindow].stCapWin.width > 3000) && (gSrcInfo[eWindow].stCapWin.height> 1050)) 999 #define IS_INPUT_2K2K(eWindow) ((gSrcInfo[eWindow].stCapWin.width>=XC_2K2K_WIDTH_MIN)&&(gSrcInfo[eWindow].stCapWin.height>=XC_2K2K_HIGH_MIN)) 1000 #define IS_OUTPUT_4K2K(width, height) (((width) >= XC_4K2K_WIDTH_MIN) && ((height) >= XC_4K2K_HIGH_MIN)) 1001 #define IS_OUTPUT_FHD(width, height) (((width) >= XC_FHD_WIDTH_MIN) && ((width) <= XC_FHD_WIDTH_MAX) && ((height) >= XC_FHD_HIGH_MIN) && ((height) <= XC_FHD_HIGH_MAX)) 1002 #define IS_OUTPUT_720(width, height) (((width) >= XC_720_WIDTH_MIN) && ((width) <= XC_720_WIDTH_MAX) && ((height) >= XC_720_HIGH_MIN) && ((height) <= XC_720_HIGH_MAX)) 1003 #define IS_OUTPUT_576(width, height) (((width) >= XC_576_WIDTH_MIN) && ((width) <= XC_576_WIDTH_MAX) && ((height) >= XC_576_HIGH_MIN) && ((height) <= XC_576_HIGH_MAX)) 1004 #define IS_OUTPUT_480(width, height) (((width) >= XC_480_WIDTH_MIN) && ((width) <= XC_480_WIDTH_MAX) && ((height) >= XC_480_HIGH_MIN) && ((height) <= XC_480_HIGH_MAX)) 1005 1006 #define IS_OUTPUT_4K1K(width, height) (((width) >= XC_4K2K_WIDTH_MIN) && ((height) >= XC_FHD_HIGH_MIN) && ((height) <= XC_FHD_HIGH_MAX)) 1007 #define IS_OUTPUT_4K0_5K(width, height) (((width) >= XC_4K2K_WIDTH_MIN) && ((height) >= XC_4K_HALFK_HIGH_MIN) && ((height) <= XC_4K_HALFK_HIGH_MAX)) 1008 #define IS_OUTPUT_FP1080P(width, height) (((width) == XC_FP1080P_H_SIZE) && ((height) == XC_FP1080P_V_SIZE)) 1009 #define IS_DS_FHD(eWindow) ((gSrcInfo[eWindow].stCropWin.width <= 1920) &&(gSrcInfo[eWindow].stCropWin.height <= 1080)) 1010 #define IS_DS_4K2K(eWindow) ((gSrcInfo[eWindow].stCapWin.width > 3000) && (gSrcInfo[eWindow].stCapWin.height> 2000) && (gSrcInfo[eWindow].stCropWin.width > 3000) &&(gSrcInfo[eWindow].stCropWin.height> 1600)) 1011 //Real 4K2K size when IS_DS_4K2K() is true 1012 //4K2K zoom2 (w,h)=(3072,1644) 1013 #ifdef XC_DUAL_MIU_SUPPORT_SUB_WINDOW 1014 #define IsEnableDualMode(eWindow) (gSrcInfo[eWindow].Status2.stMiuDualModCfg.bEnableMiuDualMod == TRUE) 1015 #else 1016 #define IsEnableDualMode(eWindow) ((eWindow == MAIN_WINDOW) && (gSrcInfo[eWindow].Status2.stMiuDualModCfg.bEnableMiuDualMod == TRUE)) 1017 #endif 1018 // for Fast Boot 1019 #define HDCP_KEY_LENGTH 289 1020 #define EDID_KEY_LENGTH 256 1021 1022 INTERFACE MS_U16 _u16XCDbgSwitch_InternalUseOnly; 1023 // for Utopia 2.0 to Utopia 1.0 compatibility. 1024 INTERFACE void* pu32XCInst; 1025 INTERFACE void* pu32XCInst_private; 1026 INTERFACE void* pu32XCInst_1_private; 1027 //K3_U2 move to EX later 1028 INTERFACE void* pu32XCInst_1; 1029 INTERFACE void* g_pXCResource[E_XC_POOL_ID_MAX]; 1030 //EX_ADD 1031 INTERFACE MS_BOOL g_bIsIMMESWITCH; 1032 INTERFACE MS_BOOL g_bDVI_AUTO_EQ; 1033 INTERFACE MS_BOOL g_bIMMESWITCH_DVI_POWERSAVING; 1034 1035 INTERFACE MS_BOOL g_bSWDSGenScenario; 1036 INTERFACE XC_DS_CMDCNT PSTXC_DS_CMDCNT; 1037 1038 #if (defined (ANDROID)) 1039 #define CHECK_XC_SWDS_ENABLE_START \ 1040 ( {\ 1041 if(!g_bSWDSGenScenario) \ 1042 { 1043 1044 #define CHECK_XC_SWDS_ENABLE_END \ 1045 ;} \ 1046 } ) 1047 1048 #define CHECK_XC_SWDS_ENABLE \ 1049 {\ 1050 if(g_bSWDSGenScenario) \ 1051 {\ 1052 return TRUE; \ 1053 } \ 1054 } 1055 #else 1056 #define CHECK_XC_SWDS_ENABLE_START 1057 #define CHECK_XC_SWDS_ENABLE_END 1058 #define CHECK_XC_SWDS_ENABLE 1059 #endif 1060 1061 #ifndef DONT_USE_CMA 1062 #if (XC_SUPPORT_CMA ==TRUE) 1063 //CMA 1064 #ifdef UFO_XC_SUPPORT_SUB_CMA 1065 INTERFACE struct CMA_Pool_Init_Param CMA_Pool_Init_PARAM[MAX_WINDOW][CMA_XC_MEM_NUM]; 1066 #else 1067 INTERFACE struct CMA_Pool_Init_Param CMA_Pool_Init_PARAM[CMA_XC_MEM_NUM]; 1068 #endif 1069 1070 INTERFACE MS_BOOL bNeedDeattachCMAISR; 1071 #if (HW_DESIGN_4K2K_VER == 6) 1072 #define XC_DUAL_MIU_HID 19 //Cobuffer with Vdec, need put memory when 1073 #else 1074 #define XC_DUAL_MIU_HID 20 1075 #endif 1076 #endif 1077 #endif 1078 1079 INTERFACE void MDrv_XC_ShowTrace_Header(MS_U16 u16LogSwitch); //NO_NEED 1080 1081 INTERFACE void mvideo_sc_variable_init(void *pInstance, MS_BOOL bFirstInstance, XC_INITDATA *pXC_InitData); 1082 INTERFACE void mvideo_sc_getcropwin( void *pInstance, MS_WINDOW_TYPE *pCropWin, SCALER_WIN eWindow ); 1083 INTERFACE MS_U8 mvideo_pnl_is_dualport(void *pInstance); 1084 INTERFACE void mvideo_pnl_set_dclkmode(void *pInstance, E_XC_PNL_OUT_TIMING_MODE enPnl_Out_Timing_Mode); 1085 1086 INTERFACE MS_BOOL mvideo_sc_is_enable_3dnr(void *pInstance, SCALER_WIN eWindow); 1087 INTERFACE void mvideo_sc_set_3dnr(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow); 1088 1089 INTERFACE void MDrv_XC_GetInfo(void *pInstance, XC_ApiInfo *pXC_Info); 1090 INTERFACE void MDrv_XC_SetHdmiSyncMode(void *pInstance, E_HDMI_SYNC_TYPE eSynctype); 1091 INTERFACE void MDrv_XC_Switch_DE_HV_Mode_By_Timing(void *pInstance, SCALER_WIN eWindow); 1092 INTERFACE void MDrv_XC_Set_DE_Lock_Mode(void *pInstance, SCALER_WIN eWindow); 1093 1094 //DLC 1095 INTERFACE void MDrv_DLC_Handler(MS_BOOL bWindow); 1096 INTERFACE MS_BOOL MDrv_DLC_GetHistogram(MS_BOOL bWindow); 1097 INTERFACE MS_U8 MDrv_DLC_GetAverageValue(void); 1098 1099 INTERFACE MS_BOOL MDrv_XC_PCMonitor_GetDEWidthHeightInDEByPassMode(void* pInstance, MS_U16* pu16Width, MS_U16* pu16Height, SCALER_WIN eWindow); 1100 1101 INTERFACE MS_BOOL MDrv_XC_Get_SCMI_Type(void); //NO_NEED 1102 1103 INTERFACE E_APIXC_ReturnValue MDrv_XC_OSDC_Control(void *pInstance, MS_U32 eCtrl_type); 1104 1105 //------------------------------------------------------------------------------------------------- 1106 /// MDrv_XC_OSDC_TGEN_Setting 1107 /// @param pstOC_Tgen \b IN: the timing control 1108 //------------------------------------------------------------------------------------------------- 1109 INTERFACE void MDrv_XC_OSDC_TGEN_Setting(void *pInstance, MS_XC_OSDC_TGEN_INFO *pstOC_Tgen); 1110 1111 //------------------------------------------------------------------------------------------------- 1112 /// MDrv_XC_OSDC_MISC_Control 1113 /// @param pstOC_Ctrl \b IN: the OSDC MISC control 1114 //------------------------------------------------------------------------------------------------- 1115 INTERFACE void MDrv_XC_OSDC_MISC_Control(void *pInstance, MS_XC_OSDC_CTRL_INFO *pstOC_Ctrl); 1116 1117 //------------------------------------------------------------------------------------------------- 1118 /// MDrv_XC_OSDC_GetDataFromRegister 1119 /// @param pstOC_Tgen \b IN: the timing control 1120 /// @param pstOC_Ctrl \b IN: the OSDC MISC control 1121 /// @return @ref MS_BOOL 1122 //------------------------------------------------------------------------------------------------- 1123 INTERFACE MS_BOOL MDrv_XC_OSDC_GetDataFromRegister(void *pInstance, MS_XC_OSDC_TGEN_INFO *pstOC_Tgen, MS_XC_OSDC_CTRL_INFO *pstOC_Ctrl); 1124 1125 INTERFACE void MDrv_XC_OSDC_TGENRST_EN(void *pInstance, MS_BOOL bEnable); 1126 INTERFACE void MDrv_XC_OSDC_SWRST_EN(void *pInstance, MS_BOOL bEnable); 1127 1128 INTERFACE E_APIXC_ReturnValue MDrv_XC_GetChipCaps(void *pInstance, E_XC_CAPS eCapType, MS_U32* pRet, MS_U32 ret_size); 1129 INTERFACE void MDrv_XC_FreezeImg(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow); 1130 1131 INTERFACE void MDrv_XC_SetDeviceOffset(void *pInstance); 1132 1133 #ifndef DISABLE_HW_PATTERN_FUNCTION 1134 #ifdef SUPPORT_HW_TESTPATTERN 1135 // For HW internal test pattern using 1136 INTERFACE MS_BOOL MDrv_SC_OP1_PatGen_Init(void *pInstance, EN_XC_OP1_PATGEN_MODE mode); 1137 INTERFACE E_APIXC_ReturnValue MDrv_SC_Set_OP1_TestPattern(void *pInstance, EN_XC_OP1_PATTERN pattern, EN_XC_OP1_PATGEN_MODE mode); 1138 INTERFACE MS_BOOL MDrv_SC_OP1_PatGen_Disable(void *pInstance); 1139 INTERFACE void MDrv_SC_OP1_Align_Width_Height(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt, MS_U16 *u16AlignWidth, MS_U16 *u16AlignHeight); 1140 INTERFACE void MDrv_SC_OP1_HW_Default_Pattern(void *pInstance, MS_U8 u8Val); 1141 INTERFACE void MDrv_SC_OP1_WB_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1142 INTERFACE void MDrv_SC_OP1_Pure_Color_V_Bar_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1143 INTERFACE void MDrv_SC_OP1_Pure_Color_H_Bar_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1144 INTERFACE void MDrv_SC_OP1_Pure_Gray_Bar_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt, MS_U8 block_Size, MS_U8 repeat_Num, MS_U8 level); 1145 INTERFACE void MDrv_SC_OP1_Pure_RGB_32_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt, MS_U8 block_Size,MS_U8 repeat_Num,MS_U8 level); 1146 INTERFACE void MDrv_SC_OP1_Pure_RGB_Checkerboard_Pattern_GBChange(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1147 INTERFACE void MDrv_SC_OP1_Dotfade_Gray_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1148 INTERFACE void MDrv_SC_OP1_Calibratoin_Color_Dotfade_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1149 INTERFACE void MDrv_SC_OP1_1_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1150 INTERFACE void MDrv_SC_OP1_2_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1151 INTERFACE void MDrv_SC_OP1_3_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1152 INTERFACE void MDrv_SC_OP1_3D_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt); 1153 INTERFACE void MDrv_SC_OP1_Pure_Color_Tile_Pattern(void *pInstance, MS_U16 u16HTileCnt, MS_U16 u16VTileCnt, MS_U16 u16RVal, MS_U16 u16GVal, MS_U16 u16BVal); 1154 #endif 1155 #endif 1156 1157 INTERFACE E_HDMI_SYNC_TYPE MDrv_XC_GetHdmiSyncMode(void *pInstance); 1158 INTERFACE MS_BOOL MDrv_XC_IsCurrentRequest_FrameBufferLessMode(void *pInstance); 1159 INTERFACE MS_BOOL MDrv_XC_IsCurrentFrameBufferLessMode(void *pInstance); 1160 INTERFACE MS_BOOL MDrv_XC_GetStatus(void *pInstance, XC_ApiStatus *pDrvStatus, SCALER_WIN eWindow); 1161 INTERFACE MirrorMode_t MDrv_XC_GetMirrorModeTypeEx(void *pInstance, SCALER_WIN eWindow); 1162 INTERFACE MS_U32 MDrv_XC_Get_Semaphore(void *pInstance,E_XC_POOL_ID_TYPE eID_TYPE); 1163 INTERFACE MS_U32 MDrv_XC_Release_Semaphore(void *pInstance,E_XC_POOL_ID_TYPE eID_TYPE); 1164 INTERFACE E_XC_POOL_ID MDrv_XC_Resource_Mapping(MS_U32 u32InstanceID, E_XC_POOL_ID eID); 1165 INTERFACE E_APIXC_ReturnValue MDrv_XC_Init_MISC(void *pInstance, XC_INITMISC *pXC_Init_Misc, MS_U32 u32InitMiscDataLen); 1166 INTERFACE void MDrv_XC_Set_VOP(void *pInstance, MS_XC_VOP_Data *pstVOPData); 1167 INTERFACE void msAPI_Scaler_Field_Detect(void *pInstance, INPUT_SOURCE_TYPE_t enInputSrcType, EN_VIDEO_SCAN_TYPE enScanType, SCALER_WIN eWindow); 1168 INTERFACE MS_BOOL MDrv_XC_IsSupportPipPatchUsingSc1MainAsSc0Sub(void); 1169 1170 1171 #undef INTERFACE 1172 #endif /* MVIDEO_CONTEXT_H */ 1173 1174