1 /**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
10 * to uboot.
11 *
12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
13 *
14 * SPDX-License-Identifier: GPL-2.0
15 */
16
17 #include <common.h>
18 #include <malloc.h>
19 #include <fdtdec.h>
20 #include <dwc3-uboot.h>
21 #include <asm/dma-mapping.h>
22 #include <linux/ioport.h>
23 #include <dm.h>
24 #include <generic-phy.h>
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27
28 #include "core.h"
29 #include "gadget.h"
30 #include "io.h"
31
32 #include "linux-compat.h"
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 static LIST_HEAD(dwc3_list);
37 /* -------------------------------------------------------------------------- */
38
dwc3_set_mode(struct dwc3 * dwc,u32 mode)39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
40 {
41 u32 reg;
42
43 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
44 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
45 reg |= DWC3_GCTL_PRTCAPDIR(mode);
46 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
47 }
48
49 /**
50 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
51 * @dwc: pointer to our context structure
52 */
dwc3_core_soft_reset(struct dwc3 * dwc)53 static int dwc3_core_soft_reset(struct dwc3 *dwc)
54 {
55 u32 reg;
56
57 /* Before Resetting PHY, put Core in Reset */
58 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
59 reg |= DWC3_GCTL_CORESOFTRESET;
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
61
62 /* Assert USB3 PHY reset */
63 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
64 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
66
67 /* Assert USB2 PHY reset */
68 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
69 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
70 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
71
72 mdelay(100);
73
74 /* Clear USB3 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
76 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
78
79 /* Clear USB2 PHY reset */
80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
81 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
83
84 mdelay(100);
85
86 /* After PHYs are stable we can take Core out of reset state */
87 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
88 reg &= ~DWC3_GCTL_CORESOFTRESET;
89 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
90
91 return 0;
92 }
93
94 /**
95 * dwc3_free_one_event_buffer - Frees one event buffer
96 * @dwc: Pointer to our controller context structure
97 * @evt: Pointer to event buffer to be freed
98 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
100 struct dwc3_event_buffer *evt)
101 {
102 dma_free_coherent(evt->buf);
103 }
104
105 /**
106 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
107 * @dwc: Pointer to our controller context structure
108 * @length: size of the event buffer
109 *
110 * Returns a pointer to the allocated event buffer structure on success
111 * otherwise ERR_PTR(errno).
112 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
114 unsigned length)
115 {
116 struct dwc3_event_buffer *evt;
117
118 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
119 GFP_KERNEL);
120 if (!evt)
121 return ERR_PTR(-ENOMEM);
122
123 evt->dwc = dwc;
124 evt->length = length;
125 evt->buf = dma_alloc_coherent(length,
126 (unsigned long *)&evt->dma);
127 if (!evt->buf)
128 return ERR_PTR(-ENOMEM);
129
130 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
131
132 return evt;
133 }
134
135 /**
136 * dwc3_free_event_buffers - frees all allocated event buffers
137 * @dwc: Pointer to our controller context structure
138 */
dwc3_free_event_buffers(struct dwc3 * dwc)139 static void dwc3_free_event_buffers(struct dwc3 *dwc)
140 {
141 struct dwc3_event_buffer *evt;
142 int i;
143
144 for (i = 0; i < dwc->num_event_buffers; i++) {
145 evt = dwc->ev_buffs[i];
146 if (evt)
147 dwc3_free_one_event_buffer(dwc, evt);
148 }
149 }
150
151 /**
152 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
153 * @dwc: pointer to our controller context structure
154 * @length: size of event buffer
155 *
156 * Returns 0 on success otherwise negative errno. In the error case, dwc
157 * may contain some buffers allocated but not all which were requested.
158 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
160 {
161 int num;
162 int i;
163
164 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
165 dwc->num_event_buffers = num;
166
167 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
168 sizeof(*dwc->ev_buffs) * num);
169 if (!dwc->ev_buffs)
170 return -ENOMEM;
171
172 for (i = 0; i < num; i++) {
173 struct dwc3_event_buffer *evt;
174
175 evt = dwc3_alloc_one_event_buffer(dwc, length);
176 if (IS_ERR(evt)) {
177 dev_err(dwc->dev, "can't allocate event buffer\n");
178 return PTR_ERR(evt);
179 }
180 dwc->ev_buffs[i] = evt;
181 }
182
183 return 0;
184 }
185
186 /**
187 * dwc3_event_buffers_setup - setup our allocated event buffers
188 * @dwc: pointer to our controller context structure
189 *
190 * Returns 0 on success otherwise negative errno.
191 */
dwc3_event_buffers_setup(struct dwc3 * dwc)192 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
193 {
194 struct dwc3_event_buffer *evt;
195 int n;
196
197 for (n = 0; n < dwc->num_event_buffers; n++) {
198 evt = dwc->ev_buffs[n];
199 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
200 evt->buf, (unsigned long long) evt->dma,
201 evt->length);
202
203 evt->lpos = 0;
204
205 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
206 lower_32_bits(evt->dma));
207 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
208 upper_32_bits(evt->dma));
209 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
210 DWC3_GEVNTSIZ_SIZE(evt->length));
211 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
212 }
213
214 return 0;
215 }
216
dwc3_event_buffers_cleanup(struct dwc3 * dwc)217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
218 {
219 struct dwc3_event_buffer *evt;
220 int n;
221
222 for (n = 0; n < dwc->num_event_buffers; n++) {
223 evt = dwc->ev_buffs[n];
224
225 evt->lpos = 0;
226
227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
228 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
229 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
230 | DWC3_GEVNTSIZ_SIZE(0));
231 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
232 }
233 }
234
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
236 {
237 if (!dwc->has_hibernation)
238 return 0;
239
240 if (!dwc->nr_scratch)
241 return 0;
242
243 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
244 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
245 if (!dwc->scratchbuf)
246 return -ENOMEM;
247
248 return 0;
249 }
250
dwc3_setup_scratch_buffers(struct dwc3 * dwc)251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
252 {
253 dma_addr_t scratch_addr;
254 u32 param;
255 int ret;
256
257 if (!dwc->has_hibernation)
258 return 0;
259
260 if (!dwc->nr_scratch)
261 return 0;
262
263 scratch_addr = dma_map_single(dwc->scratchbuf,
264 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
265 DMA_BIDIRECTIONAL);
266 if (dma_mapping_error(dwc->dev, scratch_addr)) {
267 dev_err(dwc->dev, "failed to map scratch buffer\n");
268 ret = -EFAULT;
269 goto err0;
270 }
271
272 dwc->scratch_addr = scratch_addr;
273
274 param = lower_32_bits(scratch_addr);
275
276 ret = dwc3_send_gadget_generic_command(dwc,
277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
278 if (ret < 0)
279 goto err1;
280
281 param = upper_32_bits(scratch_addr);
282
283 ret = dwc3_send_gadget_generic_command(dwc,
284 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
285 if (ret < 0)
286 goto err1;
287
288 return 0;
289
290 err1:
291 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
292 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
293
294 err0:
295 return ret;
296 }
297
dwc3_free_scratch_buffers(struct dwc3 * dwc)298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
299 {
300 if (!dwc->has_hibernation)
301 return;
302
303 if (!dwc->nr_scratch)
304 return;
305
306 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
307 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
308 kfree(dwc->scratchbuf);
309 }
310
dwc3_core_num_eps(struct dwc3 * dwc)311 static void dwc3_core_num_eps(struct dwc3 *dwc)
312 {
313 struct dwc3_hwparams *parms = &dwc->hwparams;
314
315 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
316 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
317
318 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
319 dwc->num_in_eps, dwc->num_out_eps);
320 }
321
dwc3_cache_hwparams(struct dwc3 * dwc)322 static void dwc3_cache_hwparams(struct dwc3 *dwc)
323 {
324 struct dwc3_hwparams *parms = &dwc->hwparams;
325
326 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
327 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
328 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
329 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
330 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
331 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
332 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
333 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
334 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
335 }
336
dwc3_hsphy_mode_setup(struct dwc3 * dwc)337 static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
338 {
339 enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
340 u32 reg;
341
342 /* Set dwc3 usb2 phy config */
343 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
344
345 switch (hsphy_mode) {
346 case USBPHY_INTERFACE_MODE_UTMI:
347 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
348 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
349 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
350 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
351 break;
352 case USBPHY_INTERFACE_MODE_UTMIW:
353 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
354 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
355 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
356 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
357 break;
358 default:
359 break;
360 }
361
362 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
363 }
364
365 /**
366 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
367 * @dwc: Pointer to our controller context structure
368 */
dwc3_phy_setup(struct dwc3 * dwc)369 static void dwc3_phy_setup(struct dwc3 *dwc)
370 {
371 u32 reg;
372
373 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
374
375 /*
376 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
377 * to '0' during coreConsultant configuration. So default value
378 * will be '0' when the core is reset. Application needs to set it
379 * to '1' after the core initialization is completed.
380 */
381 if (dwc->revision > DWC3_REVISION_194A)
382 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
383
384 if (dwc->u2ss_inp3_quirk)
385 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
386
387 if (dwc->req_p1p2p3_quirk)
388 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
389
390 if (dwc->del_p1p2p3_quirk)
391 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
392
393 if (dwc->del_phy_power_chg_quirk)
394 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
395
396 if (dwc->lfps_filter_quirk)
397 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
398
399 if (dwc->rx_detect_poll_quirk)
400 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
401
402 if (dwc->tx_de_emphasis_quirk)
403 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
404
405 /*
406 * For some Rokchip SoCs like RK3588, if the USB3 PHY is suspended
407 * in U-Boot would cause the PHY initialize abortively in Linux Kernel,
408 * so disable the DWC3_GUSB3PIPECTL_SUSPHY feature here to fix it.
409 */
410 if (dwc->dis_u3_susphy_quirk || CONFIG_IS_ENABLED(ARCH_ROCKCHIP))
411 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
412
413 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
414
415 dwc3_hsphy_mode_setup(dwc);
416
417 mdelay(100);
418
419 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
420
421 /*
422 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
423 * '0' during coreConsultant configuration. So default value will
424 * be '0' when the core is reset. Application needs to set it to
425 * '1' after the core initialization is completed.
426 */
427 if (dwc->revision > DWC3_REVISION_194A)
428 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
429
430 if (dwc->dis_u2_susphy_quirk)
431 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
432
433 if (dwc->dis_enblslpm_quirk)
434 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
435
436 if (dwc->dis_u2_freeclk_exists_quirk)
437 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
438
439 if (dwc->usb2_phyif_utmi_width == 16) {
440 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
441 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
442 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
443 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT);
444 }
445 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
446
447 mdelay(100);
448 }
449
450 /**
451 * dwc3_core_init - Low-level initialization of DWC3 Core
452 * @dwc: Pointer to our controller context structure
453 *
454 * Returns 0 on success otherwise negative errno.
455 */
dwc3_core_init(struct dwc3 * dwc)456 static int dwc3_core_init(struct dwc3 *dwc)
457 {
458 unsigned long timeout;
459 u32 hwparams4 = dwc->hwparams.hwparams4;
460 u32 reg;
461 int ret;
462
463 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
464 /* This should read as U3 followed by revision number */
465 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
466 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
467 ret = -ENODEV;
468 goto err0;
469 }
470 dwc->revision = reg;
471
472 /* Handle USB2.0-only core configuration */
473 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
474 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
475 if (dwc->maximum_speed == USB_SPEED_SUPER)
476 dwc->maximum_speed = USB_SPEED_HIGH;
477 }
478
479 /* issue device SoftReset too */
480 timeout = 5000;
481 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
482 while (timeout--) {
483 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
484 if (!(reg & DWC3_DCTL_CSFTRST))
485 break;
486 };
487
488 if (!timeout) {
489 dev_err(dwc->dev, "Reset Timed Out\n");
490 ret = -ETIMEDOUT;
491 goto err0;
492 }
493
494 ret = dwc3_core_soft_reset(dwc);
495 if (ret)
496 goto err0;
497
498 if (dwc->revision >= DWC3_REVISION_250A) {
499 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
500
501 if (dwc->maximum_speed == USB_SPEED_HIGH ||
502 dwc->maximum_speed == USB_SPEED_FULL)
503 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
504
505 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
506 }
507
508 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
509 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
510
511 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
512 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
513 /**
514 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
515 * issue which would cause xHCI compliance tests to fail.
516 *
517 * Because of that we cannot enable clock gating on such
518 * configurations.
519 *
520 * Refers to:
521 *
522 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
523 * SOF/ITP Mode Used
524 */
525 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
526 dwc->dr_mode == USB_DR_MODE_OTG) &&
527 (dwc->revision >= DWC3_REVISION_210A &&
528 dwc->revision <= DWC3_REVISION_250A))
529 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
530 else
531 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
532 break;
533 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
534 /* enable hibernation here */
535 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
536
537 /*
538 * REVISIT Enabling this bit so that host-mode hibernation
539 * will work. Device-mode hibernation is not yet implemented.
540 */
541 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
542 break;
543 default:
544 dev_dbg(dwc->dev, "No power optimization available\n");
545 }
546
547 /* check if current dwc3 is on simulation board */
548 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
549 dev_dbg(dwc->dev, "it is on FPGA board\n");
550 dwc->is_fpga = true;
551 }
552
553 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
554 WARN(true,
555 "disable_scramble cannot be used on non-FPGA builds\n");
556
557 if (dwc->disable_scramble_quirk && dwc->is_fpga)
558 reg |= DWC3_GCTL_DISSCRAMBLE;
559 else
560 reg &= ~DWC3_GCTL_DISSCRAMBLE;
561
562 if (dwc->u2exit_lfps_quirk)
563 reg |= DWC3_GCTL_U2EXIT_LFPS;
564
565 /*
566 * WORKAROUND: DWC3 revisions <1.90a have a bug
567 * where the device can fail to connect at SuperSpeed
568 * and falls back to high-speed mode which causes
569 * the device to enter a Connect/Disconnect loop
570 */
571 if (dwc->revision < DWC3_REVISION_190A)
572 reg |= DWC3_GCTL_U2RSTECN;
573
574 dwc3_core_num_eps(dwc);
575
576 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
577
578 dwc3_phy_setup(dwc);
579
580 ret = dwc3_alloc_scratch_buffers(dwc);
581 if (ret)
582 goto err0;
583
584 ret = dwc3_setup_scratch_buffers(dwc);
585 if (ret)
586 goto err1;
587
588 return 0;
589
590 err1:
591 dwc3_free_scratch_buffers(dwc);
592
593 err0:
594 return ret;
595 }
596
dwc3_core_exit(struct dwc3 * dwc)597 static void dwc3_core_exit(struct dwc3 *dwc)
598 {
599 dwc3_free_scratch_buffers(dwc);
600 }
601
dwc3_core_init_mode(struct dwc3 * dwc)602 static int dwc3_core_init_mode(struct dwc3 *dwc)
603 {
604 int ret;
605
606 switch (dwc->dr_mode) {
607 case USB_DR_MODE_PERIPHERAL:
608 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
609 ret = dwc3_gadget_init(dwc);
610 if (ret) {
611 dev_err(dev, "failed to initialize gadget\n");
612 return ret;
613 }
614 break;
615 case USB_DR_MODE_HOST:
616 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
617 ret = dwc3_host_init(dwc);
618 if (ret) {
619 dev_err(dev, "failed to initialize host\n");
620 return ret;
621 }
622 break;
623 case USB_DR_MODE_OTG:
624 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
625 ret = dwc3_host_init(dwc);
626 if (ret) {
627 dev_err(dev, "failed to initialize host\n");
628 return ret;
629 }
630
631 ret = dwc3_gadget_init(dwc);
632 if (ret) {
633 dev_err(dev, "failed to initialize gadget\n");
634 return ret;
635 }
636 break;
637 default:
638 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
639 return -EINVAL;
640 }
641
642 return 0;
643 }
644
dwc3_gadget_run(struct dwc3 * dwc)645 static void dwc3_gadget_run(struct dwc3 *dwc)
646 {
647 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
648 mdelay(100);
649 }
650
dwc3_core_exit_mode(struct dwc3 * dwc)651 static void dwc3_core_exit_mode(struct dwc3 *dwc)
652 {
653 switch (dwc->dr_mode) {
654 case USB_DR_MODE_PERIPHERAL:
655 dwc3_gadget_exit(dwc);
656 break;
657 case USB_DR_MODE_HOST:
658 dwc3_host_exit(dwc);
659 break;
660 case USB_DR_MODE_OTG:
661 dwc3_host_exit(dwc);
662 dwc3_gadget_exit(dwc);
663 break;
664 default:
665 /* do nothing */
666 break;
667 }
668
669 /*
670 * switch back to peripheral mode
671 * This enables the phy to enter idle and then, if enabled, suspend.
672 */
673 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
674 dwc3_gadget_run(dwc);
675 }
676
677 #define DWC3_ALIGN_MASK (16 - 1)
678
679 /**
680 * dwc3_uboot_init - dwc3 core uboot initialization code
681 * @dwc3_dev: struct dwc3_device containing initialization data
682 *
683 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
684 * kernel driver). Pointer to dwc3_device should be passed containing
685 * base address and other initialization data. Returns '0' on success and
686 * a negative value on failure.
687 *
688 * Generally called from board_usb_init() implemented in board file.
689 */
dwc3_uboot_init(struct dwc3_device * dwc3_dev)690 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
691 {
692 struct dwc3 *dwc;
693 struct device *dev = NULL;
694 u8 lpm_nyet_threshold;
695 u8 tx_de_emphasis;
696 u8 hird_threshold;
697
698 int ret;
699
700 void *mem;
701 const void *blob = gd->fdt_blob;
702 int node;
703
704 mem = devm_kzalloc((struct udevice *)dev,
705 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
706 if (!mem)
707 return -ENOMEM;
708
709 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
710 dwc->mem = mem;
711
712 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
713 DWC3_GLOBALS_REGS_START);
714
715 /* default to highest possible threshold */
716 lpm_nyet_threshold = 0xff;
717
718 /* default to -3.5dB de-emphasis */
719 tx_de_emphasis = 1;
720
721 /*
722 * default to assert utmi_sleep_n and use maximum allowed HIRD
723 * threshold value of 0b1100
724 */
725 hird_threshold = 12;
726
727 dwc->maximum_speed = dwc3_dev->maximum_speed;
728 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
729 if (dwc3_dev->lpm_nyet_threshold)
730 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
731 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
732 if (dwc3_dev->hird_threshold)
733 hird_threshold = dwc3_dev->hird_threshold;
734
735 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
736 dwc->dr_mode = dwc3_dev->dr_mode;
737
738 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
739 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
740 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
741 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
742 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
743 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
744 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
745 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
746 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
747 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
748 dwc->dis_u1u2_quirk = dwc3_dev->dis_u2_susphy_quirk;
749
750 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
751 if (dwc3_dev->tx_de_emphasis)
752 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
753
754 /* default to superspeed if no maximum_speed passed */
755 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
756 dwc->maximum_speed = USB_SPEED_SUPER;
757
758 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
759 dwc->tx_de_emphasis = tx_de_emphasis;
760
761 dwc->hird_threshold = hird_threshold
762 | (dwc->is_utmi_l1_suspend << 4);
763
764 dwc->hsphy_mode = dwc3_dev->hsphy_mode;
765
766 dwc->index = dwc3_dev->index;
767
768 if (dwc3_dev->usb2_phyif_utmi_width)
769 dwc->usb2_phyif_utmi_width = dwc3_dev->usb2_phyif_utmi_width;
770
771 node = fdt_node_offset_by_compatible(blob, -1,
772 "rockchip,rk3399-xhci");
773 if (node < 0)
774 debug("%s dwc3 node not found\n", __func__);
775 else
776 dwc->usb2_phyif_utmi_width =
777 fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1);
778
779 dwc3_cache_hwparams(dwc);
780
781 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
782 if (ret) {
783 dev_err(dwc->dev, "failed to allocate event buffers\n");
784 return -ENOMEM;
785 }
786
787 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
788 dwc->dr_mode = USB_DR_MODE_HOST;
789 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
790 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
791
792 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
793 dwc->dr_mode = USB_DR_MODE_OTG;
794
795 ret = dwc3_core_init(dwc);
796 if (ret) {
797 dev_err(dev, "failed to initialize core\n");
798 goto err0;
799 }
800
801 ret = dwc3_event_buffers_setup(dwc);
802 if (ret) {
803 dev_err(dwc->dev, "failed to setup event buffers\n");
804 goto err1;
805 }
806
807 ret = dwc3_core_init_mode(dwc);
808 if (ret)
809 goto err2;
810
811 list_add_tail(&dwc->list, &dwc3_list);
812
813 return 0;
814
815 err2:
816 dwc3_event_buffers_cleanup(dwc);
817
818 err1:
819 dwc3_core_exit(dwc);
820
821 err0:
822 dwc3_free_event_buffers(dwc);
823
824 return ret;
825 }
826
827 /**
828 * dwc3_uboot_exit - dwc3 core uboot cleanup code
829 * @index: index of this controller
830 *
831 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
832 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
833 * should be passed and should match with the index passed in
834 * dwc3_device during init.
835 *
836 * Generally called from board file.
837 */
dwc3_uboot_exit(int index)838 void dwc3_uboot_exit(int index)
839 {
840 struct dwc3 *dwc;
841
842 list_for_each_entry(dwc, &dwc3_list, list) {
843 if (dwc->index != index)
844 continue;
845
846 dwc3_core_exit_mode(dwc);
847 dwc3_event_buffers_cleanup(dwc);
848 dwc3_free_event_buffers(dwc);
849 dwc3_core_exit(dwc);
850 list_del(&dwc->list);
851 kfree(dwc->mem);
852 break;
853 }
854 }
855
856 /**
857 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
858 * @index: index of this controller
859 *
860 * Invokes dwc3 gadget interrupts.
861 *
862 * Generally called from board file.
863 */
dwc3_uboot_handle_interrupt(int index)864 void dwc3_uboot_handle_interrupt(int index)
865 {
866 struct dwc3 *dwc = NULL;
867
868 list_for_each_entry(dwc, &dwc3_list, list) {
869 if (dwc->index != index)
870 continue;
871
872 dwc3_gadget_uboot_handle_interrupt(dwc);
873 break;
874 }
875 }
876
877 MODULE_ALIAS("platform:dwc3");
878 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
879 MODULE_LICENSE("GPL v2");
880 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
881
882 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
dwc3_setup_phy(struct udevice * dev,struct phy ** array,int * num_phys)883 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys)
884 {
885 int i, ret, count;
886 struct phy *usb_phys;
887
888 /* Return if no phy declared */
889 if (!dev_read_prop(dev, "phys", NULL))
890 return 0;
891 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
892 if (count <= 0)
893 return count;
894
895 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
896 GFP_KERNEL);
897 if (!usb_phys)
898 return -ENOMEM;
899
900 for (i = 0; i < count; i++) {
901 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
902 if (ret && ret != -ENOENT) {
903 pr_err("Failed to get USB PHY%d for %s\n",
904 i, dev->name);
905 return ret;
906 }
907 }
908
909 for (i = 0; i < count; i++) {
910 ret = generic_phy_init(&usb_phys[i]);
911 if (ret) {
912 pr_err("Can't init USB PHY%d for %s\n",
913 i, dev->name);
914 goto phys_init_err;
915 }
916 }
917
918 for (i = 0; i < count; i++) {
919 ret = generic_phy_power_on(&usb_phys[i]);
920 if (ret) {
921 pr_err("Can't power USB PHY%d for %s\n",
922 i, dev->name);
923 goto phys_poweron_err;
924 }
925 }
926
927 *array = usb_phys;
928 *num_phys = count;
929 return 0;
930
931 phys_poweron_err:
932 for (i = count - 1; i >= 0; i--)
933 generic_phy_power_off(&usb_phys[i]);
934
935 for (i = 0; i < count; i++)
936 generic_phy_exit(&usb_phys[i]);
937
938 return ret;
939
940 phys_init_err:
941 for (; i >= 0; i--)
942 generic_phy_exit(&usb_phys[i]);
943
944 return ret;
945 }
946
dwc3_shutdown_phy(struct udevice * dev,struct phy * usb_phys,int num_phys)947 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys)
948 {
949 int i, ret;
950
951 for (i = 0; i < num_phys; i++) {
952 if (!generic_phy_valid(&usb_phys[i]))
953 continue;
954
955 ret = generic_phy_power_off(&usb_phys[i]);
956 ret |= generic_phy_exit(&usb_phys[i]);
957 if (ret) {
958 pr_err("Can't shutdown USB PHY%d for %s\n",
959 i, dev->name);
960 }
961 }
962
963 return 0;
964 }
965 #endif
966
967 #if CONFIG_IS_ENABLED(DM_USB)
dwc3_of_parse(struct dwc3 * dwc)968 void dwc3_of_parse(struct dwc3 *dwc)
969 {
970 const u8 *tmp;
971 struct udevice *dev = dwc->dev;
972 u8 lpm_nyet_threshold;
973 u8 tx_de_emphasis;
974 u8 hird_threshold;
975
976 /* default to highest possible threshold */
977 lpm_nyet_threshold = 0xff;
978
979 /* default to -3.5dB de-emphasis */
980 tx_de_emphasis = 1;
981
982 /*
983 * default to assert utmi_sleep_n and use maximum allowed HIRD
984 * threshold value of 0b1100
985 */
986 hird_threshold = 12;
987
988 dwc->hsphy_mode = usb_get_phy_mode(dev->node);
989
990 dwc->has_lpm_erratum = dev_read_bool(dev,
991 "snps,has-lpm-erratum");
992 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
993 if (tmp)
994 lpm_nyet_threshold = *tmp;
995
996 dwc->is_utmi_l1_suspend = dev_read_bool(dev,
997 "snps,is-utmi-l1-suspend");
998 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
999 if (tmp)
1000 hird_threshold = *tmp;
1001
1002 dwc->disable_scramble_quirk = dev_read_bool(dev,
1003 "snps,disable_scramble_quirk");
1004 dwc->u2exit_lfps_quirk = dev_read_bool(dev,
1005 "snps,u2exit_lfps_quirk");
1006 dwc->u2ss_inp3_quirk = dev_read_bool(dev,
1007 "snps,u2ss_inp3_quirk");
1008 dwc->req_p1p2p3_quirk = dev_read_bool(dev,
1009 "snps,req_p1p2p3_quirk");
1010 dwc->del_p1p2p3_quirk = dev_read_bool(dev,
1011 "snps,del_p1p2p3_quirk");
1012 dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
1013 "snps,del_phy_power_chg_quirk");
1014 dwc->lfps_filter_quirk = dev_read_bool(dev,
1015 "snps,lfps_filter_quirk");
1016 dwc->rx_detect_poll_quirk = dev_read_bool(dev,
1017 "snps,rx_detect_poll_quirk");
1018 dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
1019 "snps,dis_u3_susphy_quirk");
1020 dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
1021 "snps,dis_u2_susphy_quirk");
1022 dwc->dis_enblslpm_quirk = dev_read_bool(dev,
1023 "snps,dis_enblslpm_quirk");
1024 dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
1025 "snps,dis-u2-freeclk-exists-quirk");
1026 dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
1027 "snps,tx_de_emphasis_quirk");
1028 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
1029 if (tmp)
1030 tx_de_emphasis = *tmp;
1031
1032 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1033 dwc->tx_de_emphasis = tx_de_emphasis;
1034
1035 dwc->hird_threshold = hird_threshold
1036 | (dwc->is_utmi_l1_suspend << 4);
1037 }
1038
dwc3_init(struct dwc3 * dwc)1039 int dwc3_init(struct dwc3 *dwc)
1040 {
1041 int ret;
1042
1043 dwc3_cache_hwparams(dwc);
1044
1045 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1046 if (ret) {
1047 dev_err(dwc->dev, "failed to allocate event buffers\n");
1048 return -ENOMEM;
1049 }
1050
1051 ret = dwc3_core_init(dwc);
1052 if (ret) {
1053 dev_err(dev, "failed to initialize core\n");
1054 goto core_fail;
1055 }
1056
1057 ret = dwc3_event_buffers_setup(dwc);
1058 if (ret) {
1059 dev_err(dwc->dev, "failed to setup event buffers\n");
1060 goto event_fail;
1061 }
1062
1063 ret = dwc3_core_init_mode(dwc);
1064 if (ret)
1065 goto mode_fail;
1066
1067 return 0;
1068
1069 mode_fail:
1070 dwc3_event_buffers_cleanup(dwc);
1071
1072 event_fail:
1073 dwc3_core_exit(dwc);
1074
1075 core_fail:
1076 dwc3_free_event_buffers(dwc);
1077
1078 return ret;
1079 }
1080
dwc3_remove(struct dwc3 * dwc)1081 void dwc3_remove(struct dwc3 *dwc)
1082 {
1083 dwc3_core_exit_mode(dwc);
1084 dwc3_event_buffers_cleanup(dwc);
1085 dwc3_free_event_buffers(dwc);
1086 dwc3_core_exit(dwc);
1087 kfree(dwc->mem);
1088 }
1089 #endif
1090