1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) 2004-2016 Synopsys, Inc.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The names of the above-listed copyright holders may not be used
15 * to endorse or promote products derived from this software without
16 * specific prior written permission.
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation; either version 2 of the License, or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/of_device.h>
39
40 #include "core.h"
41
dwc2_set_bcm_params(struct dwc2_hsotg * hsotg)42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
43 {
44 struct dwc2_core_params *p = &hsotg->params;
45
46 p->host_rx_fifo_size = 774;
47 p->max_transfer_size = 65535;
48 p->max_packet_count = 511;
49 p->ahbcfg = 0x10;
50 }
51
dwc2_set_his_params(struct dwc2_hsotg * hsotg)52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
53 {
54 struct dwc2_core_params *p = &hsotg->params;
55
56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
57 p->speed = DWC2_SPEED_PARAM_HIGH;
58 p->host_rx_fifo_size = 512;
59 p->host_nperio_tx_fifo_size = 512;
60 p->host_perio_tx_fifo_size = 512;
61 p->max_transfer_size = 65535;
62 p->max_packet_count = 511;
63 p->host_channels = 16;
64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
65 p->phy_utmi_width = 8;
66 p->i2c_enable = false;
67 p->reload_ctl = false;
68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
69 GAHBCFG_HBSTLEN_SHIFT;
70 p->change_speed_quirk = true;
71 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
72 }
73
dwc2_set_s3c6400_params(struct dwc2_hsotg * hsotg)74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
75 {
76 struct dwc2_core_params *p = &hsotg->params;
77
78 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
79 p->phy_utmi_width = 8;
80 }
81
dwc2_set_rk_params(struct dwc2_hsotg * hsotg)82 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
83 {
84 struct dwc2_core_params *p = &hsotg->params;
85
86 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
87 p->host_rx_fifo_size = 525;
88 p->host_nperio_tx_fifo_size = 128;
89 p->host_perio_tx_fifo_size = 256;
90 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
91 GAHBCFG_HBSTLEN_SHIFT;
92 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
93 p->lpm = false;
94 p->g_dma_desc = false;
95 }
96
dwc2_set_ltq_params(struct dwc2_hsotg * hsotg)97 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
98 {
99 struct dwc2_core_params *p = &hsotg->params;
100
101 p->otg_cap = 2;
102 p->host_rx_fifo_size = 288;
103 p->host_nperio_tx_fifo_size = 128;
104 p->host_perio_tx_fifo_size = 96;
105 p->max_transfer_size = 65535;
106 p->max_packet_count = 511;
107 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
108 GAHBCFG_HBSTLEN_SHIFT;
109 }
110
dwc2_set_amlogic_params(struct dwc2_hsotg * hsotg)111 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
112 {
113 struct dwc2_core_params *p = &hsotg->params;
114
115 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
116 p->speed = DWC2_SPEED_PARAM_HIGH;
117 p->host_rx_fifo_size = 512;
118 p->host_nperio_tx_fifo_size = 500;
119 p->host_perio_tx_fifo_size = 500;
120 p->host_channels = 16;
121 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
122 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
123 GAHBCFG_HBSTLEN_SHIFT;
124 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
125 }
126
dwc2_set_amlogic_g12a_params(struct dwc2_hsotg * hsotg)127 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
128 {
129 struct dwc2_core_params *p = &hsotg->params;
130
131 p->lpm = false;
132 p->lpm_clock_gating = false;
133 p->besl = false;
134 p->hird_threshold_en = false;
135 }
136
dwc2_set_amcc_params(struct dwc2_hsotg * hsotg)137 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
138 {
139 struct dwc2_core_params *p = &hsotg->params;
140
141 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
142 }
143
dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg * hsotg)144 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
145 {
146 struct dwc2_core_params *p = &hsotg->params;
147
148 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
149 p->speed = DWC2_SPEED_PARAM_FULL;
150 p->host_rx_fifo_size = 128;
151 p->host_nperio_tx_fifo_size = 96;
152 p->host_perio_tx_fifo_size = 96;
153 p->max_packet_count = 256;
154 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
155 p->i2c_enable = false;
156 p->activate_stm_fs_transceiver = true;
157 }
158
dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg * hsotg)159 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
160 {
161 struct dwc2_core_params *p = &hsotg->params;
162
163 p->host_rx_fifo_size = 622;
164 p->host_nperio_tx_fifo_size = 128;
165 p->host_perio_tx_fifo_size = 256;
166 }
167
dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg * hsotg)168 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
169 {
170 struct dwc2_core_params *p = &hsotg->params;
171
172 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
173 p->speed = DWC2_SPEED_PARAM_FULL;
174 p->host_rx_fifo_size = 128;
175 p->host_nperio_tx_fifo_size = 96;
176 p->host_perio_tx_fifo_size = 96;
177 p->max_packet_count = 256;
178 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
179 p->i2c_enable = false;
180 p->activate_stm_fs_transceiver = true;
181 p->activate_stm_id_vb_detection = true;
182 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
183 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
184 p->host_support_fs_ls_low_power = true;
185 p->host_ls_low_power_phy_clk = true;
186 }
187
dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg * hsotg)188 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
189 {
190 struct dwc2_core_params *p = &hsotg->params;
191
192 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
193 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
194 p->host_rx_fifo_size = 440;
195 p->host_nperio_tx_fifo_size = 256;
196 p->host_perio_tx_fifo_size = 256;
197 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
198 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
199 p->lpm = false;
200 p->lpm_clock_gating = false;
201 p->besl = false;
202 p->hird_threshold_en = false;
203 }
204
205 const struct of_device_id dwc2_of_match_table[] = {
206 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
207 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
208 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
209 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
210 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
211 { .compatible = "snps,dwc2" },
212 { .compatible = "samsung,s3c6400-hsotg",
213 .data = dwc2_set_s3c6400_params },
214 { .compatible = "amlogic,meson8-usb",
215 .data = dwc2_set_amlogic_params },
216 { .compatible = "amlogic,meson8b-usb",
217 .data = dwc2_set_amlogic_params },
218 { .compatible = "amlogic,meson-gxbb-usb",
219 .data = dwc2_set_amlogic_params },
220 { .compatible = "amlogic,meson-g12a-usb",
221 .data = dwc2_set_amlogic_g12a_params },
222 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
223 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
224 { .compatible = "st,stm32f4x9-fsotg",
225 .data = dwc2_set_stm32f4x9_fsotg_params },
226 { .compatible = "st,stm32f4x9-hsotg" },
227 { .compatible = "st,stm32f7-hsotg",
228 .data = dwc2_set_stm32f7_hsotg_params },
229 { .compatible = "st,stm32mp15-fsotg",
230 .data = dwc2_set_stm32mp15_fsotg_params },
231 { .compatible = "st,stm32mp15-hsotg",
232 .data = dwc2_set_stm32mp15_hsotg_params },
233 {},
234 };
235 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
236
dwc2_set_param_otg_cap(struct dwc2_hsotg * hsotg)237 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
238 {
239 u8 val;
240
241 switch (hsotg->hw_params.op_mode) {
242 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
243 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
244 break;
245 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
246 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
247 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
248 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
249 break;
250 default:
251 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
252 break;
253 }
254
255 hsotg->params.otg_cap = val;
256 }
257
dwc2_set_param_phy_type(struct dwc2_hsotg * hsotg)258 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
259 {
260 int val;
261 u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
262
263 val = DWC2_PHY_TYPE_PARAM_FS;
264 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
265 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
266 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
267 val = DWC2_PHY_TYPE_PARAM_UTMI;
268 else
269 val = DWC2_PHY_TYPE_PARAM_ULPI;
270 }
271
272 if (dwc2_is_fs_iot(hsotg))
273 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
274
275 hsotg->params.phy_type = val;
276 }
277
dwc2_set_param_speed(struct dwc2_hsotg * hsotg)278 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
279 {
280 int val;
281
282 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
283 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
284
285 if (dwc2_is_fs_iot(hsotg))
286 val = DWC2_SPEED_PARAM_FULL;
287
288 if (dwc2_is_hs_iot(hsotg))
289 val = DWC2_SPEED_PARAM_HIGH;
290
291 hsotg->params.speed = val;
292 }
293
dwc2_set_param_phy_utmi_width(struct dwc2_hsotg * hsotg)294 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
295 {
296 int val;
297
298 val = (hsotg->hw_params.utmi_phy_data_width ==
299 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
300
301 if (hsotg->phy) {
302 /*
303 * If using the generic PHY framework, check if the PHY bus
304 * width is 8-bit and set the phyif appropriately.
305 */
306 if (phy_get_bus_width(hsotg->phy) == 8)
307 val = 8;
308 }
309
310 hsotg->params.phy_utmi_width = val;
311 }
312
dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg * hsotg)313 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
314 {
315 struct dwc2_core_params *p = &hsotg->params;
316 int depth_average;
317 int fifo_count;
318 int i;
319
320 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
321
322 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
323 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
324 for (i = 1; i <= fifo_count; i++)
325 p->g_tx_fifo_size[i] = depth_average;
326 }
327
dwc2_set_param_power_down(struct dwc2_hsotg * hsotg)328 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
329 {
330 int val;
331
332 if (hsotg->hw_params.hibernation)
333 val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
334 else if (hsotg->hw_params.power_optimized)
335 val = DWC2_POWER_DOWN_PARAM_PARTIAL;
336 else
337 val = DWC2_POWER_DOWN_PARAM_NONE;
338
339 hsotg->params.power_down = val;
340 }
341
dwc2_set_param_lpm(struct dwc2_hsotg * hsotg)342 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
343 {
344 struct dwc2_core_params *p = &hsotg->params;
345
346 p->lpm = hsotg->hw_params.lpm_mode;
347 if (p->lpm) {
348 p->lpm_clock_gating = true;
349 p->besl = true;
350 p->hird_threshold_en = true;
351 p->hird_threshold = 4;
352 } else {
353 p->lpm_clock_gating = false;
354 p->besl = false;
355 p->hird_threshold_en = false;
356 }
357 }
358
359 /**
360 * dwc2_set_default_params() - Set all core parameters to their
361 * auto-detected default values.
362 *
363 * @hsotg: Programming view of the DWC_otg controller
364 *
365 */
dwc2_set_default_params(struct dwc2_hsotg * hsotg)366 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
367 {
368 struct dwc2_hw_params *hw = &hsotg->hw_params;
369 struct dwc2_core_params *p = &hsotg->params;
370 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
371
372 dwc2_set_param_otg_cap(hsotg);
373 dwc2_set_param_phy_type(hsotg);
374 dwc2_set_param_speed(hsotg);
375 dwc2_set_param_phy_utmi_width(hsotg);
376 dwc2_set_param_power_down(hsotg);
377 dwc2_set_param_lpm(hsotg);
378 p->phy_ulpi_ddr = false;
379 p->phy_ulpi_ext_vbus = false;
380
381 p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
382 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
383 p->i2c_enable = hw->i2c_enable;
384 p->acg_enable = hw->acg_enable;
385 p->ulpi_fs_ls = false;
386 p->ts_dline = false;
387 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
388 p->uframe_sched = true;
389 p->external_id_pin_ctl = false;
390 p->ipg_isoc_en = false;
391 p->service_interval = false;
392 p->max_packet_count = hw->max_packet_count;
393 p->max_transfer_size = hw->max_transfer_size;
394 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
395 p->ref_clk_per = 33333;
396 p->sof_cnt_wkup_alert = 100;
397
398 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
399 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
400 p->host_dma = dma_capable;
401 p->dma_desc_enable = false;
402 p->dma_desc_fs_enable = false;
403 p->host_support_fs_ls_low_power = false;
404 p->host_ls_low_power_phy_clk = false;
405 p->host_channels = hw->host_channels;
406 p->host_rx_fifo_size = hw->rx_fifo_size;
407 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
408 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
409 }
410
411 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
412 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
413 p->g_dma = dma_capable;
414 p->g_dma_desc = hw->dma_desc_enable;
415
416 /*
417 * The values for g_rx_fifo_size (2048) and
418 * g_np_tx_fifo_size (1024) come from the legacy s3c
419 * gadget driver. These defaults have been hard-coded
420 * for some time so many platforms depend on these
421 * values. Leave them as defaults for now and only
422 * auto-detect if the hardware does not support the
423 * default.
424 */
425 p->g_rx_fifo_size = 2048;
426 p->g_np_tx_fifo_size = 1024;
427 dwc2_set_param_tx_fifo_sizes(hsotg);
428 }
429 }
430
431 /**
432 * dwc2_get_device_properties() - Read in device properties.
433 *
434 * @hsotg: Programming view of the DWC_otg controller
435 *
436 * Read in the device properties and adjust core parameters if needed.
437 */
dwc2_get_device_properties(struct dwc2_hsotg * hsotg)438 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
439 {
440 struct dwc2_core_params *p = &hsotg->params;
441 int num;
442
443 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
444 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
445 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
446 &p->g_rx_fifo_size);
447
448 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
449 &p->g_np_tx_fifo_size);
450
451 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
452 if (num > 0) {
453 num = min(num, 15);
454 memset(p->g_tx_fifo_size, 0,
455 sizeof(p->g_tx_fifo_size));
456 device_property_read_u32_array(hsotg->dev,
457 "g-tx-fifo-size",
458 &p->g_tx_fifo_size[1],
459 num);
460 }
461 }
462
463 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
464 p->oc_disable = true;
465 }
466
dwc2_check_param_otg_cap(struct dwc2_hsotg * hsotg)467 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
468 {
469 int valid = 1;
470
471 switch (hsotg->params.otg_cap) {
472 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
473 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
474 valid = 0;
475 break;
476 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
477 switch (hsotg->hw_params.op_mode) {
478 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
479 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
480 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
481 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
482 break;
483 default:
484 valid = 0;
485 break;
486 }
487 break;
488 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
489 /* always valid */
490 break;
491 default:
492 valid = 0;
493 break;
494 }
495
496 if (!valid)
497 dwc2_set_param_otg_cap(hsotg);
498 }
499
dwc2_check_param_phy_type(struct dwc2_hsotg * hsotg)500 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
501 {
502 int valid = 0;
503 u32 hs_phy_type;
504 u32 fs_phy_type;
505
506 hs_phy_type = hsotg->hw_params.hs_phy_type;
507 fs_phy_type = hsotg->hw_params.fs_phy_type;
508
509 switch (hsotg->params.phy_type) {
510 case DWC2_PHY_TYPE_PARAM_FS:
511 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
512 valid = 1;
513 break;
514 case DWC2_PHY_TYPE_PARAM_UTMI:
515 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
516 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
517 valid = 1;
518 break;
519 case DWC2_PHY_TYPE_PARAM_ULPI:
520 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
521 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
522 valid = 1;
523 break;
524 default:
525 break;
526 }
527
528 if (!valid)
529 dwc2_set_param_phy_type(hsotg);
530 }
531
dwc2_check_param_speed(struct dwc2_hsotg * hsotg)532 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
533 {
534 int valid = 1;
535 int phy_type = hsotg->params.phy_type;
536 int speed = hsotg->params.speed;
537
538 switch (speed) {
539 case DWC2_SPEED_PARAM_HIGH:
540 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
541 (phy_type == DWC2_PHY_TYPE_PARAM_FS))
542 valid = 0;
543 break;
544 case DWC2_SPEED_PARAM_FULL:
545 case DWC2_SPEED_PARAM_LOW:
546 break;
547 default:
548 valid = 0;
549 break;
550 }
551
552 if (!valid)
553 dwc2_set_param_speed(hsotg);
554 }
555
dwc2_check_param_phy_utmi_width(struct dwc2_hsotg * hsotg)556 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
557 {
558 int valid = 0;
559 int param = hsotg->params.phy_utmi_width;
560 int width = hsotg->hw_params.utmi_phy_data_width;
561
562 switch (width) {
563 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
564 valid = (param == 8);
565 break;
566 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
567 valid = (param == 16);
568 break;
569 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
570 valid = (param == 8 || param == 16);
571 break;
572 }
573
574 if (!valid)
575 dwc2_set_param_phy_utmi_width(hsotg);
576 }
577
dwc2_check_param_power_down(struct dwc2_hsotg * hsotg)578 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
579 {
580 int param = hsotg->params.power_down;
581
582 switch (param) {
583 case DWC2_POWER_DOWN_PARAM_NONE:
584 break;
585 case DWC2_POWER_DOWN_PARAM_PARTIAL:
586 if (hsotg->hw_params.power_optimized)
587 break;
588 dev_dbg(hsotg->dev,
589 "Partial power down isn't supported by HW\n");
590 param = DWC2_POWER_DOWN_PARAM_NONE;
591 break;
592 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
593 if (hsotg->hw_params.hibernation)
594 break;
595 dev_dbg(hsotg->dev,
596 "Hibernation isn't supported by HW\n");
597 param = DWC2_POWER_DOWN_PARAM_NONE;
598 break;
599 default:
600 dev_err(hsotg->dev,
601 "%s: Invalid parameter power_down=%d\n",
602 __func__, param);
603 param = DWC2_POWER_DOWN_PARAM_NONE;
604 break;
605 }
606
607 hsotg->params.power_down = param;
608 }
609
dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg * hsotg)610 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
611 {
612 int fifo_count;
613 int fifo;
614 int min;
615 u32 total = 0;
616 u32 dptxfszn;
617
618 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
619 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
620
621 for (fifo = 1; fifo <= fifo_count; fifo++)
622 total += hsotg->params.g_tx_fifo_size[fifo];
623
624 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
625 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
626 __func__);
627 dwc2_set_param_tx_fifo_sizes(hsotg);
628 }
629
630 for (fifo = 1; fifo <= fifo_count; fifo++) {
631 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
632
633 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
634 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) {
635 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
636 __func__, fifo,
637 hsotg->params.g_tx_fifo_size[fifo]);
638 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
639 }
640 }
641 }
642
643 #define CHECK_RANGE(_param, _min, _max, _def) do { \
644 if ((int)(hsotg->params._param) < (_min) || \
645 (hsotg->params._param) > (_max)) { \
646 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
647 __func__, #_param, hsotg->params._param); \
648 hsotg->params._param = (_def); \
649 } \
650 } while (0)
651
652 #define CHECK_BOOL(_param, _check) do { \
653 if (hsotg->params._param && !(_check)) { \
654 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
655 __func__, #_param, hsotg->params._param); \
656 hsotg->params._param = false; \
657 } \
658 } while (0)
659
dwc2_check_params(struct dwc2_hsotg * hsotg)660 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
661 {
662 struct dwc2_hw_params *hw = &hsotg->hw_params;
663 struct dwc2_core_params *p = &hsotg->params;
664 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
665
666 dwc2_check_param_otg_cap(hsotg);
667 dwc2_check_param_phy_type(hsotg);
668 dwc2_check_param_speed(hsotg);
669 dwc2_check_param_phy_utmi_width(hsotg);
670 dwc2_check_param_power_down(hsotg);
671 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
672 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
673 CHECK_BOOL(i2c_enable, hw->i2c_enable);
674 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
675 CHECK_BOOL(acg_enable, hw->acg_enable);
676 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
677 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
678 CHECK_BOOL(lpm, hw->lpm_mode);
679 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
680 CHECK_BOOL(besl, hsotg->params.lpm);
681 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
682 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
683 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
684 CHECK_BOOL(service_interval, hw->service_interval_mode);
685 CHECK_RANGE(max_packet_count,
686 15, hw->max_packet_count,
687 hw->max_packet_count);
688 CHECK_RANGE(max_transfer_size,
689 2047, hw->max_transfer_size,
690 hw->max_transfer_size);
691
692 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
693 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
694 CHECK_BOOL(host_dma, dma_capable);
695 CHECK_BOOL(dma_desc_enable, p->host_dma);
696 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
697 CHECK_BOOL(host_ls_low_power_phy_clk,
698 p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
699 CHECK_RANGE(host_channels,
700 1, hw->host_channels,
701 hw->host_channels);
702 CHECK_RANGE(host_rx_fifo_size,
703 16, hw->rx_fifo_size,
704 hw->rx_fifo_size);
705 CHECK_RANGE(host_nperio_tx_fifo_size,
706 16, hw->host_nperio_tx_fifo_size,
707 hw->host_nperio_tx_fifo_size);
708 CHECK_RANGE(host_perio_tx_fifo_size,
709 16, hw->host_perio_tx_fifo_size,
710 hw->host_perio_tx_fifo_size);
711 }
712
713 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
714 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
715 CHECK_BOOL(g_dma, dma_capable);
716 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
717 CHECK_RANGE(g_rx_fifo_size,
718 16, hw->rx_fifo_size,
719 hw->rx_fifo_size);
720 CHECK_RANGE(g_np_tx_fifo_size,
721 16, hw->dev_nperio_tx_fifo_size,
722 hw->dev_nperio_tx_fifo_size);
723 dwc2_check_param_tx_fifo_sizes(hsotg);
724 }
725 }
726
727 /*
728 * Gets host hardware parameters. Forces host mode if not currently in
729 * host mode. Should be called immediately after a core soft reset in
730 * order to get the reset values.
731 */
dwc2_get_host_hwparams(struct dwc2_hsotg * hsotg)732 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
733 {
734 struct dwc2_hw_params *hw = &hsotg->hw_params;
735 u32 gnptxfsiz;
736 u32 hptxfsiz;
737
738 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
739 return;
740
741 dwc2_force_mode(hsotg, true);
742
743 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
744 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
745
746 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
747 FIFOSIZE_DEPTH_SHIFT;
748 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
749 FIFOSIZE_DEPTH_SHIFT;
750 }
751
752 /*
753 * Gets device hardware parameters. Forces device mode if not
754 * currently in device mode. Should be called immediately after a core
755 * soft reset in order to get the reset values.
756 */
dwc2_get_dev_hwparams(struct dwc2_hsotg * hsotg)757 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
758 {
759 struct dwc2_hw_params *hw = &hsotg->hw_params;
760 u32 gnptxfsiz;
761 int fifo, fifo_count;
762
763 if (hsotg->dr_mode == USB_DR_MODE_HOST)
764 return;
765
766 dwc2_force_mode(hsotg, false);
767
768 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
769
770 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
771
772 for (fifo = 1; fifo <= fifo_count; fifo++) {
773 hw->g_tx_fifo_size[fifo] =
774 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
775 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
776 }
777
778 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
779 FIFOSIZE_DEPTH_SHIFT;
780 }
781
782 /**
783 * During device initialization, read various hardware configuration
784 * registers and interpret the contents.
785 *
786 * @hsotg: Programming view of the DWC_otg controller
787 *
788 */
dwc2_get_hwparams(struct dwc2_hsotg * hsotg)789 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
790 {
791 struct dwc2_hw_params *hw = &hsotg->hw_params;
792 unsigned int width;
793 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
794 u32 grxfsiz;
795
796 hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
797 hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
798 hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
799 hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
800 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
801
802 /* hwcfg1 */
803 hw->dev_ep_dirs = hwcfg1;
804
805 /* hwcfg2 */
806 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
807 GHWCFG2_OP_MODE_SHIFT;
808 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
809 GHWCFG2_ARCHITECTURE_SHIFT;
810 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
811 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
812 GHWCFG2_NUM_HOST_CHAN_SHIFT);
813 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
814 GHWCFG2_HS_PHY_TYPE_SHIFT;
815 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
816 GHWCFG2_FS_PHY_TYPE_SHIFT;
817 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
818 GHWCFG2_NUM_DEV_EP_SHIFT;
819 hw->nperio_tx_q_depth =
820 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
821 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
822 hw->host_perio_tx_q_depth =
823 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
824 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
825 hw->dev_token_q_depth =
826 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
827 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
828
829 /* hwcfg3 */
830 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
831 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
832 hw->max_transfer_size = (1 << (width + 11)) - 1;
833 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
834 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
835 hw->max_packet_count = (1 << (width + 4)) - 1;
836 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
837 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
838 GHWCFG3_DFIFO_DEPTH_SHIFT;
839 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
840
841 /* hwcfg4 */
842 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
843 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
844 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
845 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
846 GHWCFG4_NUM_IN_EPS_SHIFT;
847 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
848 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
849 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
850 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
851 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
852 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
853 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
854 hw->service_interval_mode = !!(hwcfg4 &
855 GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
856
857 /* fifo sizes */
858 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
859 GRXFSIZ_DEPTH_SHIFT;
860 /*
861 * Host specific hardware parameters. Reading these parameters
862 * requires the controller to be in host mode. The mode will
863 * be forced, if necessary, to read these values.
864 */
865 dwc2_get_host_hwparams(hsotg);
866 dwc2_get_dev_hwparams(hsotg);
867
868 return 0;
869 }
870
dwc2_init_params(struct dwc2_hsotg * hsotg)871 int dwc2_init_params(struct dwc2_hsotg *hsotg)
872 {
873 const struct of_device_id *match;
874 void (*set_params)(struct dwc2_hsotg *data);
875
876 dwc2_set_default_params(hsotg);
877 dwc2_get_device_properties(hsotg);
878
879 match = of_match_device(dwc2_of_match_table, hsotg->dev);
880 if (match && match->data) {
881 set_params = match->data;
882 set_params(hsotg);
883 }
884
885 dwc2_check_params(hsotg);
886
887 return 0;
888 }
889