1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * platform.c - DesignWare HS OTG Controller platform driver
4 *
5 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41 #include <linux/clk.h>
42 #include <linux/device.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/of_device.h>
45 #include <linux/mutex.h>
46 #include <linux/platform_device.h>
47 #include <linux/phy/phy.h>
48 #include <linux/platform_data/s3c-hsotg.h>
49 #include <linux/reset.h>
50
51 #include <linux/usb/of.h>
52
53 #include "core.h"
54 #include "hcd.h"
55 #include "debug.h"
56
57 static const char dwc2_driver_name[] = "dwc2";
58
59 /*
60 * Check the dr_mode against the module configuration and hardware
61 * capabilities.
62 *
63 * The hardware, module, and dr_mode, can each be set to host, device,
64 * or otg. Check that all these values are compatible and adjust the
65 * value of dr_mode if possible.
66 *
67 * actual
68 * HW MOD dr_mode dr_mode
69 * ------------------------------
70 * HST HST any : HST
71 * HST DEV any : ---
72 * HST OTG any : HST
73 *
74 * DEV HST any : ---
75 * DEV DEV any : DEV
76 * DEV OTG any : DEV
77 *
78 * OTG HST any : HST
79 * OTG DEV any : DEV
80 * OTG OTG any : dr_mode
81 */
dwc2_get_dr_mode(struct dwc2_hsotg * hsotg)82 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
83 {
84 enum usb_dr_mode mode;
85
86 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
87 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
88 hsotg->dr_mode = USB_DR_MODE_OTG;
89
90 mode = hsotg->dr_mode;
91
92 if (dwc2_hw_is_device(hsotg)) {
93 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
94 dev_err(hsotg->dev,
95 "Controller does not support host mode.\n");
96 return -EINVAL;
97 }
98 mode = USB_DR_MODE_PERIPHERAL;
99 } else if (dwc2_hw_is_host(hsotg)) {
100 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
101 dev_err(hsotg->dev,
102 "Controller does not support device mode.\n");
103 return -EINVAL;
104 }
105 mode = USB_DR_MODE_HOST;
106 } else {
107 if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
108 mode = USB_DR_MODE_HOST;
109 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
110 mode = USB_DR_MODE_PERIPHERAL;
111 }
112
113 if (mode != hsotg->dr_mode) {
114 dev_warn(hsotg->dev,
115 "Configuration mismatch. dr_mode forced to %s\n",
116 mode == USB_DR_MODE_HOST ? "host" : "device");
117
118 hsotg->dr_mode = mode;
119 }
120
121 return 0;
122 }
123
__dwc2_disable_regulators(void * data)124 static void __dwc2_disable_regulators(void *data)
125 {
126 struct dwc2_hsotg *hsotg = data;
127
128 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
129 }
130
__dwc2_lowlevel_phy_enable(struct dwc2_hsotg * hsotg)131 static int __dwc2_lowlevel_phy_enable(struct dwc2_hsotg *hsotg)
132 {
133 struct platform_device *pdev = to_platform_device(hsotg->dev);
134 int ret;
135
136 if (hsotg->uphy) {
137 ret = usb_phy_init(hsotg->uphy);
138 } else if (hsotg->plat && hsotg->plat->phy_init) {
139 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
140 } else {
141 ret = phy_init(hsotg->phy);
142 if (ret == 0)
143 ret = phy_power_on(hsotg->phy);
144 }
145
146 return ret;
147 }
148
149 /**
150 * dwc2_lowlevel_phy_enable - enable lowlevel PHY resources
151 * @hsotg: The driver state
152 *
153 * A wrapper for platform code responsible for controlling
154 * low-level PHY resources.
155 */
dwc2_lowlevel_phy_enable(struct dwc2_hsotg * hsotg)156 int dwc2_lowlevel_phy_enable(struct dwc2_hsotg *hsotg)
157 {
158 int ret = __dwc2_lowlevel_phy_enable(hsotg);
159
160 if (ret == 0)
161 hsotg->ll_phy_enabled = true;
162 return ret;
163 }
164
__dwc2_lowlevel_phy_disable(struct dwc2_hsotg * hsotg)165 static int __dwc2_lowlevel_phy_disable(struct dwc2_hsotg *hsotg)
166 {
167 struct platform_device *pdev = to_platform_device(hsotg->dev);
168 int ret = 0;
169
170 if (hsotg->uphy) {
171 usb_phy_shutdown(hsotg->uphy);
172 } else if (hsotg->plat && hsotg->plat->phy_exit) {
173 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
174 } else {
175 ret = phy_power_off(hsotg->phy);
176 if (ret == 0)
177 ret = phy_exit(hsotg->phy);
178 }
179
180 return ret;
181 }
182
183 /**
184 * dwc2_lowlevel_phy_disable - disable lowlevel PHY resources
185 * @hsotg: The driver state
186 *
187 * A wrapper for platform code responsible for controlling
188 * low-level PHY platform resources.
189 */
dwc2_lowlevel_phy_disable(struct dwc2_hsotg * hsotg)190 int dwc2_lowlevel_phy_disable(struct dwc2_hsotg *hsotg)
191 {
192 int ret = __dwc2_lowlevel_phy_disable(hsotg);
193
194 if (ret == 0)
195 hsotg->ll_phy_enabled = false;
196 return ret;
197 }
198
__dwc2_lowlevel_hw_enable(struct dwc2_hsotg * hsotg)199 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
200 {
201 struct platform_device *pdev = to_platform_device(hsotg->dev);
202 int ret;
203
204 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
205 hsotg->supplies);
206 if (ret)
207 return ret;
208
209 ret = devm_add_action_or_reset(&pdev->dev,
210 __dwc2_disable_regulators, hsotg);
211 if (ret)
212 return ret;
213
214 ret = clk_bulk_prepare_enable(hsotg->num_clks, hsotg->clks);
215 if (ret)
216 return ret;
217
218 if (!hsotg->ll_phy_enabled)
219 ret = dwc2_lowlevel_phy_enable(hsotg);
220
221 return ret;
222 }
223
224 /**
225 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
226 * @hsotg: The driver state
227 *
228 * A wrapper for platform code responsible for controlling
229 * low-level USB platform resources (phy, clock, regulators)
230 */
dwc2_lowlevel_hw_enable(struct dwc2_hsotg * hsotg)231 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
232 {
233 int ret = __dwc2_lowlevel_hw_enable(hsotg);
234
235 if (ret == 0)
236 hsotg->ll_hw_enabled = true;
237 return ret;
238 }
239
__dwc2_lowlevel_hw_disable(struct dwc2_hsotg * hsotg)240 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
241 {
242 int ret = 0;
243
244 if (hsotg->ll_phy_enabled)
245 ret = dwc2_lowlevel_phy_disable(hsotg);
246
247 if (ret)
248 return ret;
249
250 clk_bulk_disable_unprepare(hsotg->num_clks, hsotg->clks);
251
252 return 0;
253 }
254
255 /**
256 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
257 * @hsotg: The driver state
258 *
259 * A wrapper for platform code responsible for controlling
260 * low-level USB platform resources (phy, clock, regulators)
261 */
dwc2_lowlevel_hw_disable(struct dwc2_hsotg * hsotg)262 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
263 {
264 int ret = __dwc2_lowlevel_hw_disable(hsotg);
265
266 if (ret == 0)
267 hsotg->ll_hw_enabled = false;
268 return ret;
269 }
270
dwc2_lowlevel_hw_init(struct dwc2_hsotg * hsotg)271 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
272 {
273 int i, ret;
274
275 hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
276 if (IS_ERR(hsotg->reset)) {
277 ret = PTR_ERR(hsotg->reset);
278 dev_err(hsotg->dev, "error getting reset control %d\n", ret);
279 return ret;
280 }
281
282 reset_control_deassert(hsotg->reset);
283
284 hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
285 if (IS_ERR(hsotg->reset_ecc)) {
286 ret = PTR_ERR(hsotg->reset_ecc);
287 dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
288 return ret;
289 }
290
291 reset_control_deassert(hsotg->reset_ecc);
292
293 /*
294 * Attempt to find a generic PHY, then look for an old style
295 * USB PHY and then fall back to pdata
296 */
297 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
298 if (IS_ERR(hsotg->phy)) {
299 ret = PTR_ERR(hsotg->phy);
300 switch (ret) {
301 case -ENODEV:
302 case -ENOSYS:
303 hsotg->phy = NULL;
304 break;
305 case -EPROBE_DEFER:
306 return ret;
307 default:
308 dev_err(hsotg->dev, "error getting phy %d\n", ret);
309 return ret;
310 }
311 }
312
313 if (!hsotg->phy) {
314 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
315 if (IS_ERR(hsotg->uphy)) {
316 ret = PTR_ERR(hsotg->uphy);
317 switch (ret) {
318 case -ENODEV:
319 case -ENXIO:
320 hsotg->uphy = NULL;
321 break;
322 case -EPROBE_DEFER:
323 return ret;
324 default:
325 dev_err(hsotg->dev, "error getting usb phy %d\n",
326 ret);
327 return ret;
328 }
329 }
330 }
331
332 hsotg->plat = dev_get_platdata(hsotg->dev);
333
334 /* Clock */
335 if (hsotg->dev->of_node) {
336 ret = devm_clk_bulk_get_all(hsotg->dev, &hsotg->clks);
337 if (ret == -EPROBE_DEFER)
338 return ret;
339 /*
340 * Clocks are optional, but new DT platforms should support all
341 * clocks as required by the DT-binding.
342 */
343 if (ret < 0)
344 hsotg->num_clks = 0;
345 else
346 hsotg->num_clks = ret;
347 }
348
349 /* Regulators */
350 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
351 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
352
353 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
354 hsotg->supplies);
355 if (ret) {
356 if (ret != -EPROBE_DEFER)
357 dev_err(hsotg->dev, "failed to request supplies: %d\n",
358 ret);
359 return ret;
360 }
361 return 0;
362 }
363
364 /**
365 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
366 * DWC_otg driver
367 *
368 * @dev: Platform device
369 *
370 * This routine is called, for example, when the rmmod command is executed. The
371 * device may or may not be electrically present. If it is present, the driver
372 * stops device processing. Any resources used on behalf of this device are
373 * freed.
374 */
dwc2_driver_remove(struct platform_device * dev)375 static int dwc2_driver_remove(struct platform_device *dev)
376 {
377 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
378
379 dwc2_debugfs_exit(hsotg);
380 if (hsotg->hcd_enabled)
381 dwc2_hcd_remove(hsotg);
382 if (hsotg->gadget_enabled)
383 dwc2_hsotg_remove(hsotg);
384
385 dwc2_drd_exit(hsotg);
386
387 if (hsotg->params.activate_stm_id_vb_detection)
388 regulator_disable(hsotg->usb33d);
389
390 pm_runtime_put_sync(hsotg->dev);
391 pm_runtime_disable(hsotg->dev);
392
393 if (hsotg->ll_hw_enabled)
394 dwc2_lowlevel_hw_disable(hsotg);
395
396 reset_control_assert(hsotg->reset);
397 reset_control_assert(hsotg->reset_ecc);
398
399 return 0;
400 }
401
402 /**
403 * dwc2_driver_shutdown() - Called on device shutdown
404 *
405 * @dev: Platform device
406 *
407 * In specific conditions (involving usb hubs) dwc2 devices can create a
408 * lot of interrupts, even to the point of overwhelming devices running
409 * at low frequencies. Some devices need to do special clock handling
410 * at shutdown-time which may bring the system clock below the threshold
411 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
412 * prevents reboots/poweroffs from getting stuck in such cases.
413 */
dwc2_driver_shutdown(struct platform_device * dev)414 static void dwc2_driver_shutdown(struct platform_device *dev)
415 {
416 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
417
418 dwc2_disable_global_interrupts(hsotg);
419 synchronize_irq(hsotg->irq);
420 }
421
422 /**
423 * dwc2_check_core_endianness() - Returns true if core and AHB have
424 * opposite endianness.
425 * @hsotg: Programming view of the DWC_otg controller.
426 */
dwc2_check_core_endianness(struct dwc2_hsotg * hsotg)427 static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
428 {
429 u32 snpsid;
430
431 snpsid = ioread32(hsotg->regs + GSNPSID);
432 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
433 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
434 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
435 return false;
436 return true;
437 }
438
439 /**
440 * Check core version
441 *
442 * @hsotg: Programming view of the DWC_otg controller
443 *
444 */
dwc2_check_core_version(struct dwc2_hsotg * hsotg)445 int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
446 {
447 struct dwc2_hw_params *hw = &hsotg->hw_params;
448
449 /*
450 * Attempt to ensure this device is really a DWC_otg Controller.
451 * Read and verify the GSNPSID register contents. The value should be
452 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
453 */
454
455 hw->snpsid = dwc2_readl(hsotg, GSNPSID);
456 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
457 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
458 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
459 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
460 hw->snpsid);
461 return -ENODEV;
462 }
463
464 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
465 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
466 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
467 return 0;
468 }
469
470 /**
471 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
472 * driver
473 *
474 * @dev: Platform device
475 *
476 * This routine creates the driver components required to control the device
477 * (core, HCD, and PCD) and initializes the device. The driver components are
478 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
479 * in the device private data. This allows the driver to access the dwc2_hsotg
480 * structure on subsequent calls to driver methods for this device.
481 */
dwc2_driver_probe(struct platform_device * dev)482 static int dwc2_driver_probe(struct platform_device *dev)
483 {
484 struct dwc2_hsotg *hsotg;
485 struct resource *res;
486 int retval;
487
488 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
489 if (!hsotg)
490 return -ENOMEM;
491
492 hsotg->dev = &dev->dev;
493
494 /*
495 * Use reasonable defaults so platforms don't have to provide these.
496 */
497 if (!dev->dev.dma_mask)
498 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
499 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
500 if (retval) {
501 dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
502 return retval;
503 }
504
505 hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res);
506 if (IS_ERR(hsotg->regs))
507 return PTR_ERR(hsotg->regs);
508
509 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
510 (unsigned long)res->start, hsotg->regs);
511
512 retval = dwc2_lowlevel_hw_init(hsotg);
513 if (retval)
514 return retval;
515
516 spin_lock_init(&hsotg->lock);
517
518 hsotg->irq = platform_get_irq(dev, 0);
519 if (hsotg->irq < 0)
520 return hsotg->irq;
521
522 dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
523 hsotg->irq);
524 retval = devm_request_irq(hsotg->dev, hsotg->irq,
525 dwc2_handle_common_intr, IRQF_SHARED,
526 dev_name(hsotg->dev), hsotg);
527 if (retval)
528 return retval;
529
530 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
531 if (IS_ERR(hsotg->vbus_supply)) {
532 retval = PTR_ERR(hsotg->vbus_supply);
533 hsotg->vbus_supply = NULL;
534 if (retval != -ENODEV)
535 return retval;
536 }
537
538 retval = dwc2_lowlevel_hw_enable(hsotg);
539 if (retval)
540 return retval;
541
542 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
543
544 pm_runtime_enable(hsotg->dev);
545 retval = pm_runtime_get_sync(hsotg->dev);
546 if (retval < 0)
547 goto error;
548
549 retval = dwc2_get_dr_mode(hsotg);
550 if (retval)
551 goto error;
552
553 hsotg->need_phy_for_wake =
554 of_property_read_bool(dev->dev.of_node,
555 "snps,need-phy-for-wake");
556
557 /*
558 * Before performing any core related operations
559 * check core version.
560 */
561 retval = dwc2_check_core_version(hsotg);
562 if (retval)
563 goto error;
564
565 /*
566 * Reset before dwc2_get_hwparams() then it could get power-on real
567 * reset value form registers.
568 */
569 retval = dwc2_core_reset(hsotg, false);
570 if (retval)
571 goto error;
572
573 /* Detect config values from hardware */
574 retval = dwc2_get_hwparams(hsotg);
575 if (retval)
576 goto error;
577
578 /*
579 * For OTG cores, set the force mode bits to reflect the value
580 * of dr_mode. Force mode bits should not be touched at any
581 * other time after this.
582 */
583 dwc2_force_dr_mode(hsotg);
584
585 retval = dwc2_init_params(hsotg);
586 if (retval)
587 goto error;
588
589 if (hsotg->params.activate_stm_id_vb_detection) {
590 u32 ggpio;
591
592 hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
593 if (IS_ERR(hsotg->usb33d)) {
594 retval = PTR_ERR(hsotg->usb33d);
595 if (retval != -EPROBE_DEFER)
596 dev_err(hsotg->dev,
597 "failed to request usb33d supply: %d\n",
598 retval);
599 goto error;
600 }
601 retval = regulator_enable(hsotg->usb33d);
602 if (retval) {
603 dev_err(hsotg->dev,
604 "failed to enable usb33d supply: %d\n", retval);
605 goto error;
606 }
607
608 ggpio = dwc2_readl(hsotg, GGPIO);
609 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
610 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
611 dwc2_writel(hsotg, ggpio, GGPIO);
612
613 /* ID/VBUS detection startup time */
614 usleep_range(5000, 7000);
615 }
616
617 retval = dwc2_drd_init(hsotg);
618 if (retval) {
619 if (retval != -EPROBE_DEFER)
620 dev_err(hsotg->dev, "failed to initialize dual-role\n");
621 goto error_init;
622 }
623
624 if (hsotg->dr_mode != USB_DR_MODE_HOST) {
625 retval = dwc2_gadget_init(hsotg);
626 if (retval)
627 goto error_drd;
628 hsotg->gadget_enabled = 1;
629 }
630
631 /*
632 * If we need PHY for wakeup we must be wakeup capable.
633 * When we have a device that can wake without the PHY we
634 * can adjust this condition.
635 */
636 if (hsotg->need_phy_for_wake)
637 device_set_wakeup_capable(&dev->dev, true);
638
639 hsotg->reset_phy_on_wake =
640 of_property_read_bool(dev->dev.of_node,
641 "snps,reset-phy-on-wake");
642 if (hsotg->reset_phy_on_wake && !hsotg->phy) {
643 dev_warn(hsotg->dev,
644 "Quirk reset-phy-on-wake only supports generic PHYs\n");
645 hsotg->reset_phy_on_wake = false;
646 }
647
648 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
649 retval = dwc2_hcd_init(hsotg);
650 if (retval) {
651 if (hsotg->gadget_enabled)
652 dwc2_hsotg_remove(hsotg);
653 goto error_drd;
654 }
655 hsotg->hcd_enabled = 1;
656 }
657
658 platform_set_drvdata(dev, hsotg);
659 hsotg->hibernated = 0;
660
661 dwc2_debugfs_init(hsotg);
662
663 /* Gadget code manages lowlevel hw on its own */
664 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
665 dwc2_lowlevel_hw_disable(hsotg);
666
667 if (hsotg->dr_mode == USB_DR_MODE_OTG && dwc2_is_device_mode(hsotg)) {
668 if (hsotg->ll_phy_enabled)
669 dwc2_lowlevel_phy_disable(hsotg);
670 }
671
672 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
673 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
674 /* Postponed adding a new gadget to the udc class driver list */
675 if (hsotg->gadget_enabled) {
676 retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
677 if (retval) {
678 hsotg->gadget.udc = NULL;
679 dwc2_hsotg_remove(hsotg);
680 goto error_debugfs;
681 }
682 }
683 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
684 return 0;
685
686 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
687 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
688 error_debugfs:
689 dwc2_debugfs_exit(hsotg);
690 if (hsotg->hcd_enabled)
691 dwc2_hcd_remove(hsotg);
692 #endif
693 error_drd:
694 dwc2_drd_exit(hsotg);
695
696 error_init:
697 if (hsotg->params.activate_stm_id_vb_detection)
698 regulator_disable(hsotg->usb33d);
699 error:
700 pm_runtime_put_sync(hsotg->dev);
701 pm_runtime_disable(hsotg->dev);
702 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL)
703 dwc2_lowlevel_hw_disable(hsotg);
704 return retval;
705 }
706
dwc2_suspend(struct device * dev)707 static int __maybe_unused dwc2_suspend(struct device *dev)
708 {
709 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
710 bool is_device_mode = dwc2_is_device_mode(dwc2);
711 int ret = 0;
712
713 if (is_device_mode)
714 dwc2_hsotg_suspend(dwc2);
715
716 dwc2_drd_suspend(dwc2);
717
718 if (dwc2->params.activate_stm_id_vb_detection) {
719 unsigned long flags;
720 u32 ggpio, gotgctl;
721
722 /*
723 * Need to force the mode to the current mode to avoid Mode
724 * Mismatch Interrupt when ID detection will be disabled.
725 */
726 dwc2_force_mode(dwc2, !is_device_mode);
727
728 spin_lock_irqsave(&dwc2->lock, flags);
729 gotgctl = dwc2_readl(dwc2, GOTGCTL);
730 /* bypass debounce filter, enable overrides */
731 gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
732 gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
733 /* Force A / B session if needed */
734 if (gotgctl & GOTGCTL_ASESVLD)
735 gotgctl |= GOTGCTL_AVALOVAL;
736 if (gotgctl & GOTGCTL_BSESVLD)
737 gotgctl |= GOTGCTL_BVALOVAL;
738 dwc2_writel(dwc2, gotgctl, GOTGCTL);
739 spin_unlock_irqrestore(&dwc2->lock, flags);
740
741 ggpio = dwc2_readl(dwc2, GGPIO);
742 ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
743 ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
744 dwc2_writel(dwc2, ggpio, GGPIO);
745
746 regulator_disable(dwc2->usb33d);
747 }
748
749 if (dwc2->ll_hw_enabled &&
750 (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
751 ret = __dwc2_lowlevel_hw_disable(dwc2);
752 dwc2->phy_off_for_suspend = true;
753 }
754
755 return ret;
756 }
757
dwc2_resume(struct device * dev)758 static int __maybe_unused dwc2_resume(struct device *dev)
759 {
760 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
761 unsigned long flags;
762 int ret = 0;
763
764 if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
765 ret = __dwc2_lowlevel_hw_enable(dwc2);
766 if (ret)
767 return ret;
768 }
769 dwc2->phy_off_for_suspend = false;
770
771 if (dwc2->params.activate_stm_id_vb_detection) {
772 unsigned long flags;
773 u32 ggpio, gotgctl;
774
775 ret = regulator_enable(dwc2->usb33d);
776 if (ret)
777 return ret;
778
779 ggpio = dwc2_readl(dwc2, GGPIO);
780 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
781 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
782 dwc2_writel(dwc2, ggpio, GGPIO);
783
784 /* ID/VBUS detection startup time */
785 usleep_range(5000, 7000);
786
787 spin_lock_irqsave(&dwc2->lock, flags);
788 gotgctl = dwc2_readl(dwc2, GOTGCTL);
789 gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
790 gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
791 GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
792 dwc2_writel(dwc2, gotgctl, GOTGCTL);
793 spin_unlock_irqrestore(&dwc2->lock, flags);
794 }
795
796 /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
797 dwc2_force_dr_mode(dwc2);
798
799 dwc2_drd_resume(dwc2);
800
801 if (dwc2->dr_mode == USB_DR_MODE_HOST && dwc2_is_device_mode(dwc2)) {
802 /* Reinit for Host mode if lost power */
803 dwc2_force_mode(dwc2, true);
804
805 spin_lock_irqsave(&dwc2->lock, flags);
806 dwc2_hsotg_disconnect(dwc2);
807 spin_unlock_irqrestore(&dwc2->lock, flags);
808
809 dwc2->op_state = OTG_STATE_A_HOST;
810 /* Initialize the Core for Host mode */
811 dwc2_core_init(dwc2, false);
812 dwc2_enable_global_interrupts(dwc2);
813 dwc2_hcd_start(dwc2);
814 } else if (dwc2->dr_mode == USB_DR_MODE_OTG &&
815 dwc2->op_state == OTG_STATE_A_HOST &&
816 !(dwc2_readl(dwc2, HPRT0) & HPRT0_PWR)) {
817 /*
818 * Reinit the core to device mode, and later
819 * after do dwc2_hsotg_resume, it can trigger
820 * the ID status change interrupt if the OTG
821 * cable is still connected, then we can init
822 * for Host mode in the ID status change
823 * interrupt handler.
824 */
825 spin_lock_irqsave(&dwc2->lock, flags);
826 dwc2_hcd_disconnect(dwc2, true);
827 dwc2->op_state = OTG_STATE_B_PERIPHERAL;
828 dwc2->lx_state = DWC2_L3;
829 if (!dwc2->driver)
830 dwc2_hsotg_core_init_disconnected(dwc2, false);
831 spin_unlock_irqrestore(&dwc2->lock, flags);
832
833 ret = dwc2_hsotg_resume(dwc2);
834 } else if (dwc2_is_device_mode(dwc2) ||
835 (dwc2_is_host_mode(dwc2) &&
836 dwc2->dr_mode == USB_DR_MODE_OTG &&
837 dwc2->op_state == OTG_STATE_B_PERIPHERAL)) {
838 ret = dwc2_hsotg_resume(dwc2);
839 }
840
841 return ret;
842 }
843
844 static const struct dev_pm_ops dwc2_dev_pm_ops = {
845 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
846 };
847
848 static struct platform_driver dwc2_platform_driver = {
849 .driver = {
850 .name = dwc2_driver_name,
851 .of_match_table = dwc2_of_match_table,
852 .pm = &dwc2_dev_pm_ops,
853 },
854 .probe = dwc2_driver_probe,
855 .remove = dwc2_driver_remove,
856 .shutdown = dwc2_driver_shutdown,
857 };
858
859 module_platform_driver(dwc2_platform_driver);
860
861 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
862 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
863 MODULE_LICENSE("Dual BSD/GPL");
864