1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * This file contains the interrupt handlers for Host mode
40 */
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/io.h>
47 #include <linux/slab.h>
48 #include <linux/usb.h>
49
50 #include <linux/usb/hcd.h>
51 #include <linux/usb/ch11.h>
52
53 #include "core.h"
54 #include "hcd.h"
55
56 /*
57 * If we get this many NAKs on a split transaction we'll slow down
58 * retransmission. A 1 here means delay after the first NAK.
59 */
60 #define DWC2_NAKS_BEFORE_DELAY 3
61
62 /* This function is for debug only */
dwc2_track_missed_sofs(struct dwc2_hsotg * hsotg)63 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
64 {
65 u16 curr_frame_number = hsotg->frame_number;
66 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
67
68 if (expected != curr_frame_number)
69 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
70 expected, curr_frame_number);
71
72 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
73 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
74 if (expected != curr_frame_number) {
75 hsotg->frame_num_array[hsotg->frame_num_idx] =
76 curr_frame_number;
77 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
78 hsotg->last_frame_num;
79 hsotg->frame_num_idx++;
80 }
81 } else if (!hsotg->dumped_frame_num_array) {
82 int i;
83
84 dev_info(hsotg->dev, "Frame Last Frame\n");
85 dev_info(hsotg->dev, "----- ----------\n");
86 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
87 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
88 hsotg->frame_num_array[i],
89 hsotg->last_frame_num_array[i]);
90 }
91 hsotg->dumped_frame_num_array = 1;
92 }
93 #endif
94 hsotg->last_frame_num = curr_frame_number;
95 }
96
dwc2_hc_handle_tt_clear(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,struct dwc2_qtd * qtd)97 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
98 struct dwc2_host_chan *chan,
99 struct dwc2_qtd *qtd)
100 {
101 struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
102 struct urb *usb_urb;
103
104 if (!chan->qh)
105 return;
106
107 if (chan->qh->dev_speed == USB_SPEED_HIGH)
108 return;
109
110 if (!qtd->urb)
111 return;
112
113 usb_urb = qtd->urb->priv;
114 if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
115 return;
116
117 /*
118 * The root hub doesn't really have a TT, but Linux thinks it
119 * does because how could you have a "high speed hub" that
120 * directly talks directly to low speed devices without a TT?
121 * It's all lies. Lies, I tell you.
122 */
123 if (usb_urb->dev->tt->hub == root_hub)
124 return;
125
126 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
127 chan->qh->tt_buffer_dirty = 1;
128 if (usb_hub_clear_tt_buffer(usb_urb))
129 /* Clear failed; let's hope things work anyway */
130 chan->qh->tt_buffer_dirty = 0;
131 }
132 }
133
134 /*
135 * Handles the start-of-frame interrupt in host mode. Non-periodic
136 * transactions may be queued to the DWC_otg controller for the current
137 * (micro)frame. Periodic transactions may be queued to the controller
138 * for the next (micro)frame.
139 */
dwc2_sof_intr(struct dwc2_hsotg * hsotg)140 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
141 {
142 struct list_head *qh_entry;
143 struct dwc2_qh *qh;
144 enum dwc2_transaction_type tr_type;
145
146 /* Clear interrupt */
147 dwc2_writel(hsotg, GINTSTS_SOF, GINTSTS);
148
149 #ifdef DEBUG_SOF
150 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
151 #endif
152
153 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
154
155 dwc2_track_missed_sofs(hsotg);
156
157 /* Determine whether any periodic QHs should be executed */
158 qh_entry = hsotg->periodic_sched_inactive.next;
159 while (qh_entry != &hsotg->periodic_sched_inactive) {
160 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
161 qh_entry = qh_entry->next;
162 if (dwc2_frame_num_le(qh->next_active_frame,
163 hsotg->frame_number)) {
164 dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
165 qh, hsotg->frame_number,
166 qh->next_active_frame);
167
168 /*
169 * Move QH to the ready list to be executed next
170 * (micro)frame
171 */
172 list_move_tail(&qh->qh_list_entry,
173 &hsotg->periodic_sched_ready);
174 }
175 }
176 tr_type = dwc2_hcd_select_transactions(hsotg);
177 if (tr_type != DWC2_TRANSACTION_NONE)
178 dwc2_hcd_queue_transactions(hsotg, tr_type);
179 }
180
181 /*
182 * Handles the Rx FIFO Level Interrupt, which indicates that there is
183 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
184 * memory if the DWC_otg controller is operating in Slave mode.
185 */
dwc2_rx_fifo_level_intr(struct dwc2_hsotg * hsotg)186 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
187 {
188 u32 grxsts, chnum, bcnt, dpid, pktsts;
189 struct dwc2_host_chan *chan;
190
191 if (dbg_perio())
192 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
193
194 grxsts = dwc2_readl(hsotg, GRXSTSP);
195 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
196 chan = hsotg->hc_ptr_array[chnum];
197 if (!chan) {
198 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
199 return;
200 }
201
202 bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
203 dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
204 pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
205
206 /* Packet Status */
207 if (dbg_perio()) {
208 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
209 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
210 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
211 chan->data_pid_start);
212 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
213 }
214
215 switch (pktsts) {
216 case GRXSTS_PKTSTS_HCHIN:
217 /* Read the data into the host buffer */
218 if (bcnt > 0) {
219 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
220
221 /* Update the HC fields for the next packet received */
222 chan->xfer_count += bcnt;
223 chan->xfer_buf += bcnt;
224 }
225 break;
226 case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
227 case GRXSTS_PKTSTS_DATATOGGLEERR:
228 case GRXSTS_PKTSTS_HCHHALTED:
229 /* Handled in interrupt, just ignore data */
230 break;
231 default:
232 dev_err(hsotg->dev,
233 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
234 break;
235 }
236 }
237
238 /*
239 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
240 * data packets may be written to the FIFO for OUT transfers. More requests
241 * may be written to the non-periodic request queue for IN transfers. This
242 * interrupt is enabled only in Slave mode.
243 */
dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg * hsotg)244 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
245 {
246 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
247 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
248 }
249
250 /*
251 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
252 * packets may be written to the FIFO for OUT transfers. More requests may be
253 * written to the periodic request queue for IN transfers. This interrupt is
254 * enabled only in Slave mode.
255 */
dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg * hsotg)256 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
257 {
258 if (dbg_perio())
259 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
260 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
261 }
262
dwc2_hprt0_enable(struct dwc2_hsotg * hsotg,u32 hprt0,u32 * hprt0_modify)263 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
264 u32 *hprt0_modify)
265 {
266 struct dwc2_core_params *params = &hsotg->params;
267 int do_reset = 0;
268 u32 usbcfg;
269 u32 prtspd;
270 u32 hcfg;
271 u32 fslspclksel;
272 u32 hfir;
273
274 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
275
276 /* Every time when port enables calculate HFIR.FrInterval */
277 hfir = dwc2_readl(hsotg, HFIR);
278 hfir &= ~HFIR_FRINT_MASK;
279 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
280 HFIR_FRINT_MASK;
281 dwc2_writel(hsotg, hfir, HFIR);
282
283 /* Check if we need to adjust the PHY clock speed for low power */
284 if (!params->host_support_fs_ls_low_power) {
285 /* Port has been enabled, set the reset change flag */
286 hsotg->flags.b.port_reset_change = 1;
287 return;
288 }
289
290 usbcfg = dwc2_readl(hsotg, GUSBCFG);
291 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
292
293 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
294 /* Low power */
295 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
296 /* Set PHY low power clock select for FS/LS devices */
297 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
298 dwc2_writel(hsotg, usbcfg, GUSBCFG);
299 do_reset = 1;
300 }
301
302 hcfg = dwc2_readl(hsotg, HCFG);
303 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
304 HCFG_FSLSPCLKSEL_SHIFT;
305
306 if (prtspd == HPRT0_SPD_LOW_SPEED &&
307 params->host_ls_low_power_phy_clk) {
308 /* 6 MHZ */
309 dev_vdbg(hsotg->dev,
310 "FS_PHY programming HCFG to 6 MHz\n");
311 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
312 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
313 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
314 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
315 dwc2_writel(hsotg, hcfg, HCFG);
316 do_reset = 1;
317 }
318 } else {
319 /* 48 MHZ */
320 dev_vdbg(hsotg->dev,
321 "FS_PHY programming HCFG to 48 MHz\n");
322 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
323 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
324 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
325 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
326 dwc2_writel(hsotg, hcfg, HCFG);
327 do_reset = 1;
328 }
329 }
330 } else {
331 /* Not low power */
332 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
333 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
334 dwc2_writel(hsotg, usbcfg, GUSBCFG);
335 do_reset = 1;
336 }
337 }
338
339 if (do_reset) {
340 *hprt0_modify |= HPRT0_RST;
341 dwc2_writel(hsotg, *hprt0_modify, HPRT0);
342 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
343 msecs_to_jiffies(60));
344 } else {
345 /* Port has been enabled, set the reset change flag */
346 hsotg->flags.b.port_reset_change = 1;
347 }
348 }
349
350 /*
351 * There are multiple conditions that can cause a port interrupt. This function
352 * determines which interrupt conditions have occurred and handles them
353 * appropriately.
354 */
dwc2_port_intr(struct dwc2_hsotg * hsotg)355 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
356 {
357 u32 hprt0;
358 u32 hprt0_modify;
359
360 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
361
362 hprt0 = dwc2_readl(hsotg, HPRT0);
363 hprt0_modify = hprt0;
364
365 /*
366 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
367 * GINTSTS
368 */
369 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
370 HPRT0_OVRCURRCHG);
371
372 /*
373 * Port Connect Detected
374 * Set flag and clear if detected
375 */
376 if (hprt0 & HPRT0_CONNDET) {
377 dwc2_writel(hsotg, hprt0_modify | HPRT0_CONNDET, HPRT0);
378
379 dev_vdbg(hsotg->dev,
380 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
381 hprt0);
382 dwc2_hcd_connect(hsotg);
383
384 /*
385 * The Hub driver asserts a reset when it sees port connect
386 * status change flag
387 */
388 }
389
390 /*
391 * Port Enable Changed
392 * Clear if detected - Set internal flag if disabled
393 */
394 if (hprt0 & HPRT0_ENACHG) {
395 dwc2_writel(hsotg, hprt0_modify | HPRT0_ENACHG, HPRT0);
396 dev_vdbg(hsotg->dev,
397 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
398 hprt0, !!(hprt0 & HPRT0_ENA));
399 if (hprt0 & HPRT0_ENA) {
400 hsotg->new_connection = true;
401 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
402 } else {
403 hsotg->flags.b.port_enable_change = 1;
404 if (hsotg->params.dma_desc_fs_enable) {
405 u32 hcfg;
406
407 hsotg->params.dma_desc_enable = false;
408 hsotg->new_connection = false;
409 hcfg = dwc2_readl(hsotg, HCFG);
410 hcfg &= ~HCFG_DESCDMA;
411 dwc2_writel(hsotg, hcfg, HCFG);
412 }
413 }
414 }
415
416 /* Overcurrent Change Interrupt */
417 if (hprt0 & HPRT0_OVRCURRCHG) {
418 dwc2_writel(hsotg, hprt0_modify | HPRT0_OVRCURRCHG,
419 HPRT0);
420 dev_vdbg(hsotg->dev,
421 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
422 hprt0);
423 hsotg->flags.b.port_over_current_change = 1;
424 }
425 }
426
427 /*
428 * Gets the actual length of a transfer after the transfer halts. halt_status
429 * holds the reason for the halt.
430 *
431 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
432 * is set to 1 upon return if less than the requested number of bytes were
433 * transferred. short_read may also be NULL on entry, in which case it remains
434 * unchanged.
435 */
dwc2_get_actual_xfer_length(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status,int * short_read)436 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
437 struct dwc2_host_chan *chan, int chnum,
438 struct dwc2_qtd *qtd,
439 enum dwc2_halt_status halt_status,
440 int *short_read)
441 {
442 u32 hctsiz, count, length;
443
444 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
445
446 if (halt_status == DWC2_HC_XFER_COMPLETE) {
447 if (chan->ep_is_in) {
448 count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
449 TSIZ_XFERSIZE_SHIFT;
450 length = chan->xfer_len - count;
451 if (short_read)
452 *short_read = (count != 0);
453 } else if (chan->qh->do_split) {
454 length = qtd->ssplit_out_xfer_count;
455 } else {
456 length = chan->xfer_len;
457 }
458 } else {
459 /*
460 * Must use the hctsiz.pktcnt field to determine how much data
461 * has been transferred. This field reflects the number of
462 * packets that have been transferred via the USB. This is
463 * always an integral number of packets if the transfer was
464 * halted before its normal completion. (Can't use the
465 * hctsiz.xfersize field because that reflects the number of
466 * bytes transferred via the AHB, not the USB).
467 */
468 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
469 length = (chan->start_pkt_count - count) * chan->max_packet;
470 }
471
472 return length;
473 }
474
475 /**
476 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
477 * Complete interrupt on the host channel. Updates the actual_length field
478 * of the URB based on the number of bytes transferred via the host channel.
479 * Sets the URB status if the data transfer is finished.
480 *
481 * @hsotg: Programming view of the DWC_otg controller
482 * @chan: Programming view of host channel
483 * @chnum: Channel number
484 * @urb: Processing URB
485 * @qtd: Queue transfer descriptor
486 *
487 * Return: 1 if the data transfer specified by the URB is completely finished,
488 * 0 otherwise
489 */
dwc2_update_urb_state(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_hcd_urb * urb,struct dwc2_qtd * qtd)490 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
491 struct dwc2_host_chan *chan, int chnum,
492 struct dwc2_hcd_urb *urb,
493 struct dwc2_qtd *qtd)
494 {
495 u32 hctsiz;
496 int xfer_done = 0;
497 int short_read = 0;
498 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
499 DWC2_HC_XFER_COMPLETE,
500 &short_read);
501
502 if (urb->actual_length + xfer_length > urb->length) {
503 dev_dbg(hsotg->dev, "%s(): trimming xfer length\n", __func__);
504 xfer_length = urb->length - urb->actual_length;
505 }
506
507 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
508 urb->actual_length, xfer_length);
509 urb->actual_length += xfer_length;
510
511 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
512 (urb->flags & URB_SEND_ZERO_PACKET) &&
513 urb->actual_length >= urb->length &&
514 !(urb->length % chan->max_packet)) {
515 xfer_done = 0;
516 } else if (short_read || urb->actual_length >= urb->length) {
517 xfer_done = 1;
518 urb->status = 0;
519 }
520
521 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
522 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
523 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
524 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
525 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
526 (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
527 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
528 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
529 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
530 xfer_done);
531
532 return xfer_done;
533 }
534
535 /*
536 * Save the starting data toggle for the next transfer. The data toggle is
537 * saved in the QH for non-control transfers and it's saved in the QTD for
538 * control transfers.
539 */
dwc2_hcd_save_data_toggle(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)540 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
541 struct dwc2_host_chan *chan, int chnum,
542 struct dwc2_qtd *qtd)
543 {
544 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
545 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
546
547 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
548 if (WARN(!chan || !chan->qh,
549 "chan->qh must be specified for non-control eps\n"))
550 return;
551
552 if (pid == TSIZ_SC_MC_PID_DATA0)
553 chan->qh->data_toggle = DWC2_HC_PID_DATA0;
554 else
555 chan->qh->data_toggle = DWC2_HC_PID_DATA1;
556 } else {
557 if (WARN(!qtd,
558 "qtd must be specified for control eps\n"))
559 return;
560
561 if (pid == TSIZ_SC_MC_PID_DATA0)
562 qtd->data_toggle = DWC2_HC_PID_DATA0;
563 else
564 qtd->data_toggle = DWC2_HC_PID_DATA1;
565 }
566 }
567
568 /**
569 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
570 * the transfer is stopped for any reason. The fields of the current entry in
571 * the frame descriptor array are set based on the transfer state and the input
572 * halt_status. Completes the Isochronous URB if all the URB frames have been
573 * completed.
574 *
575 * @hsotg: Programming view of the DWC_otg controller
576 * @chan: Programming view of host channel
577 * @chnum: Channel number
578 * @halt_status: Reason for halting a host channel
579 * @qtd: Queue transfer descriptor
580 *
581 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
582 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
583 */
dwc2_update_isoc_urb_state(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)584 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
585 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
586 int chnum, struct dwc2_qtd *qtd,
587 enum dwc2_halt_status halt_status)
588 {
589 struct dwc2_hcd_iso_packet_desc *frame_desc;
590 struct dwc2_hcd_urb *urb = qtd->urb;
591
592 if (!urb)
593 return DWC2_HC_XFER_NO_HALT_STATUS;
594
595 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
596
597 switch (halt_status) {
598 case DWC2_HC_XFER_COMPLETE:
599 frame_desc->status = 0;
600 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
601 chan, chnum, qtd, halt_status, NULL);
602 break;
603 case DWC2_HC_XFER_FRAME_OVERRUN:
604 urb->error_count++;
605 if (chan->ep_is_in)
606 frame_desc->status = -ENOSR;
607 else
608 frame_desc->status = -ECOMM;
609 frame_desc->actual_length = 0;
610 break;
611 case DWC2_HC_XFER_BABBLE_ERR:
612 urb->error_count++;
613 frame_desc->status = -EOVERFLOW;
614 /* Don't need to update actual_length in this case */
615 break;
616 case DWC2_HC_XFER_XACT_ERR:
617 urb->error_count++;
618 frame_desc->status = -EPROTO;
619 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
620 chan, chnum, qtd, halt_status, NULL);
621
622 /* Skip whole frame */
623 if (chan->qh->do_split &&
624 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
625 hsotg->params.host_dma) {
626 qtd->complete_split = 0;
627 qtd->isoc_split_offset = 0;
628 }
629
630 break;
631 default:
632 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
633 halt_status);
634 break;
635 }
636
637 if (++qtd->isoc_frame_index == urb->packet_count) {
638 /*
639 * urb->status is not used for isoc transfers. The individual
640 * frame_desc statuses are used instead.
641 */
642 dwc2_host_complete(hsotg, qtd, 0);
643 halt_status = DWC2_HC_XFER_URB_COMPLETE;
644 } else {
645 halt_status = DWC2_HC_XFER_COMPLETE;
646 }
647
648 return halt_status;
649 }
650
651 /*
652 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
653 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
654 * still linked to the QH, the QH is added to the end of the inactive
655 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
656 * schedule if no more QTDs are linked to the QH.
657 */
dwc2_deactivate_qh(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,int free_qtd)658 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
659 int free_qtd)
660 {
661 int continue_split = 0;
662 struct dwc2_qtd *qtd;
663
664 if (dbg_qh(qh))
665 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
666 hsotg, qh, free_qtd);
667
668 if (list_empty(&qh->qtd_list)) {
669 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
670 goto no_qtd;
671 }
672
673 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
674
675 if (qtd->complete_split)
676 continue_split = 1;
677 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
678 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
679 continue_split = 1;
680
681 if (free_qtd) {
682 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
683 continue_split = 0;
684 }
685
686 no_qtd:
687 qh->channel = NULL;
688 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
689 }
690
691 /**
692 * dwc2_release_channel() - Releases a host channel for use by other transfers
693 *
694 * @hsotg: The HCD state structure
695 * @chan: The host channel to release
696 * @qtd: The QTD associated with the host channel. This QTD may be
697 * freed if the transfer is complete or an error has occurred.
698 * @halt_status: Reason the channel is being released. This status
699 * determines the actions taken by this function.
700 *
701 * Also attempts to select and queue more transactions since at least one host
702 * channel is available.
703 */
dwc2_release_channel(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)704 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
705 struct dwc2_host_chan *chan,
706 struct dwc2_qtd *qtd,
707 enum dwc2_halt_status halt_status)
708 {
709 enum dwc2_transaction_type tr_type;
710 u32 haintmsk;
711 int free_qtd = 0;
712
713 if (dbg_hc(chan))
714 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
715 __func__, chan->hc_num, halt_status);
716
717 switch (halt_status) {
718 case DWC2_HC_XFER_URB_COMPLETE:
719 free_qtd = 1;
720 break;
721 case DWC2_HC_XFER_AHB_ERR:
722 case DWC2_HC_XFER_STALL:
723 case DWC2_HC_XFER_BABBLE_ERR:
724 free_qtd = 1;
725 break;
726 case DWC2_HC_XFER_XACT_ERR:
727 if (qtd && qtd->error_count >= 3) {
728 dev_vdbg(hsotg->dev,
729 " Complete URB with transaction error\n");
730 free_qtd = 1;
731 dwc2_host_complete(hsotg, qtd, -EPROTO);
732 }
733 break;
734 case DWC2_HC_XFER_URB_DEQUEUE:
735 /*
736 * The QTD has already been removed and the QH has been
737 * deactivated. Don't want to do anything except release the
738 * host channel and try to queue more transfers.
739 */
740 goto cleanup;
741 case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
742 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
743 free_qtd = 1;
744 dwc2_host_complete(hsotg, qtd, -EIO);
745 break;
746 case DWC2_HC_XFER_NO_HALT_STATUS:
747 default:
748 break;
749 }
750
751 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
752
753 cleanup:
754 /*
755 * Release the host channel for use by other transfers. The cleanup
756 * function clears the channel interrupt enables and conditions, so
757 * there's no need to clear the Channel Halted interrupt separately.
758 */
759 if (!list_empty(&chan->hc_list_entry))
760 list_del(&chan->hc_list_entry);
761 dwc2_hc_cleanup(hsotg, chan);
762 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
763
764 if (hsotg->params.uframe_sched) {
765 hsotg->available_host_channels++;
766 } else {
767 switch (chan->ep_type) {
768 case USB_ENDPOINT_XFER_CONTROL:
769 case USB_ENDPOINT_XFER_BULK:
770 hsotg->non_periodic_channels--;
771 break;
772 default:
773 /*
774 * Don't release reservations for periodic channels
775 * here. That's done when a periodic transfer is
776 * descheduled (i.e. when the QH is removed from the
777 * periodic schedule).
778 */
779 break;
780 }
781 }
782
783 haintmsk = dwc2_readl(hsotg, HAINTMSK);
784 haintmsk &= ~(1 << chan->hc_num);
785 dwc2_writel(hsotg, haintmsk, HAINTMSK);
786
787 /* Try to queue more transfers now that there's a free channel */
788 tr_type = dwc2_hcd_select_transactions(hsotg);
789 if (tr_type != DWC2_TRANSACTION_NONE)
790 dwc2_hcd_queue_transactions(hsotg, tr_type);
791 }
792
793 /*
794 * Halts a host channel. If the channel cannot be halted immediately because
795 * the request queue is full, this function ensures that the FIFO empty
796 * interrupt for the appropriate queue is enabled so that the halt request can
797 * be queued when there is space in the request queue.
798 *
799 * This function may also be called in DMA mode. In that case, the channel is
800 * simply released since the core always halts the channel automatically in
801 * DMA mode.
802 */
dwc2_halt_channel(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)803 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
804 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
805 enum dwc2_halt_status halt_status)
806 {
807 if (dbg_hc(chan))
808 dev_vdbg(hsotg->dev, "%s()\n", __func__);
809
810 if (hsotg->params.host_dma) {
811 if (dbg_hc(chan))
812 dev_vdbg(hsotg->dev, "DMA enabled\n");
813 dwc2_release_channel(hsotg, chan, qtd, halt_status);
814 return;
815 }
816
817 /* Slave mode processing */
818 dwc2_hc_halt(hsotg, chan, halt_status);
819
820 if (chan->halt_on_queue) {
821 u32 gintmsk;
822
823 dev_vdbg(hsotg->dev, "Halt on queue\n");
824 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
825 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
826 dev_vdbg(hsotg->dev, "control/bulk\n");
827 /*
828 * Make sure the Non-periodic Tx FIFO empty interrupt
829 * is enabled so that the non-periodic schedule will
830 * be processed
831 */
832 gintmsk = dwc2_readl(hsotg, GINTMSK);
833 gintmsk |= GINTSTS_NPTXFEMP;
834 dwc2_writel(hsotg, gintmsk, GINTMSK);
835 } else {
836 dev_vdbg(hsotg->dev, "isoc/intr\n");
837 /*
838 * Move the QH from the periodic queued schedule to
839 * the periodic assigned schedule. This allows the
840 * halt to be queued when the periodic schedule is
841 * processed.
842 */
843 list_move_tail(&chan->qh->qh_list_entry,
844 &hsotg->periodic_sched_assigned);
845
846 /*
847 * Make sure the Periodic Tx FIFO Empty interrupt is
848 * enabled so that the periodic schedule will be
849 * processed
850 */
851 gintmsk = dwc2_readl(hsotg, GINTMSK);
852 gintmsk |= GINTSTS_PTXFEMP;
853 dwc2_writel(hsotg, gintmsk, GINTMSK);
854 }
855 }
856 }
857
858 /*
859 * Performs common cleanup for non-periodic transfers after a Transfer
860 * Complete interrupt. This function should be called after any endpoint type
861 * specific handling is finished to release the host channel.
862 */
dwc2_complete_non_periodic_xfer(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)863 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
864 struct dwc2_host_chan *chan,
865 int chnum, struct dwc2_qtd *qtd,
866 enum dwc2_halt_status halt_status)
867 {
868 dev_vdbg(hsotg->dev, "%s()\n", __func__);
869
870 qtd->error_count = 0;
871
872 if (chan->hcint & HCINTMSK_NYET) {
873 /*
874 * Got a NYET on the last transaction of the transfer. This
875 * means that the endpoint should be in the PING state at the
876 * beginning of the next transfer.
877 */
878 dev_vdbg(hsotg->dev, "got NYET\n");
879 chan->qh->ping_state = 1;
880 }
881
882 /*
883 * Always halt and release the host channel to make it available for
884 * more transfers. There may still be more phases for a control
885 * transfer or more data packets for a bulk transfer at this point,
886 * but the host channel is still halted. A channel will be reassigned
887 * to the transfer when the non-periodic schedule is processed after
888 * the channel is released. This allows transactions to be queued
889 * properly via dwc2_hcd_queue_transactions, which also enables the
890 * Tx FIFO Empty interrupt if necessary.
891 */
892 if (chan->ep_is_in) {
893 /*
894 * IN transfers in Slave mode require an explicit disable to
895 * halt the channel. (In DMA mode, this call simply releases
896 * the channel.)
897 */
898 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
899 } else {
900 /*
901 * The channel is automatically disabled by the core for OUT
902 * transfers in Slave mode
903 */
904 dwc2_release_channel(hsotg, chan, qtd, halt_status);
905 }
906 }
907
908 /*
909 * Performs common cleanup for periodic transfers after a Transfer Complete
910 * interrupt. This function should be called after any endpoint type specific
911 * handling is finished to release the host channel.
912 */
dwc2_complete_periodic_xfer(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)913 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
914 struct dwc2_host_chan *chan, int chnum,
915 struct dwc2_qtd *qtd,
916 enum dwc2_halt_status halt_status)
917 {
918 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
919
920 qtd->error_count = 0;
921
922 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
923 /* Core halts channel in these cases */
924 dwc2_release_channel(hsotg, chan, qtd, halt_status);
925 else
926 /* Flush any outstanding requests from the Tx queue */
927 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
928 }
929
dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)930 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
931 struct dwc2_host_chan *chan, int chnum,
932 struct dwc2_qtd *qtd)
933 {
934 struct dwc2_hcd_iso_packet_desc *frame_desc;
935 u32 len;
936 u32 hctsiz;
937 u32 pid;
938
939 if (!qtd->urb)
940 return 0;
941
942 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
943 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
944 DWC2_HC_XFER_COMPLETE, NULL);
945 if (!len && !qtd->isoc_split_offset) {
946 qtd->complete_split = 0;
947 return 0;
948 }
949
950 frame_desc->actual_length += len;
951
952 if (chan->align_buf) {
953 dev_vdbg(hsotg->dev, "non-aligned buffer\n");
954 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
955 DWC2_KMEM_UNALIGNED_BUF_SIZE, DMA_FROM_DEVICE);
956 memcpy(qtd->urb->buf + (chan->xfer_dma - qtd->urb->dma),
957 chan->qh->dw_align_buf, len);
958 }
959
960 qtd->isoc_split_offset += len;
961
962 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
963 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
964
965 if (frame_desc->actual_length >= frame_desc->length || pid == 0) {
966 frame_desc->status = 0;
967 qtd->isoc_frame_index++;
968 qtd->complete_split = 0;
969 qtd->isoc_split_offset = 0;
970 }
971
972 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
973 dwc2_host_complete(hsotg, qtd, 0);
974 dwc2_release_channel(hsotg, chan, qtd,
975 DWC2_HC_XFER_URB_COMPLETE);
976 } else {
977 dwc2_release_channel(hsotg, chan, qtd,
978 DWC2_HC_XFER_NO_HALT_STATUS);
979 }
980
981 return 1; /* Indicates that channel released */
982 }
983
984 /*
985 * Handles a host channel Transfer Complete interrupt. This handler may be
986 * called in either DMA mode or Slave mode.
987 */
dwc2_hc_xfercomp_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)988 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
989 struct dwc2_host_chan *chan, int chnum,
990 struct dwc2_qtd *qtd)
991 {
992 struct dwc2_hcd_urb *urb = qtd->urb;
993 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
994 int pipe_type;
995 int urb_xfer_done;
996
997 if (dbg_hc(chan))
998 dev_vdbg(hsotg->dev,
999 "--Host Channel %d Interrupt: Transfer Complete--\n",
1000 chnum);
1001
1002 if (!urb)
1003 goto handle_xfercomp_done;
1004
1005 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1006
1007 if (hsotg->params.dma_desc_enable) {
1008 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
1009 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
1010 /* Do not disable the interrupt, just clear it */
1011 return;
1012 goto handle_xfercomp_done;
1013 }
1014
1015 /* Handle xfer complete on CSPLIT */
1016 if (chan->qh->do_split) {
1017 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
1018 hsotg->params.host_dma) {
1019 if (qtd->complete_split &&
1020 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1021 qtd))
1022 goto handle_xfercomp_done;
1023 } else {
1024 qtd->complete_split = 0;
1025 }
1026 }
1027
1028 /* Update the QTD and URB states */
1029 switch (pipe_type) {
1030 case USB_ENDPOINT_XFER_CONTROL:
1031 switch (qtd->control_phase) {
1032 case DWC2_CONTROL_SETUP:
1033 if (urb->length > 0)
1034 qtd->control_phase = DWC2_CONTROL_DATA;
1035 else
1036 qtd->control_phase = DWC2_CONTROL_STATUS;
1037 dev_vdbg(hsotg->dev,
1038 " Control setup transaction done\n");
1039 halt_status = DWC2_HC_XFER_COMPLETE;
1040 break;
1041 case DWC2_CONTROL_DATA:
1042 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1043 chnum, urb, qtd);
1044 if (urb_xfer_done) {
1045 qtd->control_phase = DWC2_CONTROL_STATUS;
1046 dev_vdbg(hsotg->dev,
1047 " Control data transfer done\n");
1048 } else {
1049 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1050 qtd);
1051 }
1052 halt_status = DWC2_HC_XFER_COMPLETE;
1053 break;
1054 case DWC2_CONTROL_STATUS:
1055 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1056 if (urb->status == -EINPROGRESS)
1057 urb->status = 0;
1058 dwc2_host_complete(hsotg, qtd, urb->status);
1059 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1060 break;
1061 }
1062
1063 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1064 halt_status);
1065 break;
1066 case USB_ENDPOINT_XFER_BULK:
1067 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1068 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1069 qtd);
1070 if (urb_xfer_done) {
1071 dwc2_host_complete(hsotg, qtd, urb->status);
1072 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1073 } else {
1074 halt_status = DWC2_HC_XFER_COMPLETE;
1075 }
1076
1077 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1078 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1079 halt_status);
1080 break;
1081 case USB_ENDPOINT_XFER_INT:
1082 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1083 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1084 qtd);
1085
1086 /*
1087 * Interrupt URB is done on the first transfer complete
1088 * interrupt
1089 */
1090 if (urb_xfer_done) {
1091 dwc2_host_complete(hsotg, qtd, urb->status);
1092 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1093 } else {
1094 halt_status = DWC2_HC_XFER_COMPLETE;
1095 }
1096
1097 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1098 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1099 halt_status);
1100 break;
1101 case USB_ENDPOINT_XFER_ISOC:
1102 if (dbg_perio())
1103 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1104 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1105 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1106 chnum, qtd,
1107 DWC2_HC_XFER_COMPLETE);
1108 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1109 halt_status);
1110 break;
1111 }
1112
1113 handle_xfercomp_done:
1114 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1115 }
1116
1117 /*
1118 * Handles a host channel STALL interrupt. This handler may be called in
1119 * either DMA mode or Slave mode.
1120 */
dwc2_hc_stall_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1121 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1122 struct dwc2_host_chan *chan, int chnum,
1123 struct dwc2_qtd *qtd)
1124 {
1125 struct dwc2_hcd_urb *urb = qtd->urb;
1126 int pipe_type;
1127
1128 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1129 chnum);
1130
1131 if (hsotg->params.dma_desc_enable) {
1132 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1133 DWC2_HC_XFER_STALL);
1134 goto handle_stall_done;
1135 }
1136
1137 if (!urb)
1138 goto handle_stall_halt;
1139
1140 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1141
1142 if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1143 dwc2_host_complete(hsotg, qtd, -EPIPE);
1144
1145 if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1146 pipe_type == USB_ENDPOINT_XFER_INT) {
1147 dwc2_host_complete(hsotg, qtd, -EPIPE);
1148 /*
1149 * USB protocol requires resetting the data toggle for bulk
1150 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1151 * setup command is issued to the endpoint. Anticipate the
1152 * CLEAR_FEATURE command since a STALL has occurred and reset
1153 * the data toggle now.
1154 */
1155 chan->qh->data_toggle = 0;
1156 }
1157
1158 handle_stall_halt:
1159 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1160
1161 handle_stall_done:
1162 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1163 }
1164
1165 /*
1166 * Updates the state of the URB when a transfer has been stopped due to an
1167 * abnormal condition before the transfer completes. Modifies the
1168 * actual_length field of the URB to reflect the number of bytes that have
1169 * actually been transferred via the host channel.
1170 */
dwc2_update_urb_state_abn(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_hcd_urb * urb,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)1171 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1172 struct dwc2_host_chan *chan, int chnum,
1173 struct dwc2_hcd_urb *urb,
1174 struct dwc2_qtd *qtd,
1175 enum dwc2_halt_status halt_status)
1176 {
1177 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1178 qtd, halt_status, NULL);
1179 u32 hctsiz;
1180
1181 if (urb->actual_length + xfer_length > urb->length) {
1182 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1183 if (urb->length & 0x3)
1184 xfer_length = 0;
1185 else
1186 xfer_length = urb->length - urb->actual_length;
1187 }
1188
1189 urb->actual_length += xfer_length;
1190
1191 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1192 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1193 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1194 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1195 chan->start_pkt_count);
1196 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1197 (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1198 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1199 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1200 xfer_length);
1201 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1202 urb->actual_length);
1203 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1204 urb->length);
1205 }
1206
1207 /*
1208 * Handles a host channel NAK interrupt. This handler may be called in either
1209 * DMA mode or Slave mode.
1210 */
dwc2_hc_nak_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1211 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1212 struct dwc2_host_chan *chan, int chnum,
1213 struct dwc2_qtd *qtd)
1214 {
1215 if (!qtd) {
1216 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1217 return;
1218 }
1219
1220 if (!qtd->urb) {
1221 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1222 return;
1223 }
1224
1225 if (dbg_hc(chan))
1226 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1227 chnum);
1228
1229 /*
1230 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1231 * interrupt. Re-start the SSPLIT transfer.
1232 *
1233 * Normally for non-periodic transfers we'll retry right away, but to
1234 * avoid interrupt storms we'll wait before retrying if we've got
1235 * several NAKs. If we didn't do this we'd retry directly from the
1236 * interrupt handler and could end up quickly getting another
1237 * interrupt (another NAK), which we'd retry. Note that we do not
1238 * delay retries for IN parts of control requests, as those are expected
1239 * to complete fairly quickly, and if we delay them we risk confusing
1240 * the device and cause it issue STALL.
1241 *
1242 * Note that in DMA mode software only gets involved to re-send NAKed
1243 * transfers for split transactions, so we only need to apply this
1244 * delaying logic when handling splits. In non-DMA mode presumably we
1245 * might want a similar delay if someone can demonstrate this problem
1246 * affects that code path too.
1247 */
1248 if (chan->do_split) {
1249 if (chan->complete_split)
1250 qtd->error_count = 0;
1251 qtd->complete_split = 0;
1252 qtd->num_naks++;
1253 qtd->qh->want_wait = qtd->num_naks >= DWC2_NAKS_BEFORE_DELAY &&
1254 !(chan->ep_type == USB_ENDPOINT_XFER_CONTROL &&
1255 chan->ep_is_in);
1256 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1257 goto handle_nak_done;
1258 }
1259
1260 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1261 case USB_ENDPOINT_XFER_CONTROL:
1262 case USB_ENDPOINT_XFER_BULK:
1263 if (hsotg->params.host_dma && chan->ep_is_in) {
1264 /*
1265 * NAK interrupts are enabled on bulk/control IN
1266 * transfers in DMA mode for the sole purpose of
1267 * resetting the error count after a transaction error
1268 * occurs. The core will continue transferring data.
1269 */
1270 qtd->error_count = 0;
1271 break;
1272 }
1273
1274 /*
1275 * NAK interrupts normally occur during OUT transfers in DMA
1276 * or Slave mode. For IN transfers, more requests will be
1277 * queued as request queue space is available.
1278 */
1279 qtd->error_count = 0;
1280
1281 if (!chan->qh->ping_state) {
1282 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1283 qtd, DWC2_HC_XFER_NAK);
1284 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1285
1286 if (chan->speed == USB_SPEED_HIGH)
1287 chan->qh->ping_state = 1;
1288 }
1289
1290 /*
1291 * Halt the channel so the transfer can be re-started from
1292 * the appropriate point or the PING protocol will
1293 * start/continue
1294 */
1295 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1296 break;
1297 case USB_ENDPOINT_XFER_INT:
1298 qtd->error_count = 0;
1299 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1300 break;
1301 case USB_ENDPOINT_XFER_ISOC:
1302 /* Should never get called for isochronous transfers */
1303 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1304 break;
1305 }
1306
1307 handle_nak_done:
1308 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1309 }
1310
1311 /*
1312 * Handles a host channel ACK interrupt. This interrupt is enabled when
1313 * performing the PING protocol in Slave mode, when errors occur during
1314 * either Slave mode or DMA mode, and during Start Split transactions.
1315 */
dwc2_hc_ack_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1316 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1317 struct dwc2_host_chan *chan, int chnum,
1318 struct dwc2_qtd *qtd)
1319 {
1320 struct dwc2_hcd_iso_packet_desc *frame_desc;
1321
1322 if (dbg_hc(chan))
1323 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1324 chnum);
1325
1326 if (chan->do_split) {
1327 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1328 if (!chan->ep_is_in &&
1329 chan->data_pid_start != DWC2_HC_PID_SETUP)
1330 qtd->ssplit_out_xfer_count = chan->xfer_len;
1331
1332 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1333 qtd->complete_split = 1;
1334 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1335 } else {
1336 /* ISOC OUT */
1337 switch (chan->xact_pos) {
1338 case DWC2_HCSPLT_XACTPOS_ALL:
1339 break;
1340 case DWC2_HCSPLT_XACTPOS_END:
1341 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1342 qtd->isoc_split_offset = 0;
1343 break;
1344 case DWC2_HCSPLT_XACTPOS_BEGIN:
1345 case DWC2_HCSPLT_XACTPOS_MID:
1346 /*
1347 * For BEGIN or MID, calculate the length for
1348 * the next microframe to determine the correct
1349 * SSPLIT token, either MID or END
1350 */
1351 frame_desc = &qtd->urb->iso_descs[
1352 qtd->isoc_frame_index];
1353 qtd->isoc_split_offset += 188;
1354
1355 if (frame_desc->length - qtd->isoc_split_offset
1356 <= 188)
1357 qtd->isoc_split_pos =
1358 DWC2_HCSPLT_XACTPOS_END;
1359 else
1360 qtd->isoc_split_pos =
1361 DWC2_HCSPLT_XACTPOS_MID;
1362 break;
1363 }
1364 }
1365 } else {
1366 qtd->error_count = 0;
1367
1368 if (chan->qh->ping_state) {
1369 chan->qh->ping_state = 0;
1370 /*
1371 * Halt the channel so the transfer can be re-started
1372 * from the appropriate point. This only happens in
1373 * Slave mode. In DMA mode, the ping_state is cleared
1374 * when the transfer is started because the core
1375 * automatically executes the PING, then the transfer.
1376 */
1377 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1378 }
1379 }
1380
1381 /*
1382 * If the ACK occurred when _not_ in the PING state, let the channel
1383 * continue transferring data after clearing the error count
1384 */
1385 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1386 }
1387
1388 /*
1389 * Handles a host channel NYET interrupt. This interrupt should only occur on
1390 * Bulk and Control OUT endpoints and for complete split transactions. If a
1391 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1392 * handled in the xfercomp interrupt handler, not here. This handler may be
1393 * called in either DMA mode or Slave mode.
1394 */
dwc2_hc_nyet_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1395 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1396 struct dwc2_host_chan *chan, int chnum,
1397 struct dwc2_qtd *qtd)
1398 {
1399 if (dbg_hc(chan))
1400 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1401 chnum);
1402
1403 /*
1404 * NYET on CSPLIT
1405 * re-do the CSPLIT immediately on non-periodic
1406 */
1407 if (chan->do_split && chan->complete_split) {
1408 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1409 hsotg->params.host_dma) {
1410 qtd->complete_split = 0;
1411 qtd->isoc_split_offset = 0;
1412 qtd->isoc_frame_index++;
1413 if (qtd->urb &&
1414 qtd->isoc_frame_index == qtd->urb->packet_count) {
1415 dwc2_host_complete(hsotg, qtd, 0);
1416 dwc2_release_channel(hsotg, chan, qtd,
1417 DWC2_HC_XFER_URB_COMPLETE);
1418 } else {
1419 dwc2_release_channel(hsotg, chan, qtd,
1420 DWC2_HC_XFER_NO_HALT_STATUS);
1421 }
1422 goto handle_nyet_done;
1423 }
1424
1425 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1426 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1427 struct dwc2_qh *qh = chan->qh;
1428 bool past_end;
1429
1430 if (!hsotg->params.uframe_sched) {
1431 int frnum = dwc2_hcd_get_frame_number(hsotg);
1432
1433 /* Don't have num_hs_transfers; simple logic */
1434 past_end = dwc2_full_frame_num(frnum) !=
1435 dwc2_full_frame_num(qh->next_active_frame);
1436 } else {
1437 int end_frnum;
1438
1439 /*
1440 * Figure out the end frame based on
1441 * schedule.
1442 *
1443 * We don't want to go on trying again
1444 * and again forever. Let's stop when
1445 * we've done all the transfers that
1446 * were scheduled.
1447 *
1448 * We're going to be comparing
1449 * start_active_frame and
1450 * next_active_frame, both of which
1451 * are 1 before the time the packet
1452 * goes on the wire, so that cancels
1453 * out. Basically if had 1 transfer
1454 * and we saw 1 NYET then we're done.
1455 * We're getting a NYET here so if
1456 * next >= (start + num_transfers)
1457 * we're done. The complexity is that
1458 * for all but ISOC_OUT we skip one
1459 * slot.
1460 */
1461 end_frnum = dwc2_frame_num_inc(
1462 qh->start_active_frame,
1463 qh->num_hs_transfers);
1464
1465 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
1466 qh->ep_is_in)
1467 end_frnum =
1468 dwc2_frame_num_inc(end_frnum, 1);
1469
1470 past_end = dwc2_frame_num_le(
1471 end_frnum, qh->next_active_frame);
1472 }
1473
1474 if (past_end) {
1475 /* Treat this as a transaction error. */
1476 #if 0
1477 /*
1478 * Todo: Fix system performance so this can
1479 * be treated as an error. Right now complete
1480 * splits cannot be scheduled precisely enough
1481 * due to other system activity, so this error
1482 * occurs regularly in Slave mode.
1483 */
1484 qtd->error_count++;
1485 #endif
1486 qtd->complete_split = 0;
1487 dwc2_halt_channel(hsotg, chan, qtd,
1488 DWC2_HC_XFER_XACT_ERR);
1489 /* Todo: add support for isoc release */
1490 goto handle_nyet_done;
1491 }
1492 }
1493
1494 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1495 goto handle_nyet_done;
1496 }
1497
1498 chan->qh->ping_state = 1;
1499 qtd->error_count = 0;
1500
1501 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1502 DWC2_HC_XFER_NYET);
1503 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1504
1505 /*
1506 * Halt the channel and re-start the transfer so the PING protocol
1507 * will start
1508 */
1509 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1510
1511 handle_nyet_done:
1512 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1513 }
1514
1515 /*
1516 * Handles a host channel babble interrupt. This handler may be called in
1517 * either DMA mode or Slave mode.
1518 */
dwc2_hc_babble_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1519 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1520 struct dwc2_host_chan *chan, int chnum,
1521 struct dwc2_qtd *qtd)
1522 {
1523 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1524 chnum);
1525
1526 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1527
1528 if (hsotg->params.dma_desc_enable) {
1529 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1530 DWC2_HC_XFER_BABBLE_ERR);
1531 goto disable_int;
1532 }
1533
1534 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1535 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1536 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1537 } else {
1538 enum dwc2_halt_status halt_status;
1539
1540 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1541 qtd, DWC2_HC_XFER_BABBLE_ERR);
1542 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1543 }
1544
1545 disable_int:
1546 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1547 }
1548
1549 /*
1550 * Handles a host channel AHB error interrupt. This handler is only called in
1551 * DMA mode.
1552 */
dwc2_hc_ahberr_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1553 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1554 struct dwc2_host_chan *chan, int chnum,
1555 struct dwc2_qtd *qtd)
1556 {
1557 struct dwc2_hcd_urb *urb = qtd->urb;
1558 char *pipetype, *speed;
1559 u32 hcchar;
1560 u32 hcsplt;
1561 u32 hctsiz;
1562 u32 hc_dma;
1563
1564 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1565 chnum);
1566
1567 if (!urb)
1568 goto handle_ahberr_halt;
1569
1570 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1571
1572 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1573 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1574 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1575 hc_dma = dwc2_readl(hsotg, HCDMA(chnum));
1576
1577 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1578 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1579 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1580 dev_err(hsotg->dev, " Device address: %d\n",
1581 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1582 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1583 dwc2_hcd_get_ep_num(&urb->pipe_info),
1584 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1585
1586 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1587 case USB_ENDPOINT_XFER_CONTROL:
1588 pipetype = "CONTROL";
1589 break;
1590 case USB_ENDPOINT_XFER_BULK:
1591 pipetype = "BULK";
1592 break;
1593 case USB_ENDPOINT_XFER_INT:
1594 pipetype = "INTERRUPT";
1595 break;
1596 case USB_ENDPOINT_XFER_ISOC:
1597 pipetype = "ISOCHRONOUS";
1598 break;
1599 default:
1600 pipetype = "UNKNOWN";
1601 break;
1602 }
1603
1604 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1605
1606 switch (chan->speed) {
1607 case USB_SPEED_HIGH:
1608 speed = "HIGH";
1609 break;
1610 case USB_SPEED_FULL:
1611 speed = "FULL";
1612 break;
1613 case USB_SPEED_LOW:
1614 speed = "LOW";
1615 break;
1616 default:
1617 speed = "UNKNOWN";
1618 break;
1619 }
1620
1621 dev_err(hsotg->dev, " Speed: %s\n", speed);
1622
1623 dev_err(hsotg->dev, " Max packet size: %d (mult %d)\n",
1624 dwc2_hcd_get_maxp(&urb->pipe_info),
1625 dwc2_hcd_get_maxp_mult(&urb->pipe_info));
1626 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1627 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1628 urb->buf, (unsigned long)urb->dma);
1629 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1630 urb->setup_packet, (unsigned long)urb->setup_dma);
1631 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1632
1633 /* Core halts the channel for Descriptor DMA mode */
1634 if (hsotg->params.dma_desc_enable) {
1635 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1636 DWC2_HC_XFER_AHB_ERR);
1637 goto handle_ahberr_done;
1638 }
1639
1640 dwc2_host_complete(hsotg, qtd, -EIO);
1641
1642 handle_ahberr_halt:
1643 /*
1644 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1645 * write to the HCCHARn register in DMA mode to force the halt.
1646 */
1647 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1648
1649 handle_ahberr_done:
1650 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1651 }
1652
1653 /*
1654 * Handles a host channel transaction error interrupt. This handler may be
1655 * called in either DMA mode or Slave mode.
1656 */
dwc2_hc_xacterr_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1657 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1658 struct dwc2_host_chan *chan, int chnum,
1659 struct dwc2_qtd *qtd)
1660 {
1661 dev_dbg(hsotg->dev,
1662 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1663
1664 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1665
1666 if (hsotg->params.dma_desc_enable) {
1667 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1668 DWC2_HC_XFER_XACT_ERR);
1669 goto handle_xacterr_done;
1670 }
1671
1672 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1673 case USB_ENDPOINT_XFER_CONTROL:
1674 case USB_ENDPOINT_XFER_BULK:
1675 qtd->error_count++;
1676 if (!chan->qh->ping_state) {
1677 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1678 qtd, DWC2_HC_XFER_XACT_ERR);
1679 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1680 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1681 chan->qh->ping_state = 1;
1682 }
1683
1684 /*
1685 * Halt the channel so the transfer can be re-started from
1686 * the appropriate point or the PING protocol will start
1687 */
1688 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1689 break;
1690 case USB_ENDPOINT_XFER_INT:
1691 qtd->error_count++;
1692 if (chan->do_split && chan->complete_split)
1693 qtd->complete_split = 0;
1694 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1695 break;
1696 case USB_ENDPOINT_XFER_ISOC:
1697 {
1698 enum dwc2_halt_status halt_status;
1699
1700 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1701 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1702 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1703 }
1704 break;
1705 }
1706
1707 handle_xacterr_done:
1708 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1709 }
1710
1711 /*
1712 * Handles a host channel frame overrun interrupt. This handler may be called
1713 * in either DMA mode or Slave mode.
1714 */
dwc2_hc_frmovrun_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1715 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1716 struct dwc2_host_chan *chan, int chnum,
1717 struct dwc2_qtd *qtd)
1718 {
1719 enum dwc2_halt_status halt_status;
1720
1721 if (dbg_hc(chan))
1722 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1723 chnum);
1724
1725 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1726
1727 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1728 case USB_ENDPOINT_XFER_CONTROL:
1729 case USB_ENDPOINT_XFER_BULK:
1730 break;
1731 case USB_ENDPOINT_XFER_INT:
1732 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1733 break;
1734 case USB_ENDPOINT_XFER_ISOC:
1735 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1736 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1737 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1738 break;
1739 }
1740
1741 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1742 }
1743
1744 /*
1745 * Handles a host channel data toggle error interrupt. This handler may be
1746 * called in either DMA mode or Slave mode.
1747 */
dwc2_hc_datatglerr_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1748 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1749 struct dwc2_host_chan *chan, int chnum,
1750 struct dwc2_qtd *qtd)
1751 {
1752 dev_dbg(hsotg->dev,
1753 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1754
1755 if (chan->ep_is_in)
1756 qtd->error_count = 0;
1757 else
1758 dev_err(hsotg->dev,
1759 "Data Toggle Error on OUT transfer, channel %d\n",
1760 chnum);
1761
1762 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1763 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1764 }
1765
1766 /*
1767 * For debug only. It checks that a valid halt status is set and that
1768 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1769 * taken and a warning is issued.
1770 *
1771 * Return: true if halt status is ok, false otherwise
1772 */
dwc2_halt_status_ok(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1773 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1774 struct dwc2_host_chan *chan, int chnum,
1775 struct dwc2_qtd *qtd)
1776 {
1777 #ifdef DEBUG
1778 u32 hcchar;
1779 u32 hctsiz;
1780 u32 hcintmsk;
1781 u32 hcsplt;
1782
1783 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1784 /*
1785 * This code is here only as a check. This condition should
1786 * never happen. Ignore the halt if it does occur.
1787 */
1788 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1789 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1790 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1791 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1792 dev_dbg(hsotg->dev,
1793 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1794 __func__);
1795 dev_dbg(hsotg->dev,
1796 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1797 chnum, hcchar, hctsiz);
1798 dev_dbg(hsotg->dev,
1799 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1800 chan->hcint, hcintmsk, hcsplt);
1801 if (qtd)
1802 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1803 qtd->complete_split);
1804 dev_warn(hsotg->dev,
1805 "%s: no halt status, channel %d, ignoring interrupt\n",
1806 __func__, chnum);
1807 return false;
1808 }
1809
1810 /*
1811 * This code is here only as a check. hcchar.chdis should never be set
1812 * when the halt interrupt occurs. Halt the channel again if it does
1813 * occur.
1814 */
1815 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1816 if (hcchar & HCCHAR_CHDIS) {
1817 dev_warn(hsotg->dev,
1818 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1819 __func__, hcchar);
1820 chan->halt_pending = 0;
1821 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1822 return false;
1823 }
1824 #endif
1825
1826 return true;
1827 }
1828
1829 /*
1830 * Handles a host Channel Halted interrupt in DMA mode. This handler
1831 * determines the reason the channel halted and proceeds accordingly.
1832 */
dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1833 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1834 struct dwc2_host_chan *chan, int chnum,
1835 struct dwc2_qtd *qtd)
1836 {
1837 u32 hcintmsk;
1838 int out_nak_enh = 0;
1839
1840 if (dbg_hc(chan))
1841 dev_vdbg(hsotg->dev,
1842 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1843 chnum);
1844
1845 /*
1846 * For core with OUT NAK enhancement, the flow for high-speed
1847 * CONTROL/BULK OUT is handled a little differently
1848 */
1849 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1850 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1851 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1852 chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1853 out_nak_enh = 1;
1854 }
1855 }
1856
1857 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1858 (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1859 !hsotg->params.dma_desc_enable)) {
1860 if (hsotg->params.dma_desc_enable)
1861 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1862 chan->halt_status);
1863 else
1864 /*
1865 * Just release the channel. A dequeue can happen on a
1866 * transfer timeout. In the case of an AHB Error, the
1867 * channel was forced to halt because there's no way to
1868 * gracefully recover.
1869 */
1870 dwc2_release_channel(hsotg, chan, qtd,
1871 chan->halt_status);
1872 return;
1873 }
1874
1875 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1876
1877 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1878 /*
1879 * Todo: This is here because of a possible hardware bug. Spec
1880 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1881 * interrupt w/ACK bit set should occur, but I only see the
1882 * XFERCOMP bit, even with it masked out. This is a workaround
1883 * for that behavior. Should fix this when hardware is fixed.
1884 */
1885 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1886 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1887 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1888 } else if (chan->hcint & HCINTMSK_STALL) {
1889 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1890 } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1891 !hsotg->params.dma_desc_enable) {
1892 if (out_nak_enh) {
1893 if (chan->hcint &
1894 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1895 dev_vdbg(hsotg->dev,
1896 "XactErr with NYET/NAK/ACK\n");
1897 qtd->error_count = 0;
1898 } else {
1899 dev_vdbg(hsotg->dev,
1900 "XactErr without NYET/NAK/ACK\n");
1901 }
1902 }
1903
1904 /*
1905 * Must handle xacterr before nak or ack. Could get a xacterr
1906 * at the same time as either of these on a BULK/CONTROL OUT
1907 * that started with a PING. The xacterr takes precedence.
1908 */
1909 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1910 } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1911 hsotg->params.dma_desc_enable) {
1912 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1913 } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1914 hsotg->params.dma_desc_enable) {
1915 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1916 } else if (chan->hcint & HCINTMSK_BBLERR) {
1917 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1918 } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1919 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1920 } else if (!out_nak_enh) {
1921 if (chan->hcint & HCINTMSK_NYET) {
1922 /*
1923 * Must handle nyet before nak or ack. Could get a nyet
1924 * at the same time as either of those on a BULK/CONTROL
1925 * OUT that started with a PING. The nyet takes
1926 * precedence.
1927 */
1928 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1929 } else if ((chan->hcint & HCINTMSK_NAK) &&
1930 !(hcintmsk & HCINTMSK_NAK)) {
1931 /*
1932 * If nak is not masked, it's because a non-split IN
1933 * transfer is in an error state. In that case, the nak
1934 * is handled by the nak interrupt handler, not here.
1935 * Handle nak here for BULK/CONTROL OUT transfers, which
1936 * halt on a NAK to allow rewinding the buffer pointer.
1937 */
1938 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1939 } else if ((chan->hcint & HCINTMSK_ACK) &&
1940 !(hcintmsk & HCINTMSK_ACK)) {
1941 /*
1942 * If ack is not masked, it's because a non-split IN
1943 * transfer is in an error state. In that case, the ack
1944 * is handled by the ack interrupt handler, not here.
1945 * Handle ack here for split transfers. Start splits
1946 * halt on ACK.
1947 */
1948 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1949 } else {
1950 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1951 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1952 /*
1953 * A periodic transfer halted with no other
1954 * channel interrupts set. Assume it was halted
1955 * by the core because it could not be completed
1956 * in its scheduled (micro)frame.
1957 */
1958 dev_dbg(hsotg->dev,
1959 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1960 __func__, chnum);
1961 dwc2_halt_channel(hsotg, chan, qtd,
1962 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1963 } else {
1964 dev_err(hsotg->dev,
1965 "%s: Channel %d - ChHltd set, but reason is unknown\n",
1966 __func__, chnum);
1967 dev_err(hsotg->dev,
1968 "hcint 0x%08x, intsts 0x%08x\n",
1969 chan->hcint,
1970 dwc2_readl(hsotg, GINTSTS));
1971 goto error;
1972 }
1973 }
1974 } else {
1975 dev_info(hsotg->dev,
1976 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1977 chan->hcint);
1978 error:
1979 /* Failthrough: use 3-strikes rule */
1980 qtd->error_count++;
1981 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1982 qtd, DWC2_HC_XFER_XACT_ERR);
1983 /*
1984 * We can get here after a completed transaction
1985 * (urb->actual_length >= urb->length) which was not reported
1986 * as completed. If that is the case, and we do not abort
1987 * the transfer, a transfer of size 0 will be enqueued
1988 * subsequently. If urb->actual_length is not DMA-aligned,
1989 * the buffer will then point to an unaligned address, and
1990 * the resulting behavior is undefined. Bail out in that
1991 * situation.
1992 */
1993 if (qtd->urb->actual_length >= qtd->urb->length)
1994 qtd->error_count = 3;
1995 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1996 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1997 }
1998 }
1999
2000 /*
2001 * Handles a host channel Channel Halted interrupt
2002 *
2003 * In slave mode, this handler is called only when the driver specifically
2004 * requests a halt. This occurs during handling other host channel interrupts
2005 * (e.g. nak, xacterr, stall, nyet, etc.).
2006 *
2007 * In DMA mode, this is the interrupt that occurs when the core has finished
2008 * processing a transfer on a channel. Other host channel interrupts (except
2009 * ahberr) are disabled in DMA mode.
2010 */
dwc2_hc_chhltd_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)2011 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
2012 struct dwc2_host_chan *chan, int chnum,
2013 struct dwc2_qtd *qtd)
2014 {
2015 if (dbg_hc(chan))
2016 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
2017 chnum);
2018
2019 if (hsotg->params.host_dma) {
2020 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
2021 } else {
2022 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
2023 return;
2024 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
2025 }
2026 }
2027
2028 /*
2029 * Check if the given qtd is still the top of the list (and thus valid).
2030 *
2031 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
2032 * the qtd from the top of the list, this will return false (otherwise true).
2033 */
dwc2_check_qtd_still_ok(struct dwc2_qtd * qtd,struct dwc2_qh * qh)2034 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
2035 {
2036 struct dwc2_qtd *cur_head;
2037
2038 if (!qh)
2039 return false;
2040
2041 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
2042 qtd_list_entry);
2043 return (cur_head == qtd);
2044 }
2045
2046 /* Handles interrupt for a specific Host Channel */
dwc2_hc_n_intr(struct dwc2_hsotg * hsotg,int chnum)2047 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2048 {
2049 struct dwc2_qtd *qtd;
2050 struct dwc2_host_chan *chan;
2051 u32 hcint, hcintmsk;
2052
2053 chan = hsotg->hc_ptr_array[chnum];
2054
2055 hcint = dwc2_readl(hsotg, HCINT(chnum));
2056 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
2057 if (!chan) {
2058 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2059 dwc2_writel(hsotg, hcint, HCINT(chnum));
2060 return;
2061 }
2062
2063 if (dbg_hc(chan)) {
2064 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2065 chnum);
2066 dev_vdbg(hsotg->dev,
2067 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2068 hcint, hcintmsk, hcint & hcintmsk);
2069 }
2070
2071 /*
2072 * If we got an interrupt after someone called
2073 * dwc2_hcd_endpoint_disable() we don't want to crash below
2074 */
2075 if (!chan->qh) {
2076 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2077 return;
2078 }
2079
2080 chan->hcint = hcint;
2081 hcint &= hcintmsk;
2082
2083 dwc2_writel(hsotg, hcint, HCINT(chnum));
2084
2085 /*
2086 * If the channel was halted due to a dequeue, the qtd list might
2087 * be empty or at least the first entry will not be the active qtd.
2088 * In this case, take a shortcut and just release the channel.
2089 */
2090 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2091 /*
2092 * If the channel was halted, this should be the only
2093 * interrupt unmasked
2094 */
2095 WARN_ON(hcint != HCINTMSK_CHHLTD);
2096 if (hsotg->params.dma_desc_enable)
2097 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2098 chan->halt_status);
2099 else
2100 dwc2_release_channel(hsotg, chan, NULL,
2101 chan->halt_status);
2102 return;
2103 }
2104
2105 if (list_empty(&chan->qh->qtd_list)) {
2106 /*
2107 * TODO: Will this ever happen with the
2108 * DWC2_HC_XFER_URB_DEQUEUE handling above?
2109 */
2110 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2111 chnum);
2112 dev_dbg(hsotg->dev,
2113 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2114 chan->hcint, hcintmsk, hcint);
2115 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2116 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2117 chan->hcint = 0;
2118 return;
2119 }
2120
2121 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2122 qtd_list_entry);
2123
2124 if (!hsotg->params.host_dma) {
2125 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2126 hcint &= ~HCINTMSK_CHHLTD;
2127 }
2128
2129 if (hcint & HCINTMSK_XFERCOMPL) {
2130 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2131 /*
2132 * If NYET occurred at same time as Xfer Complete, the NYET is
2133 * handled by the Xfer Complete interrupt handler. Don't want
2134 * to call the NYET interrupt handler in this case.
2135 */
2136 hcint &= ~HCINTMSK_NYET;
2137 }
2138
2139 if (hcint & HCINTMSK_CHHLTD) {
2140 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2141 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2142 goto exit;
2143 }
2144 if (hcint & HCINTMSK_AHBERR) {
2145 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2146 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2147 goto exit;
2148 }
2149 if (hcint & HCINTMSK_STALL) {
2150 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2151 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2152 goto exit;
2153 }
2154 if (hcint & HCINTMSK_NAK) {
2155 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2156 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2157 goto exit;
2158 }
2159 if (hcint & HCINTMSK_ACK) {
2160 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2161 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2162 goto exit;
2163 }
2164 if (hcint & HCINTMSK_NYET) {
2165 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2166 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2167 goto exit;
2168 }
2169 if (hcint & HCINTMSK_XACTERR) {
2170 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2171 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2172 goto exit;
2173 }
2174 if (hcint & HCINTMSK_BBLERR) {
2175 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2176 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2177 goto exit;
2178 }
2179 if (hcint & HCINTMSK_FRMOVRUN) {
2180 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2181 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2182 goto exit;
2183 }
2184 if (hcint & HCINTMSK_DATATGLERR) {
2185 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2186 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2187 goto exit;
2188 }
2189
2190 exit:
2191 chan->hcint = 0;
2192 }
2193
2194 /*
2195 * This interrupt indicates that one or more host channels has a pending
2196 * interrupt. There are multiple conditions that can cause each host channel
2197 * interrupt. This function determines which conditions have occurred for each
2198 * host channel interrupt and handles them appropriately.
2199 */
dwc2_hc_intr(struct dwc2_hsotg * hsotg)2200 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2201 {
2202 u32 haint;
2203 int i;
2204 struct dwc2_host_chan *chan, *chan_tmp;
2205
2206 haint = dwc2_readl(hsotg, HAINT);
2207 if (dbg_perio()) {
2208 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2209
2210 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2211 }
2212
2213 /*
2214 * According to USB 2.0 spec section 11.18.8, a host must
2215 * issue complete-split transactions in a microframe for a
2216 * set of full-/low-speed endpoints in the same relative
2217 * order as the start-splits were issued in a microframe for.
2218 */
2219 list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2220 split_order_list_entry) {
2221 int hc_num = chan->hc_num;
2222
2223 if (haint & (1 << hc_num)) {
2224 dwc2_hc_n_intr(hsotg, hc_num);
2225 haint &= ~(1 << hc_num);
2226 }
2227 }
2228
2229 for (i = 0; i < hsotg->params.host_channels; i++) {
2230 if (haint & (1 << i))
2231 dwc2_hc_n_intr(hsotg, i);
2232 }
2233 }
2234
2235 /* This function handles interrupts for the HCD */
dwc2_handle_hcd_intr(struct dwc2_hsotg * hsotg)2236 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2237 {
2238 u32 gintsts, dbg_gintsts;
2239 irqreturn_t retval = IRQ_NONE;
2240
2241 if (!dwc2_is_controller_alive(hsotg)) {
2242 dev_warn(hsotg->dev, "Controller is dead\n");
2243 return retval;
2244 }
2245
2246 spin_lock(&hsotg->lock);
2247
2248 /* Check if HOST Mode */
2249 if (dwc2_is_host_mode(hsotg)) {
2250 gintsts = dwc2_read_core_intr(hsotg);
2251 if (!gintsts) {
2252 spin_unlock(&hsotg->lock);
2253 return retval;
2254 }
2255
2256 retval = IRQ_HANDLED;
2257
2258 dbg_gintsts = gintsts;
2259 #ifndef DEBUG_SOF
2260 dbg_gintsts &= ~GINTSTS_SOF;
2261 #endif
2262 if (!dbg_perio())
2263 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2264 GINTSTS_PTXFEMP);
2265
2266 /* Only print if there are any non-suppressed interrupts left */
2267 if (dbg_gintsts)
2268 dev_vdbg(hsotg->dev,
2269 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2270 gintsts);
2271
2272 if (gintsts & GINTSTS_SOF)
2273 dwc2_sof_intr(hsotg);
2274 if (gintsts & GINTSTS_RXFLVL)
2275 dwc2_rx_fifo_level_intr(hsotg);
2276 if (gintsts & GINTSTS_NPTXFEMP)
2277 dwc2_np_tx_fifo_empty_intr(hsotg);
2278 if (gintsts & GINTSTS_PRTINT)
2279 dwc2_port_intr(hsotg);
2280 if (gintsts & GINTSTS_HCHINT)
2281 dwc2_hc_intr(hsotg);
2282 if (gintsts & GINTSTS_PTXFEMP)
2283 dwc2_perio_tx_fifo_empty_intr(hsotg);
2284
2285 if (dbg_gintsts) {
2286 dev_vdbg(hsotg->dev,
2287 "DWC OTG HCD Finished Servicing Interrupts\n");
2288 dev_vdbg(hsotg->dev,
2289 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2290 dwc2_readl(hsotg, GINTSTS),
2291 dwc2_readl(hsotg, GINTMSK));
2292 }
2293 }
2294
2295 spin_unlock(&hsotg->lock);
2296
2297 return retval;
2298 }
2299