1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * This file contains the core HCD code, and implements the Linux hc_driver
40 * API
41 */
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
49 #include <linux/io.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
52
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
55
56 #include "core.h"
57 #include "hcd.h"
58
59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
60
61 /*
62 * =========================================================================
63 * Host Core Layer Functions
64 * =========================================================================
65 */
66
67 /**
68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
69 * used in both device and host modes
70 *
71 * @hsotg: Programming view of the DWC_otg controller
72 */
dwc2_enable_common_interrupts(struct dwc2_hsotg * hsotg)73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
74 {
75 u32 intmsk;
76
77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
79
80 /* Clear any pending interrupts */
81 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
82
83 /* Enable the interrupts in the GINTMSK */
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
85
86 if (!hsotg->params.host_dma)
87 intmsk |= GINTSTS_RXFLVL;
88 if (!hsotg->params.external_id_pin_ctl)
89 intmsk |= GINTSTS_CONIDSTSCHNG;
90
91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
92 GINTSTS_SESSREQINT;
93
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD;
96
97 dwc2_writel(hsotg, intmsk, GINTMSK);
98 }
99
dwc2_gahbcfg_init(struct dwc2_hsotg * hsotg)100 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
101 {
102 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
103
104 switch (hsotg->hw_params.arch) {
105 case GHWCFG2_EXT_DMA_ARCH:
106 dev_err(hsotg->dev, "External DMA Mode not supported\n");
107 return -EINVAL;
108
109 case GHWCFG2_INT_DMA_ARCH:
110 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
111 if (hsotg->params.ahbcfg != -1) {
112 ahbcfg &= GAHBCFG_CTRL_MASK;
113 ahbcfg |= hsotg->params.ahbcfg &
114 ~GAHBCFG_CTRL_MASK;
115 }
116 break;
117
118 case GHWCFG2_SLAVE_ONLY_ARCH:
119 default:
120 dev_dbg(hsotg->dev, "Slave Only Mode\n");
121 break;
122 }
123
124 if (hsotg->params.host_dma)
125 ahbcfg |= GAHBCFG_DMA_EN;
126 else
127 hsotg->params.dma_desc_enable = false;
128
129 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
130
131 return 0;
132 }
133
dwc2_gusbcfg_init(struct dwc2_hsotg * hsotg)134 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
135 {
136 u32 usbcfg;
137
138 usbcfg = dwc2_readl(hsotg, GUSBCFG);
139 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
140
141 switch (hsotg->hw_params.op_mode) {
142 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
143 if (hsotg->params.otg_cap ==
144 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
145 usbcfg |= GUSBCFG_HNPCAP;
146 if (hsotg->params.otg_cap !=
147 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
148 usbcfg |= GUSBCFG_SRPCAP;
149 break;
150
151 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
152 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
153 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
154 if (hsotg->params.otg_cap !=
155 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
156 usbcfg |= GUSBCFG_SRPCAP;
157 break;
158
159 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
160 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
161 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
162 default:
163 break;
164 }
165
166 dwc2_writel(hsotg, usbcfg, GUSBCFG);
167 }
168
dwc2_vbus_supply_init(struct dwc2_hsotg * hsotg)169 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
170 {
171 if (hsotg->vbus_supply)
172 return regulator_enable(hsotg->vbus_supply);
173
174 return 0;
175 }
176
dwc2_vbus_supply_exit(struct dwc2_hsotg * hsotg)177 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
178 {
179 if (hsotg->vbus_supply)
180 return regulator_disable(hsotg->vbus_supply);
181
182 return 0;
183 }
184
185 /**
186 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
187 *
188 * @hsotg: Programming view of DWC_otg controller
189 */
dwc2_enable_host_interrupts(struct dwc2_hsotg * hsotg)190 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
191 {
192 u32 intmsk;
193
194 dev_dbg(hsotg->dev, "%s()\n", __func__);
195
196 /* Disable all interrupts */
197 dwc2_writel(hsotg, 0, GINTMSK);
198 dwc2_writel(hsotg, 0, HAINTMSK);
199
200 /* Enable the common interrupts */
201 dwc2_enable_common_interrupts(hsotg);
202
203 /* Enable host mode interrupts without disturbing common interrupts */
204 intmsk = dwc2_readl(hsotg, GINTMSK);
205 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
206 dwc2_writel(hsotg, intmsk, GINTMSK);
207 }
208
209 /**
210 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
211 *
212 * @hsotg: Programming view of DWC_otg controller
213 */
dwc2_disable_host_interrupts(struct dwc2_hsotg * hsotg)214 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
215 {
216 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
217
218 /* Disable host mode interrupts without disturbing common interrupts */
219 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
220 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
221 dwc2_writel(hsotg, intmsk, GINTMSK);
222 }
223
224 /*
225 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
226 * For system that have a total fifo depth that is smaller than the default
227 * RX + TX fifo size.
228 *
229 * @hsotg: Programming view of DWC_otg controller
230 */
dwc2_calculate_dynamic_fifo(struct dwc2_hsotg * hsotg)231 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
232 {
233 struct dwc2_core_params *params = &hsotg->params;
234 struct dwc2_hw_params *hw = &hsotg->hw_params;
235 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
236
237 total_fifo_size = hw->total_fifo_size;
238 rxfsiz = params->host_rx_fifo_size;
239 nptxfsiz = params->host_nperio_tx_fifo_size;
240 ptxfsiz = params->host_perio_tx_fifo_size;
241
242 /*
243 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
244 * allocation with support for high bandwidth endpoints. Synopsys
245 * defines MPS(Max Packet size) for a periodic EP=1024, and for
246 * non-periodic as 512.
247 */
248 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
249 /*
250 * For Buffer DMA mode/Scatter Gather DMA mode
251 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
252 * with n = number of host channel.
253 * 2 * ((1024/4) + 2) = 516
254 */
255 rxfsiz = 516 + hw->host_channels;
256
257 /*
258 * min non-periodic tx fifo depth
259 * 2 * (largest non-periodic USB packet used / 4)
260 * 2 * (512/4) = 256
261 */
262 nptxfsiz = 256;
263
264 /*
265 * min periodic tx fifo depth
266 * (largest packet size*MC)/4
267 * (1024 * 3)/4 = 768
268 */
269 ptxfsiz = 768;
270
271 params->host_rx_fifo_size = rxfsiz;
272 params->host_nperio_tx_fifo_size = nptxfsiz;
273 params->host_perio_tx_fifo_size = ptxfsiz;
274 }
275
276 /*
277 * If the summation of RX, NPTX and PTX fifo sizes is still
278 * bigger than the total_fifo_size, then we have a problem.
279 *
280 * We won't be able to allocate as many endpoints. Right now,
281 * we're just printing an error message, but ideally this FIFO
282 * allocation algorithm would be improved in the future.
283 *
284 * FIXME improve this FIFO allocation algorithm.
285 */
286 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
287 dev_err(hsotg->dev, "invalid fifo sizes\n");
288 }
289
dwc2_config_fifos(struct dwc2_hsotg * hsotg)290 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
291 {
292 struct dwc2_core_params *params = &hsotg->params;
293 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
294
295 if (!params->enable_dynamic_fifo)
296 return;
297
298 dwc2_calculate_dynamic_fifo(hsotg);
299
300 /* Rx FIFO */
301 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
302 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
303 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
304 grxfsiz |= params->host_rx_fifo_size <<
305 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
306 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
307 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
308 dwc2_readl(hsotg, GRXFSIZ));
309
310 /* Non-periodic Tx FIFO */
311 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
312 dwc2_readl(hsotg, GNPTXFSIZ));
313 nptxfsiz = params->host_nperio_tx_fifo_size <<
314 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
315 nptxfsiz |= params->host_rx_fifo_size <<
316 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
317 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
318 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
319 dwc2_readl(hsotg, GNPTXFSIZ));
320
321 /* Periodic Tx FIFO */
322 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
323 dwc2_readl(hsotg, HPTXFSIZ));
324 hptxfsiz = params->host_perio_tx_fifo_size <<
325 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
326 hptxfsiz |= (params->host_rx_fifo_size +
327 params->host_nperio_tx_fifo_size) <<
328 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
329 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
330 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
331 dwc2_readl(hsotg, HPTXFSIZ));
332
333 if (hsotg->params.en_multiple_tx_fifo &&
334 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
335 /*
336 * This feature was implemented in 2.91a version
337 * Global DFIFOCFG calculation for Host mode -
338 * include RxFIFO, NPTXFIFO and HPTXFIFO
339 */
340 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
341 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
342 dfifocfg |= (params->host_rx_fifo_size +
343 params->host_nperio_tx_fifo_size +
344 params->host_perio_tx_fifo_size) <<
345 GDFIFOCFG_EPINFOBASE_SHIFT &
346 GDFIFOCFG_EPINFOBASE_MASK;
347 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
348 }
349 }
350
351 /**
352 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
353 * the HFIR register according to PHY type and speed
354 *
355 * @hsotg: Programming view of DWC_otg controller
356 *
357 * NOTE: The caller can modify the value of the HFIR register only after the
358 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
359 * has been set
360 */
dwc2_calc_frame_interval(struct dwc2_hsotg * hsotg)361 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
362 {
363 u32 usbcfg;
364 u32 hprt0;
365 int clock = 60; /* default value */
366
367 usbcfg = dwc2_readl(hsotg, GUSBCFG);
368 hprt0 = dwc2_readl(hsotg, HPRT0);
369
370 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
371 !(usbcfg & GUSBCFG_PHYIF16))
372 clock = 60;
373 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
374 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
375 clock = 48;
376 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
377 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
378 clock = 30;
379 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
380 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
381 clock = 60;
382 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
383 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
384 clock = 48;
385 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
386 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
387 clock = 48;
388 if ((usbcfg & GUSBCFG_PHYSEL) &&
389 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
390 clock = 48;
391
392 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
393 /* High speed case */
394 return 125 * clock - 1;
395
396 /* FS/LS case */
397 return 1000 * clock - 1;
398 }
399
400 /**
401 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
402 * buffer
403 *
404 * @hsotg: Programming view of DWC_otg controller
405 * @dest: Destination buffer for the packet
406 * @bytes: Number of bytes to copy to the destination
407 */
dwc2_read_packet(struct dwc2_hsotg * hsotg,u8 * dest,u16 bytes)408 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
409 {
410 u32 *data_buf = (u32 *)dest;
411 int word_count = (bytes + 3) / 4;
412 int i;
413
414 /*
415 * Todo: Account for the case where dest is not dword aligned. This
416 * requires reading data from the FIFO into a u32 temp buffer, then
417 * moving it into the data buffer.
418 */
419
420 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
421
422 for (i = 0; i < word_count; i++, data_buf++)
423 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
424 }
425
426 /**
427 * dwc2_dump_channel_info() - Prints the state of a host channel
428 *
429 * @hsotg: Programming view of DWC_otg controller
430 * @chan: Pointer to the channel to dump
431 *
432 * Must be called with interrupt disabled and spinlock held
433 *
434 * NOTE: This function will be removed once the peripheral controller code
435 * is integrated and the driver is stable
436 */
dwc2_dump_channel_info(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)437 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
438 struct dwc2_host_chan *chan)
439 {
440 #ifdef VERBOSE_DEBUG
441 int num_channels = hsotg->params.host_channels;
442 struct dwc2_qh *qh;
443 u32 hcchar;
444 u32 hcsplt;
445 u32 hctsiz;
446 u32 hc_dma;
447 int i;
448
449 if (!chan)
450 return;
451
452 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
453 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
454 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
455 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
456
457 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
458 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
459 hcchar, hcsplt);
460 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
461 hctsiz, hc_dma);
462 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
463 chan->dev_addr, chan->ep_num, chan->ep_is_in);
464 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
465 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
466 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
467 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
468 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
469 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
470 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
471 (unsigned long)chan->xfer_dma);
472 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
473 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
474 dev_dbg(hsotg->dev, " NP inactive sched:\n");
475 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
476 qh_list_entry)
477 dev_dbg(hsotg->dev, " %p\n", qh);
478 dev_dbg(hsotg->dev, " NP waiting sched:\n");
479 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
480 qh_list_entry)
481 dev_dbg(hsotg->dev, " %p\n", qh);
482 dev_dbg(hsotg->dev, " NP active sched:\n");
483 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
484 qh_list_entry)
485 dev_dbg(hsotg->dev, " %p\n", qh);
486 dev_dbg(hsotg->dev, " Channels:\n");
487 for (i = 0; i < num_channels; i++) {
488 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
489
490 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
491 }
492 #endif /* VERBOSE_DEBUG */
493 }
494
495 static int _dwc2_hcd_start(struct usb_hcd *hcd);
496
dwc2_host_start(struct dwc2_hsotg * hsotg)497 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
498 {
499 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
500
501 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
502 _dwc2_hcd_start(hcd);
503 }
504
dwc2_host_disconnect(struct dwc2_hsotg * hsotg)505 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
506 {
507 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
508
509 hcd->self.is_b_host = 0;
510 }
511
dwc2_host_hub_info(struct dwc2_hsotg * hsotg,void * context,int * hub_addr,int * hub_port)512 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
513 int *hub_addr, int *hub_port)
514 {
515 struct urb *urb = context;
516
517 if (urb->dev->tt)
518 *hub_addr = urb->dev->tt->hub->devnum;
519 else
520 *hub_addr = 0;
521 *hub_port = urb->dev->ttport;
522 }
523
524 /*
525 * =========================================================================
526 * Low Level Host Channel Access Functions
527 * =========================================================================
528 */
529
dwc2_hc_enable_slave_ints(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)530 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
531 struct dwc2_host_chan *chan)
532 {
533 u32 hcintmsk = HCINTMSK_CHHLTD;
534
535 switch (chan->ep_type) {
536 case USB_ENDPOINT_XFER_CONTROL:
537 case USB_ENDPOINT_XFER_BULK:
538 dev_vdbg(hsotg->dev, "control/bulk\n");
539 hcintmsk |= HCINTMSK_XFERCOMPL;
540 hcintmsk |= HCINTMSK_STALL;
541 hcintmsk |= HCINTMSK_XACTERR;
542 hcintmsk |= HCINTMSK_DATATGLERR;
543 if (chan->ep_is_in) {
544 hcintmsk |= HCINTMSK_BBLERR;
545 } else {
546 hcintmsk |= HCINTMSK_NAK;
547 hcintmsk |= HCINTMSK_NYET;
548 if (chan->do_ping)
549 hcintmsk |= HCINTMSK_ACK;
550 }
551
552 if (chan->do_split) {
553 hcintmsk |= HCINTMSK_NAK;
554 if (chan->complete_split)
555 hcintmsk |= HCINTMSK_NYET;
556 else
557 hcintmsk |= HCINTMSK_ACK;
558 }
559
560 if (chan->error_state)
561 hcintmsk |= HCINTMSK_ACK;
562 break;
563
564 case USB_ENDPOINT_XFER_INT:
565 if (dbg_perio())
566 dev_vdbg(hsotg->dev, "intr\n");
567 hcintmsk |= HCINTMSK_XFERCOMPL;
568 hcintmsk |= HCINTMSK_NAK;
569 hcintmsk |= HCINTMSK_STALL;
570 hcintmsk |= HCINTMSK_XACTERR;
571 hcintmsk |= HCINTMSK_DATATGLERR;
572 hcintmsk |= HCINTMSK_FRMOVRUN;
573
574 if (chan->ep_is_in)
575 hcintmsk |= HCINTMSK_BBLERR;
576 if (chan->error_state)
577 hcintmsk |= HCINTMSK_ACK;
578 if (chan->do_split) {
579 if (chan->complete_split)
580 hcintmsk |= HCINTMSK_NYET;
581 else
582 hcintmsk |= HCINTMSK_ACK;
583 }
584 break;
585
586 case USB_ENDPOINT_XFER_ISOC:
587 if (dbg_perio())
588 dev_vdbg(hsotg->dev, "isoc\n");
589 hcintmsk |= HCINTMSK_XFERCOMPL;
590 hcintmsk |= HCINTMSK_FRMOVRUN;
591 hcintmsk |= HCINTMSK_ACK;
592
593 if (chan->ep_is_in) {
594 hcintmsk |= HCINTMSK_XACTERR;
595 hcintmsk |= HCINTMSK_BBLERR;
596 }
597 break;
598 default:
599 dev_err(hsotg->dev, "## Unknown EP type ##\n");
600 break;
601 }
602
603 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
604 if (dbg_hc(chan))
605 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
606 }
607
dwc2_hc_enable_dma_ints(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)608 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
609 struct dwc2_host_chan *chan)
610 {
611 u32 hcintmsk = HCINTMSK_CHHLTD;
612
613 /*
614 * For Descriptor DMA mode core halts the channel on AHB error.
615 * Interrupt is not required.
616 */
617 if (!hsotg->params.dma_desc_enable) {
618 if (dbg_hc(chan))
619 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
620 hcintmsk |= HCINTMSK_AHBERR;
621 } else {
622 if (dbg_hc(chan))
623 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
624 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
625 hcintmsk |= HCINTMSK_XFERCOMPL;
626 }
627
628 if (chan->error_state && !chan->do_split &&
629 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
630 if (dbg_hc(chan))
631 dev_vdbg(hsotg->dev, "setting ACK\n");
632 hcintmsk |= HCINTMSK_ACK;
633 if (chan->ep_is_in) {
634 hcintmsk |= HCINTMSK_DATATGLERR;
635 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
636 hcintmsk |= HCINTMSK_NAK;
637 }
638 }
639
640 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
641 if (dbg_hc(chan))
642 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
643 }
644
dwc2_hc_enable_ints(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)645 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
646 struct dwc2_host_chan *chan)
647 {
648 u32 intmsk;
649
650 if (hsotg->params.host_dma) {
651 if (dbg_hc(chan))
652 dev_vdbg(hsotg->dev, "DMA enabled\n");
653 dwc2_hc_enable_dma_ints(hsotg, chan);
654 } else {
655 if (dbg_hc(chan))
656 dev_vdbg(hsotg->dev, "DMA disabled\n");
657 dwc2_hc_enable_slave_ints(hsotg, chan);
658 }
659
660 /* Enable the top level host channel interrupt */
661 intmsk = dwc2_readl(hsotg, HAINTMSK);
662 intmsk |= 1 << chan->hc_num;
663 dwc2_writel(hsotg, intmsk, HAINTMSK);
664 if (dbg_hc(chan))
665 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
666
667 /* Make sure host channel interrupts are enabled */
668 intmsk = dwc2_readl(hsotg, GINTMSK);
669 intmsk |= GINTSTS_HCHINT;
670 dwc2_writel(hsotg, intmsk, GINTMSK);
671 if (dbg_hc(chan))
672 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
673 }
674
675 /**
676 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
677 * a specific endpoint
678 *
679 * @hsotg: Programming view of DWC_otg controller
680 * @chan: Information needed to initialize the host channel
681 *
682 * The HCCHARn register is set up with the characteristics specified in chan.
683 * Host channel interrupts that may need to be serviced while this transfer is
684 * in progress are enabled.
685 */
dwc2_hc_init(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)686 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
687 {
688 u8 hc_num = chan->hc_num;
689 u32 hcintmsk;
690 u32 hcchar;
691 u32 hcsplt = 0;
692
693 if (dbg_hc(chan))
694 dev_vdbg(hsotg->dev, "%s()\n", __func__);
695
696 /* Clear old interrupt conditions for this host channel */
697 hcintmsk = 0xffffffff;
698 hcintmsk &= ~HCINTMSK_RESERVED14_31;
699 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
700
701 /* Enable channel interrupts required for this transfer */
702 dwc2_hc_enable_ints(hsotg, chan);
703
704 /*
705 * Program the HCCHARn register with the endpoint characteristics for
706 * the current transfer
707 */
708 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
709 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
710 if (chan->ep_is_in)
711 hcchar |= HCCHAR_EPDIR;
712 if (chan->speed == USB_SPEED_LOW)
713 hcchar |= HCCHAR_LSPDDEV;
714 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
715 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
716 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
717 if (dbg_hc(chan)) {
718 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
719 hc_num, hcchar);
720
721 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
722 __func__, hc_num);
723 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
724 chan->dev_addr);
725 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
726 chan->ep_num);
727 dev_vdbg(hsotg->dev, " Is In: %d\n",
728 chan->ep_is_in);
729 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
730 chan->speed == USB_SPEED_LOW);
731 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
732 chan->ep_type);
733 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
734 chan->max_packet);
735 }
736
737 /* Program the HCSPLT register for SPLITs */
738 if (chan->do_split) {
739 if (dbg_hc(chan))
740 dev_vdbg(hsotg->dev,
741 "Programming HC %d with split --> %s\n",
742 hc_num,
743 chan->complete_split ? "CSPLIT" : "SSPLIT");
744 if (chan->complete_split)
745 hcsplt |= HCSPLT_COMPSPLT;
746 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
747 HCSPLT_XACTPOS_MASK;
748 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
749 HCSPLT_HUBADDR_MASK;
750 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
751 HCSPLT_PRTADDR_MASK;
752 if (dbg_hc(chan)) {
753 dev_vdbg(hsotg->dev, " comp split %d\n",
754 chan->complete_split);
755 dev_vdbg(hsotg->dev, " xact pos %d\n",
756 chan->xact_pos);
757 dev_vdbg(hsotg->dev, " hub addr %d\n",
758 chan->hub_addr);
759 dev_vdbg(hsotg->dev, " hub port %d\n",
760 chan->hub_port);
761 dev_vdbg(hsotg->dev, " is_in %d\n",
762 chan->ep_is_in);
763 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
764 chan->max_packet);
765 dev_vdbg(hsotg->dev, " xferlen %d\n",
766 chan->xfer_len);
767 }
768 }
769
770 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
771 }
772
773 /**
774 * dwc2_hc_halt() - Attempts to halt a host channel
775 *
776 * @hsotg: Controller register interface
777 * @chan: Host channel to halt
778 * @halt_status: Reason for halting the channel
779 *
780 * This function should only be called in Slave mode or to abort a transfer in
781 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
782 * controller halts the channel when the transfer is complete or a condition
783 * occurs that requires application intervention.
784 *
785 * In slave mode, checks for a free request queue entry, then sets the Channel
786 * Enable and Channel Disable bits of the Host Channel Characteristics
787 * register of the specified channel to intiate the halt. If there is no free
788 * request queue entry, sets only the Channel Disable bit of the HCCHARn
789 * register to flush requests for this channel. In the latter case, sets a
790 * flag to indicate that the host channel needs to be halted when a request
791 * queue slot is open.
792 *
793 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
794 * HCCHARn register. The controller ensures there is space in the request
795 * queue before submitting the halt request.
796 *
797 * Some time may elapse before the core flushes any posted requests for this
798 * host channel and halts. The Channel Halted interrupt handler completes the
799 * deactivation of the host channel.
800 */
dwc2_hc_halt(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,enum dwc2_halt_status halt_status)801 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
802 enum dwc2_halt_status halt_status)
803 {
804 u32 nptxsts, hptxsts, hcchar;
805
806 if (dbg_hc(chan))
807 dev_vdbg(hsotg->dev, "%s()\n", __func__);
808
809 /*
810 * In buffer DMA or external DMA mode channel can't be halted
811 * for non-split periodic channels. At the end of the next
812 * uframe/frame (in the worst case), the core generates a channel
813 * halted and disables the channel automatically.
814 */
815 if ((hsotg->params.host_dma && !hsotg->params.dma_desc_enable) ||
816 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
817 if (!chan->do_split &&
818 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
819 chan->ep_type == USB_ENDPOINT_XFER_INT) &&
820 (halt_status == DWC2_HC_XFER_URB_DEQUEUE)) {
821 chan->halt_status = halt_status;
822 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
823 __func__);
824 return;
825 }
826 }
827
828 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
829 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
830
831 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
832 halt_status == DWC2_HC_XFER_AHB_ERR) {
833 /*
834 * Disable all channel interrupts except Ch Halted. The QTD
835 * and QH state associated with this transfer has been cleared
836 * (in the case of URB_DEQUEUE), so the channel needs to be
837 * shut down carefully to prevent crashes.
838 */
839 u32 hcintmsk = HCINTMSK_CHHLTD;
840
841 dev_vdbg(hsotg->dev, "dequeue/error\n");
842 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
843
844 /*
845 * Make sure no other interrupts besides halt are currently
846 * pending. Handling another interrupt could cause a crash due
847 * to the QTD and QH state.
848 */
849 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
850
851 /*
852 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
853 * even if the channel was already halted for some other
854 * reason
855 */
856 chan->halt_status = halt_status;
857
858 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
859 if (!(hcchar & HCCHAR_CHENA)) {
860 /*
861 * The channel is either already halted or it hasn't
862 * started yet. In DMA mode, the transfer may halt if
863 * it finishes normally or a condition occurs that
864 * requires driver intervention. Don't want to halt
865 * the channel again. In either Slave or DMA mode,
866 * it's possible that the transfer has been assigned
867 * to a channel, but not started yet when an URB is
868 * dequeued. Don't want to halt a channel that hasn't
869 * started yet.
870 */
871 return;
872 }
873 }
874 if (chan->halt_pending) {
875 /*
876 * A halt has already been issued for this channel. This might
877 * happen when a transfer is aborted by a higher level in
878 * the stack.
879 */
880 dev_vdbg(hsotg->dev,
881 "*** %s: Channel %d, chan->halt_pending already set ***\n",
882 __func__, chan->hc_num);
883 return;
884 }
885
886 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
887
888 /* No need to set the bit in DDMA for disabling the channel */
889 /* TODO check it everywhere channel is disabled */
890 if (!hsotg->params.dma_desc_enable) {
891 if (dbg_hc(chan))
892 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
893 hcchar |= HCCHAR_CHENA;
894 } else {
895 if (dbg_hc(chan))
896 dev_dbg(hsotg->dev, "desc DMA enabled\n");
897 }
898 hcchar |= HCCHAR_CHDIS;
899
900 if (!hsotg->params.host_dma) {
901 if (dbg_hc(chan))
902 dev_vdbg(hsotg->dev, "DMA not enabled\n");
903 hcchar |= HCCHAR_CHENA;
904
905 /* Check for space in the request queue to issue the halt */
906 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
907 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
908 dev_vdbg(hsotg->dev, "control/bulk\n");
909 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
910 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
911 dev_vdbg(hsotg->dev, "Disabling channel\n");
912 hcchar &= ~HCCHAR_CHENA;
913 }
914 } else {
915 if (dbg_perio())
916 dev_vdbg(hsotg->dev, "isoc/intr\n");
917 hptxsts = dwc2_readl(hsotg, HPTXSTS);
918 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
919 hsotg->queuing_high_bandwidth) {
920 if (dbg_perio())
921 dev_vdbg(hsotg->dev, "Disabling channel\n");
922 hcchar &= ~HCCHAR_CHENA;
923 }
924 }
925 } else {
926 if (dbg_hc(chan))
927 dev_vdbg(hsotg->dev, "DMA enabled\n");
928 }
929
930 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
931 chan->halt_status = halt_status;
932
933 if (hcchar & HCCHAR_CHENA) {
934 if (dbg_hc(chan))
935 dev_vdbg(hsotg->dev, "Channel enabled\n");
936 chan->halt_pending = 1;
937 chan->halt_on_queue = 0;
938 } else {
939 if (dbg_hc(chan))
940 dev_vdbg(hsotg->dev, "Channel disabled\n");
941 chan->halt_on_queue = 1;
942 }
943
944 if (dbg_hc(chan)) {
945 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
946 chan->hc_num);
947 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
948 hcchar);
949 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
950 chan->halt_pending);
951 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
952 chan->halt_on_queue);
953 dev_vdbg(hsotg->dev, " halt_status: %d\n",
954 chan->halt_status);
955 }
956 }
957
958 /**
959 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
960 *
961 * @hsotg: Programming view of DWC_otg controller
962 * @chan: Identifies the host channel to clean up
963 *
964 * This function is normally called after a transfer is done and the host
965 * channel is being released
966 */
dwc2_hc_cleanup(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)967 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
968 {
969 u32 hcintmsk;
970
971 chan->xfer_started = 0;
972
973 list_del_init(&chan->split_order_list_entry);
974
975 /*
976 * Clear channel interrupt enables and any unhandled channel interrupt
977 * conditions
978 */
979 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
980 hcintmsk = 0xffffffff;
981 hcintmsk &= ~HCINTMSK_RESERVED14_31;
982 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
983 }
984
985 /**
986 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
987 * which frame a periodic transfer should occur
988 *
989 * @hsotg: Programming view of DWC_otg controller
990 * @chan: Identifies the host channel to set up and its properties
991 * @hcchar: Current value of the HCCHAR register for the specified host channel
992 *
993 * This function has no effect on non-periodic transfers
994 */
dwc2_hc_set_even_odd_frame(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,u32 * hcchar)995 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
996 struct dwc2_host_chan *chan, u32 *hcchar)
997 {
998 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
999 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1000 int host_speed;
1001 int xfer_ns;
1002 int xfer_us;
1003 int bytes_in_fifo;
1004 u16 fifo_space;
1005 u16 frame_number;
1006 u16 wire_frame;
1007
1008 /*
1009 * Try to figure out if we're an even or odd frame. If we set
1010 * even and the current frame number is even the the transfer
1011 * will happen immediately. Similar if both are odd. If one is
1012 * even and the other is odd then the transfer will happen when
1013 * the frame number ticks.
1014 *
1015 * There's a bit of a balancing act to get this right.
1016 * Sometimes we may want to send data in the current frame (AK
1017 * right away). We might want to do this if the frame number
1018 * _just_ ticked, but we might also want to do this in order
1019 * to continue a split transaction that happened late in a
1020 * microframe (so we didn't know to queue the next transfer
1021 * until the frame number had ticked). The problem is that we
1022 * need a lot of knowledge to know if there's actually still
1023 * time to send things or if it would be better to wait until
1024 * the next frame.
1025 *
1026 * We can look at how much time is left in the current frame
1027 * and make a guess about whether we'll have time to transfer.
1028 * We'll do that.
1029 */
1030
1031 /* Get speed host is running at */
1032 host_speed = (chan->speed != USB_SPEED_HIGH &&
1033 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1034
1035 /* See how many bytes are in the periodic FIFO right now */
1036 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1037 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1038 bytes_in_fifo = sizeof(u32) *
1039 (hsotg->params.host_perio_tx_fifo_size -
1040 fifo_space);
1041
1042 /*
1043 * Roughly estimate bus time for everything in the periodic
1044 * queue + our new transfer. This is "rough" because we're
1045 * using a function that makes takes into account IN/OUT
1046 * and INT/ISO and we're just slamming in one value for all
1047 * transfers. This should be an over-estimate and that should
1048 * be OK, but we can probably tighten it.
1049 */
1050 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1051 chan->xfer_len + bytes_in_fifo);
1052 xfer_us = NS_TO_US(xfer_ns);
1053
1054 /* See what frame number we'll be at by the time we finish */
1055 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1056
1057 /* This is when we were scheduled to be on the wire */
1058 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1059
1060 /*
1061 * If we'd finish _after_ the frame we're scheduled in then
1062 * it's hopeless. Just schedule right away and hope for the
1063 * best. Note that it _might_ be wise to call back into the
1064 * scheduler to pick a better frame, but this is better than
1065 * nothing.
1066 */
1067 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1068 dwc2_sch_vdbg(hsotg,
1069 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1070 chan->qh, wire_frame, frame_number,
1071 dwc2_frame_num_dec(frame_number,
1072 wire_frame));
1073 wire_frame = frame_number;
1074
1075 /*
1076 * We picked a different frame number; communicate this
1077 * back to the scheduler so it doesn't try to schedule
1078 * another in the same frame.
1079 *
1080 * Remember that next_active_frame is 1 before the wire
1081 * frame.
1082 */
1083 chan->qh->next_active_frame =
1084 dwc2_frame_num_dec(frame_number, 1);
1085 }
1086
1087 if (wire_frame & 1)
1088 *hcchar |= HCCHAR_ODDFRM;
1089 else
1090 *hcchar &= ~HCCHAR_ODDFRM;
1091 }
1092 }
1093
dwc2_set_pid_isoc(struct dwc2_host_chan * chan)1094 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1095 {
1096 /* Set up the initial PID for the transfer */
1097 if (chan->speed == USB_SPEED_HIGH) {
1098 if (chan->ep_is_in) {
1099 if (chan->multi_count == 1)
1100 chan->data_pid_start = DWC2_HC_PID_DATA0;
1101 else if (chan->multi_count == 2)
1102 chan->data_pid_start = DWC2_HC_PID_DATA1;
1103 else
1104 chan->data_pid_start = DWC2_HC_PID_DATA2;
1105 } else {
1106 if (chan->multi_count == 1)
1107 chan->data_pid_start = DWC2_HC_PID_DATA0;
1108 else
1109 chan->data_pid_start = DWC2_HC_PID_MDATA;
1110 }
1111 } else {
1112 chan->data_pid_start = DWC2_HC_PID_DATA0;
1113 }
1114 }
1115
1116 /**
1117 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1118 * the Host Channel
1119 *
1120 * @hsotg: Programming view of DWC_otg controller
1121 * @chan: Information needed to initialize the host channel
1122 *
1123 * This function should only be called in Slave mode. For a channel associated
1124 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1125 * associated with a periodic EP, the periodic Tx FIFO is written.
1126 *
1127 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1128 * the number of bytes written to the Tx FIFO.
1129 */
dwc2_hc_write_packet(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)1130 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1131 struct dwc2_host_chan *chan)
1132 {
1133 u32 i;
1134 u32 remaining_count;
1135 u32 byte_count;
1136 u32 dword_count;
1137 u32 *data_buf = (u32 *)chan->xfer_buf;
1138
1139 if (dbg_hc(chan))
1140 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1141
1142 remaining_count = chan->xfer_len - chan->xfer_count;
1143 if (remaining_count > chan->max_packet)
1144 byte_count = chan->max_packet;
1145 else
1146 byte_count = remaining_count;
1147
1148 dword_count = (byte_count + 3) / 4;
1149
1150 if (((unsigned long)data_buf & 0x3) == 0) {
1151 /* xfer_buf is DWORD aligned */
1152 for (i = 0; i < dword_count; i++, data_buf++)
1153 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1154 } else {
1155 /* xfer_buf is not DWORD aligned */
1156 for (i = 0; i < dword_count; i++, data_buf++) {
1157 u32 data = data_buf[0] | data_buf[1] << 8 |
1158 data_buf[2] << 16 | data_buf[3] << 24;
1159 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1160 }
1161 }
1162
1163 chan->xfer_count += byte_count;
1164 chan->xfer_buf += byte_count;
1165 }
1166
1167 /**
1168 * dwc2_hc_do_ping() - Starts a PING transfer
1169 *
1170 * @hsotg: Programming view of DWC_otg controller
1171 * @chan: Information needed to initialize the host channel
1172 *
1173 * This function should only be called in Slave mode. The Do Ping bit is set in
1174 * the HCTSIZ register, then the channel is enabled.
1175 */
dwc2_hc_do_ping(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)1176 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1177 struct dwc2_host_chan *chan)
1178 {
1179 u32 hcchar;
1180 u32 hctsiz;
1181
1182 if (dbg_hc(chan))
1183 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1184 chan->hc_num);
1185
1186 hctsiz = TSIZ_DOPNG;
1187 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1188 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1189
1190 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1191 hcchar |= HCCHAR_CHENA;
1192 hcchar &= ~HCCHAR_CHDIS;
1193 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1194 }
1195
1196 /**
1197 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1198 * channel and starts the transfer
1199 *
1200 * @hsotg: Programming view of DWC_otg controller
1201 * @chan: Information needed to initialize the host channel. The xfer_len value
1202 * may be reduced to accommodate the max widths of the XferSize and
1203 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1204 * changed to reflect the final xfer_len value.
1205 *
1206 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1207 * the caller must ensure that there is sufficient space in the request queue
1208 * and Tx Data FIFO.
1209 *
1210 * For an OUT transfer in Slave mode, it loads a data packet into the
1211 * appropriate FIFO. If necessary, additional data packets are loaded in the
1212 * Host ISR.
1213 *
1214 * For an IN transfer in Slave mode, a data packet is requested. The data
1215 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1216 * additional data packets are requested in the Host ISR.
1217 *
1218 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1219 * register along with a packet count of 1 and the channel is enabled. This
1220 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1221 * simply set to 0 since no data transfer occurs in this case.
1222 *
1223 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1224 * all the information required to perform the subsequent data transfer. In
1225 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1226 * controller performs the entire PING protocol, then starts the data
1227 * transfer.
1228 */
dwc2_hc_start_transfer(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)1229 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1230 struct dwc2_host_chan *chan)
1231 {
1232 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1233 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1234 u32 hcchar;
1235 u32 hctsiz = 0;
1236 u16 num_packets;
1237 u32 ec_mc;
1238
1239 if (dbg_hc(chan))
1240 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1241
1242 if (chan->do_ping) {
1243 if (!hsotg->params.host_dma) {
1244 if (dbg_hc(chan))
1245 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1246 dwc2_hc_do_ping(hsotg, chan);
1247 chan->xfer_started = 1;
1248 return;
1249 }
1250
1251 if (dbg_hc(chan))
1252 dev_vdbg(hsotg->dev, "ping, DMA\n");
1253
1254 hctsiz |= TSIZ_DOPNG;
1255 }
1256
1257 if (chan->do_split) {
1258 if (dbg_hc(chan))
1259 dev_vdbg(hsotg->dev, "split\n");
1260 num_packets = 1;
1261
1262 if (chan->complete_split && !chan->ep_is_in)
1263 /*
1264 * For CSPLIT OUT Transfer, set the size to 0 so the
1265 * core doesn't expect any data written to the FIFO
1266 */
1267 chan->xfer_len = 0;
1268 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1269 chan->xfer_len = chan->max_packet;
1270 else if (!chan->ep_is_in && chan->xfer_len > 188)
1271 chan->xfer_len = 188;
1272
1273 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1274 TSIZ_XFERSIZE_MASK;
1275
1276 /* For split set ec_mc for immediate retries */
1277 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1278 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1279 ec_mc = 3;
1280 else
1281 ec_mc = 1;
1282 } else {
1283 if (dbg_hc(chan))
1284 dev_vdbg(hsotg->dev, "no split\n");
1285 /*
1286 * Ensure that the transfer length and packet count will fit
1287 * in the widths allocated for them in the HCTSIZn register
1288 */
1289 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1290 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1291 /*
1292 * Make sure the transfer size is no larger than one
1293 * (micro)frame's worth of data. (A check was done
1294 * when the periodic transfer was accepted to ensure
1295 * that a (micro)frame's worth of data can be
1296 * programmed into a channel.)
1297 */
1298 u32 max_periodic_len =
1299 chan->multi_count * chan->max_packet;
1300
1301 if (chan->xfer_len > max_periodic_len)
1302 chan->xfer_len = max_periodic_len;
1303 } else if (chan->xfer_len > max_hc_xfer_size) {
1304 /*
1305 * Make sure that xfer_len is a multiple of max packet
1306 * size
1307 */
1308 chan->xfer_len =
1309 max_hc_xfer_size - chan->max_packet + 1;
1310 }
1311
1312 if (chan->xfer_len > 0) {
1313 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1314 chan->max_packet;
1315 if (num_packets > max_hc_pkt_count) {
1316 num_packets = max_hc_pkt_count;
1317 chan->xfer_len = num_packets * chan->max_packet;
1318 } else if (chan->ep_is_in) {
1319 /*
1320 * Always program an integral # of max packets
1321 * for IN transfers.
1322 * Note: This assumes that the input buffer is
1323 * aligned and sized accordingly.
1324 */
1325 chan->xfer_len = num_packets * chan->max_packet;
1326 }
1327 } else {
1328 /* Need 1 packet for transfer length of 0 */
1329 num_packets = 1;
1330 }
1331
1332 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1333 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1334 /*
1335 * Make sure that the multi_count field matches the
1336 * actual transfer length
1337 */
1338 chan->multi_count = num_packets;
1339
1340 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1341 dwc2_set_pid_isoc(chan);
1342
1343 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1344 TSIZ_XFERSIZE_MASK;
1345
1346 /* The ec_mc gets the multi_count for non-split */
1347 ec_mc = chan->multi_count;
1348 }
1349
1350 chan->start_pkt_count = num_packets;
1351 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1352 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1353 TSIZ_SC_MC_PID_MASK;
1354 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1355 if (dbg_hc(chan)) {
1356 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1357 hctsiz, chan->hc_num);
1358
1359 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1360 chan->hc_num);
1361 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1362 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1363 TSIZ_XFERSIZE_SHIFT);
1364 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1365 (hctsiz & TSIZ_PKTCNT_MASK) >>
1366 TSIZ_PKTCNT_SHIFT);
1367 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1368 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1369 TSIZ_SC_MC_PID_SHIFT);
1370 }
1371
1372 if (hsotg->params.host_dma) {
1373 dma_addr_t dma_addr;
1374
1375 if (chan->align_buf) {
1376 if (dbg_hc(chan))
1377 dev_vdbg(hsotg->dev, "align_buf\n");
1378 dma_addr = chan->align_buf;
1379 } else {
1380 dma_addr = chan->xfer_dma;
1381 }
1382 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1383
1384 if (dbg_hc(chan))
1385 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1386 (unsigned long)dma_addr, chan->hc_num);
1387 }
1388
1389 /* Start the split */
1390 if (chan->do_split) {
1391 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1392
1393 hcsplt |= HCSPLT_SPLTENA;
1394 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1395 }
1396
1397 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1398 hcchar &= ~HCCHAR_MULTICNT_MASK;
1399 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1400 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1401
1402 if (hcchar & HCCHAR_CHDIS)
1403 dev_warn(hsotg->dev,
1404 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1405 __func__, chan->hc_num, hcchar);
1406
1407 /* Set host channel enable after all other setup is complete */
1408 hcchar |= HCCHAR_CHENA;
1409 hcchar &= ~HCCHAR_CHDIS;
1410
1411 if (dbg_hc(chan))
1412 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1413 (hcchar & HCCHAR_MULTICNT_MASK) >>
1414 HCCHAR_MULTICNT_SHIFT);
1415
1416 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1417 if (dbg_hc(chan))
1418 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1419 chan->hc_num);
1420
1421 chan->xfer_started = 1;
1422 chan->requests++;
1423
1424 if (!hsotg->params.host_dma &&
1425 !chan->ep_is_in && chan->xfer_len > 0)
1426 /* Load OUT packet into the appropriate Tx FIFO */
1427 dwc2_hc_write_packet(hsotg, chan);
1428 }
1429
1430 /**
1431 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1432 * host channel and starts the transfer in Descriptor DMA mode
1433 *
1434 * @hsotg: Programming view of DWC_otg controller
1435 * @chan: Information needed to initialize the host channel
1436 *
1437 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1438 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1439 * with micro-frame bitmap.
1440 *
1441 * Initializes HCDMA register with descriptor list address and CTD value then
1442 * starts the transfer via enabling the channel.
1443 */
dwc2_hc_start_transfer_ddma(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)1444 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1445 struct dwc2_host_chan *chan)
1446 {
1447 u32 hcchar;
1448 u32 hctsiz = 0;
1449
1450 if (chan->do_ping)
1451 hctsiz |= TSIZ_DOPNG;
1452
1453 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1454 dwc2_set_pid_isoc(chan);
1455
1456 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1457 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1458 TSIZ_SC_MC_PID_MASK;
1459
1460 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1461 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1462
1463 /* Non-zero only for high-speed interrupt endpoints */
1464 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1465
1466 if (dbg_hc(chan)) {
1467 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1468 chan->hc_num);
1469 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1470 chan->data_pid_start);
1471 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1472 }
1473
1474 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1475
1476 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1477 chan->desc_list_sz, DMA_TO_DEVICE);
1478
1479 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1480
1481 if (dbg_hc(chan))
1482 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1483 &chan->desc_list_addr, chan->hc_num);
1484
1485 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1486 hcchar &= ~HCCHAR_MULTICNT_MASK;
1487 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1488 HCCHAR_MULTICNT_MASK;
1489
1490 if (hcchar & HCCHAR_CHDIS)
1491 dev_warn(hsotg->dev,
1492 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1493 __func__, chan->hc_num, hcchar);
1494
1495 /* Set host channel enable after all other setup is complete */
1496 hcchar |= HCCHAR_CHENA;
1497 hcchar &= ~HCCHAR_CHDIS;
1498
1499 if (dbg_hc(chan))
1500 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1501 (hcchar & HCCHAR_MULTICNT_MASK) >>
1502 HCCHAR_MULTICNT_SHIFT);
1503
1504 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1505 if (dbg_hc(chan))
1506 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1507 chan->hc_num);
1508
1509 chan->xfer_started = 1;
1510 chan->requests++;
1511 }
1512
1513 /**
1514 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1515 * a previous call to dwc2_hc_start_transfer()
1516 *
1517 * @hsotg: Programming view of DWC_otg controller
1518 * @chan: Information needed to initialize the host channel
1519 *
1520 * The caller must ensure there is sufficient space in the request queue and Tx
1521 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1522 * the controller acts autonomously to complete transfers programmed to a host
1523 * channel.
1524 *
1525 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1526 * if there is any data remaining to be queued. For an IN transfer, another
1527 * data packet is always requested. For the SETUP phase of a control transfer,
1528 * this function does nothing.
1529 *
1530 * Return: 1 if a new request is queued, 0 if no more requests are required
1531 * for this transfer
1532 */
dwc2_hc_continue_transfer(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan)1533 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1534 struct dwc2_host_chan *chan)
1535 {
1536 if (dbg_hc(chan))
1537 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1538 chan->hc_num);
1539
1540 if (chan->do_split)
1541 /* SPLITs always queue just once per channel */
1542 return 0;
1543
1544 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1545 /* SETUPs are queued only once since they can't be NAK'd */
1546 return 0;
1547
1548 if (chan->ep_is_in) {
1549 /*
1550 * Always queue another request for other IN transfers. If
1551 * back-to-back INs are issued and NAKs are received for both,
1552 * the driver may still be processing the first NAK when the
1553 * second NAK is received. When the interrupt handler clears
1554 * the NAK interrupt for the first NAK, the second NAK will
1555 * not be seen. So we can't depend on the NAK interrupt
1556 * handler to requeue a NAK'd request. Instead, IN requests
1557 * are issued each time this function is called. When the
1558 * transfer completes, the extra requests for the channel will
1559 * be flushed.
1560 */
1561 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1562
1563 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1564 hcchar |= HCCHAR_CHENA;
1565 hcchar &= ~HCCHAR_CHDIS;
1566 if (dbg_hc(chan))
1567 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1568 hcchar);
1569 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1570 chan->requests++;
1571 return 1;
1572 }
1573
1574 /* OUT transfers */
1575
1576 if (chan->xfer_count < chan->xfer_len) {
1577 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1578 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1579 u32 hcchar = dwc2_readl(hsotg,
1580 HCCHAR(chan->hc_num));
1581
1582 dwc2_hc_set_even_odd_frame(hsotg, chan,
1583 &hcchar);
1584 }
1585
1586 /* Load OUT packet into the appropriate Tx FIFO */
1587 dwc2_hc_write_packet(hsotg, chan);
1588 chan->requests++;
1589 return 1;
1590 }
1591
1592 return 0;
1593 }
1594
1595 /*
1596 * =========================================================================
1597 * HCD
1598 * =========================================================================
1599 */
1600
1601 /*
1602 * Processes all the URBs in a single list of QHs. Completes them with
1603 * -ETIMEDOUT and frees the QTD.
1604 *
1605 * Must be called with interrupt disabled and spinlock held
1606 */
dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg * hsotg,struct list_head * qh_list)1607 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1608 struct list_head *qh_list)
1609 {
1610 struct dwc2_qh *qh, *qh_tmp;
1611 struct dwc2_qtd *qtd, *qtd_tmp;
1612
1613 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1614 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1615 qtd_list_entry) {
1616 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1617 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1618 }
1619 }
1620 }
1621
dwc2_qh_list_free(struct dwc2_hsotg * hsotg,struct list_head * qh_list)1622 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1623 struct list_head *qh_list)
1624 {
1625 struct dwc2_qtd *qtd, *qtd_tmp;
1626 struct dwc2_qh *qh, *qh_tmp;
1627 unsigned long flags;
1628
1629 if (!qh_list->next)
1630 /* The list hasn't been initialized yet */
1631 return;
1632
1633 spin_lock_irqsave(&hsotg->lock, flags);
1634
1635 /* Ensure there are no QTDs or URBs left */
1636 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1637
1638 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1639 dwc2_hcd_qh_unlink(hsotg, qh);
1640
1641 /* Free each QTD in the QH's QTD list */
1642 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1643 qtd_list_entry)
1644 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1645
1646 if (qh->channel && qh->channel->qh == qh)
1647 qh->channel->qh = NULL;
1648
1649 spin_unlock_irqrestore(&hsotg->lock, flags);
1650 dwc2_hcd_qh_free(hsotg, qh);
1651 spin_lock_irqsave(&hsotg->lock, flags);
1652 }
1653
1654 spin_unlock_irqrestore(&hsotg->lock, flags);
1655 }
1656
1657 /*
1658 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1659 * and periodic schedules. The QTD associated with each URB is removed from
1660 * the schedule and freed. This function may be called when a disconnect is
1661 * detected or when the HCD is being stopped.
1662 *
1663 * Must be called with interrupt disabled and spinlock held
1664 */
dwc2_kill_all_urbs(struct dwc2_hsotg * hsotg)1665 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1666 {
1667 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1668 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1669 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1670 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1671 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1672 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1673 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1674 }
1675
1676 /**
1677 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1678 *
1679 * @hsotg: Pointer to struct dwc2_hsotg
1680 */
dwc2_hcd_start(struct dwc2_hsotg * hsotg)1681 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1682 {
1683 u32 hprt0;
1684
1685 if (hsotg->op_state == OTG_STATE_B_HOST) {
1686 /*
1687 * Reset the port. During a HNP mode switch the reset
1688 * needs to occur within 1ms and have a duration of at
1689 * least 50ms.
1690 */
1691 hprt0 = dwc2_read_hprt0(hsotg);
1692 hprt0 |= HPRT0_RST;
1693 dwc2_writel(hsotg, hprt0, HPRT0);
1694 }
1695
1696 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1697 msecs_to_jiffies(50));
1698 }
1699
1700 /* Must be called with interrupt disabled and spinlock held */
dwc2_hcd_cleanup_channels(struct dwc2_hsotg * hsotg)1701 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1702 {
1703 int num_channels = hsotg->params.host_channels;
1704 struct dwc2_host_chan *channel;
1705 u32 hcchar;
1706 int i;
1707
1708 if (!hsotg->params.host_dma) {
1709 /* Flush out any channel requests in slave mode */
1710 for (i = 0; i < num_channels; i++) {
1711 channel = hsotg->hc_ptr_array[i];
1712 if (!list_empty(&channel->hc_list_entry))
1713 continue;
1714 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1715 if (hcchar & HCCHAR_CHENA) {
1716 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1717 hcchar |= HCCHAR_CHDIS;
1718 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1719 }
1720 }
1721 }
1722
1723 for (i = 0; i < num_channels; i++) {
1724 channel = hsotg->hc_ptr_array[i];
1725 if (!list_empty(&channel->hc_list_entry))
1726 continue;
1727 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1728 if (hcchar & HCCHAR_CHENA) {
1729 /* Halt the channel */
1730 hcchar |= HCCHAR_CHDIS;
1731 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1732 }
1733
1734 dwc2_hc_cleanup(hsotg, channel);
1735 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1736 /*
1737 * Added for Descriptor DMA to prevent channel double cleanup in
1738 * release_channel_ddma(), which is called from ep_disable when
1739 * device disconnects
1740 */
1741 channel->qh = NULL;
1742 }
1743 /* All channels have been freed, mark them available */
1744 if (hsotg->params.uframe_sched) {
1745 hsotg->available_host_channels =
1746 hsotg->params.host_channels;
1747 } else {
1748 hsotg->non_periodic_channels = 0;
1749 hsotg->periodic_channels = 0;
1750 }
1751 }
1752
1753 /**
1754 * dwc2_hcd_connect() - Handles connect of the HCD
1755 *
1756 * @hsotg: Pointer to struct dwc2_hsotg
1757 *
1758 * Must be called with interrupt disabled and spinlock held
1759 */
dwc2_hcd_connect(struct dwc2_hsotg * hsotg)1760 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1761 {
1762 if (hsotg->lx_state != DWC2_L0)
1763 usb_hcd_resume_root_hub(hsotg->priv);
1764
1765 hsotg->flags.b.port_connect_status_change = 1;
1766 hsotg->flags.b.port_connect_status = 1;
1767 }
1768
1769 /**
1770 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1771 *
1772 * @hsotg: Pointer to struct dwc2_hsotg
1773 * @force: If true, we won't try to reconnect even if we see device connected.
1774 *
1775 * Must be called with interrupt disabled and spinlock held
1776 */
dwc2_hcd_disconnect(struct dwc2_hsotg * hsotg,bool force)1777 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1778 {
1779 u32 intr;
1780 u32 hprt0;
1781
1782 /* Set status flags for the hub driver */
1783 hsotg->flags.b.port_connect_status_change = 1;
1784 hsotg->flags.b.port_connect_status = 0;
1785
1786 /*
1787 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1788 * interrupt mask and status bits and disabling subsequent host
1789 * channel interrupts.
1790 */
1791 intr = dwc2_readl(hsotg, GINTMSK);
1792 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1793 dwc2_writel(hsotg, intr, GINTMSK);
1794 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1795 dwc2_writel(hsotg, intr, GINTSTS);
1796
1797 /*
1798 * Turn off the vbus power only if the core has transitioned to device
1799 * mode. If still in host mode, need to keep power on to detect a
1800 * reconnection.
1801 */
1802 if (dwc2_is_device_mode(hsotg)) {
1803 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1804 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1805 dwc2_writel(hsotg, 0, HPRT0);
1806 }
1807
1808 dwc2_disable_host_interrupts(hsotg);
1809 }
1810
1811 /* Respond with an error status to all URBs in the schedule */
1812 dwc2_kill_all_urbs(hsotg);
1813
1814 if (dwc2_is_host_mode(hsotg))
1815 /* Clean up any host channels that were in use */
1816 dwc2_hcd_cleanup_channels(hsotg);
1817
1818 dwc2_host_disconnect(hsotg);
1819
1820 /*
1821 * Add an extra check here to see if we're actually connected but
1822 * we don't have a detection interrupt pending. This can happen if:
1823 * 1. hardware sees connect
1824 * 2. hardware sees disconnect
1825 * 3. hardware sees connect
1826 * 4. dwc2_port_intr() - clears connect interrupt
1827 * 5. dwc2_handle_common_intr() - calls here
1828 *
1829 * Without the extra check here we will end calling disconnect
1830 * and won't get any future interrupts to handle the connect.
1831 */
1832 hprt0 = dwc2_readl(hsotg, HPRT0);
1833
1834 if (!force && !(hprt0 & HPRT0_CONNDET) &&
1835 (hprt0 & HPRT0_CONNSTS))
1836 dwc2_hcd_connect(hsotg);
1837 else if (hsotg->lx_state != DWC2_L0)
1838 usb_hcd_resume_root_hub(hsotg->priv);
1839 }
1840
1841 /**
1842 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1843 *
1844 * @hsotg: Pointer to struct dwc2_hsotg
1845 */
dwc2_hcd_rem_wakeup(struct dwc2_hsotg * hsotg)1846 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1847 {
1848 if (hsotg->bus_suspended) {
1849 hsotg->flags.b.port_suspend_change = 1;
1850 usb_hcd_resume_root_hub(hsotg->priv);
1851 }
1852
1853 if (hsotg->lx_state == DWC2_L1)
1854 hsotg->flags.b.port_l1_change = 1;
1855 }
1856
1857 /**
1858 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1859 *
1860 * @hsotg: Pointer to struct dwc2_hsotg
1861 *
1862 * Must be called with interrupt disabled and spinlock held
1863 */
dwc2_hcd_stop(struct dwc2_hsotg * hsotg)1864 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1865 {
1866 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1867
1868 /*
1869 * The root hub should be disconnected before this function is called.
1870 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1871 * and the QH lists (via ..._hcd_endpoint_disable).
1872 */
1873
1874 /* Turn off all host-specific interrupts */
1875 dwc2_disable_host_interrupts(hsotg);
1876
1877 /* Turn off the vbus power */
1878 dev_dbg(hsotg->dev, "PortPower off\n");
1879 dwc2_writel(hsotg, 0, HPRT0);
1880 }
1881
1882 /* Caller must hold driver lock */
dwc2_hcd_urb_enqueue(struct dwc2_hsotg * hsotg,struct dwc2_hcd_urb * urb,struct dwc2_qh * qh,struct dwc2_qtd * qtd)1883 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
1884 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
1885 struct dwc2_qtd *qtd)
1886 {
1887 u32 intr_mask;
1888 int retval;
1889 int dev_speed;
1890
1891 if (!hsotg->flags.b.port_connect_status) {
1892 /* No longer connected */
1893 dev_err(hsotg->dev, "Not connected\n");
1894 return -ENODEV;
1895 }
1896
1897 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1898
1899 /* Some configurations cannot support LS traffic on a FS root port */
1900 if ((dev_speed == USB_SPEED_LOW) &&
1901 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
1902 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
1903 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
1904 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1905
1906 if (prtspd == HPRT0_SPD_FULL_SPEED)
1907 return -ENODEV;
1908 }
1909
1910 if (!qtd)
1911 return -EINVAL;
1912
1913 dwc2_hcd_qtd_init(qtd, urb);
1914 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
1915 if (retval) {
1916 dev_err(hsotg->dev,
1917 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
1918 retval);
1919 return retval;
1920 }
1921
1922 intr_mask = dwc2_readl(hsotg, GINTMSK);
1923 if (!(intr_mask & GINTSTS_SOF)) {
1924 enum dwc2_transaction_type tr_type;
1925
1926 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
1927 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
1928 /*
1929 * Do not schedule SG transactions until qtd has
1930 * URB_GIVEBACK_ASAP set
1931 */
1932 return 0;
1933
1934 tr_type = dwc2_hcd_select_transactions(hsotg);
1935 if (tr_type != DWC2_TRANSACTION_NONE)
1936 dwc2_hcd_queue_transactions(hsotg, tr_type);
1937 }
1938
1939 return 0;
1940 }
1941
1942 /* Must be called with interrupt disabled and spinlock held */
dwc2_hcd_urb_dequeue(struct dwc2_hsotg * hsotg,struct dwc2_hcd_urb * urb)1943 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
1944 struct dwc2_hcd_urb *urb)
1945 {
1946 struct dwc2_qh *qh;
1947 struct dwc2_qtd *urb_qtd;
1948
1949 urb_qtd = urb->qtd;
1950 if (!urb_qtd) {
1951 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
1952 return -EINVAL;
1953 }
1954
1955 qh = urb_qtd->qh;
1956 if (!qh) {
1957 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
1958 return -EINVAL;
1959 }
1960
1961 urb->priv = NULL;
1962
1963 if (urb_qtd->in_process && qh->channel) {
1964 dwc2_dump_channel_info(hsotg, qh->channel);
1965
1966 /* The QTD is in process (it has been assigned to a channel) */
1967 if (hsotg->flags.b.port_connect_status)
1968 /*
1969 * If still connected (i.e. in host mode), halt the
1970 * channel so it can be used for other transfers. If
1971 * no longer connected, the host registers can't be
1972 * written to halt the channel since the core is in
1973 * device mode.
1974 */
1975 dwc2_hc_halt(hsotg, qh->channel,
1976 DWC2_HC_XFER_URB_DEQUEUE);
1977 }
1978
1979 /*
1980 * Free the QTD and clean up the associated QH. Leave the QH in the
1981 * schedule if it has any remaining QTDs.
1982 */
1983 if (!hsotg->params.dma_desc_enable) {
1984 u8 in_process = urb_qtd->in_process;
1985
1986 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1987 if (in_process) {
1988 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
1989 qh->channel = NULL;
1990 } else if (list_empty(&qh->qtd_list)) {
1991 dwc2_hcd_qh_unlink(hsotg, qh);
1992 }
1993 } else {
1994 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1995 }
1996
1997 return 0;
1998 }
1999
2000 /* Must NOT be called with interrupt disabled or spinlock held */
dwc2_hcd_endpoint_disable(struct dwc2_hsotg * hsotg,struct usb_host_endpoint * ep,int retry)2001 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2002 struct usb_host_endpoint *ep, int retry)
2003 {
2004 struct dwc2_qtd *qtd, *qtd_tmp;
2005 struct dwc2_qh *qh;
2006 unsigned long flags;
2007 int rc;
2008
2009 spin_lock_irqsave(&hsotg->lock, flags);
2010
2011 qh = ep->hcpriv;
2012 if (!qh) {
2013 rc = -EINVAL;
2014 goto err;
2015 }
2016
2017 while (!list_empty(&qh->qtd_list) && retry--) {
2018 if (retry == 0) {
2019 dev_err(hsotg->dev,
2020 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2021 rc = -EBUSY;
2022 goto err;
2023 }
2024
2025 spin_unlock_irqrestore(&hsotg->lock, flags);
2026 msleep(20);
2027 spin_lock_irqsave(&hsotg->lock, flags);
2028 qh = ep->hcpriv;
2029 if (!qh) {
2030 rc = -EINVAL;
2031 goto err;
2032 }
2033 }
2034
2035 dwc2_hcd_qh_unlink(hsotg, qh);
2036
2037 /* Free each QTD in the QH's QTD list */
2038 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2039 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2040
2041 ep->hcpriv = NULL;
2042
2043 if (qh->channel && qh->channel->qh == qh)
2044 qh->channel->qh = NULL;
2045
2046 spin_unlock_irqrestore(&hsotg->lock, flags);
2047
2048 dwc2_hcd_qh_free(hsotg, qh);
2049
2050 return 0;
2051
2052 err:
2053 ep->hcpriv = NULL;
2054 spin_unlock_irqrestore(&hsotg->lock, flags);
2055
2056 return rc;
2057 }
2058
2059 /* Must be called with interrupt disabled and spinlock held */
dwc2_hcd_endpoint_reset(struct dwc2_hsotg * hsotg,struct usb_host_endpoint * ep)2060 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2061 struct usb_host_endpoint *ep)
2062 {
2063 struct dwc2_qh *qh = ep->hcpriv;
2064
2065 if (!qh)
2066 return -EINVAL;
2067
2068 qh->data_toggle = DWC2_HC_PID_DATA0;
2069
2070 return 0;
2071 }
2072
2073 /**
2074 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2075 * prepares the core for device mode or host mode operation
2076 *
2077 * @hsotg: Programming view of the DWC_otg controller
2078 * @initial_setup: If true then this is the first init for this instance.
2079 */
dwc2_core_init(struct dwc2_hsotg * hsotg,bool initial_setup)2080 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2081 {
2082 u32 usbcfg, otgctl;
2083 int retval;
2084
2085 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2086
2087 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2088
2089 /* Set ULPI External VBUS bit if needed */
2090 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2091 if (hsotg->params.phy_ulpi_ext_vbus)
2092 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2093
2094 /* Set external TS Dline pulsing bit if needed */
2095 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2096 if (hsotg->params.ts_dline)
2097 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2098
2099 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2100
2101 /*
2102 * Reset the Controller
2103 *
2104 * We only need to reset the controller if this is a re-init.
2105 * For the first init we know for sure that earlier code reset us (it
2106 * needed to in order to properly detect various parameters).
2107 */
2108 if (!initial_setup) {
2109 retval = dwc2_core_reset(hsotg, false);
2110 if (retval) {
2111 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2112 __func__);
2113 return retval;
2114 }
2115 }
2116
2117 /*
2118 * This needs to happen in FS mode before any other programming occurs
2119 */
2120 retval = dwc2_phy_init(hsotg, initial_setup);
2121 if (retval)
2122 return retval;
2123
2124 /* Program the GAHBCFG Register */
2125 retval = dwc2_gahbcfg_init(hsotg);
2126 if (retval)
2127 return retval;
2128
2129 /* Program the GUSBCFG register */
2130 dwc2_gusbcfg_init(hsotg);
2131
2132 /* Program the GOTGCTL register */
2133 otgctl = dwc2_readl(hsotg, GOTGCTL);
2134 otgctl &= ~GOTGCTL_OTGVER;
2135 dwc2_writel(hsotg, otgctl, GOTGCTL);
2136
2137 /* Clear the SRP success bit for FS-I2c */
2138 hsotg->srp_success = 0;
2139
2140 /* Enable common interrupts */
2141 dwc2_enable_common_interrupts(hsotg);
2142
2143 /*
2144 * Do device or host initialization based on mode during PCD and
2145 * HCD initialization
2146 */
2147 if (dwc2_is_host_mode(hsotg)) {
2148 dev_dbg(hsotg->dev, "Host Mode\n");
2149 hsotg->op_state = OTG_STATE_A_HOST;
2150 } else {
2151 dev_dbg(hsotg->dev, "Device Mode\n");
2152 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2153 }
2154
2155 return 0;
2156 }
2157
2158 /**
2159 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2160 * Host mode
2161 *
2162 * @hsotg: Programming view of DWC_otg controller
2163 *
2164 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2165 * request queues. Host channels are reset to ensure that they are ready for
2166 * performing transfers.
2167 */
dwc2_core_host_init(struct dwc2_hsotg * hsotg)2168 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2169 {
2170 u32 hcfg, hfir, otgctl, usbcfg;
2171
2172 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2173
2174 /* Set HS/FS Timeout Calibration to 7 (max available value).
2175 * The number of PHY clocks that the application programs in
2176 * this field is added to the high/full speed interpacket timeout
2177 * duration in the core to account for any additional delays
2178 * introduced by the PHY. This can be required, because the delay
2179 * introduced by the PHY in generating the linestate condition
2180 * can vary from one PHY to another.
2181 */
2182 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2183 usbcfg |= GUSBCFG_TOUTCAL(7);
2184 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2185
2186 /* Restart the Phy Clock */
2187 dwc2_writel(hsotg, 0, PCGCTL);
2188
2189 /* Initialize Host Configuration Register */
2190 dwc2_init_fs_ls_pclk_sel(hsotg);
2191 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2192 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2193 hcfg = dwc2_readl(hsotg, HCFG);
2194 hcfg |= HCFG_FSLSSUPP;
2195 dwc2_writel(hsotg, hcfg, HCFG);
2196 }
2197
2198 /*
2199 * This bit allows dynamic reloading of the HFIR register during
2200 * runtime. This bit needs to be programmed during initial configuration
2201 * and its value must not be changed during runtime.
2202 */
2203 if (hsotg->params.reload_ctl) {
2204 hfir = dwc2_readl(hsotg, HFIR);
2205 hfir |= HFIR_RLDCTRL;
2206 dwc2_writel(hsotg, hfir, HFIR);
2207 }
2208
2209 if (hsotg->params.dma_desc_enable) {
2210 u32 op_mode = hsotg->hw_params.op_mode;
2211
2212 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2213 !hsotg->hw_params.dma_desc_enable ||
2214 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2215 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2216 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2217 dev_err(hsotg->dev,
2218 "Hardware does not support descriptor DMA mode -\n");
2219 dev_err(hsotg->dev,
2220 "falling back to buffer DMA mode.\n");
2221 hsotg->params.dma_desc_enable = false;
2222 } else {
2223 hcfg = dwc2_readl(hsotg, HCFG);
2224 hcfg |= HCFG_DESCDMA;
2225 dwc2_writel(hsotg, hcfg, HCFG);
2226 }
2227 }
2228
2229 /* Configure data FIFO sizes */
2230 dwc2_config_fifos(hsotg);
2231
2232 /* TODO - check this */
2233 /* Clear Host Set HNP Enable in the OTG Control Register */
2234 otgctl = dwc2_readl(hsotg, GOTGCTL);
2235 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2236 dwc2_writel(hsotg, otgctl, GOTGCTL);
2237
2238 /* Make sure the FIFOs are flushed */
2239 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2240 dwc2_flush_rx_fifo(hsotg);
2241
2242 /* Clear Host Set HNP Enable in the OTG Control Register */
2243 otgctl = dwc2_readl(hsotg, GOTGCTL);
2244 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2245 dwc2_writel(hsotg, otgctl, GOTGCTL);
2246
2247 if (!hsotg->params.dma_desc_enable) {
2248 int num_channels, i;
2249 u32 hcchar;
2250
2251 /* Flush out any leftover queued requests */
2252 num_channels = hsotg->params.host_channels;
2253 for (i = 0; i < num_channels; i++) {
2254 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2255 if (hcchar & HCCHAR_CHENA) {
2256 hcchar &= ~HCCHAR_CHENA;
2257 hcchar |= HCCHAR_CHDIS;
2258 hcchar &= ~HCCHAR_EPDIR;
2259 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2260 }
2261 }
2262
2263 /* Halt all channels to put them into a known state */
2264 for (i = 0; i < num_channels; i++) {
2265 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2266 if (hcchar & HCCHAR_CHENA) {
2267 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2268 hcchar &= ~HCCHAR_EPDIR;
2269 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2270 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2271 __func__, i);
2272
2273 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2274 HCCHAR_CHENA,
2275 1000)) {
2276 dev_warn(hsotg->dev,
2277 "Unable to clear enable on channel %d\n",
2278 i);
2279 }
2280 }
2281 }
2282 }
2283
2284 /* Enable ACG feature in host mode, if supported */
2285 dwc2_enable_acg(hsotg);
2286
2287 /* Turn on the vbus power */
2288 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2289 if (hsotg->op_state == OTG_STATE_A_HOST) {
2290 u32 hprt0 = dwc2_read_hprt0(hsotg);
2291
2292 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2293 !!(hprt0 & HPRT0_PWR));
2294 if (!(hprt0 & HPRT0_PWR)) {
2295 hprt0 |= HPRT0_PWR;
2296 dwc2_writel(hsotg, hprt0, HPRT0);
2297 }
2298 }
2299
2300 dwc2_enable_host_interrupts(hsotg);
2301 }
2302
2303 /*
2304 * Initializes dynamic portions of the DWC_otg HCD state
2305 *
2306 * Must be called with interrupt disabled and spinlock held
2307 */
dwc2_hcd_reinit(struct dwc2_hsotg * hsotg)2308 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2309 {
2310 struct dwc2_host_chan *chan, *chan_tmp;
2311 int num_channels;
2312 int i;
2313
2314 hsotg->flags.d32 = 0;
2315 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2316
2317 if (hsotg->params.uframe_sched) {
2318 hsotg->available_host_channels =
2319 hsotg->params.host_channels;
2320 } else {
2321 hsotg->non_periodic_channels = 0;
2322 hsotg->periodic_channels = 0;
2323 }
2324
2325 /*
2326 * Put all channels in the free channel list and clean up channel
2327 * states
2328 */
2329 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2330 hc_list_entry)
2331 list_del_init(&chan->hc_list_entry);
2332
2333 num_channels = hsotg->params.host_channels;
2334 for (i = 0; i < num_channels; i++) {
2335 chan = hsotg->hc_ptr_array[i];
2336 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2337 dwc2_hc_cleanup(hsotg, chan);
2338 }
2339
2340 /* Initialize the DWC core for host mode operation */
2341 dwc2_core_host_init(hsotg);
2342 }
2343
dwc2_hc_init_split(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,struct dwc2_qtd * qtd,struct dwc2_hcd_urb * urb)2344 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2345 struct dwc2_host_chan *chan,
2346 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2347 {
2348 int hub_addr, hub_port;
2349
2350 chan->do_split = 1;
2351 chan->xact_pos = qtd->isoc_split_pos;
2352 chan->complete_split = qtd->complete_split;
2353 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2354 chan->hub_addr = (u8)hub_addr;
2355 chan->hub_port = (u8)hub_port;
2356 }
2357
dwc2_hc_init_xfer(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,struct dwc2_qtd * qtd)2358 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2359 struct dwc2_host_chan *chan,
2360 struct dwc2_qtd *qtd)
2361 {
2362 struct dwc2_hcd_urb *urb = qtd->urb;
2363 struct dwc2_hcd_iso_packet_desc *frame_desc;
2364
2365 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2366 case USB_ENDPOINT_XFER_CONTROL:
2367 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2368
2369 switch (qtd->control_phase) {
2370 case DWC2_CONTROL_SETUP:
2371 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2372 chan->do_ping = 0;
2373 chan->ep_is_in = 0;
2374 chan->data_pid_start = DWC2_HC_PID_SETUP;
2375 if (hsotg->params.host_dma)
2376 chan->xfer_dma = urb->setup_dma;
2377 else
2378 chan->xfer_buf = urb->setup_packet;
2379 chan->xfer_len = 8;
2380 break;
2381
2382 case DWC2_CONTROL_DATA:
2383 dev_vdbg(hsotg->dev, " Control data transaction\n");
2384 chan->data_pid_start = qtd->data_toggle;
2385 break;
2386
2387 case DWC2_CONTROL_STATUS:
2388 /*
2389 * Direction is opposite of data direction or IN if no
2390 * data
2391 */
2392 dev_vdbg(hsotg->dev, " Control status transaction\n");
2393 if (urb->length == 0)
2394 chan->ep_is_in = 1;
2395 else
2396 chan->ep_is_in =
2397 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2398 if (chan->ep_is_in)
2399 chan->do_ping = 0;
2400 chan->data_pid_start = DWC2_HC_PID_DATA1;
2401 chan->xfer_len = 0;
2402 if (hsotg->params.host_dma)
2403 chan->xfer_dma = hsotg->status_buf_dma;
2404 else
2405 chan->xfer_buf = hsotg->status_buf;
2406 break;
2407 }
2408 break;
2409
2410 case USB_ENDPOINT_XFER_BULK:
2411 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2412 break;
2413
2414 case USB_ENDPOINT_XFER_INT:
2415 chan->ep_type = USB_ENDPOINT_XFER_INT;
2416 break;
2417
2418 case USB_ENDPOINT_XFER_ISOC:
2419 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2420 if (hsotg->params.dma_desc_enable)
2421 break;
2422
2423 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2424 frame_desc->status = 0;
2425
2426 if (hsotg->params.host_dma) {
2427 chan->xfer_dma = urb->dma;
2428 chan->xfer_dma += frame_desc->offset +
2429 qtd->isoc_split_offset;
2430 } else {
2431 chan->xfer_buf = urb->buf;
2432 chan->xfer_buf += frame_desc->offset +
2433 qtd->isoc_split_offset;
2434 }
2435
2436 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2437
2438 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2439 if (chan->xfer_len <= 188)
2440 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2441 else
2442 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2443 }
2444 break;
2445 }
2446 }
2447
dwc2_alloc_qh_dma_aligned_buf(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,struct dwc2_qtd * qtd,struct dwc2_host_chan * chan)2448 static int dwc2_alloc_qh_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2449 struct dwc2_qh *qh,
2450 struct dwc2_qtd *qtd,
2451 struct dwc2_host_chan *chan)
2452 {
2453 u32 offset;
2454
2455 if (!hsotg->unaligned_cache ||
2456 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2457 return -ENOMEM;
2458
2459 if (!qh->dw_align_buf) {
2460 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2461 GFP_ATOMIC | GFP_DMA);
2462 if (!qh->dw_align_buf)
2463 return -ENOMEM;
2464 }
2465
2466 if (!chan->ep_is_in) {
2467 if (qh->do_split) {
2468 offset = chan->xfer_dma - qtd->urb->dma;
2469 memcpy(qh->dw_align_buf, (u8 *)qtd->urb->buf + offset,
2470 (chan->xfer_len > 188 ? 188 : chan->xfer_len));
2471 } else {
2472 offset = chan->xfer_dma - qtd->urb->dma;
2473 memcpy(qh->dw_align_buf, (u8 *)qtd->urb->buf + offset,
2474 chan->xfer_len);
2475 }
2476 }
2477
2478 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2479 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2480 DMA_FROM_DEVICE);
2481
2482 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2483 dev_err(hsotg->dev, "can't map align_buf\n");
2484 chan->align_buf = 0;
2485 return -EINVAL;
2486 }
2487
2488 chan->align_buf = qh->dw_align_buf_dma;
2489 return 0;
2490 }
2491
2492 #define DWC2_USB_DMA_ALIGN 4
2493
dwc2_free_dma_aligned_buffer(struct urb * urb)2494 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2495 {
2496 void *stored_xfer_buffer;
2497 size_t length;
2498
2499 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2500 return;
2501
2502 /* Restore urb->transfer_buffer from the end of the allocated area */
2503 memcpy(&stored_xfer_buffer,
2504 PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length,
2505 dma_get_cache_alignment()),
2506 sizeof(urb->transfer_buffer));
2507
2508 if (usb_urb_dir_in(urb)) {
2509 if (usb_pipeisoc(urb->pipe))
2510 length = urb->transfer_buffer_length;
2511 else
2512 length = urb->actual_length;
2513
2514 memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
2515 }
2516 kfree(urb->transfer_buffer);
2517 urb->transfer_buffer = stored_xfer_buffer;
2518
2519 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2520 }
2521
dwc2_alloc_dma_aligned_buffer(struct urb * urb,gfp_t mem_flags)2522 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2523 {
2524 void *kmalloc_ptr;
2525 size_t kmalloc_size;
2526
2527 if (urb->num_sgs || urb->sg ||
2528 urb->transfer_buffer_length == 0 ||
2529 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2530 return 0;
2531
2532 /*
2533 * Allocate a buffer with enough padding for original transfer_buffer
2534 * pointer. This allocation is guaranteed to be aligned properly for
2535 * DMA
2536 */
2537 kmalloc_size = urb->transfer_buffer_length +
2538 (dma_get_cache_alignment() - 1) +
2539 sizeof(urb->transfer_buffer);
2540
2541 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2542 if (!kmalloc_ptr)
2543 return -ENOMEM;
2544
2545 /*
2546 * Position value of original urb->transfer_buffer pointer to the end
2547 * of allocation for later referencing
2548 */
2549 memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length,
2550 dma_get_cache_alignment()),
2551 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2552
2553 if (usb_urb_dir_out(urb))
2554 memcpy(kmalloc_ptr, urb->transfer_buffer,
2555 urb->transfer_buffer_length);
2556 urb->transfer_buffer = kmalloc_ptr;
2557
2558 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2559
2560 return 0;
2561 }
2562
dwc2_map_urb_for_dma(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)2563 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2564 gfp_t mem_flags)
2565 {
2566 int ret;
2567
2568 /* We assume setup_dma is always aligned; warn if not */
2569 WARN_ON_ONCE(urb->setup_dma &&
2570 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2571
2572 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2573 if (ret)
2574 return ret;
2575
2576 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2577 if (ret)
2578 dwc2_free_dma_aligned_buffer(urb);
2579
2580 return ret;
2581 }
2582
dwc2_unmap_urb_for_dma(struct usb_hcd * hcd,struct urb * urb)2583 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2584 {
2585 usb_hcd_unmap_urb_for_dma(hcd, urb);
2586 dwc2_free_dma_aligned_buffer(urb);
2587 }
2588
2589 /**
2590 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2591 * channel and initializes the host channel to perform the transactions. The
2592 * host channel is removed from the free list.
2593 *
2594 * @hsotg: The HCD state structure
2595 * @qh: Transactions from the first QTD for this QH are selected and assigned
2596 * to a free host channel
2597 */
dwc2_assign_and_init_hc(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)2598 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2599 {
2600 struct dwc2_host_chan *chan;
2601 struct dwc2_hcd_urb *urb;
2602 struct dwc2_qtd *qtd;
2603
2604 if (dbg_qh(qh))
2605 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2606
2607 if (list_empty(&qh->qtd_list)) {
2608 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2609 return -ENOMEM;
2610 }
2611
2612 if (list_empty(&hsotg->free_hc_list)) {
2613 dev_dbg(hsotg->dev, "No free channel to assign\n");
2614 return -ENOMEM;
2615 }
2616
2617 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2618 hc_list_entry);
2619
2620 /* Remove host channel from free list */
2621 list_del_init(&chan->hc_list_entry);
2622
2623 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2624 urb = qtd->urb;
2625 qh->channel = chan;
2626 qtd->in_process = 1;
2627
2628 /*
2629 * Use usb_pipedevice to determine device address. This address is
2630 * 0 before the SET_ADDRESS command and the correct address afterward.
2631 */
2632 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2633 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2634 chan->speed = qh->dev_speed;
2635 chan->max_packet = qh->maxp;
2636
2637 chan->xfer_started = 0;
2638 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2639 chan->error_state = (qtd->error_count > 0);
2640 chan->halt_on_queue = 0;
2641 chan->halt_pending = 0;
2642 chan->requests = 0;
2643
2644 /*
2645 * The following values may be modified in the transfer type section
2646 * below. The xfer_len value may be reduced when the transfer is
2647 * started to accommodate the max widths of the XferSize and PktCnt
2648 * fields in the HCTSIZn register.
2649 */
2650
2651 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2652 if (chan->ep_is_in)
2653 chan->do_ping = 0;
2654 else
2655 chan->do_ping = qh->ping_state;
2656
2657 chan->data_pid_start = qh->data_toggle;
2658 chan->multi_count = 1;
2659
2660 if (urb->actual_length > urb->length &&
2661 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2662 urb->actual_length = urb->length;
2663
2664 if (hsotg->params.host_dma)
2665 chan->xfer_dma = urb->dma + urb->actual_length;
2666 else
2667 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2668
2669 chan->xfer_len = urb->length - urb->actual_length;
2670 chan->xfer_count = 0;
2671
2672 /* Set the split attributes if required */
2673 if (qh->do_split)
2674 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2675 else
2676 chan->do_split = 0;
2677
2678 /* Set the transfer attributes */
2679 dwc2_hc_init_xfer(hsotg, chan, qtd);
2680
2681 /* For non-dword aligned buffers */
2682 if (hsotg->params.host_dma && (chan->xfer_dma & 0x3) &&
2683 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2684 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2685 if (dwc2_alloc_qh_dma_aligned_buf(hsotg, qh, qtd, chan)) {
2686 dev_err(hsotg->dev,
2687 "Failed to allocate memory to handle non-aligned buffer\n");
2688 /* Add channel back to free list */
2689 chan->align_buf = 0;
2690 chan->multi_count = 0;
2691 list_add_tail(&chan->hc_list_entry,
2692 &hsotg->free_hc_list);
2693 qtd->in_process = 0;
2694 qh->channel = NULL;
2695 return -ENOMEM;
2696 }
2697 } else {
2698 /*
2699 * We assume that DMA is always aligned in other case,
2700 * Warn if not.
2701 */
2702 WARN_ON_ONCE(hsotg->params.host_dma &&
2703 (chan->xfer_dma & 0x3));
2704 chan->align_buf = 0;
2705 }
2706
2707 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2708 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2709 /*
2710 * This value may be modified when the transfer is started
2711 * to reflect the actual transfer length
2712 */
2713 chan->multi_count = qh->maxp_mult;
2714
2715 if (hsotg->params.dma_desc_enable) {
2716 chan->desc_list_addr = qh->desc_list_dma;
2717 chan->desc_list_sz = qh->desc_list_sz;
2718 }
2719
2720 dwc2_hc_init(hsotg, chan);
2721 chan->qh = qh;
2722
2723 return 0;
2724 }
2725
2726 /**
2727 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2728 * schedule and assigns them to available host channels. Called from the HCD
2729 * interrupt handler functions.
2730 *
2731 * @hsotg: The HCD state structure
2732 *
2733 * Return: The types of new transactions that were assigned to host channels
2734 */
dwc2_hcd_select_transactions(struct dwc2_hsotg * hsotg)2735 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2736 struct dwc2_hsotg *hsotg)
2737 {
2738 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2739 struct list_head *qh_ptr;
2740 struct dwc2_qh *qh;
2741 int num_channels;
2742
2743 #ifdef DWC2_DEBUG_SOF
2744 dev_vdbg(hsotg->dev, " Select Transactions\n");
2745 #endif
2746
2747 /* Process entries in the periodic ready list */
2748 qh_ptr = hsotg->periodic_sched_ready.next;
2749 while (qh_ptr != &hsotg->periodic_sched_ready) {
2750 if (list_empty(&hsotg->free_hc_list))
2751 break;
2752 if (hsotg->params.uframe_sched) {
2753 if (hsotg->available_host_channels <= 1)
2754 break;
2755 hsotg->available_host_channels--;
2756 }
2757 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2758 if (dwc2_assign_and_init_hc(hsotg, qh))
2759 break;
2760
2761 /*
2762 * Move the QH from the periodic ready schedule to the
2763 * periodic assigned schedule
2764 */
2765 qh_ptr = qh_ptr->next;
2766 list_move_tail(&qh->qh_list_entry,
2767 &hsotg->periodic_sched_assigned);
2768 ret_val = DWC2_TRANSACTION_PERIODIC;
2769 }
2770
2771 /*
2772 * Process entries in the inactive portion of the non-periodic
2773 * schedule. Some free host channels may not be used if they are
2774 * reserved for periodic transfers.
2775 */
2776 num_channels = hsotg->params.host_channels;
2777 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2778 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2779 if (!hsotg->params.uframe_sched &&
2780 hsotg->non_periodic_channels >= num_channels -
2781 hsotg->periodic_channels)
2782 break;
2783 if (list_empty(&hsotg->free_hc_list))
2784 break;
2785 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2786 if (hsotg->params.uframe_sched) {
2787 if (hsotg->available_host_channels < 1)
2788 break;
2789 hsotg->available_host_channels--;
2790 }
2791
2792 if (dwc2_assign_and_init_hc(hsotg, qh))
2793 break;
2794
2795 /*
2796 * Move the QH from the non-periodic inactive schedule to the
2797 * non-periodic active schedule
2798 */
2799 qh_ptr = qh_ptr->next;
2800 list_move_tail(&qh->qh_list_entry,
2801 &hsotg->non_periodic_sched_active);
2802
2803 if (ret_val == DWC2_TRANSACTION_NONE)
2804 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2805 else
2806 ret_val = DWC2_TRANSACTION_ALL;
2807
2808 if (!hsotg->params.uframe_sched)
2809 hsotg->non_periodic_channels++;
2810 }
2811
2812 return ret_val;
2813 }
2814
2815 /**
2816 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2817 * a host channel associated with either a periodic or non-periodic transfer
2818 *
2819 * @hsotg: The HCD state structure
2820 * @chan: Host channel descriptor associated with either a periodic or
2821 * non-periodic transfer
2822 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2823 * for periodic transfers or the non-periodic Tx FIFO
2824 * for non-periodic transfers
2825 *
2826 * Return: 1 if a request is queued and more requests may be needed to
2827 * complete the transfer, 0 if no more requests are required for this
2828 * transfer, -1 if there is insufficient space in the Tx FIFO
2829 *
2830 * This function assumes that there is space available in the appropriate
2831 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2832 * it checks whether space is available in the appropriate Tx FIFO.
2833 *
2834 * Must be called with interrupt disabled and spinlock held
2835 */
dwc2_queue_transaction(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,u16 fifo_dwords_avail)2836 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2837 struct dwc2_host_chan *chan,
2838 u16 fifo_dwords_avail)
2839 {
2840 int retval = 0;
2841
2842 if (chan->do_split)
2843 /* Put ourselves on the list to keep order straight */
2844 list_move_tail(&chan->split_order_list_entry,
2845 &hsotg->split_order);
2846
2847 if (hsotg->params.host_dma && chan->qh) {
2848 if (hsotg->params.dma_desc_enable) {
2849 if (!chan->xfer_started ||
2850 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2851 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2852 chan->qh->ping_state = 0;
2853 }
2854 } else if (!chan->xfer_started) {
2855 dwc2_hc_start_transfer(hsotg, chan);
2856 chan->qh->ping_state = 0;
2857 }
2858 } else if (chan->halt_pending) {
2859 /* Don't queue a request if the channel has been halted */
2860 } else if (chan->halt_on_queue) {
2861 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2862 } else if (chan->do_ping) {
2863 if (!chan->xfer_started)
2864 dwc2_hc_start_transfer(hsotg, chan);
2865 } else if (!chan->ep_is_in ||
2866 chan->data_pid_start == DWC2_HC_PID_SETUP) {
2867 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2868 if (!chan->xfer_started) {
2869 dwc2_hc_start_transfer(hsotg, chan);
2870 retval = 1;
2871 } else if (!hsotg->params.host_dma) {
2872 retval = dwc2_hc_continue_transfer(hsotg, chan);
2873 }
2874 } else {
2875 retval = -1;
2876 }
2877 } else {
2878 if (!chan->xfer_started) {
2879 dwc2_hc_start_transfer(hsotg, chan);
2880 retval = 1;
2881 } else if (!hsotg->params.host_dma) {
2882 retval = dwc2_hc_continue_transfer(hsotg, chan);
2883 }
2884 }
2885
2886 return retval;
2887 }
2888
2889 /*
2890 * Processes periodic channels for the next frame and queues transactions for
2891 * these channels to the DWC_otg controller. After queueing transactions, the
2892 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2893 * to queue as Periodic Tx FIFO or request queue space becomes available.
2894 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2895 *
2896 * Must be called with interrupt disabled and spinlock held
2897 */
dwc2_process_periodic_channels(struct dwc2_hsotg * hsotg)2898 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2899 {
2900 struct list_head *qh_ptr;
2901 struct dwc2_qh *qh;
2902 u32 tx_status;
2903 u32 fspcavail;
2904 u32 gintmsk;
2905 int status;
2906 bool no_queue_space = false;
2907 bool no_fifo_space = false;
2908 u32 qspcavail;
2909
2910 /* If empty list then just adjust interrupt enables */
2911 if (list_empty(&hsotg->periodic_sched_assigned))
2912 goto exit;
2913
2914 if (dbg_perio())
2915 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2916
2917 tx_status = dwc2_readl(hsotg, HPTXSTS);
2918 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2919 TXSTS_QSPCAVAIL_SHIFT;
2920 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2921 TXSTS_FSPCAVAIL_SHIFT;
2922
2923 if (dbg_perio()) {
2924 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
2925 qspcavail);
2926 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
2927 fspcavail);
2928 }
2929
2930 qh_ptr = hsotg->periodic_sched_assigned.next;
2931 while (qh_ptr != &hsotg->periodic_sched_assigned) {
2932 tx_status = dwc2_readl(hsotg, HPTXSTS);
2933 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2934 TXSTS_QSPCAVAIL_SHIFT;
2935 if (qspcavail == 0) {
2936 no_queue_space = true;
2937 break;
2938 }
2939
2940 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2941 if (!qh->channel) {
2942 qh_ptr = qh_ptr->next;
2943 continue;
2944 }
2945
2946 /* Make sure EP's TT buffer is clean before queueing qtds */
2947 if (qh->tt_buffer_dirty) {
2948 qh_ptr = qh_ptr->next;
2949 continue;
2950 }
2951
2952 /*
2953 * Set a flag if we're queuing high-bandwidth in slave mode.
2954 * The flag prevents any halts to get into the request queue in
2955 * the middle of multiple high-bandwidth packets getting queued.
2956 */
2957 if (!hsotg->params.host_dma &&
2958 qh->channel->multi_count > 1)
2959 hsotg->queuing_high_bandwidth = 1;
2960
2961 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2962 TXSTS_FSPCAVAIL_SHIFT;
2963 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2964 if (status < 0) {
2965 no_fifo_space = true;
2966 break;
2967 }
2968
2969 /*
2970 * In Slave mode, stay on the current transfer until there is
2971 * nothing more to do or the high-bandwidth request count is
2972 * reached. In DMA mode, only need to queue one request. The
2973 * controller automatically handles multiple packets for
2974 * high-bandwidth transfers.
2975 */
2976 if (hsotg->params.host_dma || status == 0 ||
2977 qh->channel->requests == qh->channel->multi_count) {
2978 qh_ptr = qh_ptr->next;
2979 /*
2980 * Move the QH from the periodic assigned schedule to
2981 * the periodic queued schedule
2982 */
2983 list_move_tail(&qh->qh_list_entry,
2984 &hsotg->periodic_sched_queued);
2985
2986 /* done queuing high bandwidth */
2987 hsotg->queuing_high_bandwidth = 0;
2988 }
2989 }
2990
2991 exit:
2992 if (no_queue_space || no_fifo_space ||
2993 (!hsotg->params.host_dma &&
2994 !list_empty(&hsotg->periodic_sched_assigned))) {
2995 /*
2996 * May need to queue more transactions as the request
2997 * queue or Tx FIFO empties. Enable the periodic Tx
2998 * FIFO empty interrupt. (Always use the half-empty
2999 * level to ensure that new requests are loaded as
3000 * soon as possible.)
3001 */
3002 gintmsk = dwc2_readl(hsotg, GINTMSK);
3003 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3004 gintmsk |= GINTSTS_PTXFEMP;
3005 dwc2_writel(hsotg, gintmsk, GINTMSK);
3006 }
3007 } else {
3008 /*
3009 * Disable the Tx FIFO empty interrupt since there are
3010 * no more transactions that need to be queued right
3011 * now. This function is called from interrupt
3012 * handlers to queue more transactions as transfer
3013 * states change.
3014 */
3015 gintmsk = dwc2_readl(hsotg, GINTMSK);
3016 if (gintmsk & GINTSTS_PTXFEMP) {
3017 gintmsk &= ~GINTSTS_PTXFEMP;
3018 dwc2_writel(hsotg, gintmsk, GINTMSK);
3019 }
3020 }
3021 }
3022
3023 /*
3024 * Processes active non-periodic channels and queues transactions for these
3025 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3026 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3027 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3028 * FIFO Empty interrupt is disabled.
3029 *
3030 * Must be called with interrupt disabled and spinlock held
3031 */
dwc2_process_non_periodic_channels(struct dwc2_hsotg * hsotg)3032 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3033 {
3034 struct list_head *orig_qh_ptr;
3035 struct dwc2_qh *qh;
3036 u32 tx_status;
3037 u32 qspcavail;
3038 u32 fspcavail;
3039 u32 gintmsk;
3040 int status;
3041 int no_queue_space = 0;
3042 int no_fifo_space = 0;
3043 int more_to_do = 0;
3044
3045 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3046
3047 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3048 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3049 TXSTS_QSPCAVAIL_SHIFT;
3050 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3051 TXSTS_FSPCAVAIL_SHIFT;
3052 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3053 qspcavail);
3054 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3055 fspcavail);
3056
3057 /*
3058 * Keep track of the starting point. Skip over the start-of-list
3059 * entry.
3060 */
3061 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3062 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3063 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3064
3065 /*
3066 * Process once through the active list or until no more space is
3067 * available in the request queue or the Tx FIFO
3068 */
3069 do {
3070 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3071 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3072 TXSTS_QSPCAVAIL_SHIFT;
3073 if (!hsotg->params.host_dma && qspcavail == 0) {
3074 no_queue_space = 1;
3075 break;
3076 }
3077
3078 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3079 qh_list_entry);
3080 if (!qh->channel)
3081 goto next;
3082
3083 /* Make sure EP's TT buffer is clean before queueing qtds */
3084 if (qh->tt_buffer_dirty)
3085 goto next;
3086
3087 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3088 TXSTS_FSPCAVAIL_SHIFT;
3089 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3090
3091 if (status > 0) {
3092 more_to_do = 1;
3093 } else if (status < 0) {
3094 no_fifo_space = 1;
3095 break;
3096 }
3097 next:
3098 /* Advance to next QH, skipping start-of-list entry */
3099 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3100 if (hsotg->non_periodic_qh_ptr ==
3101 &hsotg->non_periodic_sched_active)
3102 hsotg->non_periodic_qh_ptr =
3103 hsotg->non_periodic_qh_ptr->next;
3104 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3105
3106 if (!hsotg->params.host_dma) {
3107 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3108 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3109 TXSTS_QSPCAVAIL_SHIFT;
3110 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3111 TXSTS_FSPCAVAIL_SHIFT;
3112 dev_vdbg(hsotg->dev,
3113 " NP Tx Req Queue Space Avail (after queue): %d\n",
3114 qspcavail);
3115 dev_vdbg(hsotg->dev,
3116 " NP Tx FIFO Space Avail (after queue): %d\n",
3117 fspcavail);
3118
3119 if (more_to_do || no_queue_space || no_fifo_space) {
3120 /*
3121 * May need to queue more transactions as the request
3122 * queue or Tx FIFO empties. Enable the non-periodic
3123 * Tx FIFO empty interrupt. (Always use the half-empty
3124 * level to ensure that new requests are loaded as
3125 * soon as possible.)
3126 */
3127 gintmsk = dwc2_readl(hsotg, GINTMSK);
3128 gintmsk |= GINTSTS_NPTXFEMP;
3129 dwc2_writel(hsotg, gintmsk, GINTMSK);
3130 } else {
3131 /*
3132 * Disable the Tx FIFO empty interrupt since there are
3133 * no more transactions that need to be queued right
3134 * now. This function is called from interrupt
3135 * handlers to queue more transactions as transfer
3136 * states change.
3137 */
3138 gintmsk = dwc2_readl(hsotg, GINTMSK);
3139 gintmsk &= ~GINTSTS_NPTXFEMP;
3140 dwc2_writel(hsotg, gintmsk, GINTMSK);
3141 }
3142 }
3143 }
3144
3145 /**
3146 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3147 * and queues transactions for these channels to the DWC_otg controller. Called
3148 * from the HCD interrupt handler functions.
3149 *
3150 * @hsotg: The HCD state structure
3151 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3152 * or both)
3153 *
3154 * Must be called with interrupt disabled and spinlock held
3155 */
dwc2_hcd_queue_transactions(struct dwc2_hsotg * hsotg,enum dwc2_transaction_type tr_type)3156 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3157 enum dwc2_transaction_type tr_type)
3158 {
3159 #ifdef DWC2_DEBUG_SOF
3160 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3161 #endif
3162 /* Process host channels associated with periodic transfers */
3163 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3164 tr_type == DWC2_TRANSACTION_ALL)
3165 dwc2_process_periodic_channels(hsotg);
3166
3167 /* Process host channels associated with non-periodic transfers */
3168 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3169 tr_type == DWC2_TRANSACTION_ALL) {
3170 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3171 dwc2_process_non_periodic_channels(hsotg);
3172 } else {
3173 /*
3174 * Ensure NP Tx FIFO empty interrupt is disabled when
3175 * there are no non-periodic transfers to process
3176 */
3177 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3178
3179 gintmsk &= ~GINTSTS_NPTXFEMP;
3180 dwc2_writel(hsotg, gintmsk, GINTMSK);
3181 }
3182 }
3183 }
3184
dwc2_conn_id_status_change(struct work_struct * work)3185 static void dwc2_conn_id_status_change(struct work_struct *work)
3186 {
3187 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3188 wf_otg);
3189 u32 count = 0;
3190 u32 gotgctl;
3191 unsigned long flags;
3192
3193 dev_dbg(hsotg->dev, "%s()\n", __func__);
3194
3195 if (!hsotg->ll_phy_enabled && dwc2_is_host_mode(hsotg))
3196 dwc2_lowlevel_phy_enable(hsotg);
3197
3198 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3199 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3200 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3201 !!(gotgctl & GOTGCTL_CONID_B));
3202
3203 /* B-Device connector (Device Mode) */
3204 if (gotgctl & GOTGCTL_CONID_B) {
3205 dwc2_vbus_supply_exit(hsotg);
3206 /* Wait for switch to device mode */
3207 dev_dbg(hsotg->dev, "connId B\n");
3208 if (hsotg->bus_suspended) {
3209 dev_info(hsotg->dev,
3210 "Do port resume before switching to device mode\n");
3211 dwc2_port_resume(hsotg);
3212 }
3213 while (!dwc2_is_device_mode(hsotg)) {
3214 dev_info(hsotg->dev,
3215 "Waiting for Peripheral Mode, Mode=%s\n",
3216 dwc2_is_host_mode(hsotg) ? "Host" :
3217 "Peripheral");
3218 msleep(20);
3219 /*
3220 * Sometimes the initial GOTGCTRL read is wrong, so
3221 * check it again and jump to host mode if that was
3222 * the case.
3223 */
3224 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3225 if (!(gotgctl & GOTGCTL_CONID_B))
3226 goto host;
3227 if (++count > 250)
3228 break;
3229 }
3230 if (count > 250)
3231 dev_err(hsotg->dev,
3232 "Connection id status change timed out\n");
3233 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3234 dwc2_core_init(hsotg, false);
3235 dwc2_enable_global_interrupts(hsotg);
3236 spin_lock_irqsave(&hsotg->lock, flags);
3237 dwc2_hsotg_core_init_disconnected(hsotg, false);
3238 spin_unlock_irqrestore(&hsotg->lock, flags);
3239 /* Enable ACG feature in device mode,if supported */
3240 dwc2_enable_acg(hsotg);
3241 dwc2_hsotg_core_connect(hsotg);
3242 } else {
3243 host:
3244 /* A-Device connector (Host Mode) */
3245 dev_dbg(hsotg->dev, "connId A\n");
3246 while (!dwc2_is_host_mode(hsotg)) {
3247 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3248 dwc2_is_host_mode(hsotg) ?
3249 "Host" : "Peripheral");
3250 msleep(20);
3251 if (++count > 250)
3252 break;
3253 }
3254 if (count > 250)
3255 dev_err(hsotg->dev,
3256 "Connection id status change timed out\n");
3257
3258 spin_lock_irqsave(&hsotg->lock, flags);
3259 dwc2_hsotg_disconnect(hsotg);
3260 spin_unlock_irqrestore(&hsotg->lock, flags);
3261
3262 hsotg->op_state = OTG_STATE_A_HOST;
3263 /* Initialize the Core for Host mode */
3264 dwc2_core_init(hsotg, false);
3265 dwc2_enable_global_interrupts(hsotg);
3266 dwc2_hcd_start(hsotg);
3267 }
3268 }
3269
dwc2_wakeup_detected(struct timer_list * t)3270 static void dwc2_wakeup_detected(struct timer_list *t)
3271 {
3272 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3273 u32 hprt0;
3274
3275 dev_dbg(hsotg->dev, "%s()\n", __func__);
3276
3277 /*
3278 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3279 * so that OPT tests pass with all PHYs.)
3280 */
3281 hprt0 = dwc2_read_hprt0(hsotg);
3282 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3283 hprt0 &= ~HPRT0_RES;
3284 dwc2_writel(hsotg, hprt0, HPRT0);
3285 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3286 dwc2_readl(hsotg, HPRT0));
3287
3288 dwc2_hcd_rem_wakeup(hsotg);
3289 hsotg->bus_suspended = false;
3290
3291 /* Change to L0 state */
3292 hsotg->lx_state = DWC2_L0;
3293 }
3294
dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg * hsotg)3295 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3296 {
3297 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3298
3299 return hcd->self.b_hnp_enable;
3300 }
3301
3302 /* Must NOT be called with interrupt disabled or spinlock held */
dwc2_port_suspend(struct dwc2_hsotg * hsotg,u16 windex)3303 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3304 {
3305 unsigned long flags;
3306 u32 hprt0;
3307 u32 pcgctl;
3308 u32 gotgctl;
3309
3310 dev_dbg(hsotg->dev, "%s()\n", __func__);
3311
3312 spin_lock_irqsave(&hsotg->lock, flags);
3313
3314 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3315 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3316 gotgctl |= GOTGCTL_HSTSETHNPEN;
3317 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3318 hsotg->op_state = OTG_STATE_A_SUSPEND;
3319 }
3320
3321 hprt0 = dwc2_read_hprt0(hsotg);
3322 hprt0 |= HPRT0_SUSP;
3323 dwc2_writel(hsotg, hprt0, HPRT0);
3324
3325 hsotg->bus_suspended = true;
3326
3327 /*
3328 * If power_down is supported, Phy clock will be suspended
3329 * after registers are backuped.
3330 */
3331 if (!hsotg->params.power_down) {
3332 /* Suspend the Phy Clock */
3333 pcgctl = dwc2_readl(hsotg, PCGCTL);
3334 pcgctl |= PCGCTL_STOPPCLK;
3335 dwc2_writel(hsotg, pcgctl, PCGCTL);
3336 udelay(10);
3337 }
3338
3339 /* For HNP the bus must be suspended for at least 200ms */
3340 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3341 pcgctl = dwc2_readl(hsotg, PCGCTL);
3342 pcgctl &= ~PCGCTL_STOPPCLK;
3343 dwc2_writel(hsotg, pcgctl, PCGCTL);
3344
3345 spin_unlock_irqrestore(&hsotg->lock, flags);
3346
3347 msleep(200);
3348 } else {
3349 spin_unlock_irqrestore(&hsotg->lock, flags);
3350 }
3351 }
3352
3353 /* Must NOT be called with interrupt disabled or spinlock held */
dwc2_port_resume(struct dwc2_hsotg * hsotg)3354 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3355 {
3356 unsigned long flags;
3357 u32 hprt0;
3358 u32 pcgctl;
3359
3360 spin_lock_irqsave(&hsotg->lock, flags);
3361
3362 /*
3363 * If power_down is supported, Phy clock is already resumed
3364 * after registers restore.
3365 */
3366 if (!hsotg->params.power_down) {
3367 pcgctl = dwc2_readl(hsotg, PCGCTL);
3368 pcgctl &= ~PCGCTL_STOPPCLK;
3369 dwc2_writel(hsotg, pcgctl, PCGCTL);
3370 spin_unlock_irqrestore(&hsotg->lock, flags);
3371 msleep(20);
3372 spin_lock_irqsave(&hsotg->lock, flags);
3373 }
3374
3375 hprt0 = dwc2_read_hprt0(hsotg);
3376 hprt0 |= HPRT0_RES;
3377 hprt0 &= ~HPRT0_SUSP;
3378 dwc2_writel(hsotg, hprt0, HPRT0);
3379 spin_unlock_irqrestore(&hsotg->lock, flags);
3380
3381 msleep(USB_RESUME_TIMEOUT);
3382
3383 spin_lock_irqsave(&hsotg->lock, flags);
3384 hprt0 = dwc2_read_hprt0(hsotg);
3385 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3386 dwc2_writel(hsotg, hprt0, HPRT0);
3387 hsotg->bus_suspended = false;
3388 spin_unlock_irqrestore(&hsotg->lock, flags);
3389 }
3390
3391 /* Handles hub class-specific requests */
dwc2_hcd_hub_control(struct dwc2_hsotg * hsotg,u16 typereq,u16 wvalue,u16 windex,char * buf,u16 wlength)3392 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3393 u16 wvalue, u16 windex, char *buf, u16 wlength)
3394 {
3395 struct usb_hub_descriptor *hub_desc;
3396 int retval = 0;
3397 u32 hprt0;
3398 u32 port_status;
3399 u32 speed;
3400 u32 pcgctl;
3401 u32 pwr;
3402
3403 switch (typereq) {
3404 case ClearHubFeature:
3405 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3406
3407 switch (wvalue) {
3408 case C_HUB_LOCAL_POWER:
3409 case C_HUB_OVER_CURRENT:
3410 /* Nothing required here */
3411 break;
3412
3413 default:
3414 retval = -EINVAL;
3415 dev_err(hsotg->dev,
3416 "ClearHubFeature request %1xh unknown\n",
3417 wvalue);
3418 }
3419 break;
3420
3421 case ClearPortFeature:
3422 if (wvalue != USB_PORT_FEAT_L1)
3423 if (!windex || windex > 1)
3424 goto error;
3425 switch (wvalue) {
3426 case USB_PORT_FEAT_ENABLE:
3427 dev_dbg(hsotg->dev,
3428 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3429 hprt0 = dwc2_read_hprt0(hsotg);
3430 hprt0 |= HPRT0_ENA;
3431 dwc2_writel(hsotg, hprt0, HPRT0);
3432 break;
3433
3434 case USB_PORT_FEAT_SUSPEND:
3435 dev_dbg(hsotg->dev,
3436 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3437
3438 if (hsotg->bus_suspended) {
3439 if (hsotg->hibernated)
3440 dwc2_exit_hibernation(hsotg, 0, 0, 1);
3441 else
3442 dwc2_port_resume(hsotg);
3443 }
3444 break;
3445
3446 case USB_PORT_FEAT_POWER:
3447 dev_dbg(hsotg->dev,
3448 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3449 hprt0 = dwc2_read_hprt0(hsotg);
3450 pwr = hprt0 & HPRT0_PWR;
3451 hprt0 &= ~HPRT0_PWR;
3452 dwc2_writel(hsotg, hprt0, HPRT0);
3453 if (pwr)
3454 dwc2_vbus_supply_exit(hsotg);
3455 break;
3456
3457 case USB_PORT_FEAT_INDICATOR:
3458 dev_dbg(hsotg->dev,
3459 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3460 /* Port indicator not supported */
3461 break;
3462
3463 case USB_PORT_FEAT_C_CONNECTION:
3464 /*
3465 * Clears driver's internal Connect Status Change flag
3466 */
3467 dev_dbg(hsotg->dev,
3468 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3469 hsotg->flags.b.port_connect_status_change = 0;
3470 break;
3471
3472 case USB_PORT_FEAT_C_RESET:
3473 /* Clears driver's internal Port Reset Change flag */
3474 dev_dbg(hsotg->dev,
3475 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3476 hsotg->flags.b.port_reset_change = 0;
3477 break;
3478
3479 case USB_PORT_FEAT_C_ENABLE:
3480 /*
3481 * Clears the driver's internal Port Enable/Disable
3482 * Change flag
3483 */
3484 dev_dbg(hsotg->dev,
3485 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3486 hsotg->flags.b.port_enable_change = 0;
3487 break;
3488
3489 case USB_PORT_FEAT_C_SUSPEND:
3490 /*
3491 * Clears the driver's internal Port Suspend Change
3492 * flag, which is set when resume signaling on the host
3493 * port is complete
3494 */
3495 dev_dbg(hsotg->dev,
3496 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3497 hsotg->flags.b.port_suspend_change = 0;
3498 break;
3499
3500 case USB_PORT_FEAT_C_PORT_L1:
3501 dev_dbg(hsotg->dev,
3502 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3503 hsotg->flags.b.port_l1_change = 0;
3504 break;
3505
3506 case USB_PORT_FEAT_C_OVER_CURRENT:
3507 dev_dbg(hsotg->dev,
3508 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3509 hsotg->flags.b.port_over_current_change = 0;
3510 break;
3511
3512 default:
3513 retval = -EINVAL;
3514 dev_err(hsotg->dev,
3515 "ClearPortFeature request %1xh unknown or unsupported\n",
3516 wvalue);
3517 }
3518 break;
3519
3520 case GetHubDescriptor:
3521 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3522 hub_desc = (struct usb_hub_descriptor *)buf;
3523 hub_desc->bDescLength = 9;
3524 hub_desc->bDescriptorType = USB_DT_HUB;
3525 hub_desc->bNbrPorts = 1;
3526 hub_desc->wHubCharacteristics =
3527 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3528 HUB_CHAR_INDV_PORT_OCPM);
3529 hub_desc->bPwrOn2PwrGood = 1;
3530 hub_desc->bHubContrCurrent = 0;
3531 hub_desc->u.hs.DeviceRemovable[0] = 0;
3532 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3533 break;
3534
3535 case GetHubStatus:
3536 dev_dbg(hsotg->dev, "GetHubStatus\n");
3537 memset(buf, 0, 4);
3538 break;
3539
3540 case GetPortStatus:
3541 dev_vdbg(hsotg->dev,
3542 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3543 hsotg->flags.d32);
3544 if (!windex || windex > 1)
3545 goto error;
3546
3547 port_status = 0;
3548 if (hsotg->flags.b.port_connect_status_change)
3549 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3550 if (hsotg->flags.b.port_enable_change)
3551 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3552 if (hsotg->flags.b.port_suspend_change)
3553 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3554 if (hsotg->flags.b.port_l1_change)
3555 port_status |= USB_PORT_STAT_C_L1 << 16;
3556 if (hsotg->flags.b.port_reset_change)
3557 port_status |= USB_PORT_STAT_C_RESET << 16;
3558 if (hsotg->flags.b.port_over_current_change) {
3559 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3560 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3561 }
3562
3563 if (!hsotg->flags.b.port_connect_status) {
3564 /*
3565 * The port is disconnected, which means the core is
3566 * either in device mode or it soon will be. Just
3567 * return 0's for the remainder of the port status
3568 * since the port register can't be read if the core
3569 * is in device mode.
3570 */
3571 *(__le32 *)buf = cpu_to_le32(port_status);
3572 break;
3573 }
3574
3575 hprt0 = dwc2_readl(hsotg, HPRT0);
3576 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3577
3578 if (hprt0 & HPRT0_CONNSTS)
3579 port_status |= USB_PORT_STAT_CONNECTION;
3580 if (hprt0 & HPRT0_ENA)
3581 port_status |= USB_PORT_STAT_ENABLE;
3582 if (hprt0 & HPRT0_SUSP)
3583 port_status |= USB_PORT_STAT_SUSPEND;
3584 if (hprt0 & HPRT0_OVRCURRACT)
3585 port_status |= USB_PORT_STAT_OVERCURRENT;
3586 if (hprt0 & HPRT0_RST)
3587 port_status |= USB_PORT_STAT_RESET;
3588 if (hprt0 & HPRT0_PWR)
3589 port_status |= USB_PORT_STAT_POWER;
3590
3591 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3592 if (speed == HPRT0_SPD_HIGH_SPEED)
3593 port_status |= USB_PORT_STAT_HIGH_SPEED;
3594 else if (speed == HPRT0_SPD_LOW_SPEED)
3595 port_status |= USB_PORT_STAT_LOW_SPEED;
3596
3597 if (hprt0 & HPRT0_TSTCTL_MASK)
3598 port_status |= USB_PORT_STAT_TEST;
3599 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3600
3601 if (hsotg->params.dma_desc_fs_enable) {
3602 /*
3603 * Enable descriptor DMA only if a full speed
3604 * device is connected.
3605 */
3606 if (hsotg->new_connection &&
3607 ((port_status &
3608 (USB_PORT_STAT_CONNECTION |
3609 USB_PORT_STAT_HIGH_SPEED |
3610 USB_PORT_STAT_LOW_SPEED)) ==
3611 USB_PORT_STAT_CONNECTION)) {
3612 u32 hcfg;
3613
3614 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3615 hsotg->params.dma_desc_enable = true;
3616 hcfg = dwc2_readl(hsotg, HCFG);
3617 hcfg |= HCFG_DESCDMA;
3618 dwc2_writel(hsotg, hcfg, HCFG);
3619 hsotg->new_connection = false;
3620 }
3621 }
3622
3623 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3624 *(__le32 *)buf = cpu_to_le32(port_status);
3625 break;
3626
3627 case SetHubFeature:
3628 dev_dbg(hsotg->dev, "SetHubFeature\n");
3629 /* No HUB features supported */
3630 break;
3631
3632 case SetPortFeature:
3633 dev_dbg(hsotg->dev, "SetPortFeature\n");
3634 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3635 goto error;
3636
3637 if (!hsotg->flags.b.port_connect_status) {
3638 /*
3639 * The port is disconnected, which means the core is
3640 * either in device mode or it soon will be. Just
3641 * return without doing anything since the port
3642 * register can't be written if the core is in device
3643 * mode.
3644 */
3645 break;
3646 }
3647
3648 switch (wvalue) {
3649 case USB_PORT_FEAT_SUSPEND:
3650 dev_dbg(hsotg->dev,
3651 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3652 if (windex != hsotg->otg_port)
3653 goto error;
3654 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION)
3655 dwc2_enter_hibernation(hsotg, 1);
3656 else
3657 dwc2_port_suspend(hsotg, windex);
3658 break;
3659
3660 case USB_PORT_FEAT_POWER:
3661 dev_dbg(hsotg->dev,
3662 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3663 hprt0 = dwc2_read_hprt0(hsotg);
3664 pwr = hprt0 & HPRT0_PWR;
3665 hprt0 |= HPRT0_PWR;
3666 dwc2_writel(hsotg, hprt0, HPRT0);
3667 if (!pwr)
3668 dwc2_vbus_supply_init(hsotg);
3669 break;
3670
3671 case USB_PORT_FEAT_RESET:
3672 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION &&
3673 hsotg->hibernated)
3674 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3675 hprt0 = dwc2_read_hprt0(hsotg);
3676 dev_dbg(hsotg->dev,
3677 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3678 pcgctl = dwc2_readl(hsotg, PCGCTL);
3679 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3680 dwc2_writel(hsotg, pcgctl, PCGCTL);
3681 /* ??? Original driver does this */
3682 dwc2_writel(hsotg, 0, PCGCTL);
3683
3684 hprt0 = dwc2_read_hprt0(hsotg);
3685 pwr = hprt0 & HPRT0_PWR;
3686 /* Clear suspend bit if resetting from suspend state */
3687 hprt0 &= ~HPRT0_SUSP;
3688
3689 /*
3690 * When B-Host the Port reset bit is set in the Start
3691 * HCD Callback function, so that the reset is started
3692 * within 1ms of the HNP success interrupt
3693 */
3694 if (!dwc2_hcd_is_b_host(hsotg)) {
3695 hprt0 |= HPRT0_PWR | HPRT0_RST;
3696 dev_dbg(hsotg->dev,
3697 "In host mode, hprt0=%08x\n", hprt0);
3698 dwc2_writel(hsotg, hprt0, HPRT0);
3699 if (!pwr)
3700 dwc2_vbus_supply_init(hsotg);
3701 }
3702
3703 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3704 msleep(50);
3705 hprt0 &= ~HPRT0_RST;
3706 dwc2_writel(hsotg, hprt0, HPRT0);
3707 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3708 break;
3709
3710 case USB_PORT_FEAT_INDICATOR:
3711 dev_dbg(hsotg->dev,
3712 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3713 /* Not supported */
3714 break;
3715
3716 case USB_PORT_FEAT_TEST:
3717 hprt0 = dwc2_read_hprt0(hsotg);
3718 dev_dbg(hsotg->dev,
3719 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3720 hprt0 &= ~HPRT0_TSTCTL_MASK;
3721 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3722 dwc2_writel(hsotg, hprt0, HPRT0);
3723 break;
3724
3725 default:
3726 retval = -EINVAL;
3727 dev_err(hsotg->dev,
3728 "SetPortFeature %1xh unknown or unsupported\n",
3729 wvalue);
3730 break;
3731 }
3732 break;
3733
3734 default:
3735 error:
3736 retval = -EINVAL;
3737 dev_dbg(hsotg->dev,
3738 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3739 typereq, windex, wvalue);
3740 break;
3741 }
3742
3743 return retval;
3744 }
3745
dwc2_hcd_is_status_changed(struct dwc2_hsotg * hsotg,int port)3746 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3747 {
3748 int retval;
3749
3750 if (port != 1)
3751 return -EINVAL;
3752
3753 retval = (hsotg->flags.b.port_connect_status_change ||
3754 hsotg->flags.b.port_reset_change ||
3755 hsotg->flags.b.port_enable_change ||
3756 hsotg->flags.b.port_suspend_change ||
3757 hsotg->flags.b.port_over_current_change);
3758
3759 if (retval) {
3760 dev_dbg(hsotg->dev,
3761 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3762 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3763 hsotg->flags.b.port_connect_status_change);
3764 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3765 hsotg->flags.b.port_reset_change);
3766 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3767 hsotg->flags.b.port_enable_change);
3768 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3769 hsotg->flags.b.port_suspend_change);
3770 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3771 hsotg->flags.b.port_over_current_change);
3772 }
3773
3774 return retval;
3775 }
3776
dwc2_hcd_get_frame_number(struct dwc2_hsotg * hsotg)3777 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3778 {
3779 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3780
3781 #ifdef DWC2_DEBUG_SOF
3782 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3783 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3784 #endif
3785 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3786 }
3787
dwc2_hcd_get_future_frame_number(struct dwc2_hsotg * hsotg,int us)3788 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3789 {
3790 u32 hprt = dwc2_readl(hsotg, HPRT0);
3791 u32 hfir = dwc2_readl(hsotg, HFIR);
3792 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3793 unsigned int us_per_frame;
3794 unsigned int frame_number;
3795 unsigned int remaining;
3796 unsigned int interval;
3797 unsigned int phy_clks;
3798
3799 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3800 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3801
3802 /* Extract fields */
3803 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3804 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3805 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3806
3807 /*
3808 * Number of phy clocks since the last tick of the frame number after
3809 * "us" has passed.
3810 */
3811 phy_clks = (interval - remaining) +
3812 DIV_ROUND_UP(interval * us, us_per_frame);
3813
3814 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3815 }
3816
dwc2_hcd_is_b_host(struct dwc2_hsotg * hsotg)3817 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3818 {
3819 return hsotg->op_state == OTG_STATE_B_HOST;
3820 }
3821
dwc2_hcd_urb_alloc(struct dwc2_hsotg * hsotg,int iso_desc_count,gfp_t mem_flags)3822 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3823 int iso_desc_count,
3824 gfp_t mem_flags)
3825 {
3826 struct dwc2_hcd_urb *urb;
3827
3828 urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags);
3829 if (urb)
3830 urb->packet_count = iso_desc_count;
3831 return urb;
3832 }
3833
dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg * hsotg,struct dwc2_hcd_urb * urb,u8 dev_addr,u8 ep_num,u8 ep_type,u8 ep_dir,u16 maxp,u16 maxp_mult)3834 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3835 struct dwc2_hcd_urb *urb, u8 dev_addr,
3836 u8 ep_num, u8 ep_type, u8 ep_dir,
3837 u16 maxp, u16 maxp_mult)
3838 {
3839 if (dbg_perio() ||
3840 ep_type == USB_ENDPOINT_XFER_BULK ||
3841 ep_type == USB_ENDPOINT_XFER_CONTROL)
3842 dev_vdbg(hsotg->dev,
3843 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, maxp=%d (%d mult)\n",
3844 dev_addr, ep_num, ep_dir, ep_type, maxp, maxp_mult);
3845 urb->pipe_info.dev_addr = dev_addr;
3846 urb->pipe_info.ep_num = ep_num;
3847 urb->pipe_info.pipe_type = ep_type;
3848 urb->pipe_info.pipe_dir = ep_dir;
3849 urb->pipe_info.maxp = maxp;
3850 urb->pipe_info.maxp_mult = maxp_mult;
3851 }
3852
3853 /*
3854 * NOTE: This function will be removed once the peripheral controller code
3855 * is integrated and the driver is stable
3856 */
dwc2_hcd_dump_state(struct dwc2_hsotg * hsotg)3857 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3858 {
3859 #ifdef DEBUG
3860 struct dwc2_host_chan *chan;
3861 struct dwc2_hcd_urb *urb;
3862 struct dwc2_qtd *qtd;
3863 int num_channels;
3864 u32 np_tx_status;
3865 u32 p_tx_status;
3866 int i;
3867
3868 num_channels = hsotg->params.host_channels;
3869 dev_dbg(hsotg->dev, "\n");
3870 dev_dbg(hsotg->dev,
3871 "************************************************************\n");
3872 dev_dbg(hsotg->dev, "HCD State:\n");
3873 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3874
3875 for (i = 0; i < num_channels; i++) {
3876 chan = hsotg->hc_ptr_array[i];
3877 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3878 dev_dbg(hsotg->dev,
3879 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3880 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3881 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3882 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3883 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3884 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3885 chan->data_pid_start);
3886 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3887 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3888 chan->xfer_started);
3889 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3890 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3891 (unsigned long)chan->xfer_dma);
3892 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3893 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3894 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3895 chan->halt_on_queue);
3896 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3897 chan->halt_pending);
3898 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3899 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3900 dev_dbg(hsotg->dev, " complete_split: %d\n",
3901 chan->complete_split);
3902 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3903 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3904 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3905 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3906 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3907
3908 if (chan->xfer_started) {
3909 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3910
3911 hfnum = dwc2_readl(hsotg, HFNUM);
3912 hcchar = dwc2_readl(hsotg, HCCHAR(i));
3913 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
3914 hcint = dwc2_readl(hsotg, HCINT(i));
3915 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
3916 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3917 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3918 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3919 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
3920 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
3921 }
3922
3923 if (!(chan->xfer_started && chan->qh))
3924 continue;
3925
3926 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3927 if (!qtd->in_process)
3928 break;
3929 urb = qtd->urb;
3930 dev_dbg(hsotg->dev, " URB Info:\n");
3931 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
3932 qtd, urb);
3933 if (urb) {
3934 dev_dbg(hsotg->dev,
3935 " Dev: %d, EP: %d %s\n",
3936 dwc2_hcd_get_dev_addr(&urb->pipe_info),
3937 dwc2_hcd_get_ep_num(&urb->pipe_info),
3938 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3939 "IN" : "OUT");
3940 dev_dbg(hsotg->dev,
3941 " Max packet size: %d (%d mult)\n",
3942 dwc2_hcd_get_maxp(&urb->pipe_info),
3943 dwc2_hcd_get_maxp_mult(&urb->pipe_info));
3944 dev_dbg(hsotg->dev,
3945 " transfer_buffer: %p\n",
3946 urb->buf);
3947 dev_dbg(hsotg->dev,
3948 " transfer_dma: %08lx\n",
3949 (unsigned long)urb->dma);
3950 dev_dbg(hsotg->dev,
3951 " transfer_buffer_length: %d\n",
3952 urb->length);
3953 dev_dbg(hsotg->dev, " actual_length: %d\n",
3954 urb->actual_length);
3955 }
3956 }
3957 }
3958
3959 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
3960 hsotg->non_periodic_channels);
3961 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
3962 hsotg->periodic_channels);
3963 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
3964 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
3965 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
3966 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3967 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
3968 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3969 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
3970 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
3971 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3972 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
3973 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3974 dwc2_dump_global_registers(hsotg);
3975 dwc2_dump_host_registers(hsotg);
3976 dev_dbg(hsotg->dev,
3977 "************************************************************\n");
3978 dev_dbg(hsotg->dev, "\n");
3979 #endif
3980 }
3981
3982 struct wrapper_priv_data {
3983 struct dwc2_hsotg *hsotg;
3984 };
3985
3986 /* Gets the dwc2_hsotg from a usb_hcd */
dwc2_hcd_to_hsotg(struct usb_hcd * hcd)3987 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
3988 {
3989 struct wrapper_priv_data *p;
3990
3991 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
3992 return p->hsotg;
3993 }
3994
3995 /**
3996 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
3997 *
3998 * This will get the dwc2_tt structure (and ttport) associated with the given
3999 * context (which is really just a struct urb pointer).
4000 *
4001 * The first time this is called for a given TT we allocate memory for our
4002 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4003 * then the refcount for the structure will go to 0 and we'll free it.
4004 *
4005 * @hsotg: The HCD state structure for the DWC OTG controller.
4006 * @context: The priv pointer from a struct dwc2_hcd_urb.
4007 * @mem_flags: Flags for allocating memory.
4008 * @ttport: We'll return this device's port number here. That's used to
4009 * reference into the bitmap if we're on a multi_tt hub.
4010 *
4011 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4012 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4013 */
4014
dwc2_host_get_tt_info(struct dwc2_hsotg * hsotg,void * context,gfp_t mem_flags,int * ttport)4015 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4016 gfp_t mem_flags, int *ttport)
4017 {
4018 struct urb *urb = context;
4019 struct dwc2_tt *dwc_tt = NULL;
4020
4021 if (urb->dev->tt) {
4022 *ttport = urb->dev->ttport;
4023
4024 dwc_tt = urb->dev->tt->hcpriv;
4025 if (!dwc_tt) {
4026 size_t bitmap_size;
4027
4028 /*
4029 * For single_tt we need one schedule. For multi_tt
4030 * we need one per port.
4031 */
4032 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4033 sizeof(dwc_tt->periodic_bitmaps[0]);
4034 if (urb->dev->tt->multi)
4035 bitmap_size *= urb->dev->tt->hub->maxchild;
4036
4037 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4038 mem_flags);
4039 if (!dwc_tt)
4040 return NULL;
4041
4042 dwc_tt->usb_tt = urb->dev->tt;
4043 dwc_tt->usb_tt->hcpriv = dwc_tt;
4044 }
4045
4046 dwc_tt->refcount++;
4047 }
4048
4049 return dwc_tt;
4050 }
4051
4052 /**
4053 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4054 *
4055 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4056 * of the structure are done.
4057 *
4058 * It's OK to call this with NULL.
4059 *
4060 * @hsotg: The HCD state structure for the DWC OTG controller.
4061 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4062 */
dwc2_host_put_tt_info(struct dwc2_hsotg * hsotg,struct dwc2_tt * dwc_tt)4063 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4064 {
4065 /* Model kfree and make put of NULL a no-op */
4066 if (!dwc_tt)
4067 return;
4068
4069 WARN_ON(dwc_tt->refcount < 1);
4070
4071 dwc_tt->refcount--;
4072 if (!dwc_tt->refcount) {
4073 dwc_tt->usb_tt->hcpriv = NULL;
4074 kfree(dwc_tt);
4075 }
4076 }
4077
dwc2_host_get_speed(struct dwc2_hsotg * hsotg,void * context)4078 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4079 {
4080 struct urb *urb = context;
4081
4082 return urb->dev->speed;
4083 }
4084
dwc2_allocate_bus_bandwidth(struct usb_hcd * hcd,u16 bw,struct urb * urb)4085 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4086 struct urb *urb)
4087 {
4088 struct usb_bus *bus = hcd_to_bus(hcd);
4089
4090 if (urb->interval)
4091 bus->bandwidth_allocated += bw / urb->interval;
4092 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4093 bus->bandwidth_isoc_reqs++;
4094 else
4095 bus->bandwidth_int_reqs++;
4096 }
4097
dwc2_free_bus_bandwidth(struct usb_hcd * hcd,u16 bw,struct urb * urb)4098 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4099 struct urb *urb)
4100 {
4101 struct usb_bus *bus = hcd_to_bus(hcd);
4102
4103 if (urb->interval)
4104 bus->bandwidth_allocated -= bw / urb->interval;
4105 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4106 bus->bandwidth_isoc_reqs--;
4107 else
4108 bus->bandwidth_int_reqs--;
4109 }
4110
4111 /*
4112 * Sets the final status of an URB and returns it to the upper layer. Any
4113 * required cleanup of the URB is performed.
4114 *
4115 * Must be called with interrupt disabled and spinlock held
4116 */
dwc2_host_complete(struct dwc2_hsotg * hsotg,struct dwc2_qtd * qtd,int status)4117 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4118 int status)
4119 {
4120 struct urb *urb;
4121 int i;
4122
4123 if (!qtd) {
4124 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4125 return;
4126 }
4127
4128 if (!qtd->urb) {
4129 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4130 return;
4131 }
4132
4133 urb = qtd->urb->priv;
4134 if (!urb) {
4135 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4136 return;
4137 }
4138
4139 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4140
4141 if (dbg_urb(urb))
4142 dev_vdbg(hsotg->dev,
4143 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4144 __func__, urb, usb_pipedevice(urb->pipe),
4145 usb_pipeendpoint(urb->pipe),
4146 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4147 urb->actual_length);
4148
4149 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4150 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4151 for (i = 0; i < urb->number_of_packets; ++i) {
4152 urb->iso_frame_desc[i].actual_length =
4153 dwc2_hcd_urb_get_iso_desc_actual_length(
4154 qtd->urb, i);
4155 urb->iso_frame_desc[i].status =
4156 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4157 }
4158 }
4159
4160 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4161 for (i = 0; i < urb->number_of_packets; i++)
4162 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4163 i, urb->iso_frame_desc[i].status);
4164 }
4165
4166 urb->status = status;
4167 if (!status) {
4168 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4169 urb->actual_length < urb->transfer_buffer_length)
4170 urb->status = -EREMOTEIO;
4171 }
4172
4173 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4174 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4175 struct usb_host_endpoint *ep = urb->ep;
4176
4177 if (ep)
4178 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4179 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4180 urb);
4181 }
4182
4183 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4184 urb->hcpriv = NULL;
4185 kfree(qtd->urb);
4186 qtd->urb = NULL;
4187
4188 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4189 }
4190
4191 /*
4192 * Work queue function for starting the HCD when A-Cable is connected
4193 */
dwc2_hcd_start_func(struct work_struct * work)4194 static void dwc2_hcd_start_func(struct work_struct *work)
4195 {
4196 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4197 start_work.work);
4198
4199 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4200 dwc2_host_start(hsotg);
4201 }
4202
4203 /*
4204 * Reset work queue function
4205 */
dwc2_hcd_reset_func(struct work_struct * work)4206 static void dwc2_hcd_reset_func(struct work_struct *work)
4207 {
4208 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4209 reset_work.work);
4210 unsigned long flags;
4211 u32 hprt0;
4212
4213 dev_dbg(hsotg->dev, "USB RESET function called\n");
4214
4215 spin_lock_irqsave(&hsotg->lock, flags);
4216
4217 hprt0 = dwc2_read_hprt0(hsotg);
4218 hprt0 &= ~HPRT0_RST;
4219 dwc2_writel(hsotg, hprt0, HPRT0);
4220 hsotg->flags.b.port_reset_change = 1;
4221
4222 spin_unlock_irqrestore(&hsotg->lock, flags);
4223 }
4224
dwc2_hcd_phy_reset_func(struct work_struct * work)4225 static void dwc2_hcd_phy_reset_func(struct work_struct *work)
4226 {
4227 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4228 phy_reset_work);
4229 int ret;
4230
4231 ret = phy_reset(hsotg->phy);
4232 if (ret)
4233 dev_warn(hsotg->dev, "PHY reset failed\n");
4234 }
4235
4236 /*
4237 * =========================================================================
4238 * Linux HC Driver Functions
4239 * =========================================================================
4240 */
4241
4242 /*
4243 * Initializes the DWC_otg controller and its root hub and prepares it for host
4244 * mode operation. Activates the root port. Returns 0 on success and a negative
4245 * error code on failure.
4246 */
_dwc2_hcd_start(struct usb_hcd * hcd)4247 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4248 {
4249 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4250 struct usb_bus *bus = hcd_to_bus(hcd);
4251 unsigned long flags;
4252 u32 hprt0;
4253 int ret;
4254
4255 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4256
4257 spin_lock_irqsave(&hsotg->lock, flags);
4258 hsotg->lx_state = DWC2_L0;
4259 hcd->state = HC_STATE_RUNNING;
4260 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4261
4262 if (dwc2_is_device_mode(hsotg)) {
4263 spin_unlock_irqrestore(&hsotg->lock, flags);
4264 return 0; /* why 0 ?? */
4265 }
4266
4267 dwc2_hcd_reinit(hsotg);
4268
4269 hprt0 = dwc2_read_hprt0(hsotg);
4270 /* Has vbus power been turned on in dwc2_core_host_init ? */
4271 if (hprt0 & HPRT0_PWR) {
4272 /* Enable external vbus supply before resuming root hub */
4273 spin_unlock_irqrestore(&hsotg->lock, flags);
4274 ret = dwc2_vbus_supply_init(hsotg);
4275 if (ret)
4276 return ret;
4277 spin_lock_irqsave(&hsotg->lock, flags);
4278 }
4279
4280 /* Initialize and connect root hub if one is not already attached */
4281 if (bus->root_hub) {
4282 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4283 /* Inform the HUB driver to resume */
4284 usb_hcd_resume_root_hub(hcd);
4285 }
4286
4287 spin_unlock_irqrestore(&hsotg->lock, flags);
4288
4289 return 0;
4290 }
4291
4292 /*
4293 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4294 * stopped.
4295 */
_dwc2_hcd_stop(struct usb_hcd * hcd)4296 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4297 {
4298 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4299 unsigned long flags;
4300 u32 hprt0;
4301
4302 /* Turn off all host-specific interrupts */
4303 dwc2_disable_host_interrupts(hsotg);
4304
4305 /* Wait for interrupt processing to finish */
4306 synchronize_irq(hcd->irq);
4307
4308 spin_lock_irqsave(&hsotg->lock, flags);
4309 hprt0 = dwc2_read_hprt0(hsotg);
4310 /* Ensure hcd is disconnected */
4311 dwc2_hcd_disconnect(hsotg, true);
4312 dwc2_hcd_stop(hsotg);
4313 hsotg->lx_state = DWC2_L3;
4314 hcd->state = HC_STATE_HALT;
4315 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4316 spin_unlock_irqrestore(&hsotg->lock, flags);
4317
4318 /* keep balanced supply init/exit by checking HPRT0_PWR */
4319 if (hprt0 & HPRT0_PWR)
4320 dwc2_vbus_supply_exit(hsotg);
4321
4322 usleep_range(1000, 3000);
4323 }
4324
_dwc2_hcd_suspend(struct usb_hcd * hcd)4325 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4326 {
4327 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4328 unsigned long flags;
4329 int ret = 0;
4330 u32 hprt0;
4331 u32 pcgctl;
4332
4333 spin_lock_irqsave(&hsotg->lock, flags);
4334
4335 if (dwc2_is_device_mode(hsotg))
4336 goto unlock;
4337
4338 if (hsotg->lx_state != DWC2_L0)
4339 goto unlock;
4340
4341 if (!HCD_HW_ACCESSIBLE(hcd))
4342 goto unlock;
4343
4344 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4345 goto unlock;
4346
4347 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL ||
4348 hsotg->flags.b.port_connect_status == 0)
4349 goto skip_power_saving;
4350
4351 /*
4352 * Drive USB suspend and disable port Power
4353 * if usb bus is not suspended.
4354 */
4355 if (!hsotg->bus_suspended) {
4356 hprt0 = dwc2_read_hprt0(hsotg);
4357 if (hprt0 & HPRT0_CONNSTS) {
4358 hprt0 |= HPRT0_SUSP;
4359 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL)
4360 hprt0 &= ~HPRT0_PWR;
4361 dwc2_writel(hsotg, hprt0, HPRT0);
4362 }
4363 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4364 spin_unlock_irqrestore(&hsotg->lock, flags);
4365 dwc2_vbus_supply_exit(hsotg);
4366 spin_lock_irqsave(&hsotg->lock, flags);
4367 } else {
4368 pcgctl = readl(hsotg->regs + PCGCTL);
4369 pcgctl |= PCGCTL_STOPPCLK;
4370 writel(pcgctl, hsotg->regs + PCGCTL);
4371 }
4372 }
4373
4374 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4375 /* Enter partial_power_down */
4376 ret = dwc2_enter_partial_power_down(hsotg);
4377 if (ret) {
4378 if (ret != -ENOTSUPP)
4379 dev_err(hsotg->dev,
4380 "enter partial_power_down failed\n");
4381 goto skip_power_saving;
4382 }
4383
4384 /* After entering partial_power_down, hardware is no more accessible */
4385 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4386 }
4387
4388 /* Ask phy to be suspended */
4389 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4390 spin_unlock_irqrestore(&hsotg->lock, flags);
4391 usb_phy_set_suspend(hsotg->uphy, true);
4392 spin_lock_irqsave(&hsotg->lock, flags);
4393 }
4394
4395 skip_power_saving:
4396 hsotg->lx_state = DWC2_L2;
4397 unlock:
4398 spin_unlock_irqrestore(&hsotg->lock, flags);
4399
4400 return ret;
4401 }
4402
_dwc2_hcd_resume(struct usb_hcd * hcd)4403 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4404 {
4405 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4406 unsigned long flags;
4407 u32 pcgctl;
4408 int ret = 0;
4409
4410 spin_lock_irqsave(&hsotg->lock, flags);
4411
4412 if (dwc2_is_device_mode(hsotg))
4413 goto unlock;
4414
4415 if (hsotg->lx_state != DWC2_L2)
4416 goto unlock;
4417
4418 if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) {
4419 hsotg->lx_state = DWC2_L0;
4420 goto unlock;
4421 }
4422
4423 /*
4424 * Enable power if not already done.
4425 * This must not be spinlocked since duration
4426 * of this call is unknown.
4427 */
4428 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4429 spin_unlock_irqrestore(&hsotg->lock, flags);
4430 usb_phy_set_suspend(hsotg->uphy, false);
4431 spin_lock_irqsave(&hsotg->lock, flags);
4432 }
4433
4434 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4435 /*
4436 * Set HW accessible bit before powering on the controller
4437 * since an interrupt may rise.
4438 */
4439 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4440
4441
4442 /* Exit partial_power_down */
4443 ret = dwc2_exit_partial_power_down(hsotg, true);
4444 if (ret && (ret != -ENOTSUPP))
4445 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4446 } else {
4447 pcgctl = readl(hsotg->regs + PCGCTL);
4448 pcgctl &= ~PCGCTL_STOPPCLK;
4449 writel(pcgctl, hsotg->regs + PCGCTL);
4450 }
4451
4452 hsotg->lx_state = DWC2_L0;
4453
4454 spin_unlock_irqrestore(&hsotg->lock, flags);
4455
4456 if (hsotg->bus_suspended) {
4457 spin_lock_irqsave(&hsotg->lock, flags);
4458 hsotg->flags.b.port_suspend_change = 1;
4459 spin_unlock_irqrestore(&hsotg->lock, flags);
4460 dwc2_port_resume(hsotg);
4461 } else {
4462 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4463 dwc2_vbus_supply_init(hsotg);
4464
4465 /* Wait for controller to correctly update D+/D- level */
4466 usleep_range(3000, 5000);
4467 }
4468
4469 /*
4470 * Clear Port Enable and Port Status changes.
4471 * Enable Port Power.
4472 */
4473 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4474 HPRT0_ENACHG, HPRT0);
4475 /* Wait for controller to detect Port Connect */
4476 usleep_range(5000, 7000);
4477 }
4478
4479 return ret;
4480 unlock:
4481 spin_unlock_irqrestore(&hsotg->lock, flags);
4482
4483 return ret;
4484 }
4485
4486 /* Returns the current frame number */
_dwc2_hcd_get_frame_number(struct usb_hcd * hcd)4487 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4488 {
4489 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4490
4491 return dwc2_hcd_get_frame_number(hsotg);
4492 }
4493
dwc2_dump_urb_info(struct usb_hcd * hcd,struct urb * urb,char * fn_name)4494 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4495 char *fn_name)
4496 {
4497 #ifdef VERBOSE_DEBUG
4498 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4499 char *pipetype = NULL;
4500 char *speed = NULL;
4501
4502 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4503 dev_vdbg(hsotg->dev, " Device address: %d\n",
4504 usb_pipedevice(urb->pipe));
4505 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4506 usb_pipeendpoint(urb->pipe),
4507 usb_pipein(urb->pipe) ? "IN" : "OUT");
4508
4509 switch (usb_pipetype(urb->pipe)) {
4510 case PIPE_CONTROL:
4511 pipetype = "CONTROL";
4512 break;
4513 case PIPE_BULK:
4514 pipetype = "BULK";
4515 break;
4516 case PIPE_INTERRUPT:
4517 pipetype = "INTERRUPT";
4518 break;
4519 case PIPE_ISOCHRONOUS:
4520 pipetype = "ISOCHRONOUS";
4521 break;
4522 }
4523
4524 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4525 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4526 "IN" : "OUT");
4527
4528 switch (urb->dev->speed) {
4529 case USB_SPEED_HIGH:
4530 speed = "HIGH";
4531 break;
4532 case USB_SPEED_FULL:
4533 speed = "FULL";
4534 break;
4535 case USB_SPEED_LOW:
4536 speed = "LOW";
4537 break;
4538 default:
4539 speed = "UNKNOWN";
4540 break;
4541 }
4542
4543 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4544 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n",
4545 usb_endpoint_maxp(&urb->ep->desc),
4546 usb_endpoint_maxp_mult(&urb->ep->desc));
4547
4548 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4549 urb->transfer_buffer_length);
4550 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4551 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4552 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4553 urb->setup_packet, (unsigned long)urb->setup_dma);
4554 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4555
4556 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4557 int i;
4558
4559 for (i = 0; i < urb->number_of_packets; i++) {
4560 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4561 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4562 urb->iso_frame_desc[i].offset,
4563 urb->iso_frame_desc[i].length);
4564 }
4565 }
4566 #endif
4567 }
4568
4569 /*
4570 * Starts processing a USB transfer request specified by a USB Request Block
4571 * (URB). mem_flags indicates the type of memory allocation to use while
4572 * processing this URB.
4573 */
_dwc2_hcd_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)4574 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4575 gfp_t mem_flags)
4576 {
4577 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4578 struct usb_host_endpoint *ep = urb->ep;
4579 struct dwc2_hcd_urb *dwc2_urb;
4580 int i;
4581 int retval;
4582 int alloc_bandwidth = 0;
4583 u8 ep_type = 0;
4584 u32 tflags = 0;
4585 void *buf;
4586 unsigned long flags;
4587 struct dwc2_qh *qh;
4588 bool qh_allocated = false;
4589 struct dwc2_qtd *qtd;
4590
4591 if (dbg_urb(urb)) {
4592 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4593 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4594 }
4595
4596 if (!ep)
4597 return -EINVAL;
4598
4599 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4600 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4601 spin_lock_irqsave(&hsotg->lock, flags);
4602 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4603 alloc_bandwidth = 1;
4604 spin_unlock_irqrestore(&hsotg->lock, flags);
4605 }
4606
4607 switch (usb_pipetype(urb->pipe)) {
4608 case PIPE_CONTROL:
4609 ep_type = USB_ENDPOINT_XFER_CONTROL;
4610 break;
4611 case PIPE_ISOCHRONOUS:
4612 ep_type = USB_ENDPOINT_XFER_ISOC;
4613 break;
4614 case PIPE_BULK:
4615 ep_type = USB_ENDPOINT_XFER_BULK;
4616 break;
4617 case PIPE_INTERRUPT:
4618 ep_type = USB_ENDPOINT_XFER_INT;
4619 break;
4620 }
4621
4622 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4623 mem_flags);
4624 if (!dwc2_urb)
4625 return -ENOMEM;
4626
4627 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4628 usb_pipeendpoint(urb->pipe), ep_type,
4629 usb_pipein(urb->pipe),
4630 usb_endpoint_maxp(&ep->desc),
4631 usb_endpoint_maxp_mult(&ep->desc));
4632
4633 buf = urb->transfer_buffer;
4634
4635 if (hcd_uses_dma(hcd)) {
4636 if (!buf && (urb->transfer_dma & 3)) {
4637 dev_err(hsotg->dev,
4638 "%s: unaligned transfer with no transfer_buffer",
4639 __func__);
4640 retval = -EINVAL;
4641 goto fail0;
4642 }
4643 }
4644
4645 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4646 tflags |= URB_GIVEBACK_ASAP;
4647 if (urb->transfer_flags & URB_ZERO_PACKET)
4648 tflags |= URB_SEND_ZERO_PACKET;
4649
4650 dwc2_urb->priv = urb;
4651 dwc2_urb->buf = buf;
4652 dwc2_urb->dma = urb->transfer_dma;
4653 dwc2_urb->length = urb->transfer_buffer_length;
4654 dwc2_urb->setup_packet = urb->setup_packet;
4655 dwc2_urb->setup_dma = urb->setup_dma;
4656 dwc2_urb->flags = tflags;
4657 dwc2_urb->interval = urb->interval;
4658 dwc2_urb->status = -EINPROGRESS;
4659
4660 for (i = 0; i < urb->number_of_packets; ++i)
4661 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4662 urb->iso_frame_desc[i].offset,
4663 urb->iso_frame_desc[i].length);
4664
4665 urb->hcpriv = dwc2_urb;
4666 qh = (struct dwc2_qh *)ep->hcpriv;
4667 /* Create QH for the endpoint if it doesn't exist */
4668 if (!qh) {
4669 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4670 if (!qh) {
4671 retval = -ENOMEM;
4672 goto fail0;
4673 }
4674 ep->hcpriv = qh;
4675 qh_allocated = true;
4676 }
4677
4678 qtd = kzalloc(sizeof(*qtd), mem_flags);
4679 if (!qtd) {
4680 retval = -ENOMEM;
4681 goto fail1;
4682 }
4683
4684 spin_lock_irqsave(&hsotg->lock, flags);
4685 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4686 if (retval)
4687 goto fail2;
4688
4689 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4690 if (retval)
4691 goto fail3;
4692
4693 if (alloc_bandwidth) {
4694 dwc2_allocate_bus_bandwidth(hcd,
4695 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4696 urb);
4697 }
4698
4699 spin_unlock_irqrestore(&hsotg->lock, flags);
4700
4701 return 0;
4702
4703 fail3:
4704 dwc2_urb->priv = NULL;
4705 usb_hcd_unlink_urb_from_ep(hcd, urb);
4706 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4707 qh->channel->qh = NULL;
4708 fail2:
4709 spin_unlock_irqrestore(&hsotg->lock, flags);
4710 urb->hcpriv = NULL;
4711 kfree(qtd);
4712 fail1:
4713 if (qh_allocated) {
4714 struct dwc2_qtd *qtd2, *qtd2_tmp;
4715
4716 ep->hcpriv = NULL;
4717 dwc2_hcd_qh_unlink(hsotg, qh);
4718 /* Free each QTD in the QH's QTD list */
4719 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4720 qtd_list_entry)
4721 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4722 dwc2_hcd_qh_free(hsotg, qh);
4723 }
4724 fail0:
4725 kfree(dwc2_urb);
4726
4727 return retval;
4728 }
4729
4730 /*
4731 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4732 */
_dwc2_hcd_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)4733 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4734 int status)
4735 {
4736 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4737 int rc;
4738 unsigned long flags;
4739
4740 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4741 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4742
4743 spin_lock_irqsave(&hsotg->lock, flags);
4744
4745 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4746 if (rc)
4747 goto out;
4748
4749 if (!urb->hcpriv) {
4750 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4751 goto out;
4752 }
4753
4754 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4755
4756 usb_hcd_unlink_urb_from_ep(hcd, urb);
4757
4758 kfree(urb->hcpriv);
4759 urb->hcpriv = NULL;
4760
4761 /* Higher layer software sets URB status */
4762 spin_unlock(&hsotg->lock);
4763 usb_hcd_giveback_urb(hcd, urb, status);
4764 spin_lock(&hsotg->lock);
4765
4766 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4767 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4768 out:
4769 spin_unlock_irqrestore(&hsotg->lock, flags);
4770
4771 return rc;
4772 }
4773
4774 /*
4775 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4776 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4777 * must already be dequeued.
4778 */
_dwc2_hcd_endpoint_disable(struct usb_hcd * hcd,struct usb_host_endpoint * ep)4779 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4780 struct usb_host_endpoint *ep)
4781 {
4782 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4783
4784 dev_dbg(hsotg->dev,
4785 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4786 ep->desc.bEndpointAddress, ep->hcpriv);
4787 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4788 }
4789
4790 /*
4791 * Resets endpoint specific parameter values, in current version used to reset
4792 * the data toggle (as a WA). This function can be called from usb_clear_halt
4793 * routine.
4794 */
_dwc2_hcd_endpoint_reset(struct usb_hcd * hcd,struct usb_host_endpoint * ep)4795 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4796 struct usb_host_endpoint *ep)
4797 {
4798 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4799 unsigned long flags;
4800
4801 dev_dbg(hsotg->dev,
4802 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4803 ep->desc.bEndpointAddress);
4804
4805 spin_lock_irqsave(&hsotg->lock, flags);
4806 dwc2_hcd_endpoint_reset(hsotg, ep);
4807 spin_unlock_irqrestore(&hsotg->lock, flags);
4808 }
4809
4810 /*
4811 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4812 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4813 * interrupt.
4814 *
4815 * This function is called by the USB core when an interrupt occurs
4816 */
_dwc2_hcd_irq(struct usb_hcd * hcd)4817 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4818 {
4819 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4820
4821 return dwc2_handle_hcd_intr(hsotg);
4822 }
4823
4824 /*
4825 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4826 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4827 * is the status change indicator for the single root port. Returns 1 if either
4828 * change indicator is 1, otherwise returns 0.
4829 */
_dwc2_hcd_hub_status_data(struct usb_hcd * hcd,char * buf)4830 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4831 {
4832 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4833
4834 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4835 return buf[0] != 0;
4836 }
4837
4838 /* Handles hub class-specific requests */
_dwc2_hcd_hub_control(struct usb_hcd * hcd,u16 typereq,u16 wvalue,u16 windex,char * buf,u16 wlength)4839 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4840 u16 windex, char *buf, u16 wlength)
4841 {
4842 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4843 wvalue, windex, buf, wlength);
4844 return retval;
4845 }
4846
4847 /* Handles hub TT buffer clear completions */
_dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd * hcd,struct usb_host_endpoint * ep)4848 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4849 struct usb_host_endpoint *ep)
4850 {
4851 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4852 struct dwc2_qh *qh;
4853 unsigned long flags;
4854
4855 qh = ep->hcpriv;
4856 if (!qh)
4857 return;
4858
4859 spin_lock_irqsave(&hsotg->lock, flags);
4860 qh->tt_buffer_dirty = 0;
4861
4862 if (hsotg->flags.b.port_connect_status)
4863 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4864
4865 spin_unlock_irqrestore(&hsotg->lock, flags);
4866 }
4867
4868 /*
4869 * HPRT0_SPD_HIGH_SPEED: high speed
4870 * HPRT0_SPD_FULL_SPEED: full speed
4871 */
dwc2_change_bus_speed(struct usb_hcd * hcd,int speed)4872 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4873 {
4874 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4875
4876 if (hsotg->params.speed == speed)
4877 return;
4878
4879 hsotg->params.speed = speed;
4880 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4881 }
4882
dwc2_free_dev(struct usb_hcd * hcd,struct usb_device * udev)4883 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4884 {
4885 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4886
4887 if (!hsotg->params.change_speed_quirk)
4888 return;
4889
4890 /*
4891 * On removal, set speed to default high-speed.
4892 */
4893 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4894 udev->parent->speed < USB_SPEED_HIGH) {
4895 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4896 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4897 }
4898 }
4899
dwc2_reset_device(struct usb_hcd * hcd,struct usb_device * udev)4900 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4901 {
4902 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4903
4904 if (!hsotg->params.change_speed_quirk)
4905 return 0;
4906
4907 if (udev->speed == USB_SPEED_HIGH) {
4908 dev_info(hsotg->dev, "Set speed to high-speed\n");
4909 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4910 } else if ((udev->speed == USB_SPEED_FULL ||
4911 udev->speed == USB_SPEED_LOW)) {
4912 /*
4913 * Change speed setting to full-speed if there's
4914 * a full-speed or low-speed device plugged in.
4915 */
4916 dev_info(hsotg->dev, "Set speed to full-speed\n");
4917 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
4918 }
4919
4920 return 0;
4921 }
4922
4923 static struct hc_driver dwc2_hc_driver = {
4924 .description = "dwc2_hsotg",
4925 .product_desc = "DWC OTG Controller",
4926 .hcd_priv_size = sizeof(struct wrapper_priv_data),
4927
4928 .irq = _dwc2_hcd_irq,
4929 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4930
4931 .start = _dwc2_hcd_start,
4932 .stop = _dwc2_hcd_stop,
4933 .urb_enqueue = _dwc2_hcd_urb_enqueue,
4934 .urb_dequeue = _dwc2_hcd_urb_dequeue,
4935 .endpoint_disable = _dwc2_hcd_endpoint_disable,
4936 .endpoint_reset = _dwc2_hcd_endpoint_reset,
4937 .get_frame_number = _dwc2_hcd_get_frame_number,
4938
4939 .hub_status_data = _dwc2_hcd_hub_status_data,
4940 .hub_control = _dwc2_hcd_hub_control,
4941 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4942
4943 .bus_suspend = _dwc2_hcd_suspend,
4944 .bus_resume = _dwc2_hcd_resume,
4945
4946 .map_urb_for_dma = dwc2_map_urb_for_dma,
4947 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
4948 };
4949
4950 /*
4951 * Frees secondary storage associated with the dwc2_hsotg structure contained
4952 * in the struct usb_hcd field
4953 */
dwc2_hcd_free(struct dwc2_hsotg * hsotg)4954 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4955 {
4956 u32 ahbcfg;
4957 u32 dctl;
4958 int i;
4959
4960 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4961
4962 /* Free memory for QH/QTD lists */
4963 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4964 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
4965 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4966 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4967 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4968 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4969 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4970
4971 /* Free memory for the host channels */
4972 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
4973 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4974
4975 if (chan) {
4976 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4977 i, chan);
4978 hsotg->hc_ptr_array[i] = NULL;
4979 kfree(chan);
4980 }
4981 }
4982
4983 if (hsotg->params.host_dma) {
4984 if (hsotg->status_buf) {
4985 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
4986 hsotg->status_buf,
4987 hsotg->status_buf_dma);
4988 hsotg->status_buf = NULL;
4989 }
4990 } else {
4991 kfree(hsotg->status_buf);
4992 hsotg->status_buf = NULL;
4993 }
4994
4995 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
4996
4997 /* Disable all interrupts */
4998 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
4999 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
5000 dwc2_writel(hsotg, 0, GINTMSK);
5001
5002 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5003 dctl = dwc2_readl(hsotg, DCTL);
5004 dctl |= DCTL_SFTDISCON;
5005 dwc2_writel(hsotg, dctl, DCTL);
5006 }
5007
5008 if (hsotg->wq_otg) {
5009 if (!cancel_work_sync(&hsotg->wf_otg))
5010 flush_workqueue(hsotg->wq_otg);
5011 destroy_workqueue(hsotg->wq_otg);
5012 }
5013
5014 cancel_work_sync(&hsotg->phy_reset_work);
5015
5016 del_timer(&hsotg->wkp_timer);
5017 }
5018
dwc2_hcd_release(struct dwc2_hsotg * hsotg)5019 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5020 {
5021 /* Turn off all host-specific interrupts */
5022 dwc2_disable_host_interrupts(hsotg);
5023
5024 dwc2_hcd_free(hsotg);
5025 }
5026
5027 /*
5028 * Initializes the HCD. This function allocates memory for and initializes the
5029 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5030 * USB bus with the core and calls the hc_driver->start() function. It returns
5031 * a negative error on failure.
5032 */
dwc2_hcd_init(struct dwc2_hsotg * hsotg)5033 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5034 {
5035 struct platform_device *pdev = to_platform_device(hsotg->dev);
5036 struct resource *res;
5037 struct usb_hcd *hcd;
5038 struct dwc2_host_chan *channel;
5039 u32 hcfg;
5040 int i, num_channels;
5041 int retval;
5042
5043 if (usb_disabled())
5044 return -ENODEV;
5045
5046 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5047
5048 retval = -ENOMEM;
5049
5050 hcfg = dwc2_readl(hsotg, HCFG);
5051 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5052
5053 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5054 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5055 sizeof(*hsotg->frame_num_array),
5056 GFP_KERNEL);
5057 if (!hsotg->frame_num_array)
5058 goto error1;
5059 hsotg->last_frame_num_array =
5060 kcalloc(FRAME_NUM_ARRAY_SIZE,
5061 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5062 if (!hsotg->last_frame_num_array)
5063 goto error1;
5064 #endif
5065 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5066
5067 /* Check if the bus driver or platform code has setup a dma_mask */
5068 if (hsotg->params.host_dma &&
5069 !hsotg->dev->dma_mask) {
5070 dev_warn(hsotg->dev,
5071 "dma_mask not set, disabling DMA\n");
5072 hsotg->params.host_dma = false;
5073 hsotg->params.dma_desc_enable = false;
5074 }
5075
5076 /* Set device flags indicating whether the HCD supports DMA */
5077 if (hsotg->params.host_dma) {
5078 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5079 dev_warn(hsotg->dev, "can't set DMA mask\n");
5080 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5081 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5082 }
5083
5084 if (hsotg->params.change_speed_quirk) {
5085 dwc2_hc_driver.free_dev = dwc2_free_dev;
5086 dwc2_hc_driver.reset_device = dwc2_reset_device;
5087 }
5088
5089 if (hsotg->params.host_dma)
5090 dwc2_hc_driver.flags |= HCD_DMA;
5091
5092 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5093 if (!hcd)
5094 goto error1;
5095
5096 hcd->has_tt = 1;
5097
5098 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5099 if (!res) {
5100 retval = -EINVAL;
5101 goto error2;
5102 }
5103 hcd->rsrc_start = res->start;
5104 hcd->rsrc_len = resource_size(res);
5105
5106 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5107 hsotg->priv = hcd;
5108
5109 /*
5110 * Disable the global interrupt until all the interrupt handlers are
5111 * installed
5112 */
5113 dwc2_disable_global_interrupts(hsotg);
5114
5115 /* Initialize the DWC_otg core, and select the Phy type */
5116 retval = dwc2_core_init(hsotg, true);
5117 if (retval)
5118 goto error2;
5119
5120 /* Create new workqueue and init work */
5121 retval = -ENOMEM;
5122 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5123 if (!hsotg->wq_otg) {
5124 dev_err(hsotg->dev, "Failed to create workqueue\n");
5125 goto error2;
5126 }
5127 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5128
5129 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5130
5131 /* Initialize the non-periodic schedule */
5132 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5133 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5134 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5135
5136 /* Initialize the periodic schedule */
5137 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5138 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5139 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5140 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5141
5142 INIT_LIST_HEAD(&hsotg->split_order);
5143
5144 /*
5145 * Create a host channel descriptor for each host channel implemented
5146 * in the controller. Initialize the channel descriptor array.
5147 */
5148 INIT_LIST_HEAD(&hsotg->free_hc_list);
5149 num_channels = hsotg->params.host_channels;
5150 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5151
5152 for (i = 0; i < num_channels; i++) {
5153 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5154 if (!channel)
5155 goto error3;
5156 channel->hc_num = i;
5157 INIT_LIST_HEAD(&channel->split_order_list_entry);
5158 hsotg->hc_ptr_array[i] = channel;
5159 }
5160
5161 /* Initialize work */
5162 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5163 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5164 INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
5165
5166 /*
5167 * Allocate space for storing data on status transactions. Normally no
5168 * data is sent, but this space acts as a bit bucket. This must be
5169 * done after usb_add_hcd since that function allocates the DMA buffer
5170 * pool.
5171 */
5172 if (hsotg->params.host_dma)
5173 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5174 DWC2_HCD_STATUS_BUF_SIZE,
5175 &hsotg->status_buf_dma, GFP_KERNEL);
5176 else
5177 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5178 GFP_KERNEL);
5179
5180 if (!hsotg->status_buf)
5181 goto error3;
5182
5183 /*
5184 * Create kmem caches to handle descriptor buffers in descriptor
5185 * DMA mode.
5186 * Alignment must be set to 512 bytes.
5187 */
5188 if (hsotg->params.dma_desc_enable ||
5189 hsotg->params.dma_desc_fs_enable) {
5190 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5191 sizeof(struct dwc2_dma_desc) *
5192 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5193 NULL);
5194 if (!hsotg->desc_gen_cache) {
5195 dev_err(hsotg->dev,
5196 "unable to create dwc2 generic desc cache\n");
5197
5198 /*
5199 * Disable descriptor dma mode since it will not be
5200 * usable.
5201 */
5202 hsotg->params.dma_desc_enable = false;
5203 hsotg->params.dma_desc_fs_enable = false;
5204 }
5205
5206 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5207 sizeof(struct dwc2_dma_desc) *
5208 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5209 if (!hsotg->desc_hsisoc_cache) {
5210 dev_err(hsotg->dev,
5211 "unable to create dwc2 hs isoc desc cache\n");
5212
5213 kmem_cache_destroy(hsotg->desc_gen_cache);
5214
5215 /*
5216 * Disable descriptor dma mode since it will not be
5217 * usable.
5218 */
5219 hsotg->params.dma_desc_enable = false;
5220 hsotg->params.dma_desc_fs_enable = false;
5221 }
5222 }
5223
5224 if (hsotg->params.host_dma) {
5225 /*
5226 * Create kmem caches to handle non-aligned buffer
5227 * in Buffer DMA mode.
5228 */
5229 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5230 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5231 SLAB_CACHE_DMA, NULL);
5232 if (!hsotg->unaligned_cache)
5233 dev_err(hsotg->dev,
5234 "unable to create dwc2 unaligned cache\n");
5235 }
5236
5237 hsotg->otg_port = 1;
5238 hsotg->frame_list = NULL;
5239 hsotg->frame_list_dma = 0;
5240 hsotg->periodic_qh_count = 0;
5241
5242 /* Initiate lx_state to L3 disconnected state */
5243 hsotg->lx_state = DWC2_L3;
5244
5245 hcd->self.otg_port = hsotg->otg_port;
5246
5247 /* Don't support SG list at this point */
5248 hcd->self.sg_tablesize = 0;
5249
5250 if (!IS_ERR_OR_NULL(hsotg->uphy))
5251 otg_set_host(hsotg->uphy->otg, &hcd->self);
5252
5253 /*
5254 * do not manage the PHY state in the HCD core, instead let the driver
5255 * handle this (for example if the PHY can only be turned on after a
5256 * specific event)
5257 */
5258 hcd->skip_phy_initialization = 1;
5259
5260 /*
5261 * Finish generic HCD initialization and start the HCD. This function
5262 * allocates the DMA buffer pool, registers the USB bus, requests the
5263 * IRQ line, and calls hcd_start method.
5264 */
5265 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5266 if (retval < 0)
5267 goto error4;
5268
5269 device_wakeup_enable(hcd->self.controller);
5270
5271 dwc2_hcd_dump_state(hsotg);
5272
5273 dwc2_enable_global_interrupts(hsotg);
5274
5275 return 0;
5276
5277 error4:
5278 kmem_cache_destroy(hsotg->unaligned_cache);
5279 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5280 kmem_cache_destroy(hsotg->desc_gen_cache);
5281 error3:
5282 dwc2_hcd_release(hsotg);
5283 error2:
5284 usb_put_hcd(hcd);
5285 error1:
5286
5287 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5288 kfree(hsotg->last_frame_num_array);
5289 kfree(hsotg->frame_num_array);
5290 #endif
5291
5292 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5293 return retval;
5294 }
5295
5296 /*
5297 * Removes the HCD.
5298 * Frees memory and resources associated with the HCD and deregisters the bus.
5299 */
dwc2_hcd_remove(struct dwc2_hsotg * hsotg)5300 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5301 {
5302 struct usb_hcd *hcd;
5303
5304 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5305
5306 hcd = dwc2_hsotg_to_hcd(hsotg);
5307 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5308
5309 if (!hcd) {
5310 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5311 __func__);
5312 return;
5313 }
5314
5315 if (!IS_ERR_OR_NULL(hsotg->uphy))
5316 otg_set_host(hsotg->uphy->otg, NULL);
5317
5318 usb_remove_hcd(hcd);
5319 hsotg->priv = NULL;
5320
5321 kmem_cache_destroy(hsotg->unaligned_cache);
5322 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5323 kmem_cache_destroy(hsotg->desc_gen_cache);
5324
5325 dwc2_hcd_release(hsotg);
5326 usb_put_hcd(hcd);
5327
5328 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5329 kfree(hsotg->last_frame_num_array);
5330 kfree(hsotg->frame_num_array);
5331 #endif
5332 }
5333
5334 /**
5335 * dwc2_backup_host_registers() - Backup controller host registers.
5336 * When suspending usb bus, registers needs to be backuped
5337 * if controller power is disabled once suspended.
5338 *
5339 * @hsotg: Programming view of the DWC_otg controller
5340 */
dwc2_backup_host_registers(struct dwc2_hsotg * hsotg)5341 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5342 {
5343 struct dwc2_hregs_backup *hr;
5344 int i;
5345
5346 dev_dbg(hsotg->dev, "%s\n", __func__);
5347
5348 /* Backup Host regs */
5349 hr = &hsotg->hr_backup;
5350 hr->hcfg = dwc2_readl(hsotg, HCFG);
5351 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5352 for (i = 0; i < hsotg->params.host_channels; ++i)
5353 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5354
5355 hr->hprt0 = dwc2_read_hprt0(hsotg);
5356 hr->hfir = dwc2_readl(hsotg, HFIR);
5357 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5358 hr->valid = true;
5359
5360 return 0;
5361 }
5362
5363 /**
5364 * dwc2_restore_host_registers() - Restore controller host registers.
5365 * When resuming usb bus, device registers needs to be restored
5366 * if controller power were disabled.
5367 *
5368 * @hsotg: Programming view of the DWC_otg controller
5369 */
dwc2_restore_host_registers(struct dwc2_hsotg * hsotg)5370 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5371 {
5372 struct dwc2_hregs_backup *hr;
5373 int i;
5374
5375 dev_dbg(hsotg->dev, "%s\n", __func__);
5376
5377 /* Restore host regs */
5378 hr = &hsotg->hr_backup;
5379 if (!hr->valid) {
5380 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5381 __func__);
5382 return -EINVAL;
5383 }
5384 hr->valid = false;
5385
5386 dwc2_writel(hsotg, hr->hcfg, HCFG);
5387 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5388
5389 for (i = 0; i < hsotg->params.host_channels; ++i)
5390 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5391
5392 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5393 dwc2_writel(hsotg, hr->hfir, HFIR);
5394 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5395 hsotg->frame_number = 0;
5396
5397 return 0;
5398 }
5399
5400 /**
5401 * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5402 *
5403 * @hsotg: Programming view of the DWC_otg controller
5404 */
dwc2_host_enter_hibernation(struct dwc2_hsotg * hsotg)5405 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5406 {
5407 unsigned long flags;
5408 int ret = 0;
5409 u32 hprt0;
5410 u32 pcgcctl;
5411 u32 gusbcfg;
5412 u32 gpwrdn;
5413
5414 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5415 ret = dwc2_backup_global_registers(hsotg);
5416 if (ret) {
5417 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5418 __func__);
5419 return ret;
5420 }
5421 ret = dwc2_backup_host_registers(hsotg);
5422 if (ret) {
5423 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5424 __func__);
5425 return ret;
5426 }
5427
5428 /* Enter USB Suspend Mode */
5429 hprt0 = dwc2_readl(hsotg, HPRT0);
5430 hprt0 |= HPRT0_SUSP;
5431 hprt0 &= ~HPRT0_ENA;
5432 dwc2_writel(hsotg, hprt0, HPRT0);
5433
5434 /* Wait for the HPRT0.PrtSusp register field to be set */
5435 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 5000))
5436 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5437
5438 /*
5439 * We need to disable interrupts to prevent servicing of any IRQ
5440 * during going to hibernation
5441 */
5442 spin_lock_irqsave(&hsotg->lock, flags);
5443 hsotg->lx_state = DWC2_L2;
5444
5445 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5446 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5447 /* ULPI interface */
5448 /* Suspend the Phy Clock */
5449 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5450 pcgcctl |= PCGCTL_STOPPCLK;
5451 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5452 udelay(10);
5453
5454 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5455 gpwrdn |= GPWRDN_PMUACTV;
5456 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5457 udelay(10);
5458 } else {
5459 /* UTMI+ Interface */
5460 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5461 gpwrdn |= GPWRDN_PMUACTV;
5462 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5463 udelay(10);
5464
5465 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5466 pcgcctl |= PCGCTL_STOPPCLK;
5467 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5468 udelay(10);
5469 }
5470
5471 /* Enable interrupts from wake up logic */
5472 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5473 gpwrdn |= GPWRDN_PMUINTSEL;
5474 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5475 udelay(10);
5476
5477 /* Unmask host mode interrupts in GPWRDN */
5478 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5479 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5480 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5481 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5482 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5483 udelay(10);
5484
5485 /* Enable Power Down Clamp */
5486 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5487 gpwrdn |= GPWRDN_PWRDNCLMP;
5488 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5489 udelay(10);
5490
5491 /* Switch off VDD */
5492 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5493 gpwrdn |= GPWRDN_PWRDNSWTCH;
5494 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5495
5496 hsotg->hibernated = 1;
5497 hsotg->bus_suspended = 1;
5498 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5499 spin_unlock_irqrestore(&hsotg->lock, flags);
5500 return ret;
5501 }
5502
5503 /*
5504 * dwc2_host_exit_hibernation()
5505 *
5506 * @hsotg: Programming view of the DWC_otg controller
5507 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5508 * @param reset: indicates whether resume is initiated by Reset.
5509 *
5510 * Return: non-zero if failed to enter to hibernation.
5511 *
5512 * This function is for exiting from Host mode hibernation by
5513 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5514 */
dwc2_host_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)5515 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5516 int reset)
5517 {
5518 u32 gpwrdn;
5519 u32 hprt0;
5520 int ret = 0;
5521 struct dwc2_gregs_backup *gr;
5522 struct dwc2_hregs_backup *hr;
5523
5524 gr = &hsotg->gr_backup;
5525 hr = &hsotg->hr_backup;
5526
5527 dev_dbg(hsotg->dev,
5528 "%s: called with rem_wakeup = %d reset = %d\n",
5529 __func__, rem_wakeup, reset);
5530
5531 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5532 hsotg->hibernated = 0;
5533
5534 /*
5535 * This step is not described in functional spec but if not wait for
5536 * this delay, mismatch interrupts occurred because just after restore
5537 * core is in Device mode(gintsts.curmode == 0)
5538 */
5539 mdelay(100);
5540
5541 /* Clear all pending interupts */
5542 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5543
5544 /* De-assert Restore */
5545 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5546 gpwrdn &= ~GPWRDN_RESTORE;
5547 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5548 udelay(10);
5549
5550 /* Restore GUSBCFG, HCFG */
5551 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5552 dwc2_writel(hsotg, hr->hcfg, HCFG);
5553
5554 /* De-assert Wakeup Logic */
5555 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5556 gpwrdn &= ~GPWRDN_PMUACTV;
5557 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5558 udelay(10);
5559
5560 hprt0 = hr->hprt0;
5561 hprt0 |= HPRT0_PWR;
5562 hprt0 &= ~HPRT0_ENA;
5563 hprt0 &= ~HPRT0_SUSP;
5564 dwc2_writel(hsotg, hprt0, HPRT0);
5565
5566 hprt0 = hr->hprt0;
5567 hprt0 |= HPRT0_PWR;
5568 hprt0 &= ~HPRT0_ENA;
5569 hprt0 &= ~HPRT0_SUSP;
5570
5571 if (reset) {
5572 hprt0 |= HPRT0_RST;
5573 dwc2_writel(hsotg, hprt0, HPRT0);
5574
5575 /* Wait for Resume time and then program HPRT again */
5576 mdelay(60);
5577 hprt0 &= ~HPRT0_RST;
5578 dwc2_writel(hsotg, hprt0, HPRT0);
5579 } else {
5580 hprt0 |= HPRT0_RES;
5581 dwc2_writel(hsotg, hprt0, HPRT0);
5582
5583 /* Wait for Resume time and then program HPRT again */
5584 mdelay(100);
5585 hprt0 &= ~HPRT0_RES;
5586 dwc2_writel(hsotg, hprt0, HPRT0);
5587 }
5588 /* Clear all interrupt status */
5589 hprt0 = dwc2_readl(hsotg, HPRT0);
5590 hprt0 |= HPRT0_CONNDET;
5591 hprt0 |= HPRT0_ENACHG;
5592 hprt0 &= ~HPRT0_ENA;
5593 dwc2_writel(hsotg, hprt0, HPRT0);
5594
5595 hprt0 = dwc2_readl(hsotg, HPRT0);
5596
5597 /* Clear all pending interupts */
5598 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5599
5600 /* Restore global registers */
5601 ret = dwc2_restore_global_registers(hsotg);
5602 if (ret) {
5603 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5604 __func__);
5605 return ret;
5606 }
5607
5608 /* Restore host registers */
5609 ret = dwc2_restore_host_registers(hsotg);
5610 if (ret) {
5611 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5612 __func__);
5613 return ret;
5614 }
5615
5616 if (rem_wakeup) {
5617 dwc2_hcd_rem_wakeup(hsotg);
5618 /*
5619 * Change "port_connect_status_change" flag to re-enumerate,
5620 * because after exit from hibernation port connection status
5621 * is not detected.
5622 */
5623 hsotg->flags.b.port_connect_status_change = 1;
5624 }
5625
5626 hsotg->hibernated = 0;
5627 hsotg->bus_suspended = 0;
5628 hsotg->lx_state = DWC2_L0;
5629 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
5630 return ret;
5631 }
5632
dwc2_host_can_poweroff_phy(struct dwc2_hsotg * dwc2)5633 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
5634 {
5635 struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub;
5636
5637 /* If the controller isn't allowed to wakeup then we can power off. */
5638 if (!device_may_wakeup(dwc2->dev))
5639 return true;
5640
5641 /*
5642 * We don't want to power off the PHY if something under the
5643 * root hub has wakeup enabled.
5644 */
5645 if (usb_wakeup_enabled_descendants(root_hub))
5646 return false;
5647
5648 /* No reason to keep the PHY powered, so allow poweroff */
5649 return true;
5650 }
5651