1 /* 2 * Copyright 2020 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef __HAL_JPEGD_RKV_REG_H__ 17 #define __HAL_JPEGD_RKV_REG_H__ 18 19 #define JPEGD_REG_NUM (42) 20 21 #define RKV_JPEGD_LITTLE_ENDIAN (0) 22 #define RKV_JPEGD_BIG_ENDIAN (1) 23 24 #define SCALEDOWN_DISABLE (0) 25 #define SCALEDOWN_HALF (1) 26 #define SCALEDOWN_QUARTER (2) 27 #define SCALEDOWN_ONE_EIGHTS (3) 28 29 #define OUTPUT_RASTER (0) 30 #define OUTPUT_TILE (1) 31 32 #define TIMEOUT_MODE_CYCLE_24 (0) 33 #define TIMEOUT_MODE_CYCLE_18 (1) 34 35 #define OUT_SEQUENCE_RASTER (0) 36 #define OUT_SEQUENCE_TILE (1) 37 38 #define YUV_TO_RGB_REC_BT601 (0) 39 #define YUV_TO_RGB_REC_BT709 (1) 40 41 #define YUV_TO_RGB_FULL_RANGE (1) 42 #define YUV_TO_RGB_LIMIT_RANGE (0) 43 44 #define YUV_OUT_FMT_NO_TRANS (0) 45 #define YUV_OUT_FMT_2_RGB888 (1) 46 #define YUV_OUT_FMT_2_RGB565 (2) 47 // Not support YUV400 transmit to NV12 48 #define YUV_OUT_FMT_2_NV12 (3) 49 // Only support YUV422 or YUV444, YUV444 should scaledown uv 50 #define YUV_OUT_FMT_2_YUYV (4) 51 52 #define YUV_MODE_400 (0) 53 #define YUV_MODE_411 (1) 54 #define YUV_MODE_420 (2) 55 #define YUV_MODE_422 (3) 56 #define YUV_MODE_440 (4) 57 #define YUV_MODE_444 (5) 58 59 #define BIT_DEPTH_8 (0) 60 #define BIT_DEPTH_12 (1) 61 62 // No quantization/huffman table or table is the same as previous 63 #define TBL_ENTRY_0 (0) 64 // Grayscale picture with only 1 quantization/huffman table 65 #define TBL_ENTRY_1 (1) 66 // Common case, one table for luma, one for chroma 67 #define TBL_ENTRY_2 (2) 68 // 3 table entries, one for luma, one for cb, one for cr 69 #define TBL_ENTRY_3 (3) 70 71 // Restart interval marker disable 72 #define RST_DISABLE (0) 73 // Restart interval marker enable 74 #define RST_ENABLE (1) 75 76 typedef struct { 77 struct { 78 RK_U32 minor_ver : 8; 79 RK_U32 bit_depth : 1; 80 RK_U32 : 7; 81 RK_U32 prod_num : 16; 82 } reg0_id; 83 84 struct { 85 RK_U32 dec_e : 1; 86 RK_U32 dec_irq_dis : 1; 87 RK_U32 dec_timeout_e : 1; 88 RK_U32 buf_empty_e : 1; 89 RK_U32 buf_empty_reload_p : 1; 90 RK_U32 soft_rst_en_p : 1; 91 RK_U32 dec_irq_raw : 1; 92 RK_U32 wait_reset_e : 1; 93 RK_U32 dec_irq : 1; 94 RK_U32 dec_rdy_sta : 1; 95 RK_U32 dec_bus_sta : 1; 96 RK_U32 dec_error_sta : 1; 97 RK_U32 dec_timeout_sta : 1; 98 RK_U32 dec_buf_empty_sta : 1; 99 RK_U32 soft_rest_rdy : 1; 100 RK_U32 buf_empty_force_end_flag : 1; 101 RK_U32 care_strm_error_e : 1; 102 RK_U32 : 15; 103 } reg1_int; 104 105 struct { 106 RK_U32 in_endian : 1; 107 RK_U32 in_swap32_e : 1; 108 RK_U32 in_swap64_e : 1; 109 RK_U32 str_endian : 1; 110 RK_U32 str_swap32_e : 1; 111 RK_U32 str_swap64_e : 1; 112 RK_U32 out_endian : 1; 113 RK_U32 out_swap32_e : 1; 114 RK_U32 out_swap64_e : 1; 115 RK_U32 out_cbcr_swap : 1; 116 RK_U32 : 2; 117 RK_U32 scaledown_mode : 2; 118 RK_U32 : 2; 119 RK_U32 time_out_mode : 1; 120 RK_U32 force_softrest_valid : 1; 121 RK_U32 : 2; 122 RK_U32 fbc_e : 1; 123 RK_U32 allow_16x8_cp_flag : 1; 124 RK_U32 fbc_force_uncompress : 1; 125 RK_U32 : 1; 126 RK_U32 fill_down_e : 1; 127 RK_U32 fill_right_e : 1; 128 RK_U32 dec_out_sequence : 1; 129 RK_U32 yuv_out_format : 3; 130 RK_U32 yuv2rgb_rec : 1; 131 RK_U32 yuv2rgb_range : 1; 132 133 } reg2_sys; 134 135 struct { 136 RK_U32 pic_width_m1 : 16; 137 RK_U32 pic_height_m1 : 16; 138 } reg3_pic_size; 139 140 struct { 141 RK_U32 jpeg_mode : 3; 142 RK_U32 : 1; 143 RK_U32 pixel_depth : 3; 144 RK_U32 : 1; 145 RK_U32 qtables_sel : 2; 146 RK_U32 : 2; 147 RK_U32 htables_sel : 2; 148 RK_U32 : 1; 149 RK_U32 dri_e : 1; 150 RK_U32 dri_mcu_num_m1 : 16; 151 } reg4_pic_fmt; 152 153 struct { 154 RK_U32 y_hor_virstride : 16; 155 RK_U32 uv_hor_virstride : 16; 156 } reg5_hor_virstride; 157 158 struct { 159 RK_U32 : 4; 160 RK_U32 y_virstride : 28; 161 } reg6_y_virstride; 162 163 struct { 164 RK_U32 qtbl_len : 5; 165 RK_U32 : 3; 166 RK_U32 htbl_mincode_len : 5; 167 RK_U32 : 3; 168 RK_U32 htbl_value_len : 6; 169 RK_U32 : 2; 170 RK_U32 y_hor_virstride_h : 1; 171 RK_U32 : 7; 172 } reg7_tbl_len; 173 174 struct { 175 RK_U32 strm_start_byte : 4; 176 RK_U32 stream_len : 28; 177 } reg8_strm_len; 178 179 RK_U32 reg9_qtbl_base; //64 bytes align 180 181 RK_U32 reg10_htbl_mincode_base; //64 bytes align 182 183 RK_U32 reg11_htbl_value_base; //64 bytes align 184 185 RK_U32 reg12_strm_base; //16 bytes align 186 187 RK_U32 reg13_dec_out_base; //64 bytes align 188 189 struct { 190 RK_U32 error_prc_mode : 1; 191 RK_U32 strm_r0_err_mode : 2; 192 RK_U32 strm_r1_err_mode : 2; 193 RK_U32 strm_ffff_err_mode : 2;//default skip 0xffff 194 RK_U32 strm_other_mark_mode : 2; 195 RK_U32 strm_dri_seq_err_mode : 1; 196 RK_U32 : 6; 197 RK_U32 hfm_force_stop : 5; 198 RK_U32 : 11; 199 } reg14_strm_error; 200 201 struct { 202 RK_U32 strm_r0_marker : 8; 203 RK_U32 strm_r0_mask : 8; 204 RK_U32 strm_r1_marker : 8; 205 RK_U32 strm_r1_mask : 8; 206 } reg15_strm_mask; 207 208 union { 209 struct { 210 RK_U32 dec_clkgate_e : 1; 211 RK_U32 dec_strm_gate_e : 1; 212 RK_U32 dec_huffman_gate_e : 1; 213 RK_U32 dec_izq_gate_e : 1; 214 RK_U32 dec_idct_gate_e : 1; 215 RK_U32 busifd_gate_e : 1; 216 RK_U32 post_prs_get_e : 1; 217 RK_U32 dec_sram_gate_e : 1; 218 RK_U32 : 24; 219 }; 220 RK_U32 val; 221 } reg16_clk_gate; 222 223 RK_U32 reg17_29[13]; 224 225 struct { 226 RK_U32 axi_per_work_e : 1; 227 RK_U32 axi_per_clr_e : 1; 228 RK_U32 axi_perf_frm_tyep : 1; 229 RK_U32 axi_cnt_type : 1; 230 RK_U32 rd_latency_id : 4; 231 RK_U32 rd_latency_thr : 12; 232 RK_U32 : 12; 233 } reg30_perf_latency_ctrl0; 234 235 struct { 236 RK_U32 addr_align_type : 2; 237 RK_U32 ar_cnt_id_type : 1; 238 RK_U32 aw_cnt_id_type : 1; 239 RK_U32 ar_count_id : 4; 240 RK_U32 aw_count_id : 4; 241 RK_U32 rd_totoal_bytes_mode : 1; 242 RK_U32 : 19; 243 } reg31_perf_latency_ctrl1; 244 245 struct { 246 RK_U32 mcu_pos_x : 16; 247 RK_U32 mcu_pos_y : 16; 248 } reg32_dbg_mcu_pos; 249 250 struct { 251 RK_U32 stream_dri_seq_err_sta : 1; 252 RK_U32 stream_r0_err_sta : 1; 253 RK_U32 stream_r1_err_sta : 1; 254 RK_U32 stream_ffff_err_sta : 1; 255 RK_U32 stream_other_mark_err_sta : 1; 256 RK_U32 : 3; 257 RK_U32 huffman_mcu_cnt_l : 1; 258 RK_U32 huffman_mcu_cnt_m : 1; 259 RK_U32 huffman_eoi_without_end : 1; 260 RK_U32 huffman_end_without_eoi : 1; 261 RK_U32 huffman_overflow : 1; 262 RK_U32 huffman_buf_empty : 1; 263 RK_U32 : 2; 264 RK_U32 first_error_idx : 4; 265 RK_U32 : 12; 266 } regs33_dbg_error_info; 267 268 struct { 269 RK_U32 rd_max_latency_num_ch0 : 16; 270 RK_U32 : 16; 271 } reg34_perf_rd_max_latency_num0; 272 273 RK_U32 reg35_perf_rd_latency_samp_num; 274 275 RK_U32 reg36_perf_rd_latency_acc_sum; 276 277 RK_U32 reg37_perf_rd_axi_total_byte; 278 279 RK_U32 reg38_perf_wr_axi_total_byte; 280 281 RK_U32 reg39_perf_working_cnt; 282 283 struct { 284 RK_U32 bus_status_flag : 19; 285 RK_U32 : 13; 286 } reg40_dbg_bus_sta; 287 288 struct { 289 RK_U32 work_status_flag : 18; 290 RK_U32 : 12; 291 } reg41_dbg_work_sta; 292 293 } JpegRegSet; 294 295 #endif /* __HAL_JPEGD_RKV_REG_H__ */