1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
28 #if RT_PLATFORM == PLATFORM_MACOSX
29 #include "phydm_precomp.h"
30 #else
31 #include "../phydm_precomp.h"
32 #endif
33 #else
34 #include "../../phydm_precomp.h"
35 #endif
36
37 #if (RTL8822C_SUPPORT == 1)
38
39 /*---------------------------Define Local Constant---------------------------*/
40
41 /*8822C DPK ver:0x20 20200106*/
42
43 static u32
_btc_wait_indirect_reg_ready_8822c(struct dm_struct * dm)44 _btc_wait_indirect_reg_ready_8822c(
45 struct dm_struct *dm)
46 {
47 u32 delay_count = 0;
48 u16 i;
49
50 /* wait for ready bit before access 0x1700 */
51 while (1) {
52 if ((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) {
53 for (i = 0; i < 500; i++) /*delay 10ms*/
54 ODM_delay_us(20);
55
56 if (++delay_count >= 10)
57 break;
58 } else {
59 break;
60 }
61 }
62
63 return delay_count;
64 }
65
66 static u32
_btc_read_indirect_reg_8822c(struct dm_struct * dm,u16 reg_addr)67 _btc_read_indirect_reg_8822c(
68 struct dm_struct *dm,
69 u16 reg_addr)
70 {
71 u32 delay_count = 0;
72
73 /* wait for ready bit before access 0x1700 */
74 _btc_wait_indirect_reg_ready_8822c(dm);
75
76 odm_write_4byte(dm, 0x1700, 0x800F0000 | reg_addr);
77
78 return odm_read_4byte(dm, 0x1708); /* get read data */
79 }
80
81 static void
_btc_write_indirect_reg_8822c(struct dm_struct * dm,u16 reg_addr,u32 bit_mask,u32 reg_value)82 _btc_write_indirect_reg_8822c(
83 struct dm_struct *dm,
84 u16 reg_addr,
85 u32 bit_mask,
86 u32 reg_value)
87 {
88 u32 val, i = 0, bitpos = 0, delay_count = 0;
89
90 if (bit_mask == 0x0)
91 return;
92
93 if (bit_mask == 0xffffffff) {
94 /* wait for ready bit before access 0x1700 */
95 _btc_wait_indirect_reg_ready_8822c(dm);
96
97 /* put write data */
98 odm_write_4byte(dm, 0x1704, reg_value);
99
100 odm_write_4byte(dm, 0x1700, 0xc00F0000 | reg_addr);
101 } else {
102 for (i = 0; i <= 31; i++) {
103 if (((bit_mask >> i) & 0x1) == 0x1) {
104 bitpos = i;
105 break;
106 }
107 }
108
109 /* read back register value before write */
110 val = _btc_read_indirect_reg_8822c(dm, reg_addr);
111 val = (val & (~bit_mask)) | (reg_value << bitpos);
112
113 /* wait for ready bit before access 0x1700 */
114 _btc_wait_indirect_reg_ready_8822c(dm);
115
116 odm_write_4byte(dm, 0x1704, val); /* put write data */
117 odm_write_4byte(dm, 0x1700, 0xc00F0000 | reg_addr);
118 }
119 }
120
btc_set_gnt_wl_bt_8822c(void * dm_void,boolean is_before_k)121 void btc_set_gnt_wl_bt_8822c(
122 void *dm_void,
123 boolean is_before_k)
124 {
125 struct dm_struct *dm = (struct dm_struct *)dm_void;
126 struct dm_dpk_info *dpk_info = &dm->dpk_info;
127
128 if (is_before_k) {
129 dpk_info->gnt_control = odm_get_mac_reg(dm, R_0x70, MASKDWORD);
130 dpk_info->gnt_value = _btc_read_indirect_reg_8822c(dm, 0x38);
131
132 /*force GNT control to WL*/
133 odm_set_mac_reg(dm, R_0x70, BIT(26), 0x1);
134 /*force GNT_WL=1, GNT_BT=0*/
135 _btc_write_indirect_reg_8822c(dm, 0x38, 0xFF00, 0x77);
136 #if 0
137 RF_DBG(dm, DBG_RF_DPK, "[DPK] ori 0x70 / 0x38 = 0x%x / 0x%x\n",
138 dpk_info->gnt_control, dpk_info->gnt_value);
139
140 RF_DBG(dm, DBG_RF_DPK, "[DPK] set 0x70/0x38 = 0x%x/0x%x\n",
141 odm_get_mac_reg(dm, R_0x70, MASKDWORD),
142 _btc_read_indirect_reg_8822c(dm, 0x38));
143 #endif
144 } else {
145 _btc_write_indirect_reg_8822c(dm, 0x38, MASKDWORD, dpk_info->gnt_value);
146 odm_set_mac_reg(dm, R_0x70, MASKDWORD, dpk_info->gnt_control);
147 #if 0
148 RF_DBG(dm, DBG_RF_DPK, "[DPK] load 0x70 / 0x38 = 0x%x / 0x%x\n",
149 odm_get_mac_reg(dm, R_0x70, MASKDWORD),
150 _btc_read_indirect_reg_8822c(dm, 0x38));
151 #endif
152 }
153 }
154
_backup_mac_bb_registers_8822c(struct dm_struct * dm,u32 * reg,u32 * reg_backup,u32 reg_num)155 void _backup_mac_bb_registers_8822c(
156 struct dm_struct *dm,
157 u32 *reg,
158 u32 *reg_backup,
159 u32 reg_num)
160 {
161 u32 i;
162
163 for (i = 0; i < reg_num; i++) {
164 reg_backup[i] = odm_read_4byte(dm, reg[i]);
165 #if 0
166 RF_DBG(dm, DBG_RF_DPK, "[DPK] Backup MAC/BB 0x%x = 0x%x\n",
167 reg[i], reg_backup[i]);
168 #endif
169 }
170 }
171
_backup_rf_registers_8822c(struct dm_struct * dm,u32 * rf_reg,u32 rf_reg_backup[][2])172 void _backup_rf_registers_8822c(
173 struct dm_struct *dm,
174 u32 *rf_reg,
175 u32 rf_reg_backup[][2])
176 {
177 u32 i;
178
179 for (i = 0; i < DPK_RF_REG_NUM_8822C; i++) {
180 rf_reg_backup[i][RF_PATH_A] = odm_get_rf_reg(dm, RF_PATH_A,
181 rf_reg[i], RFREG_MASK);
182 rf_reg_backup[i][RF_PATH_B] = odm_get_rf_reg(dm, RF_PATH_B,
183 rf_reg[i], RFREG_MASK);
184 #if 0
185 RF_DBG(dm, DBG_RF_DPK, "[DPK] Backup RF_A 0x%x = 0x%x\n",
186 rf_reg[i], rf_reg_backup[i][RF_PATH_A]);
187 RF_DBG(dm, DBG_RF_DPK, "[DPK] Backup RF_B 0x%x = 0x%x\n",
188 rf_reg[i], rf_reg_backup[i][RF_PATH_B]);
189 #endif
190 }
191 }
192
_reload_mac_bb_registers_8822c(struct dm_struct * dm,u32 * reg,u32 * reg_backup,u32 reg_num)193 void _reload_mac_bb_registers_8822c(
194 struct dm_struct *dm,
195 u32 *reg,
196 u32 *reg_backup,
197 u32 reg_num)
198
199 {
200 struct dm_dpk_info *dpk_info = &dm->dpk_info;
201
202 u32 i;
203
204 /*toggle IGI*/
205 odm_write_4byte(dm, 0x1d70, 0x50505050);
206
207 for (i = 0; i < reg_num; i++) {
208 odm_write_4byte(dm, reg[i], reg_backup[i]);
209 #if 0
210 RF_DBG(dm, DBG_RF_DPK, "[DPK] Reload MAC/BB 0x%x = 0x%x\n",
211 reg[i], reg_backup[i]);
212 #endif
213 }
214 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc); /*subpage 2*/
215 odm_set_bb_reg(dm, R_0x1bd4, 0x000000f0, 0x4); /*force CLK off for power saving*/
216 }
217
_reload_rf_registers_8822c(struct dm_struct * dm,u32 * rf_reg,u32 rf_reg_backup[][2])218 void _reload_rf_registers_8822c(
219 struct dm_struct *dm,
220 u32 *rf_reg,
221 u32 rf_reg_backup[][2])
222 {
223 u32 i, rf_reg_8f[DPK_RF_PATH_NUM_8822C] = {0x0};
224
225 for (i = 0; i < DPK_RF_REG_NUM_8822C; i++) {
226 odm_set_rf_reg(dm, RF_PATH_A, rf_reg[i], RFREG_MASK,
227 rf_reg_backup[i][RF_PATH_A]);
228 odm_set_rf_reg(dm, RF_PATH_B, rf_reg[i], RFREG_MASK,
229 rf_reg_backup[i][RF_PATH_B]);
230 #if 0
231 RF_DBG(dm, DBG_RF_DPK, "[DPK] Reload RF_A 0x%x = 0x%x\n",
232 rf_reg[i], rf_reg_backup[i][RF_PATH_A]);
233 RF_DBG(dm, DBG_RF_DPK, "[DPK] Reload RF_B 0x%x = 0x%x\n",
234 rf_reg[i], rf_reg_backup[i][RF_PATH_B]);
235 #endif
236 }
237 #if 0
238 /*reload RF 0x8f for non-saving power mode*/
239 for (i = 0; i < DPK_RF_PATH_NUM_8822C; i++) {
240 rf_reg_8f[i] = odm_get_rf_reg(dm, (enum rf_path)i,
241 RF_0x8f, 0x00fff);
242 odm_set_rf_reg(dm, (enum rf_path)i, RF_0x8f, RFREG_MASK,
243 0xa8000 | rf_reg_8f[i]);
244 }
245 #endif
246 }
247
_dpk_information_8822c(struct dm_struct * dm)248 void _dpk_information_8822c(
249 struct dm_struct *dm)
250 {
251 struct dm_dpk_info *dpk_info = &dm->dpk_info;
252
253 u32 reg_rf18;
254
255 if (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))
256 dpk_info->is_tssi_mode = true;
257 else
258 dpk_info->is_tssi_mode = false;
259
260 dpk_info->dpk_rf18[0] = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);
261
262 dpk_info->dpk_band = (u8)((dpk_info->dpk_rf18[0] & BIT(16)) >> 16); /*0/1:G/A*/
263 dpk_info->dpk_ch = (u8)dpk_info->dpk_rf18[0] & 0xff;
264 dpk_info->dpk_bw = (u8)((dpk_info->dpk_rf18[0] & 0x3000) >> 12); /*3/2/1:20/40/80*/
265
266 RF_DBG(dm, DBG_RF_DPK, "[DPK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\n",
267 dpk_info->is_tssi_mode, dpk_info->dpk_band == 0 ? "2G" : "5G",
268 dpk_info->dpk_ch,
269 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
270 }
271
_dpk_rxbb_dc_cal_8822c(struct dm_struct * dm,u8 path)272 void _dpk_rxbb_dc_cal_8822c(
273 struct dm_struct *dm,
274 u8 path)
275 {
276 u8 i;
277
278 odm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84800);
279 ODM_delay_us(5);
280 odm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84801);
281 for (i = 0; i < 30; i++) /*delay 600us*/
282 ODM_delay_us(20);
283 odm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84800);
284 }
285
_dpk_dc_corr_check_8822c(struct dm_struct * dm,u8 path)286 u8 _dpk_dc_corr_check_8822c(
287 struct dm_struct *dm,
288 u8 path)
289 {
290 struct dm_dpk_info *dpk_info = &dm->dpk_info;
291
292 u16 dc_i, dc_q;
293 u8 corr_val, corr_idx;
294
295 odm_write_4byte(dm, 0x1bd4, 0x000900F0);
296 dc_i = (u16)odm_get_bb_reg(dm, 0x1bfc, 0x0fff0000);
297 dc_q = (u16)odm_get_bb_reg(dm, 0x1bfc, 0x00000fff);
298
299 if (dc_i >> 11 == 1)
300 dc_i = 0x1000 - dc_i;
301 if (dc_q >> 11 == 1)
302 dc_q = 0x1000 - dc_q;
303
304 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d DC I/Q, = %d / %d\n", path, dc_i, dc_q);
305
306 dpk_info->dc_i[path] = dc_i;
307 dpk_info->dc_q[path] = dc_q;
308
309 odm_write_4byte(dm, 0x1bd4, 0x000000F0);
310 corr_idx = (u8)odm_get_bb_reg(dm, 0x1bfc, 0x000000ff);
311 corr_val = (u8)odm_get_bb_reg(dm, 0x1bfc, 0x0000ff00);
312
313 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d Corr_idx / Corr_val = %d / %d\n",
314 path, corr_idx, corr_val);
315
316 dpk_info->corr_idx[path] = corr_idx;
317 dpk_info->corr_val[path] = corr_val;
318
319 if ((dc_i > 200) || (dc_q > 200) || (corr_idx < 40) || (corr_idx > 65))
320 return 1;
321 else
322 return 0;
323
324 }
325
_dpk_tx_pause_8822c(struct dm_struct * dm)326 void _dpk_tx_pause_8822c(
327 struct dm_struct *dm)
328 {
329 u8 reg_rf0_a, reg_rf0_b;
330 u16 count = 0;
331
332 odm_write_1byte(dm, R_0x522, 0xff);
333 odm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x2); /*hw tx stop*/
334
335 reg_rf0_a = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xF0000);
336 reg_rf0_b = (u8)odm_get_rf_reg(dm, RF_PATH_B, RF_0x00, 0xF0000);
337
338 while (((reg_rf0_a == 2) || (reg_rf0_b == 2)) && count < 2500) {
339 reg_rf0_a = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xF0000);
340 reg_rf0_b = (u8)odm_get_rf_reg(dm, RF_PATH_B, RF_0x00, 0xF0000);
341 ODM_delay_us(2);
342 count++;
343 }
344
345 RF_DBG(dm, DBG_RF_DPK, "[DPK] Tx pause!!\n");
346 }
347
_dpk_mac_bb_setting_8822c(struct dm_struct * dm)348 void _dpk_mac_bb_setting_8822c(
349 struct dm_struct *dm)
350 {
351 struct dm_dpk_info *dpk_info = &dm->dpk_info;
352
353 _dpk_tx_pause_8822c(dm);
354
355 if (dpk_info->is_tssi_mode) {
356 odm_set_bb_reg(dm, R_0x1e7c, BIT(30), 0x0);
357 odm_set_bb_reg(dm, R_0x18a4, BIT(28), 0x0);
358 odm_set_bb_reg(dm, R_0x41a4, BIT(28), 0x0);
359 }
360
361 odm_set_bb_reg(dm, R_0x1e24, BIT(17), 0x1); /*r_gothrough_iqkdpk*/
362
363 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); /*BB CCA off*/
364
365 /*r_rftxen_gck_force*/
366 odm_set_bb_reg(dm, R_0x1864, BIT(31), 0x1);
367 odm_set_bb_reg(dm, R_0x4164, BIT(31), 0x1);
368 /*r_dis_sharerx_txgat*/
369 odm_set_bb_reg(dm, R_0x180c, BIT(27), 0x1);
370 odm_set_bb_reg(dm, R_0x410c, BIT(27), 0x1);
371
372 odm_set_bb_reg(dm, R_0x186c, BIT(7), 0x1);
373 odm_set_bb_reg(dm, R_0x416c, BIT(7), 0x1);
374
375 odm_set_bb_reg(dm, R_0x180c, BIT(1) | BIT(0), 0x0);
376 odm_set_bb_reg(dm, R_0x410c, BIT(1) | BIT(0), 0x0);
377
378 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3); /*CCK RXIQ weighting=0*/
379
380 odm_set_bb_reg(dm, R_0x80c, 0x0000000f, 0x8); /*freq shap filter*/
381
382 /*odm_write_1byte(dm, R_0x820, 0x33);*/
383 odm_set_bb_reg(dm, R_0x824, 0x000f0000, 0x3);
384 odm_set_bb_reg(dm, R_0x824, 0x0f000000, 0x3);
385
386 RF_DBG(dm, DBG_RF_DPK, "[DPK] MAC/BB setting for DPK mode\n");
387 }
388
_dpk_manual_txagc_8822c(struct dm_struct * dm,boolean is_manual)389 void _dpk_manual_txagc_8822c(
390 struct dm_struct *dm,
391 boolean is_manual)
392 {
393 odm_set_bb_reg(dm, R_0x18a4, BIT(7), is_manual);
394 odm_set_bb_reg(dm, R_0x41a4, BIT(7), is_manual);
395 }
396
_dpk_set_txagc_8822c(struct dm_struct * dm)397 void _dpk_set_txagc_8822c(
398 struct dm_struct *dm)
399 {
400 odm_set_bb_reg(dm, R_0x18a0, 0x007C0000, 0x1f);
401 odm_set_bb_reg(dm, R_0x41a0, 0x007C0000, 0x1f);
402 odm_set_bb_reg(dm, 0x18e8, 0x0001F000, 0x1f);
403 odm_set_bb_reg(dm, 0x41e8, 0x0001F000, 0x1f);
404 }
405
_dpk_afe_setting_8822c(struct dm_struct * dm,boolean is_do_dpk)406 void _dpk_afe_setting_8822c(
407 struct dm_struct *dm,
408 boolean is_do_dpk)
409 {
410 struct dm_dpk_info *dpk_info = &dm->dpk_info;
411
412 if (is_do_dpk) {
413 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xFFFFFFFF);
414
415 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700f0001);
416 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700f0001);
417 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0001);
418 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0001);
419 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0001);
420 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0001);
421 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705f0001);
422 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0001);
423 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707f0001);
424 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708f0001);
425 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709f0001);
426 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70af0001);
427 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bf0001);
428 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cf0001);
429 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70df0001);
430 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ef0001);
431 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ff0001);
432 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ff0001);
433
434 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700f0001);
435 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700f0001);
436 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0001);
437 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0001);
438 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0001);
439 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0001);
440 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705f0001);
441 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0001);
442 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707f0001);
443 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708f0001);
444 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709f0001);
445 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70af0001);
446 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bf0001);
447 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cf0001);
448 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70df0001);
449 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ef0001);
450 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ff0001);
451 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ff0001);
452
453 RF_DBG(dm, DBG_RF_DPK, "[DPK] AFE for DPK mode\n");
454 } else {
455 if (dpk_info->is_tssi_mode) {
456 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);
457
458 odm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4 >> dpk_info->dpk_band);
459
460 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);
461 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0040 | (0x4 >> dpk_info->dpk_band));
462 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0040 | (0x4 >> dpk_info->dpk_band));
463 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0040 | (0x4 >> dpk_info->dpk_band));
464 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0040 | (0x4 >> dpk_info->dpk_band));
465 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);
466 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0040 | (0x4 >> dpk_info->dpk_band));
467
468 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);
469 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0040 | (0x4 >> dpk_info->dpk_band));
470 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0040 | (0x4 >> dpk_info->dpk_band));
471 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0040 | (0x4 >> dpk_info->dpk_band));
472 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0040 | (0x4 >> dpk_info->dpk_band));
473 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);
474 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0040 | (0x4 >> dpk_info->dpk_band));
475
476 RF_DBG(dm, DBG_RF_DPK, "[DPK] AFE for TSSI mode\n");
477
478 } else {
479 odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xFFA1005E);
480
481 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);
482 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70144041);
483 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70244041);
484 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70344041);
485 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70444041);
486 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);
487 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70644041);
488
489 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);
490 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70144041);
491 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70244041);
492 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70344041);
493 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70444041);
494 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);
495 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70644041);
496
497 RF_DBG(dm, DBG_RF_DPK, "[DPK] AFE for non-TSSI mode\n");
498 }
499
500 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);
501 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);
502 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);
503 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);
504 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);
505 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);
506 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);
507 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);
508 odm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);
509
510 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);
511 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);
512 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);
513 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);
514 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);
515 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);
516 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);
517 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);
518 odm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);
519 }
520 }
521
_dpk_pre_setting_8822c(struct dm_struct * dm)522 void _dpk_pre_setting_8822c(
523 struct dm_struct *dm)
524 {
525 struct dm_dpk_info *dpk_info = &dm->dpk_info;
526
527 u8 path;
528
529 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
530
531 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x19, RFREG_MASK, 0x0);
532
533 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));
534 if (dpk_info->dpk_band == 0x0) /*txagc bnd*/
535 odm_set_bb_reg(dm, R_0x1b60, MASKDWORD, 0x1f100000);
536 else
537 odm_set_bb_reg(dm, R_0x1b60, MASKDWORD, 0x1f0d0000);
538 odm_set_bb_reg(dm, R_0x1b44, 0x00007000, 0x4); /*GL = val*0.5+1*/
539 odm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x3); /*CFIR to TX*/
540 }
541 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc); /*one-shot 6ms*/
542 odm_set_bb_reg(dm, R_0x1be4, MASKDWORD, 0x3b23170b);
543 odm_set_bb_reg(dm, R_0x1be8, MASKDWORD, 0x775f5347);
544 }
545
_dpk_rf_setting_8822c(struct dm_struct * dm,u8 path)546 u32 _dpk_rf_setting_8822c(
547 struct dm_struct *dm,
548 u8 path)
549 {
550 struct dm_dpk_info *dpk_info = &dm->dpk_info;
551
552 s8 txidx_offset = 0x0;
553 u32 value32 = 0, ori_txbb = 0;
554 u8 i;
555
556 #if 0
557 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x944 | (path << 9))) {
558 value32 = phydm_get_bb_dbg_port_val(dm);
559 phydm_release_bb_dbg_port(dm);
560 }
561
562 txidx_offset = (value32 >> 8) & 0x7f;
563
564 if ((txidx_offset >> 6) == 1)
565 txidx_offset = (txidx_offset - 0x80) / 4;
566 else
567 txidx_offset = txidx_offset / 4;
568
569 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d txidx_offset = 0x%x\n",
570 path, txidx_offset);
571 #endif
572 if (dpk_info->dpk_band == 0x0) { /*2G*/
573 /*TXAGC for gainloss*/
574 odm_set_rf_reg(dm, (enum rf_path)path,
575 RF_0x00, RFREG_MASK, 0x50017 + txidx_offset);
576
577 ori_txbb = odm_get_rf_reg(dm, (enum rf_path)path,
578 RF_0x56, RFREG_MASK);
579 /*debug TX Gain*/
580 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
581 /*debug power trim*/
582 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(19), 0x1);
583 /*set offset to zero*/
584 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x55, 0x7C000, 0x0);
585
586 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56,
587 RFREG_MASK, ori_txbb);
588
589 /*ATT Gain*/
590 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x55,
591 BIT(4) | BIT(3) | BIT(2), 0x1);
592 /*mixer*/
593 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x87,
594 BIT(18), 0x0);
595 /*PGA2*/
596 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x00,
597 0x003e0, 0xf);
598 } else { /*5G*/
599
600 /*TXAGC for gainloss*/
601 odm_set_rf_reg(dm, (enum rf_path)path,
602 RF_0x00, RFREG_MASK, 0x50017 + txidx_offset);
603
604 ori_txbb = odm_get_rf_reg(dm, (enum rf_path)path,
605 RF_0x56, RFREG_MASK);
606 /*debug TX Gain*/
607 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);
608 /*debug power trim*/
609 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(19), 0x1);
610 /*set offset to zero*/
611 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x55, 0x7C000, 0x0);
612
613 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56,
614 RFREG_MASK, ori_txbb);
615
616 /*ATT Gain*/
617 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x63,
618 BIT(15) | BIT(14), 0x0);
619
620 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x63,
621 BIT(4) | BIT(3) | BIT(2), 0x6);
622 /*switch*/
623 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x63,
624 BIT(13) | BIT(12), 0x1);
625 /*mixer*/
626 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x8a,
627 BIT(4) | BIT(3), 0x0);
628 /*PGA2*/
629 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x00,
630 0x003e0, 0xf);
631 }
632
633 /*Bypass RXBB filter*/
634 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xde,
635 BIT(2), 0x1);
636 /*BW of RXBB*/
637 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x1a,
638 BIT(11) | BIT(10), 0x0);
639 /*BW of TXBB*/
640 if (dpk_info->dpk_bw == 0x1) /*80M*/
641 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x1a,
642 BIT(14) | BIT(13) | BIT(12), 0x2);
643 else
644 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x1a,
645 BIT(14) | BIT(13) | BIT(12), 0x1);
646
647 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x8f,
648 BIT(1), 0x1);
649
650 RF_DBG(dm, DBG_RF_DPK, "[DPK] ori TXAGC/TXBB/offset = 0x%x / 0x%x / %+d\n",
651 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, 0x0001f),
652 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, 0x0001f),
653 (ori_txbb & 0x1f) - 0xf); /*txagc 0x17 = txbb 0xf*/
654
655 for (i = 0; i < 5; i++) /*delay 100us for TIA SV loop*/
656 ODM_delay_us(20);
657
658 return ori_txbb & 0x1f;
659 }
660
_dpk_one_shot_8822c(struct dm_struct * dm,u8 path,u8 action)661 u8 _dpk_one_shot_8822c(
662 struct dm_struct *dm,
663 u8 path,
664 u8 action)
665 {
666 struct dm_dpk_info *dpk_info = &dm->dpk_info;
667
668 u8 temp = 0x0, bw = 0x0, reg_2d9c = 0x0, sync_done = 0x0, result = 0;
669 u16 dpk_cmd = 0x0, count = 0;
670
671 if (dpk_info->dpk_bw == 0x1) /*80M*/
672 bw = 2;
673 else
674 bw = 0;
675
676 if (action == GAIN_LOSS)
677 temp = 0x14 + path;
678 else if (action == DO_DPK)
679 temp = 0x16 + path + bw;
680 else if (action == DPK_ON)
681 temp = 0x1a + path;
682 else if (action == DAGC)
683 temp = 0x1c + path + bw;
684
685 btc_set_gnt_wl_bt_8822c(dm, true);
686
687 if (action ==0) {
688 odm_set_bb_reg(dm, R_0x1bb4, BIT(12), 0x1);
689 odm_set_bb_reg(dm, R_0x1bb4, BIT(12), 0x0);
690
691 odm_set_bb_reg(dm, R_0x1bd4, 0x001f0000, 0x0);
692 ODM_delay_us(20);
693 sync_done = (u8)odm_get_bb_reg(dm, R_0x1bfc, BIT(31));
694 while (sync_done != 0x1 && count < 1000) {
695 ODM_delay_us(20);
696 sync_done = (u8)odm_get_bb_reg(dm, R_0x1bfc, BIT(31));
697 count++;
698 }
699 } else {
700 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
701 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x9); /*ItQt -6dB*/
702
703 dpk_cmd = (temp << 8) | 0x48;
704 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, dpk_cmd);
705 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, dpk_cmd + 1);
706
707 reg_2d9c = odm_read_1byte(dm, R_0x2d9c);
708 while (reg_2d9c != 0x55 && count < 1000) {
709 ODM_delay_us(20);
710 reg_2d9c = odm_read_1byte(dm, R_0x2d9c);
711 count++;
712 }
713 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
714 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x0); /*ItQt 0dB*/
715 }
716
717 RF_DBG(dm, DBG_RF_DPK, "[DPK] one-shot for S%d %s = 0x%x (count=%d)\n",
718 path, action == 1 ? "GL" : (action == 2 ? "DO_DPK" :
719 (action == 3 ? "DPK_ON" : (action == 0 ? "Cal_PWR" : "DAGC"))),
720 dpk_cmd, count);
721
722 if (count == 1000) {
723 RF_DBG(dm, DBG_RF_DPK, "[DPK] one-shot over 20ms!!!!\n");
724 result = 1;
725 }
726
727 btc_set_gnt_wl_bt_8822c(dm, false);
728
729 odm_write_1byte(dm, 0x1b10, 0x0);
730
731 return result;
732 }
733
_dpk_dgain_read_8822c(struct dm_struct * dm,u8 path)734 u16 _dpk_dgain_read_8822c(
735 struct dm_struct *dm,
736 u8 path)
737 {
738 u16 dgain = 0x0;
739
740 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc); /*subpage 2*/
741 odm_set_bb_reg(dm, R_0x1bd4, 0x00ff0000, 0x0);
742
743 dgain = (u16)odm_get_bb_reg(dm, R_0x1bfc, 0x0FFF0000); /*[27:16]*/
744
745 RF_DBG(dm, DBG_RF_DPK, "[DPK] DGain = 0x%x (%d)\n", dgain, dgain);
746
747 return dgain;
748 }
749
_dpk_thermal_read_8822c(void * dm_void,u8 path)750 u8 _dpk_thermal_read_8822c(
751 void *dm_void,
752 u8 path)
753 {
754 struct dm_struct *dm = (struct dm_struct *)dm_void;
755 struct dm_dpk_info *dpk_info = &dm->dpk_info;
756
757 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x42, BIT(19), 0x1);
758 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x42, BIT(19), 0x0);
759 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x42, BIT(19), 0x1);
760 ODM_delay_us(15);
761
762 return (u8)odm_get_rf_reg(dm, (enum rf_path)path, RF_0x42, 0x0007e);
763 }
764
_dpk_pas_read_8822c(struct dm_struct * dm,u8 path,u8 action)765 u32 _dpk_pas_read_8822c(
766 struct dm_struct *dm,
767 u8 path,
768 u8 action)
769 {
770 u8 k;
771 u32 reg_1bfc, i_val = 0, q_val = 0;
772
773 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));
774 odm_set_bb_reg(dm, R_0x1b48, BIT(14), 0x0);
775
776 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00060001);
777 odm_set_bb_reg(dm, R_0x1b4c, MASKDWORD, 0x00000000);
778
779 switch (action) {
780 case LOSS_CHK:
781
782 odm_set_bb_reg(dm, R_0x1b4c, MASKDWORD, 0x00080000);
783
784 q_val = odm_get_bb_reg(dm, R_0x1bfc, MASKHWORD);
785 i_val = odm_get_bb_reg(dm, R_0x1bfc, MASKLWORD);
786
787 if (i_val >> 15 != 0)
788 i_val = 0x10000 - i_val;
789 if (q_val >> 15 != 0)
790 q_val = 0x10000 - q_val;
791
792 #if (DPK_PAS_CHK_DBG_8822C)
793 RF_DBG(dm, DBG_RF_DPK, "[DPK][%s] i=0x%x,q=0x%x,i^2+q^2=0x%x\n",
794 "LOSS", i_val, q_val, i_val*i_val + q_val*q_val);
795 #endif
796 break;
797
798 case PAS_READ:
799
800 for (k = 0; k < 64; k++) {
801 odm_set_bb_reg(dm, R_0x1b4c, MASKDWORD,
802 (0x00080000 | (k << 24)));
803 #if 0
804 RF_DBG(dm, DBG_RF_DPK, "[DPK] 0x1b4c[%d] = 0x%x\n", k,
805 odm_get_bb_reg(dm, R_0x1b4c, MASKDWORD));
806 #endif
807 reg_1bfc = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
808 RF_DBG(dm, DBG_RF_DPK, "[DPK] PA scan_S%d = 0x%08x\n",
809 path, reg_1bfc);
810 }
811 break;
812
813 default:
814 break;
815 }
816
817 odm_set_bb_reg(dm, R_0x1b4c, MASKDWORD, 0x00000000);
818 return i_val*i_val + q_val*q_val;
819 }
820
_dpk_gainloss_result_8822c(struct dm_struct * dm,u8 path)821 u8 _dpk_gainloss_result_8822c(
822 struct dm_struct *dm,
823 u8 path)
824 {
825 u8 result;
826
827 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
828 odm_set_bb_reg(dm, R_0x1b48, BIT(14), 0x1);
829 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00060000);
830
831 result = (u8)odm_get_bb_reg(dm, R_0x1bfc, 0x000000f0);
832
833 odm_set_bb_reg(dm, R_0x1b48, BIT(14), 0x0);
834
835 RF_DBG(dm, DBG_RF_DPK, "[DPK] tmp GL = %d\n", result);
836 return result;
837 }
838
_dpk_agc_chk_8822c(struct dm_struct * dm,u8 path,u8 limited_pga,u8 check)839 u8 _dpk_agc_chk_8822c(
840 struct dm_struct *dm,
841 u8 path,
842 u8 limited_pga,
843 u8 check)
844 {
845 u8 result = 0;
846 u16 dgain =0;
847 u32 loss = 0;
848 u32 loss_db = 0;
849
850 if (check == GAIN_CHK) {
851 _dpk_one_shot_8822c(dm, path, DAGC);
852 dgain = _dpk_dgain_read_8822c(dm, path);
853
854 if ((dgain > 1535) && !limited_pga) { /*DGain > 1535 happen*/
855 RF_DBG(dm, DBG_RF_DPK, "[DPK] Small DGain!!\n");
856 result = 2;
857 return result;
858 } else if ((dgain < 768) && !limited_pga) { /*DGain < 768 happen*/
859 RF_DBG(dm, DBG_RF_DPK, "[DPK] Large DGain!!\n");
860 result = 1;
861 return result;
862 } else
863 return result;
864
865 } else if (check == LOSS_CHK) {
866 loss = _dpk_pas_read_8822c(dm, path, LOSS_CHK);
867
868 if (loss < 0x4000000) {
869 RF_DBG(dm, DBG_RF_DPK, "[DPK] GLoss < 0dB happen!!\n");
870 result = 4;
871 return result;
872 }
873 loss_db = 3 * halrf_psd_log2base(loss >> 13);
874
875 #if (DPK_PAS_CHK_DBG_8822C)
876 RF_DBG(dm, DBG_RF_DPK, "[DPK] GLoss = %d.%02ddB\n",
877 (loss_db - 3870) / 100, (loss_db -3870) % 100);
878 #endif
879 if ((loss_db - 3870) > 1000) { /*GL > 10dB*/
880 RF_DBG(dm, DBG_RF_DPK, "[DPK] GLoss > 10dB happen!!\n");
881 result = 3;
882 return result;
883 } else if ((loss_db - 3870) < 250) { /*GL < 2.5dB*/
884 RF_DBG(dm, DBG_RF_DPK, "[DPK] GLoss < 2.5dB happen!!\n");
885 result = 4;
886 return result;
887 } else
888 return result;
889 } else
890 return result;
891
892 }
893
_dpk_pas_agc_8822c(struct dm_struct * dm,u8 path,u8 gain_only,u8 loss_only)894 u8 _dpk_pas_agc_8822c(
895 struct dm_struct *dm,
896 u8 path,
897 u8 gain_only,
898 u8 loss_only)
899 {
900 u8 tmp_txbb = 0, tmp_pga = 0, i = 0;
901 u8 goout = 0, limited_pga = 0, agc_cnt = 0;
902
903 do {
904 switch (i) {
905 case 0: /*Gain check first*/
906 tmp_txbb = (u8)odm_get_rf_reg(dm, (enum rf_path)path,
907 RF_0x56, 0x0001f);
908 tmp_pga = (u8)odm_get_rf_reg(dm, (enum rf_path)path,
909 RF_0x00, 0x003e0);
910
911 RF_DBG(dm, DBG_RF_DPK,
912 "[DPK][AGC] Start TXBB=0x%x, PGA=0x%x\n",
913 tmp_txbb, tmp_pga);
914
915 if (loss_only)
916 i = 5;
917 else {
918 i = _dpk_agc_chk_8822c(dm, path, limited_pga,
919 GAIN_CHK);
920
921 if ((i == 0) && gain_only)
922 goout = 1;
923 else if (i == 0)
924 i =5;
925 }
926
927 agc_cnt++;
928 break;
929
930 case 1: /*Gain > criterion*/
931 if (tmp_pga > 0xe) {
932 odm_set_rf_reg(dm, (enum rf_path)path,
933 RF_0x00, 0x003e0, 0xc);
934 RF_DBG(dm, DBG_RF_DPK,
935 "[DPK][AGC] PGA(-1) = 0xc\n");
936 } else if ((0xb < tmp_pga) && (tmp_pga < 0xf)) {
937 odm_set_rf_reg(dm, (enum rf_path)path,
938 RF_0x00, 0x003e0, 0x0);
939 RF_DBG(dm, DBG_RF_DPK,
940 "[DPK][AGC] PGA(-1) = 0x0\n");
941 } else if (tmp_pga < 0xc) {
942 RF_DBG(dm, DBG_RF_DPK,
943 "[DPK][AGC] PGA@ lower bound!!\n");
944 limited_pga = 1;
945 }
946 i = 0;
947 break;
948
949 case 2: /*Gain < criterion*/
950 if (tmp_pga < 0xc) {
951 odm_set_rf_reg(dm, (enum rf_path)path,
952 RF_0x00, 0x003e0, 0xc);
953 RF_DBG(dm, DBG_RF_DPK,
954 "[DPK][AGC] PGA(+1) = 0xc\n");
955 } else if ((0xb < tmp_pga) && (tmp_pga < 0xf)) {
956 odm_set_rf_reg(dm, (enum rf_path)path,
957 RF_0x00, 0x003e0, 0xf);
958 RF_DBG(dm, DBG_RF_DPK,
959 "[DPK][AGC] PGA(+1) = 0xf\n");
960 } else if (tmp_pga > 0xe) {
961 RF_DBG(dm, DBG_RF_DPK,
962 "[DPK][AGC] PGA@ upper bound!!\n");
963 limited_pga = 1;
964 }
965 i = 0;
966 break;
967
968 case 3: /*GL > criterion*/
969 if (tmp_txbb == 0x0) {
970 goout = 1;
971 RF_DBG(dm, DBG_RF_DPK,
972 "[DPK][AGC] TXBB@ lower bound!!\n");
973 break;
974 }
975 tmp_txbb = tmp_txbb - 2;
976 odm_set_rf_reg(dm, (enum rf_path)path,
977 RF_0x56, 0x0001f, tmp_txbb);
978 RF_DBG(dm, DBG_RF_DPK, "[DPK][AGC] TXBB(-2) = 0x%x\n",
979 tmp_txbb);
980 limited_pga = 0;
981 i = 0;
982 break;
983
984 case 4: /*GL < criterion*/
985 if (tmp_txbb == 0x1f) {
986 goout = 1;
987 RF_DBG(dm, DBG_RF_DPK,
988 "[DPK][AGC] TXBB@ upper bound!!\n");
989 break;
990 }
991 tmp_txbb = tmp_txbb + 3;
992 odm_set_rf_reg(dm, (enum rf_path)path,
993 RF_0x56, 0x0001f, tmp_txbb);
994 RF_DBG(dm, DBG_RF_DPK, "[DPK][AGC] TXBB(+3) = 0x%x\n",
995 tmp_txbb);
996 limited_pga = 0;
997 i = 0;
998 break;
999
1000 case 5: /*Loss check*/
1001 _dpk_one_shot_8822c(dm, path, GAIN_LOSS);
1002 i = _dpk_agc_chk_8822c(dm, path, limited_pga, LOSS_CHK);
1003
1004 #if (DPK_PAS_DBG_8822C)
1005 _dpk_pas_read_8822c(dm, path, PAS_READ);
1006 #endif
1007 if (i == 0)
1008 goout = 1;
1009 break;
1010
1011 default:
1012 goout = 1;
1013 break;
1014 }
1015 } while (!goout && (agc_cnt < 6));
1016
1017 return tmp_txbb;
1018 }
1019
_dpk_coef_iq_check_8822c(struct dm_struct * dm,u16 coef_i,u16 coef_q)1020 boolean _dpk_coef_iq_check_8822c(
1021 struct dm_struct *dm,
1022 u16 coef_i,
1023 u16 coef_q)
1024 {
1025 if ((coef_i == 0x1000) || (coef_i == 0x0fff) ||
1026 (coef_q == 0x1000) || (coef_q == 0x0fff))
1027 return 1;
1028 else
1029 return 0;
1030 }
1031
_dpk_coef_transfer_8822c(void * dm_void)1032 u32 _dpk_coef_transfer_8822c(
1033 void *dm_void)
1034 {
1035 struct dm_struct *dm = (struct dm_struct *)dm_void;
1036 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1037
1038 u32 reg_1bfc = 0;
1039 u16 coef_i = 0, coef_q = 0;
1040
1041 reg_1bfc = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
1042
1043 #if (DPK_COEF_DBG_8822C)
1044 RF_DBG(dm, DBG_RF_DPK,
1045 "[DPK][coef_r] 0x1bfc = 0x%08x\n", reg_1bfc);
1046 #endif
1047
1048 #if 1
1049 coef_i = (u16)odm_get_bb_reg(dm, R_0x1bfc, MASKHWORD) & 0x1fff;
1050 coef_q = (u16)odm_get_bb_reg(dm, R_0x1bfc, MASKLWORD) & 0x1fff;
1051
1052 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
1053
1054 reg_1bfc = (coef_i << 16) | coef_q;
1055 #endif
1056 return reg_1bfc;
1057 }
1058
_dpk_get_coef_8822c(void * dm_void,u8 path)1059 void _dpk_get_coef_8822c(
1060 void *dm_void,
1061 u8 path)
1062 {
1063 struct dm_struct *dm = (struct dm_struct *)dm_void;
1064 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1065
1066 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x0000000c);
1067
1068 if (path == RF_PATH_A) {
1069 odm_set_bb_reg(dm, R_0x1bb4, BIT(24), 0x0);
1070 odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, 0x30000080);
1071 } else if (path == RF_PATH_B) {
1072 odm_set_bb_reg(dm, R_0x1bb4, BIT(24), 0x1);
1073 odm_set_bb_reg(dm, R_0x1b5c, MASKDWORD, 0x30000080);
1074 }
1075
1076 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x000400F0);
1077 dpk_info->coef[path][0] = _dpk_coef_transfer_8822c(dm);
1078 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x040400F0);
1079 dpk_info->coef[path][1] = _dpk_coef_transfer_8822c(dm);
1080 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x080400F0);
1081 dpk_info->coef[path][2] = _dpk_coef_transfer_8822c(dm);
1082 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x010400F0);
1083 dpk_info->coef[path][3] = _dpk_coef_transfer_8822c(dm);
1084 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x050400F0);
1085 dpk_info->coef[path][4] = _dpk_coef_transfer_8822c(dm);
1086 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x090400F0);
1087 dpk_info->coef[path][5] = _dpk_coef_transfer_8822c(dm);
1088 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x020400F0);
1089 dpk_info->coef[path][6] = _dpk_coef_transfer_8822c(dm);
1090 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x060400F0);
1091 dpk_info->coef[path][7] = _dpk_coef_transfer_8822c(dm);
1092 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0A0400F0);
1093 dpk_info->coef[path][8] = _dpk_coef_transfer_8822c(dm);
1094 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x030400F0);
1095 dpk_info->coef[path][9] = _dpk_coef_transfer_8822c(dm);
1096 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x070400F0);
1097 dpk_info->coef[path][10] = _dpk_coef_transfer_8822c(dm);
1098 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0B0400F0);
1099 dpk_info->coef[path][11] = _dpk_coef_transfer_8822c(dm);
1100 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0C0400F0);
1101 dpk_info->coef[path][12] = _dpk_coef_transfer_8822c(dm);
1102 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x100400F0);
1103 dpk_info->coef[path][13] = _dpk_coef_transfer_8822c(dm);
1104 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0D0400F0);
1105 dpk_info->coef[path][14] = _dpk_coef_transfer_8822c(dm);
1106 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x110400F0);
1107 dpk_info->coef[path][15] = _dpk_coef_transfer_8822c(dm);
1108 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0E0400F0);
1109 dpk_info->coef[path][16] = _dpk_coef_transfer_8822c(dm);
1110 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x120400F0);
1111 dpk_info->coef[path][17] = _dpk_coef_transfer_8822c(dm);
1112 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0F0400F0);
1113 dpk_info->coef[path][18] = _dpk_coef_transfer_8822c(dm);
1114 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x130400F0);
1115 dpk_info->coef[path][19] = _dpk_coef_transfer_8822c(dm);
1116
1117 }
1118
_dpk_coef_read_8822c(void * dm_void,u8 path)1119 u8 _dpk_coef_read_8822c(
1120 void *dm_void,
1121 u8 path)
1122 {
1123 struct dm_struct *dm = (struct dm_struct *)dm_void;
1124 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1125
1126 u8 addr, result = 1;
1127 u16 coef_i, coef_q;
1128
1129 for (addr = 0; addr < 20; addr++) {
1130 coef_i = (u16)((dpk_info->coef[path][addr] & 0x1fff0000) >> 16);
1131 coef_q = (u16)(dpk_info->coef[path][addr] & 0x1fff);
1132
1133 if (_dpk_coef_iq_check_8822c(dm, coef_i, coef_q)) {
1134 result = 0;
1135 break;
1136 }
1137 }
1138 return result;
1139 }
1140
_dpk_coef_write_8822c(void * dm_void,u8 path,u8 result)1141 void _dpk_coef_write_8822c(
1142 void *dm_void,
1143 u8 path,
1144 u8 result)
1145 {
1146 struct dm_struct *dm = (struct dm_struct *)dm_void;
1147 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1148
1149 u8 addr;
1150 u16 tmp_reg;
1151 u32 coef;
1152
1153 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x0000000c);
1154 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x000000F0);
1155
1156 for (addr = 0; addr < 20; addr++) {
1157 if (path == RF_PATH_A)
1158 tmp_reg = 0x1b0c + addr * 4;
1159 else
1160 tmp_reg = 0x1b64 + addr * 4;
1161
1162 if (!result) {
1163 if (addr == 3)
1164 coef = 0x04001fff;
1165 else
1166 coef = 0x00001fff;
1167 } else
1168 coef = dpk_info->coef[path][addr];
1169 odm_set_bb_reg(dm, tmp_reg, MASKDWORD, coef);
1170
1171 #if (DPK_COEF_DBG_8822C)
1172 RF_DBG(dm, DBG_RF_DPK,
1173 "[DPK][coef_w] S%d 0x%x = 0x%08x\n", path, tmp_reg, coef);
1174 #endif
1175 }
1176 }
1177
_dpk_coef1_read_8822c(void * dm_void,u8 path)1178 void _dpk_coef1_read_8822c(
1179 void *dm_void,
1180 u8 path)
1181 {
1182 struct dm_struct *dm = (struct dm_struct *)dm_void;
1183
1184 odm_set_bb_reg(dm, R_0x1bb4, BIT(24), path);
1185 odm_set_bb_reg(dm, 0x1b04 + path * 0x58, BIT(29) | BIT(28), 0x1);
1186
1187 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x000400F0);
1188 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1189 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1190 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x040400F0);
1191 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1192 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1193 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x080400F0);
1194 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1195 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1196 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x010400F0);
1197 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1198 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1199 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x050400F0);
1200 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1201 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1202 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x090400F0);
1203 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1204 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1205 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x020400F0);
1206 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1207 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1208 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x060400F0);
1209 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1210 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1211 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0A0400F0);
1212 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1213 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1214 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x030400F0);
1215 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1216 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1217 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x070400F0);
1218 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1219 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1220 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0B0400F0);
1221 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1222 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1223 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0C0400F0);
1224 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1225 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1226 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x100400F0);
1227 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1228 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1229 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0D0400F0);
1230 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1231 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1232 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x110400F0);
1233 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1234 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1235 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0E0400F0);
1236 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1237 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1238 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x120400F0);
1239 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1240 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1241 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0F0400F0);
1242 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1243 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1244 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x130400F0);
1245 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d coef1 = 0x%08x\n", path,
1246 odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD));
1247
1248 odm_set_bb_reg(dm, 0x1b04 + path * 0x58, 0xf0000000, 0x0); /*disable manual coef*/
1249 }
1250
_dpk_coef_default_8822c(void * dm_void,u8 path)1251 void _dpk_coef_default_8822c(
1252 void *dm_void,
1253 u8 path)
1254 {
1255 struct dm_struct *dm = (struct dm_struct *)dm_void;
1256 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1257
1258 u8 addr;
1259 u16 tmp_reg;
1260 u32 coef;
1261
1262 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x0000000c);
1263 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x000000F0);
1264
1265 for (addr = 0; addr < 20; addr++) {
1266 if (path == RF_PATH_A)
1267 tmp_reg = 0x1b0c + addr * 4;
1268 else
1269 tmp_reg = 0x1b64 + addr * 4;
1270
1271 if (addr == 3)
1272 coef = 0x04001fff;
1273 else
1274 coef = 0x00001fff;
1275 odm_set_bb_reg(dm, tmp_reg, MASKDWORD, coef);
1276 RF_DBG(dm, DBG_RF_DPK,
1277 "[DPK][Coef write] 0x%x = 0x%x\n", tmp_reg, coef);
1278 }
1279 }
1280
_dpk_fill_result_8822c(void * dm_void,u32 dpk_txagc,u8 path,u8 result)1281 void _dpk_fill_result_8822c(
1282 void *dm_void,
1283 u32 dpk_txagc,
1284 u8 path,
1285 u8 result)
1286 {
1287 struct dm_struct *dm = (struct dm_struct *)dm_void;
1288 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1289
1290 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
1291
1292 if (result) /*check PASS*/
1293 odm_write_1byte(dm, R_0x1b67, (u8)(dpk_txagc - 6)); /*ItQt -6dB*/
1294 else
1295 odm_write_1byte(dm, R_0x1b67, 0x00);
1296
1297 dpk_info->result[0] = dpk_info->result[0] | (result << path);
1298 dpk_info->dpk_txagc[path] = odm_read_1byte(dm, R_0x1b67);
1299
1300 RF_DBG(dm, DBG_RF_DPK,
1301 "[DPK] S%d 0x1b67 = 0x%x\n", path, odm_read_1byte(dm, R_0x1b67));
1302
1303 _dpk_coef_write_8822c(dm, path, result);
1304 }
1305
_dpk_gainloss_8822c(struct dm_struct * dm,u8 path)1306 u32 _dpk_gainloss_8822c(
1307 struct dm_struct *dm,
1308 u8 path)
1309 {
1310 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1311
1312 u8 k = 0, tx_agc_search = 0x0, t1 = 0, t2 = 0;
1313 u8 tx_agc, tx_bb, ori_txbb, ori_txagc;
1314 s8 txidx_offset = 0x0;
1315
1316 ori_txbb = (u8)_dpk_rf_setting_8822c(dm, path);
1317
1318 ori_txagc = (u8)odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, 0x0001f);
1319
1320 _dpk_rxbb_dc_cal_8822c(dm, path); /*DCK for DPK*/
1321
1322 _dpk_one_shot_8822c(dm, path, DAGC);
1323 _dpk_dgain_read_8822c(dm, path);
1324
1325 if (_dpk_dc_corr_check_8822c(dm, path)) {
1326 _dpk_rxbb_dc_cal_8822c(dm, path); /*re-do DCK for DPK*/
1327 _dpk_one_shot_8822c(dm, path, DAGC);
1328 _dpk_dc_corr_check_8822c(dm, path);
1329 }
1330
1331 t1 = _dpk_thermal_read_8822c(dm, path);
1332 #if 1
1333 tx_bb = _dpk_pas_agc_8822c(dm, path, false, true);
1334 #else
1335 _dpk_one_shot_8822c(dm, path, GAIN_LOSS);
1336 #endif
1337
1338 #if 0
1339 RF_DBG(dm, DBG_RF_DPK,
1340 "[DPK][GL] S%d RF_0x0=0x%x, 0x63=0x%x, 0x8a=0x%x, 0x1a=0x%x, 0x8f=0x%x\n",
1341 path, odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREG_MASK),
1342 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x63, RFREG_MASK),
1343 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8a, RFREG_MASK),
1344 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x1a, RFREG_MASK),
1345 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8f, RFREG_MASK));
1346 #endif
1347 tx_agc_search = _dpk_gainloss_result_8822c(dm, path);
1348
1349 if (tx_bb < tx_agc_search) /*aviod txbb < 0*/
1350 tx_bb = 0;
1351 else
1352 tx_bb = tx_bb - tx_agc_search;
1353
1354 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0x0001f, tx_bb);
1355
1356 tx_agc = ori_txagc - (ori_txbb - tx_bb);
1357
1358 RF_DBG(dm, DBG_RF_DPK, "[DPK][GL] S%d TXAGC=0x%x, TXBB=0x%x\n",
1359 path, tx_agc, tx_bb);
1360
1361 t2 = _dpk_thermal_read_8822c(dm, path);
1362
1363 dpk_info->thermal_dpk_delta[path] = HALRF_ABS(t2, t1);
1364
1365 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d thermal delta of GL = %d (%d - %d)\n",
1366 path, dpk_info->thermal_dpk_delta[path], t2, t1);
1367
1368 return tx_agc;
1369 }
1370
_dpk_by_path_8822c(struct dm_struct * dm,u32 tx_agc,u8 path)1371 u8 _dpk_by_path_8822c(
1372 struct dm_struct *dm,
1373 u32 tx_agc,
1374 u8 path)
1375 {
1376 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1377
1378 u8 result = 1;
1379 u16 dc_i, dc_q;
1380 #if 0
1381 tx_agc = (odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00,
1382 RFREG_MASK) & ~0x1f) | tx_agc;
1383 RF_DBG(dm, DBG_RF_DPK, "[DPK][DO_DPK] RF0x0 = 0x%x\n", tx_agc);
1384
1385 /*TXAGC for DPK*/
1386 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREG_MASK, tx_agc);
1387
1388 RF_DBG(dm, DBG_RF_DPK,
1389 "[DPK][GL] S%d RF 0x63=0x%x, 0x8a=0x%x, 0x1a=0x%x, 0x8f=0x%x\n",
1390 path, odm_get_rf_reg(dm, (enum rf_path)path, RF_0x63, RFREG_MASK),
1391 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8a, RFREG_MASK),
1392 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x1a, RFREG_MASK),
1393 odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8f, RFREG_MASK));
1394 #endif
1395 result = _dpk_one_shot_8822c(dm, path, DO_DPK);
1396
1397 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
1398
1399 result = result | (u8)odm_get_bb_reg(dm, R_0x1b08, BIT(26));
1400 RF_DBG(dm, DBG_RF_DPK, "[DPK][DO_DPK] DPK Fail = %x\n", result);
1401
1402 /*set RX high gain for RXBB DCK*/
1403 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREG_MASK, 0x33e14);
1404
1405 _dpk_get_coef_8822c(dm, path);
1406
1407 #if 0
1408 odm_write_4byte(dm, 0x1bd4, 0x000900F0);
1409 dc_i = (u16)odm_get_bb_reg(dm, 0x1bfc, 0x0fff0000);
1410 dc_q = (u16)odm_get_bb_reg(dm, 0x1bfc, 0x00000fff);
1411
1412 if (dc_i >> 11 == 1)
1413 dc_i = 0x1000 - dc_i;
1414 if (dc_q >> 11 == 1)
1415 dc_q = 0x1000 - dc_q;
1416
1417 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d DC i/q = %d / %d\n", path, dc_i, dc_q);
1418 #endif
1419 #if (DPK_PAS_DBG_8822C)
1420 _dpk_pas_read_8822c(dm, path, PAS_READ);
1421 #endif
1422 return result;
1423 }
1424
_dpk_cal_gs_8822c(struct dm_struct * dm,u8 path)1425 void _dpk_cal_gs_8822c(
1426 struct dm_struct *dm,
1427 u8 path)
1428 {
1429 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1430
1431 u16 tmp_gs = 0;
1432
1433 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
1434
1435 odm_set_bb_reg(dm, R_0x1b20, BIT(25), 0x0); /*BypassDPD=0*/
1436 odm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x0); /* disable CFIR to TX*/
1437 odm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x9); /* ItQt shift 1 bit*/
1438 odm_set_bb_reg(dm, R_0x1bcc, BIT(21), 0x1); /* inner loopback*/
1439
1440 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);
1441 odm_set_bb_reg(dm, R_0x1bd4, 0x000000f0, 0xf);
1442
1443 if (path == RF_PATH_A) {
1444 /*manual pwsf+gs*/
1445 odm_set_bb_reg(dm, R_0x1b04, 0x0fffffff, 0x1066680);
1446 /*enable MDPD*/
1447 odm_set_bb_reg(dm, R_0x1b08, BIT(31), 0x1);
1448 } else {
1449 odm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff, 0x1066680);
1450 odm_set_bb_reg(dm, R_0x1b60, BIT(31), 0x1);
1451 }
1452
1453 if (dpk_info->dpk_bw == 0x1) { /*80M*/
1454 /*TPG DC*/
1455 odm_write_4byte(dm, R_0x1bf8, 0x80001310);
1456 odm_write_4byte(dm, R_0x1bf8, 0x00001310);
1457 odm_write_4byte(dm, R_0x1bf8, 0x810000DB);
1458 odm_write_4byte(dm, R_0x1bf8, 0x010000DB);
1459 odm_write_4byte(dm, R_0x1bf8, 0x0000B428);
1460 /*set TPG*/
1461 odm_write_4byte(dm, R_0x1bf4, 0x05020000 | (BIT(path) << 28));
1462 } else {
1463 odm_write_4byte(dm, R_0x1bf8, 0x8200190C);
1464 odm_write_4byte(dm, R_0x1bf8, 0x0200190C);
1465 odm_write_4byte(dm, R_0x1bf8, 0x8301EE14);
1466 odm_write_4byte(dm, R_0x1bf8, 0x0301EE14);
1467 odm_write_4byte(dm, R_0x1bf8, 0x0000B428);
1468 odm_write_4byte(dm, R_0x1bf4, 0x05020008 | (BIT(path) << 28));
1469 }
1470
1471 odm_set_bb_reg(dm, R_0x1bb4, 0xff000000, 0x8 | path);
1472
1473 _dpk_one_shot_8822c(dm, path, 0);
1474
1475 /*restore*/
1476 odm_set_bb_reg(dm, R_0x1bf4, 0xff000000, 0x0); /*TPG off*/
1477 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
1478 odm_set_bb_reg(dm, R_0x1bcc, 0xc000003f, 0x0); /* ItQt*/
1479 odm_set_bb_reg(dm, R_0x1bcc, BIT(21), 0x0); /* inner loopback off*/
1480
1481 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);
1482
1483 if (path == RF_PATH_A)
1484 odm_set_bb_reg(dm, R_0x1b04, 0x0fffffff, 0x5b);
1485 else
1486 odm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff, 0x5b);
1487
1488 odm_set_bb_reg(dm, R_0x1bd4, 0x001f0000, 0x0);
1489
1490 tmp_gs = (u16)odm_get_bb_reg(dm, R_0x1bfc, 0x0FFF0000);
1491 #if 0
1492 RF_DBG(dm, DBG_RF_DPK, "[DPK] tmp_gs = 0x%x\n", tmp_gs);
1493 #endif
1494 tmp_gs = (tmp_gs * 910) >> 10; /*910 = 0x5b * 10*/
1495
1496 if ((tmp_gs % 10) >= 5)
1497 tmp_gs = tmp_gs / 10 + 1;
1498 else
1499 tmp_gs = tmp_gs / 10;
1500
1501 if (path == RF_PATH_A)
1502 odm_set_bb_reg(dm, R_0x1b04, 0x0fffffff, tmp_gs);
1503 else
1504 odm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff, tmp_gs);
1505
1506 dpk_info->dpk_gs[path] = tmp_gs;
1507
1508 }
1509
_dpk_cal_coef1_8822c(struct dm_struct * dm)1510 void _dpk_cal_coef1_8822c(
1511 struct dm_struct *dm)
1512 {
1513 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1514
1515 u8 reg_2d9c, path;
1516 u16 count = 0;
1517 u32 i_scaling;
1518
1519 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x0000000c);
1520 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x000000F0); /*force comp clk on*/
1521
1522 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x00001148);
1523 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x00001149);
1524
1525 reg_2d9c = odm_read_1byte(dm, R_0x2d9c);
1526 while (reg_2d9c != 0x55 && count < 1000) {
1527 ODM_delay_us(20);
1528 reg_2d9c = odm_read_1byte(dm, R_0x2d9c);
1529 count++;
1530 }
1531
1532 RF_DBG(dm, DBG_RF_DPK, "[DPK] one-shot for Cal_coef1 (count=%d)\n", count);
1533
1534 odm_write_1byte(dm, 0x1b10, 0x0);
1535
1536 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x0000000c);
1537
1538 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
1539
1540 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; /*0x16c00 = 0x400 * 0x5b*/
1541
1542 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d i_scaling = 0x%x\n", path, i_scaling);
1543
1544 /*write 4th I value*/
1545 odm_set_bb_reg(dm, 0x1b18 + path * 0x58, MASKHWORD, i_scaling);
1546
1547 /*load coef to coef1*/
1548 odm_set_bb_reg(dm, 0x1b04 + path * 0x58, 0xf0000000, 0x9);
1549 odm_set_bb_reg(dm, 0x1b04 + path * 0x58, 0xf0000000, 0x1);
1550 odm_set_bb_reg(dm, 0x1b04 + path * 0x58, 0xf0000000, 0x0);
1551
1552 /*enable 2nd coef*/
1553 odm_set_bb_reg(dm, 0x1b08 + path * 0x58, BIT(14), 0x0); /*0:enable; 1:bypass*/
1554
1555 #if DPK_COEF_DBG_8822C
1556 _dpk_coef1_read_8822c(dm, path);
1557 #endif
1558
1559 }
1560 }
1561
_dpk_on_8822c(struct dm_struct * dm,u8 path)1562 void _dpk_on_8822c(
1563 struct dm_struct *dm,
1564 u8 path)
1565 {
1566 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1567
1568 _dpk_one_shot_8822c(dm, path, DPK_ON);
1569
1570 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
1571 odm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x0); /* disable CFIR to TX*/
1572
1573 if ((dpk_info->dpk_path_ok & BIT(path)) >> path)
1574 _dpk_cal_gs_8822c(dm, path);
1575
1576 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d DPD on!!!\n\n", path);
1577 }
1578
dpk_coef_read_8822c(void * dm_void)1579 void dpk_coef_read_8822c(
1580 void *dm_void)
1581 {
1582 struct dm_struct *dm = (struct dm_struct *)dm_void;
1583 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1584
1585 u8 path, addr;
1586
1587 RF_DBG(dm, DBG_RF_DPK, "[DPK] ========= Coef Read Start =========\n");
1588
1589 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
1590 for (addr = 0; addr < 20; addr++)
1591 RF_DBG(dm, DBG_RF_DPK,
1592 "[DPK] Read S%d coef[%02d]= 0x%08x\n",
1593 path, addr, dpk_info->coef[path][addr]);
1594 }
1595 RF_DBG(dm, DBG_RF_DPK, "[DPK] ========= Coef Read Finish =========\n");
1596 }
1597
_dpk_check_fail_8822c(struct dm_struct * dm,boolean is_fail,u32 dpk_txagc,u8 path)1598 u8 _dpk_check_fail_8822c(
1599 struct dm_struct *dm,
1600 boolean is_fail,
1601 u32 dpk_txagc,
1602 u8 path)
1603 {
1604 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1605
1606 u8 result;
1607
1608 if (!is_fail)
1609 if (_dpk_coef_read_8822c(dm, path))
1610 result = 1; /*check PASS*/
1611 else
1612 result = 0; /*check FAIL*/
1613 else
1614 result = 0; /*check FAIL*/
1615
1616 _dpk_fill_result_8822c(dm, dpk_txagc, path, result);
1617 return result;
1618 }
1619
_dpk_result_reset_8822c(struct dm_struct * dm)1620 void _dpk_result_reset_8822c(
1621 struct dm_struct *dm)
1622 {
1623 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1624
1625 u8 path;
1626
1627 dpk_info->dpk_path_ok = 0x0;
1628 dpk_info->dpk_status = 0x0;
1629 dpk_info->result[0] = 0x0;
1630
1631 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
1632
1633 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
1634 odm_set_bb_reg(dm, R_0x1b58, 0x0000007f, 0x0);
1635
1636 dpk_info->dpk_txagc[path] = 0;
1637 dpk_info->dpk_gs[path] = 0x5b;
1638 dpk_info->pre_pwsf[path] = 0;
1639
1640 dpk_info->thermal_dpk[path] = _dpk_thermal_read_8822c(dm, path);
1641
1642 RF_DBG(dm, DBG_RF_DPK, "[DPK] init thermal S%d = %d\n", path,
1643 dpk_info->thermal_dpk[path]);
1644 }
1645 }
1646
_dpk_calibrate_8822c(struct dm_struct * dm,u8 path)1647 void _dpk_calibrate_8822c(
1648 struct dm_struct *dm,
1649 u8 path)
1650 {
1651 u8 dpk_fail = 1, retry_cnt;
1652 u32 dpk_txagc = 0;
1653
1654 RF_DBG(dm, DBG_RF_DPK,
1655 "[DPK] =========== S%d DPK Start ===========\n", path);
1656
1657 for (retry_cnt = 0; retry_cnt < 1; retry_cnt++) {
1658
1659 RF_DBG(dm, DBG_RF_DPK, "[DPK] retry = %d\n", retry_cnt);
1660
1661 dpk_txagc = _dpk_gainloss_8822c(dm, path);
1662
1663 dpk_fail = _dpk_by_path_8822c(dm, dpk_txagc, path);
1664
1665 if (_dpk_check_fail_8822c(dm, dpk_fail, dpk_txagc, path))
1666 break;
1667 }
1668
1669 RF_DBG(dm, DBG_RF_DPK,
1670 "[DPK] =========== S%d DPK Finish ==========\n", path);
1671 }
1672
_dpk_path_select_8822c(struct dm_struct * dm)1673 void _dpk_path_select_8822c(
1674 struct dm_struct *dm)
1675 {
1676 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1677
1678 dpk_info->dpk_status = dpk_info->dpk_status | BIT(1);
1679
1680 #if (DPK_PATH_A_8822C)
1681 _dpk_calibrate_8822c(dm, RF_PATH_A);
1682 #endif
1683
1684 #if (DPK_PATH_B_8822C)
1685 _dpk_calibrate_8822c(dm, RF_PATH_B);
1686 #endif
1687 dpk_info->dpk_path_ok = dpk_info->result[0];
1688
1689 _dpk_on_8822c(dm, RF_PATH_A);
1690 _dpk_on_8822c(dm, RF_PATH_B);
1691
1692 _dpk_cal_coef1_8822c(dm);
1693
1694 if (dpk_info->result[0] == 0x3)
1695 dpk_info->dpk_status = dpk_info->dpk_status | BIT(2);
1696
1697 }
1698
_dpk_count_8822c(void * dm_void)1699 void _dpk_count_8822c(
1700 void *dm_void)
1701 {
1702 struct dm_struct *dm = (struct dm_struct *)dm_void;
1703 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1704
1705 dpk_info->dpk_cal_cnt += (dpk_info->dpk_status & BIT(1)) >> 1;
1706 dpk_info->dpk_ok_cnt += (dpk_info->dpk_status & BIT(2)) >> 2;
1707 dpk_info->dpk_reload_cnt += dpk_info->dpk_status & BIT(0);
1708
1709 RF_DBG(dm, DBG_RF_DPK, "[DPK] Cal / OK / Reload = %d / %d / %d\n",
1710 dpk_info->dpk_cal_cnt, dpk_info->dpk_ok_cnt, dpk_info->dpk_reload_cnt);
1711 }
1712
_dpk_result_summary_8822c(struct dm_struct * dm)1713 void _dpk_result_summary_8822c(
1714 struct dm_struct *dm)
1715 {
1716 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1717
1718 u8 path;
1719
1720 RF_DBG(dm, DBG_RF_DPK, "[DPK] ======== DPK Result Summary =======\n");
1721
1722 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
1723
1724 RF_DBG(dm, DBG_RF_DPK,
1725 "[DPK] S%d dpk_txagc = 0x%x, gain scaling = 0x%x\n",
1726 path, dpk_info->dpk_txagc[path], dpk_info->dpk_gs[path]);
1727
1728 RF_DBG(dm, DBG_RF_DPK, "[DPK] S%d DPK is %s\n", path,
1729 ((dpk_info->dpk_path_ok & BIT(path)) >> path) ?
1730 "Success" : "Fail");
1731 }
1732
1733 RF_DBG(dm, DBG_RF_DPK, "[DPK] dpk_path_ok = 0x%x\n",
1734 dpk_info->dpk_path_ok);
1735 RF_DBG(dm, DBG_RF_DPK, "[DPK] ======== DPK Result Summary =======\n");
1736
1737 }
1738
_dpk_reload_index_8822c(struct dm_struct * dm)1739 u8 _dpk_reload_index_8822c(
1740 struct dm_struct *dm)
1741 {
1742 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1743
1744 u32 reg_rf18;
1745 u8 i = 99;
1746
1747 reg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);
1748
1749 if (reg_rf18 == dpk_info->dpk_rf18[0])
1750 i = 0;
1751 else if (reg_rf18 == dpk_info->dpk_rf18[1])
1752 i = 1;
1753
1754 if (i != 99) {
1755 dpk_info->dpk_path_ok = dpk_info->result[i];
1756 dpk_info->dpk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/
1757 dpk_info->dpk_ch = (u8)(reg_rf18 & 0xff);
1758 dpk_info->dpk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/
1759 }
1760
1761 #if 1
1762 RF_DBG(dm, DBG_RF_DPK, "[DPK] Current RF0x18 = 0x%x, reload idx = %d\n",
1763 reg_rf18, i);
1764 #endif
1765 return i;
1766 }
1767
_dpk_reload_data_8822c(void * dm_void,u8 reload_idx)1768 void _dpk_reload_data_8822c(
1769 void *dm_void,
1770 u8 reload_idx)
1771 {
1772 struct dm_struct *dm = (struct dm_struct *)dm_void;
1773 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1774
1775 u8 path;
1776
1777 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
1778
1779 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
1780 if (dpk_info->dpk_band == 0x0) /*txagc bnd*/
1781 odm_set_bb_reg(dm, R_0x1b60, MASKDWORD, 0x1f100000);
1782 else
1783 odm_set_bb_reg(dm, R_0x1b60, MASKDWORD, 0x1f0d0000);
1784
1785 odm_write_1byte(dm, R_0x1b67, dpk_info->dpk_txagc[path]);
1786
1787 _dpk_coef_write_8822c(dm, path, (dpk_info->dpk_path_ok & BIT(path)) >> path);
1788
1789 _dpk_one_shot_8822c(dm, path, DPK_ON);
1790
1791 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);
1792
1793 if (path == RF_PATH_A)
1794 odm_set_bb_reg(dm, R_0x1b04, 0x0fffffff, dpk_info->dpk_gs[0]);
1795 else
1796 odm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff, dpk_info->dpk_gs[1]);
1797 }
1798
1799 _dpk_cal_coef1_8822c(dm);
1800 }
1801
dpk_reload_8822c(void * dm_void)1802 u8 dpk_reload_8822c(
1803 void *dm_void)
1804 {
1805 struct dm_struct *dm = (struct dm_struct *)dm_void;
1806 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1807
1808 u8 i;
1809
1810 dpk_info->dpk_status = 0x0;
1811
1812 if (dpk_info->dpk_rf18[0] == 0)
1813 return false; /*never do DPK before*/
1814
1815 i = _dpk_reload_index_8822c(dm);
1816
1817 if (i != 99) {
1818 RF_DBG(dm, DBG_RF_DPK, "[DPK] DPK reload for RF0x18 0x%x!!\n", dpk_info->dpk_rf18[i]);
1819 _dpk_reload_data_8822c(dm, i);
1820 dpk_info->dpk_status = dpk_info->dpk_status | BIT(0);
1821 }
1822
1823 return dpk_info->dpk_status;
1824 }
1825
_dpk_by_fw_8822c(struct dm_struct * dm)1826 void _dpk_by_fw_8822c(
1827 struct dm_struct *dm)
1828 {
1829 enum hal_status status = HAL_STATUS_FAILURE;
1830
1831 RF_DBG(dm, DBG_RF_DPK, "[DPK] DPK by FW !!\n");
1832
1833 RF_DBG(dm, DBG_RF_DPK, "[DPK] FW Ver (Sub_Ver) = %d (%d)\n",
1834 dm->fw_version, dm->fw_sub_version);
1835
1836 status = odm_dpk_by_fw(dm);
1837
1838 if (status == HAL_STATUS_SUCCESS)
1839 RF_DBG(dm, DBG_RF_DPK, "[DPK] FW DPK Trigger OK!!!\n");
1840 else
1841 RF_DBG(dm, DBG_RF_DPK, "[DPK] FW DPK Trigger Fail!!!\n");
1842 }
1843
_dpk_force_bypass_8822c(void * dm_void)1844 void _dpk_force_bypass_8822c(
1845 void *dm_void)
1846 {
1847 struct dm_struct *dm = (struct dm_struct *)dm_void;
1848
1849 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc); /*subpage 2*/
1850
1851 odm_set_bb_reg(dm, R_0x1b08, BIT(15) | BIT(14), 0x3);
1852 odm_set_bb_reg(dm, R_0x1b04, 0x000000ff, 0x5b);
1853 RF_DBG(dm, DBG_RF_DPK, "[DPK] S0 DPK bypass !!!\n");
1854
1855 odm_set_bb_reg(dm, R_0x1b60, BIT(15) | BIT(14), 0x3);
1856 odm_set_bb_reg(dm, R_0x1b5c, 0x000000ff, 0x5b);
1857 RF_DBG(dm, DBG_RF_DPK, "[DPK] S1 DPK bypass !!!\n");
1858 }
1859
_rx_dc_cal_8822c(struct dm_struct * dm)1860 void _rx_dc_cal_8822c(
1861 struct dm_struct *dm)
1862 {
1863 u32 bb_reg_backup[7];
1864 u32 bb_reg[7] = {
1865 R_0x520, R_0x1d58, R_0x180c, R_0x410c, R_0x1a14,
1866 R_0x1e70, R_0x1d70};
1867 u8 path;
1868
1869 _backup_mac_bb_registers_8822c(dm, bb_reg, bb_reg_backup, 7);
1870
1871 _dpk_tx_pause_8822c(dm);
1872
1873 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); /*BB CCA off*/
1874 odm_set_bb_reg(dm, R_0x180c, BIT(1) | BIT(0), 0x0);
1875 odm_set_bb_reg(dm, R_0x410c, BIT(1) | BIT(0), 0x0);
1876 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3); /*CCK RXIQ weighting=0*/
1877
1878 for (path = 0; path < 2; path++) {
1879 /*set RX high gain for RXBB DCK*/
1880 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREG_MASK, 0x33e14);
1881 _dpk_rxbb_dc_cal_8822c(dm, path); /*DCK for DPK*/
1882 }
1883
1884 _reload_mac_bb_registers_8822c(dm, bb_reg, bb_reg_backup, 7);
1885 }
1886
do_dpk_8822c(void * dm_void)1887 void do_dpk_8822c(
1888 void *dm_void)
1889 {
1890 struct dm_struct *dm = (struct dm_struct *)dm_void;
1891 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1892 struct _hal_rf_ *rf = &dm->rf_table;
1893
1894 u32 bb_reg_backup[DPK_BB_REG_NUM_8822C];
1895 u32 rf_reg_backup[DPK_RF_REG_NUM_8822C][DPK_RF_PATH_NUM_8822C];
1896
1897 u32 bb_reg[DPK_BB_REG_NUM_8822C] = {
1898 R_0x520, R_0x820, R_0x824, R_0x1c3c, R_0x1d58,
1899 R_0x1864, R_0x4164, R_0x180c, R_0x410c, R_0x186c,
1900 R_0x416c, R_0x1a14, R_0x1e70, R_0x80c, R_0x1d70,
1901 R_0x1e7c, R_0x18a4, R_0x41a4};
1902 u32 rf_reg[DPK_RF_REG_NUM_8822C] = {
1903 RF_0x19, RF_0x1a, RF_0x55, RF_0x63, RF_0x87,
1904 RF_0x8f, RF_0xde};
1905
1906 if (rf->ext_pa && (*dm->band_type == ODM_BAND_2_4G)) {
1907 RF_DBG(dm, DBG_RF_DPK, "[DPK] Skip DPK due to ext_PA exist!!\n");
1908 _dpk_force_bypass_8822c(dm);
1909 _rx_dc_cal_8822c(dm);
1910 return;
1911 } else if (rf->ext_pa_5g && (*dm->band_type == ODM_BAND_5G)) {
1912 RF_DBG(dm, DBG_RF_DPK, "[DPK] Skip DPK due to 5G_ext_PA exist!!\n");
1913 _dpk_force_bypass_8822c(dm);
1914 _rx_dc_cal_8822c(dm);
1915 return;
1916 } else if (!dpk_info->is_dpk_pwr_on) {
1917 RF_DBG(dm, DBG_RF_DPK, "[DPK] Skip DPK due to DPD PWR off !!\n");
1918 return;
1919 } else if (!(*dm->mp_mode) && (dm->fw_offload_ability & PHYDM_RF_DPK_OFFLOAD)) {
1920 _dpk_by_fw_8822c(dm);
1921 return;
1922 } else if (!(*dm->mp_mode) && dpk_reload_8822c(dm)) {
1923 _dpk_count_8822c(dm);
1924 return;
1925 }
1926
1927 RF_DBG(dm, DBG_RF_DPK,
1928 "[DPK] ****** DPK Start (Ver: %s), Cv: %d ******\n",
1929 DPK_VER_8822C, dm->cut_version);
1930
1931 _dpk_information_8822c(dm);
1932
1933 _backup_mac_bb_registers_8822c(dm, bb_reg, bb_reg_backup,
1934 DPK_BB_REG_NUM_8822C);
1935
1936 _backup_rf_registers_8822c(dm, rf_reg, rf_reg_backup);
1937
1938 _dpk_mac_bb_setting_8822c(dm);
1939 _dpk_afe_setting_8822c(dm, true);
1940 _dpk_manual_txagc_8822c(dm, true);
1941 _dpk_pre_setting_8822c(dm);
1942
1943 _dpk_result_reset_8822c(dm);
1944 _dpk_path_select_8822c(dm);
1945 _dpk_result_summary_8822c(dm);
1946 _dpk_count_8822c(dm);
1947
1948 _dpk_manual_txagc_8822c(dm, false);
1949 _dpk_afe_setting_8822c(dm, false);
1950
1951 dpk_enable_disable_8822c(dm);
1952
1953 _reload_rf_registers_8822c(dm, rf_reg, rf_reg_backup);
1954
1955 halrf_rxbb_dc_cal_8822c(dm); /*DCK for Rx*/
1956
1957 _reload_mac_bb_registers_8822c(dm, bb_reg, bb_reg_backup,
1958 DPK_BB_REG_NUM_8822C);
1959 }
1960
dpk_enable_disable_8822c(void * dm_void)1961 void dpk_enable_disable_8822c(
1962 void *dm_void)
1963 {
1964 struct dm_struct *dm = (struct dm_struct *)dm_void;
1965 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1966
1967 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc); /*subpage 2*/
1968
1969 odm_set_bb_reg(dm, R_0x1b08, BIT(31), dpk_info->is_dpk_pwr_on);
1970 odm_set_bb_reg(dm, R_0x1b60, BIT(31), dpk_info->is_dpk_pwr_on);
1971
1972 if (dpk_info->is_dpk_enable) {
1973 if (dpk_info->dpk_path_ok & BIT(0)) {
1974 odm_set_bb_reg(dm, R_0x1b08, BIT(15) | BIT(14), 0x0);
1975 odm_set_bb_reg(dm, R_0x1b04, 0x000000ff,
1976 dpk_info->dpk_gs[RF_PATH_A]);
1977 RF_DBG(dm, DBG_RF_DPK, "[DPK] S0 DPK enable !!!\n");
1978 }
1979 if ((dpk_info->dpk_path_ok & BIT(1)) >> 1) {
1980 odm_set_bb_reg(dm, R_0x1b60, BIT(15) | BIT(14), 0x0);
1981 odm_set_bb_reg(dm, R_0x1b5c, 0x000000ff,
1982 dpk_info->dpk_gs[RF_PATH_B]);
1983 RF_DBG(dm, DBG_RF_DPK, "[DPK] S1 DPK enable !!!\n");
1984 }
1985 } else {
1986 if (dpk_info->dpk_path_ok & BIT(0)) {
1987 odm_set_bb_reg(dm, R_0x1b08, BIT(15) | BIT(14), 0x3);
1988 odm_set_bb_reg(dm, R_0x1b04, 0x000000ff, 0x5b);
1989 RF_DBG(dm, DBG_RF_DPK, "[DPK] S0 DPK bypass !!!\n");
1990 }
1991 if ((dpk_info->dpk_path_ok & BIT(1)) >> 1) {
1992 odm_set_bb_reg(dm, R_0x1b60, BIT(15) | BIT(14), 0x3);
1993 odm_set_bb_reg(dm, R_0x1b5c, 0x000000ff, 0x5b);
1994 RF_DBG(dm, DBG_RF_DPK, "[DPK] S1 DPK bypass !!!\n");
1995 }
1996 }
1997 }
1998
dpk_track_8822c(void * dm_void)1999 void dpk_track_8822c(
2000 void *dm_void)
2001 {
2002 struct dm_struct *dm = (struct dm_struct *)dm_void;
2003 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2004 struct _hal_rf_ *rf = &dm->rf_table;
2005
2006 u8 is_increase, i = 0, k = 0, path;
2007 u8 thermal_dpk_avg_count = 0, thermal_value[2] = {0};
2008 u32 thermal_dpk_avg[2] = {0};
2009 s8 offset[2], delta_dpk[2];
2010
2011 if ((dpk_info->thermal_dpk[0] == 0) && (dpk_info->thermal_dpk[1] == 0)) {
2012 RF_DBG(dm, DBG_RF_DPK_TRACK, "[DPK_track] Bypass DPK tracking!!!!\n");
2013 return;
2014 } else
2015 RF_DBG(dm, DBG_RF_DPK_TRACK,
2016 "[DPK_track] ================[CH %d]================\n",
2017 dpk_info->dpk_ch);
2018
2019 /*get thermal meter*/
2020 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
2021 thermal_value[path] = _dpk_thermal_read_8822c(dm, path);
2022
2023 RF_DBG(dm, DBG_RF_DPK_TRACK,
2024 "[DPK_track] S%d thermal now = %d\n", path, thermal_value[path]);
2025 }
2026
2027 dpk_info->thermal_dpk_avg[0][dpk_info->thermal_dpk_avg_index] =
2028 thermal_value[0];
2029 dpk_info->thermal_dpk_avg[1][dpk_info->thermal_dpk_avg_index] =
2030 thermal_value[1];
2031 dpk_info->thermal_dpk_avg_index++;
2032
2033 /*Average times */
2034 if (dpk_info->thermal_dpk_avg_index == THERMAL_DPK_AVG_NUM)
2035 dpk_info->thermal_dpk_avg_index = 0;
2036
2037 for (i = 0; i < THERMAL_DPK_AVG_NUM; i++) {
2038 if (dpk_info->thermal_dpk_avg[0][i] ||
2039 dpk_info->thermal_dpk_avg[1][i]) {
2040 thermal_dpk_avg[0] += dpk_info->thermal_dpk_avg[0][i];
2041 thermal_dpk_avg[1] += dpk_info->thermal_dpk_avg[1][i];
2042 thermal_dpk_avg_count++;
2043 }
2044 }
2045
2046 /*Calculate Average ThermalValue after average enough times*/
2047 if (thermal_dpk_avg_count) {
2048 #if 0
2049 RF_DBG(dm, DBG_RF_DPK,
2050 "[DPK_track] S0 ThermalValue_DPK_AVG (count) = %d (%d))\n",
2051 thermal_dpk_avg[0], thermal_dpk_avg_count);
2052
2053 RF_DBG(dm, DBG_RF_DPK,
2054 "[DPK_track] S1 ThermalValue_DPK_AVG (count) = %d (%d))\n",
2055 thermal_dpk_avg[1], thermal_dpk_avg_count);
2056 #endif
2057 thermal_value[0] = (u8)(thermal_dpk_avg[0] / thermal_dpk_avg_count);
2058 thermal_value[1] = (u8)(thermal_dpk_avg[1] / thermal_dpk_avg_count);
2059
2060 RF_DBG(dm, DBG_RF_DPK_TRACK,
2061 "[DPK_track] S0 thermal avg = %d (DPK @ %d)\n",
2062 thermal_value[0], dpk_info->thermal_dpk[0]);
2063
2064 RF_DBG(dm, DBG_RF_DPK_TRACK,
2065 "[DPK_track] S1 thermal avg = %d (DPK @ %d)\n",
2066 thermal_value[1], dpk_info->thermal_dpk[1]);
2067 }
2068
2069 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
2070 delta_dpk[path] = dpk_info->thermal_dpk[path] - thermal_value[path];
2071
2072 offset[path] = (delta_dpk[path] - dpk_info->thermal_dpk_delta[path]) & 0x7f;
2073
2074 RF_DBG(dm, DBG_RF_DPK_TRACK,
2075 "[DPK_track] S%d thermal_diff= %d, cal_diff= %d, offset= %d\n",
2076 path, delta_dpk[path], dpk_info->thermal_dpk_delta[path],
2077 offset[path] > 64 ? offset[path] - 128 : offset[path]);
2078 }
2079
2080 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
2081 rf->is_tssi_in_progress || rf->is_txgapk_in_progress ||
2082 !(rf->rf_supportability & HAL_RF_DPK_TRACK))
2083 return;
2084
2085 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2086 if (*dm->is_fcs_mode_enable)
2087 return;
2088 #endif
2089
2090 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
2091 if (offset[path] != dpk_info->pre_pwsf[path]) {
2092 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));
2093 odm_set_bb_reg(dm, R_0x1b58, 0x0000007f, offset[path]);
2094 dpk_info->pre_pwsf[path] = offset[path];
2095 RF_DBG(dm, DBG_RF_DPK_TRACK,
2096 "[DPK_track] S%d new pwsf is 0x%x, 0x1b58=0x%x\n",
2097 path, dpk_info->pre_pwsf[path],
2098 odm_get_bb_reg(dm, R_0x1b58, MASKDWORD));
2099 } else
2100 RF_DBG(dm, DBG_RF_DPK_TRACK,
2101 "[DPK_track] S%d pwsf unchanged (0x%x)\n",
2102 path, dpk_info->pre_pwsf[path]);
2103 }
2104 }
2105
dpk_info_by_8822c(void * dm_void,u32 * _used,char * output,u32 * _out_len)2106 void dpk_info_by_8822c(
2107 void *dm_void,
2108 u32 *_used,
2109 char *output,
2110 u32 *_out_len)
2111 {
2112 struct dm_struct *dm = (struct dm_struct *)dm_void;
2113 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2114
2115 u32 used = *_used;
2116 u32 out_len = *_out_len;
2117 u8 path, addr;
2118
2119 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
2120 "S0 DC (I/Q)", dpk_info->dc_i[0], dpk_info->dc_q[0]);
2121
2122 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
2123 "S0 Corr (idx/val)", dpk_info->corr_idx[0], dpk_info->corr_val[0]);
2124
2125 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
2126 "S1 DC (I/Q)", dpk_info->dc_i[1], dpk_info->dc_q[1]);
2127
2128 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
2129 "S1 Corr (idx/val)", dpk_info->corr_idx[1], dpk_info->corr_val[1]);
2130
2131 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x\n",
2132 "DPK TxAGC (path)", dpk_info->dpk_txagc[0], dpk_info->dpk_txagc[1]);
2133
2134 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x\n",
2135 "DPK Gain Scaling (path)", dpk_info->dpk_gs[0], dpk_info->dpk_gs[1]);
2136
2137 PDM_SNPF(out_len, used, output + used, out_len - used,
2138 "\n==============[ Coef Read Start ]==============\n");
2139
2140 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
2141 for (addr = 0; addr < 20; addr++)
2142 PDM_SNPF(out_len, used, output + used, out_len - used, " Read S%d coef[%02d] = 0x%08x\n",
2143 path, addr, dpk_info->coef[path][addr]);
2144 }
2145
2146 PDM_SNPF(out_len, used, output + used, out_len - used,
2147 "==============[ Coef Read Finish ]==============\n");
2148 }
2149
dpk_info_rsvd_page_8822c(void * dm_void,u8 * buf,u32 * buf_size)2150 void dpk_info_rsvd_page_8822c(
2151 void *dm_void,
2152 u8 *buf,
2153 u32 *buf_size)
2154 {
2155 struct dm_struct *dm = (struct dm_struct *)dm_void;
2156 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2157
2158 if (buf) {
2159 odm_move_memory(dm, buf, &(dpk_info->dpk_path_ok), 2);
2160 odm_move_memory(dm, buf + 2, dpk_info->dpk_txagc, 2);
2161 odm_move_memory(dm, buf + 4, dpk_info->dpk_gs, 4);
2162 odm_move_memory(dm, buf + 8, dpk_info->coef, 160);
2163 odm_move_memory(dm, buf + 168, &(dpk_info->dpk_ch), 1);
2164 odm_move_memory(dm, buf + 169, dpk_info->result, 2);
2165 odm_move_memory(dm, buf + 171, dpk_info->dpk_rf18, 8);
2166 }
2167
2168 if (buf_size)
2169 *buf_size = DPK_INFO_RSVD_LEN_8822C;
2170 }
2171
dpk_c2h_report_transfer_8822c(void * dm_void,boolean is_ok,u8 * buf,u8 buf_size)2172 void dpk_c2h_report_transfer_8822c(
2173 void *dm_void,
2174 boolean is_ok,
2175 u8 *buf,
2176 u8 buf_size)
2177 {
2178 struct dm_struct *dm = (struct dm_struct *)dm_void;
2179 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2180 struct dm_dpk_c2h_report dpk_c2h_report;
2181
2182 u8 i, j, idx;
2183 u8 path_status = 0;
2184
2185 if (!is_ok) {
2186 RF_DBG(dm, DBG_RF_DPK, "[DPK] FW DPK C2H data fail!!!\n");
2187 return;
2188 } else if (buf_size < DPK_C2H_REPORT_LEN_8822C) {
2189 RF_DBG(dm, DBG_RF_DPK, "[DPK] FW DPK: error buf size(%d)!!!\n", buf_size);
2190 return;
2191 } else if (!(dm->fw_offload_ability & PHYDM_RF_DPK_OFFLOAD)) {
2192 RF_DBG(dm, DBG_RF_DPK,
2193 "[DPK] Skip FW DPK transfer (DPK OFFLOAD not support)\n");
2194 return;
2195 }
2196
2197 RF_DBG(dm, DBG_RF_DPK, "[DPK] FW DPK data transfer start!!\n");
2198
2199 /*copy C2H data to struct dpk_c2h_report*/
2200 for (i = 0; i < 2; i++) {
2201 odm_move_memory(dm, &(dpk_c2h_report.result[i]), buf + i, 1);
2202
2203 for (j = 0; j < DPK_RF_PATH_NUM_8822C; j++) {
2204 odm_move_memory(dm, &(dpk_c2h_report.therm[i][j]),
2205 buf + 2 + i * 2 + j, 1);
2206 odm_move_memory(dm, &(dpk_c2h_report.therm_delta[i][j]),
2207 buf + 6 + i * 2 + j, 1);
2208 }
2209
2210 odm_move_memory(dm, &(dpk_c2h_report.dpk_rf18[i]), buf + 10 + i * 4, 4);
2211 }
2212 odm_move_memory(dm, &dpk_c2h_report.dpk_status, buf + 18, 1);
2213
2214 /*check abnormal*/
2215 if (dpk_c2h_report.dpk_rf18[0] == 0x0) {
2216 RF_DBG(dm, DBG_RF_DPK, "[DPK] Check C2H RF0x18 data fail!!!\n");
2217 return;
2218 }
2219
2220 /*copy struct dpk_c2h_report to struct dpk_info*/
2221 dpk_info->dpk_status = dpk_c2h_report.dpk_status;
2222
2223 _dpk_count_8822c(dm);
2224
2225 for (i = 0; i < 2; i++) {
2226 dpk_info->dpk_rf18[i] = dpk_c2h_report.dpk_rf18[i];
2227 dpk_info->result[i] = dpk_c2h_report.result[i];
2228 }
2229
2230 idx = _dpk_reload_index_8822c(dm);
2231
2232 for (i = 0; i < DPK_RF_PATH_NUM_8822C; i++) {
2233 dpk_info->thermal_dpk[i] = dpk_c2h_report.therm[idx][i];
2234 dpk_info->thermal_dpk_delta[i] = dpk_c2h_report.therm_delta[idx][i];
2235 }
2236 #if 0
2237 for (i = 0; i < DPK_C2H_REPORT_LEN_8822C; i++)
2238 RF_DBG(dm, DBG_RF_DPK, "[DPK] buf[%d] = 0x%x\n", i, *(buf + i));
2239
2240 RF_DBG(dm, DBG_RF_DPK, "[DPK] result[0] = 0x%x\n", dpk_c2h_report.result[0]);
2241 RF_DBG(dm, DBG_RF_DPK, "[DPK] result[1] = 0x%x\n", dpk_c2h_report.result[1]);
2242 RF_DBG(dm, DBG_RF_DPK, "[DPK] thermal_dpk[0][0] = 0x%x\n", dpk_c2h_report.therm[0][0]);
2243 RF_DBG(dm, DBG_RF_DPK, "[DPK] thermal_dpk[0][1] = 0x%x\n", dpk_c2h_report.therm[0][1]);
2244 RF_DBG(dm, DBG_RF_DPK, "[DPK] thermal_dpk[1][0] = 0x%x\n", dpk_c2h_report.therm[1][0]);
2245 RF_DBG(dm, DBG_RF_DPK, "[DPK] thermal_dpk[1][1] = 0x%x\n", dpk_c2h_report.therm[1][1]);
2246 RF_DBG(dm, DBG_RF_DPK, "[DPK] thermal_dpk_delta[0][0] = 0x%x\n", dpk_c2h_report.therm_delta[0][0]);
2247 RF_DBG(dm, DBG_RF_DPK, "[DPK] thermal_dpk_delta[0][1] = 0x%x\n", dpk_c2h_report.therm_delta[0][1]);
2248 RF_DBG(dm, DBG_RF_DPK, "[DPK] thermal_dpk_delta[1][0] = 0x%x\n", dpk_c2h_report.therm_delta[1][0]);
2249 RF_DBG(dm, DBG_RF_DPK, "[DPK] thermal_dpk_delta[1][1] = 0x%x\n", dpk_c2h_report.therm_delta[1][1]);
2250 RF_DBG(dm, DBG_RF_DPK, "[DPK] dpk_rf18[0] = 0x%x\n", dpk_c2h_report.dpk_rf18[0]);
2251 RF_DBG(dm, DBG_RF_DPK, "[DPK] dpk_rf18[1] = 0x%x\n", dpk_c2h_report.dpk_rf18[1]);
2252 RF_DBG(dm, DBG_RF_DPK, "[DPK] dpk_status = 0x%x\n", dpk_c2h_report.dpk_status);
2253 #endif
2254 }
2255 #endif
2256