1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Linux DHD Bus Module for PCIE
4 *
5 * Copyright (C) 1999-2017, Broadcom Corporation
6 *
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
12 *
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
20 *
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
24 *
25 *
26 * <<Broadcom-WL-IPTag/Open:>>
27 *
28 * $Id: dhd_pcie.h 707536 2017-06-28 04:23:48Z $
29 */
30
31
32 #ifndef dhd_pcie_h
33 #define dhd_pcie_h
34
35 #include <bcmpcie.h>
36 #include <hnd_cons.h>
37 #ifdef SUPPORT_LINKDOWN_RECOVERY
38 #ifdef CONFIG_ARCH_MSM
39 #ifdef CONFIG_PCI_MSM
40 #include <linux/msm_pcie.h>
41 #else
42 #include <mach/msm_pcie.h>
43 #endif /* CONFIG_PCI_MSM */
44 #endif /* CONFIG_ARCH_MSM */
45 #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
46 #if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895)
47 #include <linux/exynos-pci-noti.h>
48 extern int exynos_pcie_register_event(struct exynos_pcie_register_event *reg);
49 extern int exynos_pcie_deregister_event(struct exynos_pcie_register_event *reg);
50 #endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 */
51 #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
52 #endif /* SUPPORT_LINKDOWN_RECOVERY */
53
54 #ifdef DHD_PCIE_RUNTIMEPM
55 #include <linux/mutex.h>
56 #include <linux/wait.h>
57
58 #define DEFAULT_DHD_RUNTIME_MS 100
59 #ifndef CUSTOM_DHD_RUNTIME_MS
60 #define CUSTOM_DHD_RUNTIME_MS DEFAULT_DHD_RUNTIME_MS
61 #endif /* CUSTOM_DHD_RUNTIME_MS */
62
63
64 #ifndef MAX_IDLE_COUNT
65 #define MAX_IDLE_COUNT 16
66 #endif /* MAX_IDLE_COUNT */
67
68 #ifndef MAX_RESUME_WAIT
69 #define MAX_RESUME_WAIT 100
70 #endif /* MAX_RESUME_WAIT */
71 #endif /* DHD_PCIE_RUNTIMEPM */
72
73 /* defines */
74
75 #define PCMSGBUF_HDRLEN 0
76 #define DONGLE_REG_MAP_SIZE (32 * 1024)
77 #define DONGLE_TCM_MAP_SIZE (4096 * 1024)
78 #define DONGLE_MIN_MEMSIZE (128 *1024)
79 #ifdef DHD_DEBUG
80 #define DHD_PCIE_SUCCESS 0
81 #define DHD_PCIE_FAILURE 1
82 #endif /* DHD_DEBUG */
83 #define REMAP_ENAB(bus) ((bus)->remap)
84 #define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
85
86 #ifdef SUPPORT_LINKDOWN_RECOVERY
87 #ifdef CONFIG_ARCH_MSM
88 #define struct_pcie_notify struct msm_pcie_notify
89 #define struct_pcie_register_event struct msm_pcie_register_event
90 #endif /* CONFIG_ARCH_MSM */
91 #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
92 #if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895)
93 #define struct_pcie_notify struct exynos_pcie_notify
94 #define struct_pcie_register_event struct exynos_pcie_register_event
95 #endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 */
96 #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
97 #endif /* SUPPORT_LINKDOWN_RECOVERY */
98
99 #define MAX_DHD_TX_FLOWS 320
100
101 /* user defined data structures */
102 /* Device console log buffer state */
103 #define CONSOLE_LINE_MAX 192
104 #define CONSOLE_BUFFER_MAX (8 * 1024)
105
106 #ifdef IDLE_TX_FLOW_MGMT
107 #define IDLE_FLOW_LIST_TIMEOUT 5000
108 #define IDLE_FLOW_RING_TIMEOUT 5000
109 #endif /* IDLE_TX_FLOW_MGMT */
110
111 #ifdef DEVICE_TX_STUCK_DETECT
112 #define DEVICE_TX_STUCK_CKECK_TIMEOUT 1000 /* 1 sec */
113 #define DEVICE_TX_STUCK_TIMEOUT 10000 /* 10 secs */
114 #define DEVICE_TX_STUCK_WARN_DURATION (DEVICE_TX_STUCK_TIMEOUT / DEVICE_TX_STUCK_CKECK_TIMEOUT)
115 #define DEVICE_TX_STUCK_DURATION (DEVICE_TX_STUCK_WARN_DURATION * 2)
116 #endif /* DEVICE_TX_STUCK_DETECT */
117
118 /* implicit DMA for h2d wr and d2h rd indice from Host memory to TCM */
119 #define IDMA_ENAB(dhd) ((dhd)->idma_enable)
120 #define IDMA_ACTIVE(dhd) (((dhd)->idma_enable) && ((dhd)->idma_inited))
121
122 #define IDMA_DS_ENAB(dhd) ((dhd)->idma_retention_ds)
123 #define IDMA_DS_ACTIVE(dhd) ((dhd)->bus->dongle_in_ds)
124
125 /* IFRM (Implicit Flow Ring Manager enable and inited */
126 #define IFRM_ENAB(dhd) ((dhd)->ifrm_enable)
127 #define IFRM_ACTIVE(dhd) (((dhd)->ifrm_enable) && ((dhd)->ifrm_inited))
128
129 /* PCIE CTO Prevention and Recovery */
130 #define PCIECTO_ENAB(dhd) ((dhd)->cto_enable)
131
132 /* Implicit DMA index usage :
133 * Index 0 for h2d write index transfer
134 * Index 1 for d2h read index transfer
135 */
136 #define IDMA_IDX0 0
137 #define IDMA_IDX1 1
138 #define IDMA_IDX2 2
139 #define IDMA_IDX3 3
140
141 #define DHDPCIE_CONFIG_HDR_SIZE 16
142 #define DHDPCIE_CONFIG_CHECK_DELAY_MS 10 /* 10ms */
143 #define DHDPCIE_CONFIG_CHECK_RETRY_COUNT 20
144 #define DHDPCIE_DONGLE_PWR_TOGGLE_DELAY 1000 /* 1ms in units of us */
145 #define DHDPCIE_PM_D3_DELAY 200000 /* 200ms in units of us */
146 #define DHDPCIE_PM_D2_DELAY 200 /* 200us */
147
148 typedef struct dhd_console {
149 uint count; /* Poll interval msec counter */
150 uint log_addr; /* Log struct address (fixed) */
151 hnd_log_t log; /* Log struct (host copy) */
152 uint bufsize; /* Size of log buffer */
153 uint8 *buf; /* Log buffer (host copy) */
154 uint last; /* Last buffer read index */
155 } dhd_console_t;
156
157 typedef struct ring_sh_info {
158 uint32 ring_mem_addr;
159 uint32 ring_state_w;
160 uint32 ring_state_r;
161 } ring_sh_info_t;
162
163
164 #define DEVICE_WAKE_NONE 0
165 #define DEVICE_WAKE_OOB 1
166 #define DEVICE_WAKE_INB 2
167
168 #define INBAND_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_INB)
169 #define OOB_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_OOB)
170 #define NO_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_NONE)
171
172 struct dhd_bus;
173
174 struct dhd_pcie_rev {
175 uint8 fw_rev;
176 void (*handle_mb_data)(struct dhd_bus *);
177 };
178
179 typedef struct dhdpcie_config_save
180 {
181 uint32 header[DHDPCIE_CONFIG_HDR_SIZE];
182 /* pmcsr save */
183 uint32 pmcsr;
184 /* express save */
185 uint32 exp_dev_ctrl_stat;
186 uint32 exp_link_ctrl_stat;
187 uint32 exp_dev_ctrl_stat2;
188 uint32 exp_link_ctrl_stat2;
189 /* msi save */
190 uint32 msi_cap;
191 uint32 msi_addr0;
192 uint32 msi_addr1;
193 uint32 msi_data;
194 /* l1pm save */
195 uint32 l1pm0;
196 uint32 l1pm1;
197 /* ltr save */
198 uint32 ltr;
199 /* aer save */
200 uint32 aer_caps_ctrl; /* 0x18 */
201 uint32 aer_severity; /* 0x0C */
202 uint32 aer_umask; /* 0x08 */
203 uint32 aer_cmask; /* 0x14 */
204 uint32 aer_root_cmd; /* 0x2c */
205 /* BAR0 and BAR1 windows */
206 uint32 bar0_win;
207 uint32 bar1_win;
208 } dhdpcie_config_save_t;
209
210 typedef struct dhd_bus {
211 dhd_pub_t *dhd;
212 struct pci_dev *rc_dev; /* pci RC device handle */
213 struct pci_dev *dev; /* pci device handle */
214 #ifdef DHD_EFI
215 void *pcie_dev;
216 #endif
217
218 dll_t flowring_active_list; /* constructed list of tx flowring queues */
219 #ifdef IDLE_TX_FLOW_MGMT
220 uint64 active_list_last_process_ts;
221 /* stores the timestamp of active list processing */
222 #endif /* IDLE_TX_FLOW_MGMT */
223
224 #ifdef DEVICE_TX_STUCK_DETECT
225 /* Flag to enable/disable device tx stuck monitor by DHD IOVAR dev_tx_stuck_monitor */
226 uint32 dev_tx_stuck_monitor;
227 /* Stores the timestamp (msec) of the last device Tx stuck check */
228 uint32 device_tx_stuck_check;
229 #endif /* DEVICE_TX_STUCK_DETECT */
230
231 si_t *sih; /* Handle for SI calls */
232 char *vars; /* Variables (from CIS and/or other) */
233 uint varsz; /* Size of variables buffer */
234 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
235 sbpcieregs_t *reg; /* Registers for PCIE core */
236
237 uint armrev; /* CPU core revision */
238 uint ramrev; /* SOCRAM core revision */
239 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
240 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
241 bool ramsize_adjusted; /* flag to note adjustment, so that
242 * adjustment routine and file io
243 * are avoided on D3 cold -> D0
244 */
245 uint32 srmemsize; /* Size of SRMEM */
246
247 uint32 bus; /* gSPI or SDIO bus */
248 uint32 intstatus; /* Intstatus bits (events) pending */
249 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
250 bool fcstate; /* State of dongle flow-control */
251
252 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
253 char *fw_path; /* module_param: path to firmware image */
254 char *nv_path; /* module_param: path to nvram vars file */
255 #ifdef CACHE_FW_IMAGES
256 int processed_nvram_params_len; /* Modified len of NVRAM info */
257 #endif
258
259
260 struct pktq txq; /* Queue length used for flow-control */
261
262 bool intr; /* Use interrupts */
263 bool poll; /* Use polling */
264 bool ipend; /* Device interrupt is pending */
265 bool intdis; /* Interrupts disabled by isr */
266 uint intrcount; /* Count of device interrupt callbacks */
267 uint lastintrs; /* Count as of last watchdog timer */
268
269 dhd_console_t console; /* Console output polling support */
270 uint console_addr; /* Console address from shared struct */
271
272 bool alp_only; /* Don't use HT clock (ALP only) */
273
274 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
275 * Available with socram rev 16
276 * Remap region not DMA-able
277 */
278 uint32 resetinstr;
279 uint32 dongle_ram_base;
280
281 ulong shared_addr;
282 pciedev_shared_t *pcie_sh;
283 bool bus_flowctrl;
284 uint32 dma_rxoffset;
285 volatile char *regs; /* pci device memory va */
286 volatile char *tcm; /* pci device memory va */
287 osl_t *osh;
288 uint32 nvram_csm; /* Nvram checksum */
289 uint16 pollrate;
290 uint16 polltick;
291
292 volatile uint32 *pcie_mb_intr_addr;
293 volatile uint32 *pcie_mb_intr_2_addr;
294 void *pcie_mb_intr_osh;
295 bool sleep_allowed;
296
297 wake_counts_t wake_counts;
298
299 /* version 3 shared struct related info start */
300 ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
301
302 uint8 h2d_ring_count;
303 uint8 d2h_ring_count;
304 uint32 ringmem_ptr;
305 uint32 ring_state_ptr;
306
307 uint32 d2h_dma_scratch_buffer_mem_addr;
308
309 uint32 h2d_mb_data_ptr_addr;
310 uint32 d2h_mb_data_ptr_addr;
311 /* version 3 shared struct related info end */
312
313 uint32 def_intmask;
314 bool ltrsleep_on_unload;
315 uint wait_for_d3_ack;
316 uint16 max_tx_flowrings;
317 uint16 max_submission_rings;
318 uint16 max_completion_rings;
319 uint16 max_cmn_rings;
320 uint32 rw_index_sz;
321 bool db1_for_mb;
322
323 dhd_timeout_t doorbell_timer;
324 bool device_wake_state;
325 #ifdef PCIE_OOB
326 bool oob_enabled;
327 #endif /* PCIE_OOB */
328 bool irq_registered;
329 #ifdef SUPPORT_LINKDOWN_RECOVERY
330 #if defined(CONFIG_ARCH_MSM) || (defined(EXYNOS_PCIE_LINKDOWN_RECOVERY) && \
331 defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895))
332 #ifdef CONFIG_ARCH_MSM
333 uint8 no_cfg_restore;
334 #endif /* CONFIG_ARCH_MSM */
335 struct_pcie_register_event pcie_event;
336 #endif /* CONFIG_ARCH_MSM || (EXYNOS_PCIE_LINKDOWN_RECOVERY &&
337 * (CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895))
338 */
339 bool read_shm_fail;
340 #endif /* SUPPORT_LINKDOWN_RECOVERY */
341 int32 idletime; /* Control for activity timeout */
342 #ifdef DHD_PCIE_RUNTIMEPM
343 int32 idlecount; /* Activity timeout counter */
344 int32 bus_wake; /* For wake up the bus */
345 bool runtime_resume_done; /* For check runtime suspend end */
346 struct mutex pm_lock; /* Synchronize for system PM & runtime PM */
347 wait_queue_head_t rpm_queue; /* wait-queue for bus wake up */
348 #endif /* DHD_PCIE_RUNTIMEPM */
349 uint32 d3_inform_cnt;
350 uint32 d0_inform_cnt;
351 uint32 d0_inform_in_use_cnt;
352 uint8 force_suspend;
353 uint8 is_linkdown;
354 #ifdef IDLE_TX_FLOW_MGMT
355 bool enable_idle_flowring_mgmt;
356 #endif /* IDLE_TX_FLOW_MGMT */
357 struct dhd_pcie_rev api;
358 bool use_mailbox;
359 bool d3_suspend_pending;
360 bool use_d0_inform;
361 uint32 hostready_count; /* Number of hostready issued */
362 #if defined(PCIE_OOB) || defined(BCMPCIE_OOB_HOST_WAKE)
363 bool oob_presuspend;
364 #endif /* PCIE_OOB || BCMPCIE_OOB_HOST_WAKE */
365 bool dongle_in_ds;
366 uint8 dw_option;
367 #ifdef PCIE_INB_DW
368 bool inb_enabled;
369 uint32 ds_exit_timeout;
370 uint32 host_sleep_exit_timeout;
371 uint wait_for_ds_exit;
372 uint32 inband_dw_assert_cnt; /* # of inband device_wake assert */
373 uint32 inband_dw_deassert_cnt; /* # of inband device_wake deassert */
374 uint32 inband_ds_exit_host_cnt; /* # of DS-EXIT , host initiated */
375 uint32 inband_ds_exit_device_cnt; /* # of DS-EXIT , device initiated */
376 uint32 inband_ds_exit_to_cnt; /* # of DS-EXIT timeout */
377 uint32 inband_host_sleep_exit_to_cnt; /* # of Host_Sleep exit timeout */
378 void *inb_lock; /* Lock to serialize in band device wake activity */
379 /* # of contexts in the host which currently want a FW transaction */
380 uint32 host_active_cnt;
381 #endif /* PCIE_INB_DW */
382 dhdpcie_config_save_t saved_config;
383 ulong resume_intr_enable_count;
384 ulong dpc_intr_enable_count;
385 ulong isr_intr_disable_count;
386 ulong suspend_intr_disable_count;
387 ulong dpc_return_busdown_count;
388 bool idma_enabled;
389 bool ifrm_enabled;
390 #if defined(PCIE_OOB) || defined(PCIE_INB_DW)
391 bool ds_enabled;
392 #endif
393 #ifdef DHD_PCIE_RUNTIMEPM
394 bool chk_pm; /* To avoid counting of wake up from Runtime PM */
395 #endif /* DHD_PCIE_RUNTIMEPM */
396 } dhd_bus_t;
397
398 /* function declarations */
399
400 extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
401 extern int dhdpcie_bus_register(void);
402 extern void dhdpcie_bus_unregister(void);
403 extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
404
405 extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh,
406 volatile char *regs, volatile char *tcm, void *pci_dev);
407 extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
408 extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
409 extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
410 extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
411 extern int dhpcie_bus_mask_interrupt(dhd_bus_t *bus);
412 extern void dhdpcie_bus_release(struct dhd_bus *bus);
413 extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
414 extern void dhdpcie_free_irq(dhd_bus_t *bus);
415 extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
416 extern void dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value, bool devwake);
417 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
418 extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
419 extern uint32 dhdpcie_force_alp(struct dhd_bus *bus, bool enable);
420 extern uint32 dhdpcie_set_l1_entry_time(struct dhd_bus *bus, int force_l1_entry_time);
421 extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
422 extern void dhdpcie_pme_active(osl_t *osh, bool enable);
423 extern bool dhdpcie_pme_cap(osl_t *osh);
424 extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
425 extern void dhdpcie_set_pmu_min_res_mask(struct dhd_bus *bus, uint min_res_mask);
426 extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
427 extern int dhdpcie_disable_irq(dhd_bus_t *bus);
428 extern int dhdpcie_disable_irq_nosync(dhd_bus_t *bus);
429 extern int dhdpcie_enable_irq(dhd_bus_t *bus);
430 extern uint32 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset);
431 extern uint32 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
432 bool is_write, uint32 writeval);
433 extern uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus);
434 extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
435 extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
436 extern int dhdpcie_disable_device(dhd_bus_t *bus);
437 extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
438 extern void dhdpcie_free_resource(dhd_bus_t *bus);
439 extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
440 extern int dhdpcie_enable_device(dhd_bus_t *bus);
441 #ifdef BCMPCIE_OOB_HOST_WAKE
442 extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
443 extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
444 extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
445 #endif /* BCMPCIE_OOB_HOST_WAKE */
446 #ifdef PCIE_OOB
447 extern void dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val);
448 extern int dhd_oob_get_bt_reg_on(struct dhd_bus *bus);
449 extern void dhdpcie_oob_init(dhd_bus_t *bus);
450 extern void dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus);
451 extern int dhd_os_oob_set_device_wake(struct dhd_bus *bus, bool val);
452 extern void dhd_os_ib_set_device_wake(struct dhd_bus *bus, bool val);
453 #endif /* PCIE_OOB */
454
455 #if defined(CONFIG_ARCH_EXYNOS)
456 #define SAMSUNG_PCIE_VENDOR_ID 0x144d
457 #if defined(CONFIG_MACH_UNIVERSAL5433)
458 #define SAMSUNG_PCIE_DEVICE_ID 0xa5e3
459 #define SAMSUNG_PCIE_CH_NUM
460 #elif defined(CONFIG_MACH_UNIVERSAL7420)
461 #define SAMSUNG_PCIE_DEVICE_ID 0xa575
462 #define SAMSUNG_PCIE_CH_NUM 1
463 #elif defined(CONFIG_SOC_EXYNOS8890)
464 #define SAMSUNG_PCIE_DEVICE_ID 0xa544
465 #define SAMSUNG_PCIE_CH_NUM 0
466 #elif defined(CONFIG_SOC_EXYNOS7420)
467 #define SAMSUNG_PCIE_DEVICE_ID 0xa575
468 #define SAMSUNG_PCIE_CH_NUM 1
469 #elif defined(CONFIG_SOC_EXYNOS8895)
470 #define SAMSUNG_PCIE_DEVICE_ID 0xecec
471 #define SAMSUNG_PCIE_CH_NUM 0
472 #else
473 #error "Not supported platform"
474 #endif /* CONFIG_SOC_EXYNOSXXXX & CONFIG_MACH_UNIVERSALXXXX */
475 #endif /* CONFIG_ARCH_EXYNOS */
476
477 #if defined(CONFIG_ARCH_MSM)
478 #define MSM_PCIE_VENDOR_ID 0x17cb
479 #if defined(CONFIG_ARCH_APQ8084)
480 #define MSM_PCIE_DEVICE_ID 0x0101
481 #elif defined(CONFIG_ARCH_MSM8994)
482 #define MSM_PCIE_DEVICE_ID 0x0300
483 #elif defined(CONFIG_ARCH_MSM8996)
484 #define MSM_PCIE_DEVICE_ID 0x0104
485 #elif defined(CONFIG_ARCH_MSM8998)
486 #define MSM_PCIE_DEVICE_ID 0x0105
487 #else
488 #error "Not supported platform"
489 #endif
490 #endif /* CONFIG_ARCH_MSM */
491
492 #if defined(CONFIG_X86)
493 #define X86_PCIE_VENDOR_ID 0x8086
494 #define X86_PCIE_DEVICE_ID 0x9c1a
495 #endif /* CONFIG_X86 */
496
497 #if defined(CONFIG_ARCH_TEGRA)
498 #define TEGRA_PCIE_VENDOR_ID 0x14e4
499 #define TEGRA_PCIE_DEVICE_ID 0x4347
500 #endif /* CONFIG_ARCH_TEGRA */
501
502 #if defined(CONFIG_ARCH_EXYNOS)
503 #define PCIE_RC_VENDOR_ID SAMSUNG_PCIE_VENDOR_ID
504 #define PCIE_RC_DEVICE_ID SAMSUNG_PCIE_DEVICE_ID
505 #elif defined(CONFIG_ARCH_MSM)
506 #define PCIE_RC_VENDOR_ID MSM_PCIE_VENDOR_ID
507 #define PCIE_RC_DEVICE_ID MSM_PCIE_DEVICE_ID
508 #elif defined(CONFIG_X86)
509 #define PCIE_RC_VENDOR_ID X86_PCIE_VENDOR_ID
510 #define PCIE_RC_DEVICE_ID X86_PCIE_DEVICE_ID
511 #elif defined(CONFIG_ARCH_TEGRA)
512 #define PCIE_RC_VENDOR_ID TEGRA_PCIE_VENDOR_ID
513 #define PCIE_RC_DEVICE_ID TEGRA_PCIE_DEVICE_ID
514 #endif /* CONFIG_ARCH_EXYNOS */
515
516 #ifdef USE_EXYNOS_PCIE_RC_PMPATCH
517 #ifdef CONFIG_MACH_UNIVERSAL5433
518 extern int exynos_pcie_pm_suspend(void);
519 extern int exynos_pcie_pm_resume(void);
520 #else
521 extern int exynos_pcie_pm_suspend(int ch_num);
522 extern int exynos_pcie_pm_resume(int ch_num);
523 #endif /* CONFIG_MACH_UNIVERSAL5433 */
524 #endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
525
526 #ifdef CONFIG_ARCH_TEGRA
527 extern int tegra_pcie_pm_suspend(void);
528 extern int tegra_pcie_pm_resume(void);
529 #endif /* CONFIG_ARCH_TEGRA */
530
531 extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
532 #ifdef IDLE_TX_FLOW_MGMT
533 extern int dhd_bus_flow_ring_resume_request(struct dhd_bus *bus, void *arg);
534 extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus, uint16 flowid, int32 status);
535 extern int dhd_bus_flow_ring_suspend_request(struct dhd_bus *bus, void *arg);
536 extern void dhd_bus_flow_ring_suspend_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
537 extern void dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus,
538 flow_ring_node_t *flow_ring_node);
539 extern void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus,
540 flow_ring_node_t *flow_ring_node);
541 extern void dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
542 flow_ring_node_t *flow_ring_node);
543 extern void __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
544 flow_ring_node_t *flow_ring_node);
545 #endif /* IDLE_TX_FLOW_MGMT */
546
547 extern int dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
548
549 #ifdef DHD_WAKE_STATUS
550 int bcmpcie_get_total_wake(struct dhd_bus *bus);
551 int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag);
552 #endif /* DHD_WAKE_STATUS */
553 extern bool dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus);
554 extern void dhd_bus_hostready(struct dhd_bus *bus);
555 #ifdef PCIE_OOB
556 extern bool dhdpcie_bus_get_pcie_oob_dw_supported(dhd_bus_t *bus);
557 #endif /* PCIE_OOB */
558 #ifdef PCIE_INB_DW
559 extern bool dhdpcie_bus_get_pcie_inband_dw_supported(dhd_bus_t *bus);
560 extern void dhdpcie_bus_set_pcie_inband_dw_state(dhd_bus_t *bus,
561 enum dhd_bus_ds_state state);
562 extern enum dhd_bus_ds_state dhdpcie_bus_get_pcie_inband_dw_state(dhd_bus_t *bus);
563 extern const char * dhd_convert_inb_state_names(enum dhd_bus_ds_state inbstate);
564 extern const char * dhd_convert_dsval(uint32 val, bool d2h);
565 extern int dhd_bus_inb_set_device_wake(struct dhd_bus *bus, bool val);
566 extern void dhd_bus_inb_ack_pending_ds_req(dhd_bus_t *bus);
567 #endif /* PCIE_INB_DW */
568 extern void dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option);
569 extern bool dhdpcie_irq_enabled(struct dhd_bus *bus);
570 extern bool dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus);
571 extern bool dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus);
572
573 static INLINE uint32
dhd_pcie_config_read(osl_t * osh,uint offset,uint size)574 dhd_pcie_config_read(osl_t *osh, uint offset, uint size)
575 {
576 OSL_DELAY(100);
577 return OSL_PCI_READ_CONFIG(osh, offset, size);
578 }
579
580 static INLINE uint32
dhd_pcie_corereg_read(si_t * sih,uint val)581 dhd_pcie_corereg_read(si_t *sih, uint val)
582 {
583 OSL_DELAY(100);
584 si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, val);
585 return si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), 0, 0);
586 }
587
588 #ifdef DHD_SSSR_DUMP
589 extern int dhdpcie_sssr_dump(dhd_pub_t *dhd);
590 #endif /* DHD_SSSR_DUMP */
591
592 #ifdef DHD_EFI
593 extern int dhd_os_wifi_platform_set_power(uint32 value);
594 int dhd_control_signal(dhd_bus_t *bus, char *arg, int set);
595 extern int dhd_wifi_properties(struct dhd_bus *bus, char *arg);
596 extern bool dhdpcie_is_arm_halted(struct dhd_bus *bus);
597 extern void dhdpcie_dongle_pwr_toggle(dhd_bus_t *bus);
598 extern int dhd_otp_dump(dhd_bus_t *bus, char *arg);
599 #else
dhd_os_wifi_platform_set_power(uint32 value)600 static INLINE int dhd_os_wifi_platform_set_power(uint32 value) {return BCME_OK; }
dhdpcie_is_arm_halted(struct dhd_bus * bus)601 static INLINE bool dhdpcie_is_arm_halted(struct dhd_bus *bus) {return TRUE;}
602 #endif /* DHD_EFI */
603 int dhdpcie_config_check(dhd_bus_t *bus);
604 int dhdpcie_config_restore(dhd_bus_t *bus, bool restore_pmcsr);
605 int dhdpcie_config_save(dhd_bus_t *bus);
606 int dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state);
607
608 #endif /* dhd_pcie_h */
609