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77 //<MStar Software>
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93 ///////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvUrDMA.c
98 /// @brief UART DMA Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #include "MsCommon.h"
108 #include "MsTypes.h"
109 #include "MsIRQ.h"
110 #include "MsOS.h"
111 #include "MsVersion.h"
112
113 #include "drvMMIO.h"
114 #include "halURDMA.h"
115 #include "regURDMA.h"
116 #include "drvURDMA.h"
117
118 #include "ULog.h"
119 //-------------------------------------------------------------------------------------------------
120 // Driver Compiler Options
121 //-------------------------------------------------------------------------------------------------
122
123
124 //-------------------------------------------------------------------------------------------------
125 // Local Defines
126 //-------------------------------------------------------------------------------------------------
127 #define TAG_UARTDMA "UARTDMA"
128
129 //-------------------------------------------------------------------------------------------------
130 // Local Structurs
131 //-------------------------------------------------------------------------------------------------
132
133 //-------------------------------------------------------------------------------------------------
134 // Global Variables
135 //-------------------------------------------------------------------------------------------------
136 /* register base address */
137 static dma_interface_t *p_uart_dma = NULL;
138 static MS_VIRT virt_urdma_base = 0;//HS_UART_DMA_REG_BASE
139
140 /* Callback function for interrupt serivce routine. */
141 static void (*fast_uart_dma_rx_cb)(void) = NULL;
142 static void (*fast_uart_dma_tx_cb)(void) = NULL;
143
144 //-------------------------------------------------------------------------------------------------
145 // Local Variables
146 //-------------------------------------------------------------------------------------------------
147
148 static MSIF_Version _urdmaVersion = {
149 .DDI = { URDMA_DRV_VERSION },
150 };
151
152 static URDMA_DbgLv _urdmaDbgLevel = E_URDMA_DBGLV_ERR_ONLY;
153 //-------------------------------------------------------------------------------------------------
154 // Debug Functions
155 //-------------------------------------------------------------------------------------------------
156 #define DEBUG_UART_DMA(debug_level, x) do { if (_urdmaDbgLevel >= (debug_level)) (x); } while(0)
157
158 //-------------------------------------------------------------------------------------------------
159 // Local Functions
160 //-------------------------------------------------------------------------------------------------
161 #define URDMA_LOU16(u32Val) ((MS_U16)(u32Val)&0xffff)
162 #define URDMA_HIU16(u32Val) ((MS_U16)((u32Val) >> 16)&0x07ff)
163
_MDrv_UrDMA_RegisterCallback(void * rx_cb,void * tx_cb)164 static void _MDrv_UrDMA_RegisterCallback(void *rx_cb, void *tx_cb)//register_hs_uart_dma_cb(void *rx_cb, void *tx_cb)
165 {
166 /* disable interrupt */
167 MsOS_DisableInterrupt(FAST_UART_DMA_INT);
168
169 fast_uart_dma_rx_cb = rx_cb;
170 fast_uart_dma_tx_cb = tx_cb;
171
172 /* enable interrupt */
173 MsOS_EnableInterrupt(FAST_UART_DMA_INT);
174 }
175
176 //-------------------------------------------------------------------------------------------------
177 // Global Functions
178 //-------------------------------------------------------------------------------------------------
179
MDrv_UrDMA_GetLibVer(const MSIF_Version ** ppVersion)180 DRVURDMA_RESULT MDrv_UrDMA_GetLibVer(const MSIF_Version **ppVersion)
181 {
182 // No mutex check, it can be called before Init
183 if (!ppVersion)
184 {
185 return DRVURDMA_INVALID_PARAM;
186 }
187
188 *ppVersion = &_urdmaVersion;
189
190 return DRVURDMA_PASS;
191 }
192
MDrv_UrDMA_SetDbgLevel(MS_U8 level)193 void MDrv_UrDMA_SetDbgLevel(MS_U8 level)
194 {
195 _urdmaDbgLevel = (URDMA_DbgLv)level;
196 }
197
MDrv_UrDMA_TxInit(MS_PHYADDR * tx_buf,MS_U16 tx_size)198 DRVURDMA_RESULT MDrv_UrDMA_TxInit(MS_PHYADDR *tx_buf, MS_U16 tx_size)//U32 hs_uart_dma_prepare_tx(void *tx_buf, U16 tx_size)
199 {
200 DRVURDMA_RESULT ret = DRVURDMA_PASS;
201 // hank
202 // extern int dma_dbug;
203
204 // if (dma_dbug == 1)
205 // {
206 // }
207
208 /* disable interrupt */
209 MsOS_DisableInterrupt(FAST_UART_DMA_INT);
210
211 if (p_uart_dma == NULL)
212 {
213 ret = DRVURDMA_FATAL_ERROR;
214 goto dma_prepare_tx_end;
215 }
216
217 p_uart_dma->tx_urdma_en = 0; /* disable dma */
218 while (p_uart_dma->tx_busy)
219 {
220 int i = 0;
221 ret = DRVURDMA_TX_BUSY;
222 DEBUG_UART_DMA(E_URDMA_DBGLV_ERR_ONLY, ULOGE(TAG_UARTDMA,"tx_busy!\n"));
223 if (1000 == (i++))
224 {
225 //reg dump, here
226 goto dma_prepare_tx_end;
227 }
228 }
229
230 p_uart_dma->tx_buf_base_h = URDMA_HIU16((MS_PHYADDR)tx_buf);//(U16)((((U32)PHYADDR((U32)tx_buf))>>16)&0x7ff);
231 p_uart_dma->tx_buf_base_l = URDMA_LOU16((MS_PHYADDR)tx_buf);//(U16)(((U32)PHYADDR((U32)tx_buf))&0xffff);
232 // p_uart_dma->tx_buf_size = (U16)(tx_size>>3);
233 p_uart_dma->tx_buf_size = 0x1fff;
234 p_uart_dma->tx_buf_wptr = (MS_VIRT)((tx_size-1) + (((MS_VIRT)tx_buf)%8)); /* alignment issue */
235 p_uart_dma->tx_timeout = 1; /* send-out asap. */
236 p_uart_dma->tx_intr_en = 1; /* Enable tx interrupt. */
237
238 #ifdef MS_DEBUG
239 MDrv_UrDMA_DumpREG();
240 #endif
241
242 p_uart_dma->tx_urdma_en = 1;/* Enable tx dma and start transmission. */
243
244 dma_prepare_tx_end:
245 /* enable interrupt */
246 MsOS_EnableInterrupt(FAST_UART_DMA_INT);
247
248 return ret;
249 }
250
MDrv_UrDMA_RxInit(MS_PHYADDR * rx_buf,MS_U16 rx_size)251 DRVURDMA_RESULT MDrv_UrDMA_RxInit(MS_PHYADDR *rx_buf, MS_U16 rx_size)//hs_uart_dma_prepare_rx(void *rx_buf, U16 rx_size)
252 {
253 DRVURDMA_RESULT ret = DRVURDMA_PASS;
254
255 /* disable interrupt */
256 MsOS_DisableInterrupt(FAST_UART_DMA_INT);
257
258 if (p_uart_dma == NULL)
259 {
260 ret = DRVURDMA_FATAL_ERROR;
261 goto dma_prepare_rx_end;
262 }
263
264 p_uart_dma->rx_urdma_en = 0; /* disable dma */
265 while (p_uart_dma->rx_busy)
266 {
267 int i=0;
268 ret = DRVURDMA_RX_BUSY;
269 DEBUG_UART_DMA(E_URDMA_DBGLV_ERR_ONLY, ULOGE(TAG_UARTDMA,"rx_busy!\n"));
270 if (1000 == (i++))
271 {
272 goto dma_prepare_rx_end;
273 }
274 }
275
276 p_uart_dma->rx_buf_base_h = URDMA_HIU16((MS_PHYADDR)rx_buf);//(U16)((((U32)PHYADDR((U32)rx_buf))>>16)&0x7ff);
277 p_uart_dma->rx_buf_base_l = URDMA_LOU16((MS_PHYADDR)rx_buf);//(U16)(((U32)PHYADDR((U32)rx_buf))&0xffff);
278 // p_uart_dma->rx_buf_size = (U16)(rx_size>>3);
279 p_uart_dma->rx_buf_size = 0x1fff;
280 p_uart_dma->intr_threshold = (MS_U16)rx_size;
281 p_uart_dma->rx_timeout = 10; /* receive timeout. */
282 p_uart_dma->rx_intr2_en = 1; /* Enable rx threshold interrupt. */
283
284 #ifdef MS_DEBUG
285 MDrv_UrDMA_DumpREG(); //@@@ pending function
286 #endif
287
288 p_uart_dma->rx_urdma_en = 1; /* Enable rx dma and start receiving. */
289
290 dma_prepare_rx_end:
291 /* enable interrupt */
292 MsOS_EnableInterrupt(FAST_UART_DMA_INT);
293
294 return ret;
295 }
296
MDrv_UrDMA_Polling_Tx_Done(void)297 DRVURDMA_RESULT MDrv_UrDMA_Polling_Tx_Done(void)//hs_uart_dma_poll_tx_complete(void)
298 {
299 DRVURDMA_RESULT ret = DRVURDMA_PASS;
300
301 //ret = 1;
302
303 // if (!(p_uart_dma->tx_mcu_intr))
304 // {
305 // ret = 0;
306 // }
307
308 /* wait until URDMA into idle state. */
309 while (p_uart_dma->tx_busy)
310 ;
311
312 p_uart_dma->tx_intr_clr = 1; /* clear int status */
313 p_uart_dma->tx_intr_en = 0; /* disable tx int */
314
315 return ret;
316 }
317
MDrv_UrDMA_ISR(void)318 void MDrv_UrDMA_ISR(void)//void hs_uart_dma_isr(void)
319 {
320 if (p_uart_dma != NULL)
321 {
322 if (p_uart_dma->rx_mcu_intr)
323 {
324 while (p_uart_dma->rx_busy)
325 ;
326 /* RX interrupt */
327 if (p_uart_dma->rx_intr2) /* Caused by intr threshold */
328 {
329 p_uart_dma->rx_intr_clr = 1; /* clear int status */
330 p_uart_dma->rx_intr2_en = 0; /* disable rx threshold int */
331 }
332 if (p_uart_dma->rx_intr1) /* Caused by receive timeout */
333 {
334 p_uart_dma->rx_intr_clr = 1; /* clear int status */
335 p_uart_dma->rx_intr1_en = 0; /* disable rx timeout int */
336 }
337 if (fast_uart_dma_rx_cb != NULL)
338 {
339 fast_uart_dma_rx_cb();
340 }
341 }
342 if (p_uart_dma->tx_mcu_intr)
343 {
344 while (p_uart_dma->tx_busy)
345 ;
346 /* TX interrupt */
347 p_uart_dma->tx_intr_clr = 1; /* clear int status */
348 p_uart_dma->tx_intr_en = 0; /* disable tx int */
349
350 if (fast_uart_dma_tx_cb != NULL)
351 {
352 fast_uart_dma_tx_cb();
353 }
354 }
355 }
356
357 return;
358 }
359
MDrv_UrDMA_SelMode(URDMA_Mode eMode)360 void MDrv_UrDMA_SelMode(URDMA_Mode eMode)// void hs_uart_dma_mode_switch(U16 mode)
361 {
362 if (E_URDMA_DMA == eMode) /* UART DMA mode */
363 {
364 while (p_uart_dma->rx_busy) /* Wait for idle state. */
365 ;
366 /* switch to UART DMA mode. */
367 p_uart_dma->urdma_mode = 1;
368 }
369 else /* Normal uart mode */
370 {
371 p_uart_dma->tx_urdma_en = 0;/* Disable tx dma and start transmission. */
372 p_uart_dma->rx_urdma_en = 0;/* Disable rx dma and start receiving. */
373 while (p_uart_dma->rx_busy) /* Wait for idle state. */
374 ;
375
376 /* switch to UART mode. */
377 p_uart_dma->urdma_mode = 0;
378 }
379
380 return;
381 }
382
MDrv_UrDMA_Engine(MS_BOOL bEnable)383 void MDrv_UrDMA_Engine(MS_BOOL bEnable)//hs_uart_dma_enable(u_int8 enable)
384 {
385 p_uart_dma->urdma_mode = bEnable;
386 }
387
MDrv_UrDMA_Init(void * dma_rx_cb,void * dma_tx_cb,URDMA_OPmode eOp_mode)388 void MDrv_UrDMA_Init(void *dma_rx_cb, void *dma_tx_cb, URDMA_OPmode eOp_mode)
389 {
390 int i;
391 MS_VIRT virtBaseAddr;
392 MS_PHY u32BaseSize;
393
394 if(!MDrv_MMIO_GetBASE(&virtBaseAddr,&u32BaseSize,MS_MODULE_UART))
395 {
396 DEBUG_UART_DMA(E_URDMA_DBGLV_ERR_ONLY, ULOGE(TAG_UARTDMA,"%s():IOMap failure to get DRV_MMIO_NONPM_BANK\n",__FUNCTION__));
397 return;
398 }
399
400 virt_urdma_base = virtBaseAddr + FAST_UART_DMA_REG;
401
402 p_uart_dma = (dma_interface_t *)virt_urdma_base;
403 // p_uart_dma = (dma_interface_t *)0x20000;
404
405 /* disable tx and rx */
406 p_uart_dma->tx_urdma_en = 0;
407 p_uart_dma->rx_urdma_en = 0;
408
409 /* software reset */
410 p_uart_dma->sw_rst = 1;
411
412 //
413 // @@@ Dealy for HW, please use real timer!!!
414 //
415 for (i=0;i<0x100;i++)
416 ;
417
418 p_uart_dma->sw_rst = 0;
419
420 /* disable tx and rx */
421 p_uart_dma->tx_urdma_en = 0;
422 p_uart_dma->rx_urdma_en = 0;
423
424 /* make sure rx_busy is off */
425 while (p_uart_dma->rx_busy)
426 ; //@@@ add time out, here
427
428 p_uart_dma->reg00 = 0;
429
430 /* disable interrupt */
431 p_uart_dma->tx_intr_en = 0;
432 p_uart_dma->rx_intr1_en = 0;
433 p_uart_dma->rx_intr2_en = 0;
434
435 /* clear interrupt status */
436 p_uart_dma->tx_intr_clr = 1;
437 p_uart_dma->rx_intr_clr = 1;
438
439 _MDrv_UrDMA_RegisterCallback((void *) dma_rx_cb, (void *)dma_tx_cb);//register_hs_uart_dma_cb((void *) dma_rx_cb, (void *)dma_tx_cb);
440
441 /* ToDo: install_isr */
442
443 /* Always set RX operations mode 1, Line Buffer mode */
444 p_uart_dma->rx_op_mode = eOp_mode;
445
446 /* switch to UART mode. */
447 MDrv_UrDMA_SelMode(E_URDMA_DMA);//hs_uart_dma_enable(1);
448
449 }
450
451 #ifdef MS_DEBUG
MDrv_UrDMA_DumpREG(void)452 void MDrv_UrDMA_DumpREG(void)
453 {
454 if (p_uart_dma != NULL)
455 {
456 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg00, (int)p_uart_dma->reg00));
457 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg01, (int)p_uart_dma->reg01));
458 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg02, (int)p_uart_dma->reg02));
459 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg03, (int)p_uart_dma->reg03));
460 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg04, (int)p_uart_dma->reg04));
461 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg05, (int)p_uart_dma->reg05));
462 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg06, (int)p_uart_dma->reg06));
463 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg07, (int)p_uart_dma->reg07));
464 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg08, (int)p_uart_dma->reg08));
465 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg09, (int)p_uart_dma->reg09));
466 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg0a, (int)p_uart_dma->reg0a));
467 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg0b, (int)p_uart_dma->reg0b));
468 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg0c, (int)p_uart_dma->reg0c));
469 DEBUG_UART_DMA(E_URDMA_DBGLV_ALL, ULOGE(TAG_UARTDMA,"0x%x:0x%x\n", (int)&p_uart_dma->reg0d, (int)p_uart_dma->reg0d));
470 }
471 }
472 #endif
473
474