1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _RGA_DRIVER_H_ 3 #define _RGA_DRIVER_H_ 4 5 #include <linux/mutex.h> 6 #include <linux/scatterlist.h> 7 8 /* Use 'r' as magic number */ 9 #define RGA_IOC_MAGIC 'r' 10 #define RGA_IOW(nr, type) _IOW(RGA_IOC_MAGIC, nr, type) 11 #define RGA_IOR(nr, type) _IOR(RGA_IOC_MAGIC, nr, type) 12 #define RGA_IOWR(nr, type) _IOWR(RGA_IOC_MAGIC, nr, type) 13 14 #define RGA_IOC_GET_DRVIER_VERSION RGA_IOR(0x1, struct rga_version_t) 15 #define RGA_IOC_GET_HW_VERSION RGA_IOR(0x2, struct rga_hw_versions_t) 16 #define RGA_IOC_IMPORT_BUFFER RGA_IOWR(0x3, struct rga_buffer_pool) 17 #define RGA_IOC_RELEASE_BUFFER RGA_IOW(0x4, struct rga_buffer_pool) 18 #define RGA_IOC_REQUEST_CREATE RGA_IOR(0x5, uint32_t) 19 #define RGA_IOC_REQUEST_SUBMIT RGA_IOWR(0x6, struct rga_user_request) 20 #define RGA_IOC_REQUEST_CONFIG RGA_IOWR(0x7, struct rga_user_request) 21 #define RGA_IOC_REQUEST_CANCEL RGA_IOWR(0x8, uint32_t) 22 23 #define RGA_BLIT_SYNC 0x5017 24 #define RGA_BLIT_ASYNC 0x5018 25 #define RGA_FLUSH 0x5019 26 #define RGA_GET_RESULT 0x501a 27 #define RGA_GET_VERSION 0x501b 28 #define RGA_CACHE_FLUSH 0x501c 29 30 #define RGA2_GET_VERSION 0x601b 31 #define RGA_IMPORT_DMA 0x601d 32 #define RGA_RELEASE_DMA 0x601e 33 34 #define RGA_TASK_NUM_MAX 50 35 36 #define RGA_OUT_OF_RESOURCES -10 37 #define RGA_MALLOC_ERROR -11 38 39 #define SCALE_DOWN_LARGE 1 40 #define SCALE_UP_LARGE 1 41 42 #define RGA_BUFFER_POOL_SIZE_MAX 40 43 44 #define RGA3_MAJOR_VERSION_MASK (0xF0000000) 45 #define RGA3_MINOR_VERSION_MASK (0x0FF00000) 46 #define RGA3_SVN_VERSION_MASK (0x000FFFFF) 47 48 #define RGA2_MAJOR_VERSION_MASK (0xFF000000) 49 #define RGA2_MINOR_VERSION_MASK (0x00F00000) 50 #define RGA2_SVN_VERSION_MASK (0x000FFFFF) 51 52 #define RGA_MODE_ROTATE_0 (1<<0) 53 #define RGA_MODE_ROTATE_90 (1<<1) 54 #define RGA_MODE_ROTATE_180 (1<<2) 55 #define RGA_MODE_ROTATE_270 (1<<3) 56 #define RGA_MODE_X_MIRROR (1<<4) 57 #define RGA_MODE_Y_MIRROR (1<<5) 58 59 #define RGA_MODE_CSC_BT601L (1<<0) 60 #define RGA_MODE_CSC_BT601F (1<<1) 61 #define RGA_MODE_CSC_BT709 (1<<2) 62 #define RGA_MODE_CSC_BT2020 (1<<3) 63 64 #define RGA_MODE_ROTATE_MASK (\ 65 RGA_MODE_ROTATE_0 | \ 66 RGA_MODE_ROTATE_90 | \ 67 RGA_MODE_ROTATE_180 | \ 68 RGA_MODE_ROTATE_270 | \ 69 RGA_MODE_X_MIRROR | \ 70 RGA_MODE_Y_MIRROR) 71 72 enum rga_memory_type { 73 RGA_DMA_BUFFER = 0, 74 RGA_VIRTUAL_ADDRESS, 75 RGA_PHYSICAL_ADDRESS, 76 RGA_DMA_BUFFER_PTR, 77 }; 78 79 enum rga_scale_up_mode { 80 RGA_SCALE_UP_NONE = 0x0, 81 RGA_SCALE_UP_BIC = 0x1, 82 }; 83 84 enum rga_scale_down_mode { 85 RGA_SCALE_DOWN_NONE = 0x0, 86 RGA_SCALE_DOWN_AVG = 0x1, 87 }; 88 89 /* RGA process mode enum */ 90 enum { 91 BITBLT_MODE = 0x0, 92 COLOR_PALETTE_MODE = 0x1, 93 COLOR_FILL_MODE = 0x2, 94 /* used by rga2 */ 95 UPDATE_PALETTE_TABLE_MODE = 0x6, 96 UPDATE_PATTEN_BUF_MODE = 0x7, 97 }; /*render mode*/ 98 99 /* RGA rd_mode */ 100 enum { 101 RGA_RASTER_MODE = 0x1 << 0, 102 RGA_FBC_MODE = 0x1 << 1, 103 RGA_TILE_MODE = 0x1 << 2, 104 }; 105 106 enum { 107 RGA_10BIT_COMPACT = 0x0, 108 RGA_10BIT_INCOMPACT = 0x1, 109 }; 110 111 enum { 112 RGA_CONTEXT_NONE = 0x0, 113 RGA_CONTEXT_SRC_FIX_ENABLE = 0x1 << 0, 114 RGA_CONTEXT_SRC_CACHE_INFO = 0x1 << 1, 115 RGA_CONTEXT_SRC_MASK = RGA_CONTEXT_SRC_FIX_ENABLE | 116 RGA_CONTEXT_SRC_CACHE_INFO, 117 RGA_CONTEXT_PAT_FIX_ENABLE = 0x1 << 2, 118 RGA_CONTEXT_PAT_CACHE_INFO = 0x1 << 3, 119 RGA_CONTEXT_PAT_MASK = RGA_CONTEXT_PAT_FIX_ENABLE | 120 RGA_CONTEXT_PAT_CACHE_INFO, 121 RGA_CONTEXT_DST_FIX_ENABLE = 0x1 << 4, 122 RGA_CONTEXT_DST_CACHE_INFO = 0x1 << 5, 123 RGA_CONTEXT_DST_MASK = RGA_CONTEXT_DST_FIX_ENABLE | 124 RGA_CONTEXT_DST_CACHE_INFO, 125 }; 126 127 /* RGA feature */ 128 enum { 129 RGA_COLOR_FILL = 0x1 << 0, 130 RGA_COLOR_PALETTE = 0x1 << 1, 131 RGA_COLOR_KEY = 0x1 << 2, 132 RGA_ROP_CALCULATE = 0x1 << 3, 133 RGA_NN_QUANTIZE = 0x1 << 4, 134 RGA_OSD_BLEND = 0x1 << 5, 135 RGA_DITHER = 0x1 << 6, 136 RGA_MOSAIC = 0x1 << 7, 137 RGA_YIN_YOUT = 0x1 << 8, 138 RGA_YUV_HDS = 0x1 << 9, 139 RGA_YUV_VDS = 0x1 << 10, 140 RGA_OSD = 0x1 << 11, 141 RGA_PRE_INTR = 0x1 << 12, 142 }; 143 144 enum rga_surf_format { 145 RGA_FORMAT_RGBA_8888 = 0x0, 146 RGA_FORMAT_RGBX_8888 = 0x1, 147 RGA_FORMAT_RGB_888 = 0x2, 148 RGA_FORMAT_BGRA_8888 = 0x3, 149 RGA_FORMAT_RGB_565 = 0x4, 150 RGA_FORMAT_RGBA_5551 = 0x5, 151 RGA_FORMAT_RGBA_4444 = 0x6, 152 RGA_FORMAT_BGR_888 = 0x7, 153 154 RGA_FORMAT_YCbCr_422_SP = 0x8, 155 RGA_FORMAT_YCbCr_422_P = 0x9, 156 RGA_FORMAT_YCbCr_420_SP = 0xa, 157 RGA_FORMAT_YCbCr_420_P = 0xb, 158 159 RGA_FORMAT_YCrCb_422_SP = 0xc, 160 RGA_FORMAT_YCrCb_422_P = 0xd, 161 RGA_FORMAT_YCrCb_420_SP = 0xe, 162 RGA_FORMAT_YCrCb_420_P = 0xf, 163 164 RGA_FORMAT_BPP1 = 0x10, 165 RGA_FORMAT_BPP2 = 0x11, 166 RGA_FORMAT_BPP4 = 0x12, 167 RGA_FORMAT_BPP8 = 0x13, 168 169 RGA_FORMAT_Y4 = 0x14, 170 RGA_FORMAT_YCbCr_400 = 0x15, 171 172 RGA_FORMAT_BGRX_8888 = 0x16, 173 174 RGA_FORMAT_YVYU_422 = 0x18, 175 RGA_FORMAT_YVYU_420 = 0x19, 176 RGA_FORMAT_VYUY_422 = 0x1a, 177 RGA_FORMAT_VYUY_420 = 0x1b, 178 RGA_FORMAT_YUYV_422 = 0x1c, 179 RGA_FORMAT_YUYV_420 = 0x1d, 180 RGA_FORMAT_UYVY_422 = 0x1e, 181 RGA_FORMAT_UYVY_420 = 0x1f, 182 183 RGA_FORMAT_YCbCr_420_SP_10B = 0x20, 184 RGA_FORMAT_YCrCb_420_SP_10B = 0x21, 185 RGA_FORMAT_YCbCr_422_SP_10B = 0x22, 186 RGA_FORMAT_YCrCb_422_SP_10B = 0x23, 187 188 RGA_FORMAT_BGR_565 = 0x24, 189 RGA_FORMAT_BGRA_5551 = 0x25, 190 RGA_FORMAT_BGRA_4444 = 0x26, 191 192 RGA_FORMAT_ARGB_8888 = 0x28, 193 RGA_FORMAT_XRGB_8888 = 0x29, 194 RGA_FORMAT_ARGB_5551 = 0x2a, 195 RGA_FORMAT_ARGB_4444 = 0x2b, 196 RGA_FORMAT_ABGR_8888 = 0x2c, 197 RGA_FORMAT_XBGR_8888 = 0x2d, 198 RGA_FORMAT_ABGR_5551 = 0x2e, 199 RGA_FORMAT_ABGR_4444 = 0x2f, 200 201 RGA_FORMAT_RGBA_2BPP = 0x30, 202 203 RGA_FORMAT_UNKNOWN = 0x100, 204 }; 205 206 enum rga_alpha_mode { 207 RGA_ALPHA_STRAIGHT = 0, 208 RGA_ALPHA_INVERSE = 1, 209 }; 210 211 enum rga_global_blend_mode { 212 RGA_ALPHA_GLOBAL = 0, 213 RGA_ALPHA_PER_PIXEL = 1, 214 RGA_ALPHA_PER_PIXEL_GLOBAL = 2, 215 }; 216 217 enum rga_alpha_cal_mode { 218 RGA_ALPHA_SATURATION = 0, 219 RGA_ALPHA_NO_SATURATION = 1, 220 }; 221 222 enum rga_factor_mode { 223 RGA_ALPHA_ZERO = 0, 224 RGA_ALPHA_ONE = 1, 225 /* 226 * When used as a factor for the SRC channel, it indicates 227 * the use of the DST channel's alpha value, and vice versa. 228 */ 229 RGA_ALPHA_OPPOSITE = 2, 230 RGA_ALPHA_OPPOSITE_INVERSE = 3, 231 RGA_ALPHA_OWN = 4, 232 }; 233 234 enum rga_color_mode { 235 RGA_ALPHA_PRE_MULTIPLIED = 0, 236 RGA_ALPHA_NO_PRE_MULTIPLIED = 1, 237 }; 238 239 enum rga_alpha_blend_mode { 240 RGA_ALPHA_NONE = 0, 241 RGA_ALPHA_BLEND_SRC, 242 RGA_ALPHA_BLEND_DST, 243 RGA_ALPHA_BLEND_SRC_OVER, 244 RGA_ALPHA_BLEND_DST_OVER, 245 RGA_ALPHA_BLEND_SRC_IN, 246 RGA_ALPHA_BLEND_DST_IN, 247 RGA_ALPHA_BLEND_SRC_OUT, 248 RGA_ALPHA_BLEND_DST_OUT, 249 RGA_ALPHA_BLEND_SRC_ATOP, 250 RGA_ALPHA_BLEND_DST_ATOP, 251 RGA_ALPHA_BLEND_XOR, 252 RGA_ALPHA_BLEND_CLEAR, 253 }; 254 255 #define RGA_SCHED_PRIORITY_DEFAULT 0 256 #define RGA_SCHED_PRIORITY_MAX 6 257 258 #define RGA_VERSION_SIZE 16 259 #define RGA_HW_SIZE 5 260 261 struct rga_version_t { 262 uint32_t major; 263 uint32_t minor; 264 uint32_t revision; 265 uint8_t str[RGA_VERSION_SIZE]; 266 }; 267 268 struct rga_hw_versions_t { 269 struct rga_version_t version[RGA_HW_SIZE]; 270 uint32_t size; 271 }; 272 273 struct rga_memory_parm { 274 uint32_t width; 275 uint32_t height; 276 uint32_t format; 277 278 uint32_t size; 279 }; 280 281 struct rga_external_buffer { 282 uint64_t memory; 283 uint32_t type; 284 285 uint32_t handle; 286 struct rga_memory_parm memory_parm; 287 288 uint8_t reserve[252]; 289 }; 290 291 struct rga_buffer_pool { 292 uint64_t buffers_ptr; 293 uint32_t size; 294 }; 295 296 struct rga_mmu_info_t { 297 unsigned long src0_base_addr; 298 unsigned long src1_base_addr; 299 unsigned long dst_base_addr; 300 unsigned long els_base_addr; 301 302 /* [0] mmu enable [1] flush [2] prefetch_en [3] prefetch dir */ 303 u8 src0_mmu_flag; 304 u8 src1_mmu_flag; 305 u8 dst_mmu_flag; 306 u8 els_mmu_flag; 307 }; 308 309 struct rga_color_fill_t { 310 int16_t gr_x_a; 311 int16_t gr_y_a; 312 int16_t gr_x_b; 313 int16_t gr_y_b; 314 int16_t gr_x_g; 315 int16_t gr_y_g; 316 int16_t gr_x_r; 317 int16_t gr_y_r; 318 }; 319 320 /***************************************/ 321 /* porting from rga.h for msg convert */ 322 /***************************************/ 323 324 struct rga_fading_t { 325 uint8_t b; 326 uint8_t g; 327 uint8_t r; 328 uint8_t res; 329 }; 330 331 struct rga_mmu_t { 332 uint8_t mmu_en; 333 uint64_t base_addr; 334 /* 335 * [0] mmu enable [1] src_flush [2] dst_flush 336 * [3] CMD_flush [4~5] page size 337 */ 338 uint32_t mmu_flag; 339 }; 340 341 struct rga_rect_t { 342 uint16_t xmin; 343 /* width - 1 */ 344 uint16_t xmax; 345 uint16_t ymin; 346 /* height - 1 */ 347 uint16_t ymax; 348 }; 349 350 struct rga_point_t { 351 uint16_t x; 352 uint16_t y; 353 }; 354 355 struct rga_line_draw_t { 356 /* LineDraw_start_point */ 357 struct rga_point_t start_point; 358 /* LineDraw_end_point */ 359 struct rga_point_t end_point; 360 /* LineDraw_color */ 361 uint32_t color; 362 /* (enum) LineDrawing mode sel */ 363 uint32_t flag; 364 /* range 1~16 */ 365 uint32_t line_width; 366 }; 367 368 /* color space convert coefficient. */ 369 struct rga_csc_coe { 370 int16_t r_v; 371 int16_t g_y; 372 int16_t b_u; 373 int32_t off; 374 }; 375 376 struct rga_full_csc { 377 uint8_t flag; 378 struct rga_csc_coe coe_y; 379 struct rga_csc_coe coe_u; 380 struct rga_csc_coe coe_v; 381 }; 382 383 struct rga_mosaic_info { 384 uint8_t enable; 385 uint8_t mode; 386 }; 387 388 /* MAX(min, (max - channel_value)) */ 389 struct rga_osd_invert_factor { 390 uint8_t alpha_max; 391 uint8_t alpha_min; 392 uint8_t yg_max; 393 uint8_t yg_min; 394 uint8_t crb_max; 395 uint8_t crb_min; 396 }; 397 398 struct rga_color { 399 union { 400 struct { 401 uint8_t red; 402 uint8_t green; 403 uint8_t blue; 404 uint8_t alpha; 405 }; 406 uint32_t value; 407 }; 408 }; 409 410 struct rga_osd_bpp2 { 411 uint8_t ac_swap; // ac swap flag 412 // 0: CA 413 // 1: AC 414 uint8_t endian_swap; // rgba2bpp endian swap 415 // 0: Big endian 416 // 1: Little endian 417 struct rga_color color0; 418 struct rga_color color1; 419 }; 420 421 struct rga_osd_mode_ctrl { 422 uint8_t mode; // OSD cal mode: 423 // 0b'1: statistics mode 424 // 1b'1: auto inversion overlap mode 425 uint8_t direction_mode; // horizontal or vertical 426 // 0: horizontal 427 // 1: vertical 428 uint8_t width_mode; // using @fix_width or LUT width 429 // 0: fix width 430 // 1: LUT width 431 uint16_t block_fix_width; // OSD block fixed width 432 // real width = (fix_width + 1) * 2 433 uint8_t block_num; // OSD block num 434 uint16_t flags_index; // auto invert flags index 435 436 /* invertion config */ 437 uint8_t color_mode; // selete color 438 // 0: src1 color 439 // 1: config data color 440 uint8_t invert_flags_mode; // invert flag selete 441 // 0: use RAM flag 442 // 1: usr last result 443 uint8_t default_color_sel; // default color mode 444 // 0: default is bright 445 // 1: default is dark 446 uint8_t invert_enable; // invert channel enable 447 // 1 << 0: alpha enable 448 // 1 << 1: Y/G disable 449 // 1 << 3: C/RB disable 450 uint8_t invert_mode; // invert cal mode 451 // 0: normal(max-data) 452 // 1: swap 453 uint8_t invert_thresh; // if luma > thresh, osd_flag to be 1 454 uint8_t unfix_index; // OSD width config index 455 }; 456 457 struct rga_osd_info { 458 uint8_t enable; 459 460 struct rga_osd_mode_ctrl mode_ctrl; 461 struct rga_osd_invert_factor cal_factor; 462 struct rga_osd_bpp2 bpp2_info; 463 464 union { 465 struct { 466 uint32_t last_flags0; 467 uint32_t last_flags1; 468 }; 469 uint64_t last_flags; 470 }; 471 472 union { 473 struct { 474 uint32_t cur_flags0; 475 uint32_t cur_flags1; 476 }; 477 uint64_t cur_flags; 478 }; 479 }; 480 481 struct rga_pre_intr_info { 482 uint8_t enable; 483 484 uint8_t read_intr_en; 485 uint8_t write_intr_en; 486 uint8_t read_hold_en; 487 uint32_t read_threshold; 488 uint32_t write_start; 489 uint32_t write_step; 490 }; 491 492 struct rga_win_info_t { 493 /* yrgb mem addr */ 494 unsigned long yrgb_addr; 495 /* cb/cr mem addr */ 496 unsigned long uv_addr; 497 /* cr mem addr */ 498 unsigned long v_addr; 499 /* definition by RK_FORMAT */ 500 unsigned int format; 501 502 unsigned short src_act_w; 503 unsigned short src_act_h; 504 505 unsigned short dst_act_w; 506 unsigned short dst_act_h; 507 508 unsigned short x_offset; 509 unsigned short y_offset; 510 511 unsigned short vir_w; 512 unsigned short vir_h; 513 514 unsigned short y2r_mode; 515 unsigned short r2y_mode; 516 517 unsigned short rotate_mode; 518 /* RASTER or FBCD or TILE */ 519 unsigned short rd_mode; 520 521 unsigned short is_10b_compact; 522 unsigned short is_10b_endian; 523 524 unsigned short enable; 525 }; 526 527 struct rga_img_info_t { 528 /* yrgb mem addr */ 529 uint64_t yrgb_addr; 530 /* cb/cr mem addr */ 531 uint64_t uv_addr; 532 /* cr mem addr */ 533 uint64_t v_addr; 534 /* definition by RK_FORMAT */ 535 uint32_t format; 536 537 uint16_t act_w; 538 uint16_t act_h; 539 uint16_t x_offset; 540 uint16_t y_offset; 541 542 uint16_t vir_w; 543 uint16_t vir_h; 544 545 uint16_t endian_mode; 546 /* useless */ 547 uint16_t alpha_swap; 548 549 /* used by RGA3 */ 550 uint16_t rotate_mode; 551 uint16_t rd_mode; 552 553 uint16_t compact_mode; 554 uint16_t is_10b_endian; 555 556 uint16_t enable; 557 }; 558 559 struct rga_req { 560 /* (enum) process mode sel */ 561 uint8_t render_mode; 562 563 struct rga_img_info_t src; 564 struct rga_img_info_t dst; 565 struct rga_img_info_t pat; 566 567 /* rop4 mask addr */ 568 uint64_t rop_mask_addr; 569 /* LUT addr */ 570 uint64_t LUT_addr; 571 572 /* dst clip window default value is dst_vir */ 573 /* value from [0, w-1] / [0, h-1]*/ 574 struct rga_rect_t clip; 575 576 /* dst angle default value 0 16.16 scan from table */ 577 int32_t sina; 578 /* dst angle default value 0 16.16 scan from table */ 579 int32_t cosa; 580 581 /* alpha rop process flag */ 582 /* ([0] = 1 alpha_rop_enable) */ 583 /* ([1] = 1 rop enable) */ 584 /* ([2] = 1 fading_enable) */ 585 /* ([3] = 1 PD_enable) */ 586 /* ([4] = 1 alpha cal_mode_sel) */ 587 /* ([5] = 1 dither_enable) */ 588 /* ([6] = 1 gradient fill mode sel) */ 589 /* ([7] = 1 AA_enable) */ 590 uint16_t alpha_rop_flag; 591 592 /* 0 nearst / 1 bilnear / 2 bicubic */ 593 uint8_t scale_mode; 594 595 /* color key max */ 596 uint32_t color_key_max; 597 /* color key min */ 598 uint32_t color_key_min; 599 600 /* foreground color */ 601 uint32_t fg_color; 602 /* background color */ 603 uint32_t bg_color; 604 605 /* color fill use gradient */ 606 struct rga_color_fill_t gr_color; 607 608 struct rga_line_draw_t line_draw_info; 609 610 struct rga_fading_t fading; 611 612 /* porter duff alpha mode sel */ 613 uint8_t PD_mode; 614 615 /* global alpha value */ 616 uint8_t alpha_global_value; 617 618 /* rop2/3/4 code scan from rop code table*/ 619 uint16_t rop_code; 620 621 /* [2] 0 blur 1 sharp / [1:0] filter_type*/ 622 uint8_t bsfilter_flag; 623 624 /* (enum) color palette 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 625 uint8_t palette_mode; 626 627 /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 628 uint8_t yuv2rgb_mode; 629 630 /* 0/big endian 1/little endian*/ 631 uint8_t endian_mode; 632 633 /* (enum) rotate mode */ 634 /* 0x0, no rotate */ 635 /* 0x1, rotate */ 636 /* 0x2, x_mirror */ 637 /* 0x3, y_mirror */ 638 uint8_t rotate_mode; 639 640 /* 0 solid color / 1 pattern color */ 641 uint8_t color_fill_mode; 642 643 /* mmu information */ 644 struct rga_mmu_t mmu_info; 645 646 /* ([0~1] alpha mode) */ 647 /* ([2~3] rop mode) */ 648 /* ([4] zero mode en) */ 649 /* ([5] dst alpha mode) */ 650 /* ([6] alpha output mode sel) 0 src / 1 dst*/ 651 uint8_t alpha_rop_mode; 652 653 uint8_t src_trans_mode; 654 655 uint8_t dither_mode; 656 657 /* full color space convert */ 658 struct rga_full_csc full_csc; 659 660 int32_t in_fence_fd; 661 uint8_t core; 662 uint8_t priority; 663 int32_t out_fence_fd; 664 665 uint8_t handle_flag; 666 667 /* RGA2 1106 add */ 668 struct rga_mosaic_info mosaic_info; 669 670 uint8_t uvhds_mode; 671 uint8_t uvvds_mode; 672 673 struct rga_osd_info osd_info; 674 675 struct rga_pre_intr_info pre_intr_info; 676 677 uint8_t reservr[59]; 678 }; 679 680 struct rga_alpha_config { 681 bool enable; 682 bool fg_pre_multiplied; 683 bool bg_pre_multiplied; 684 bool fg_pixel_alpha_en; 685 bool bg_pixel_alpha_en; 686 bool fg_global_alpha_en; 687 bool bg_global_alpha_en; 688 uint16_t fg_global_alpha_value; 689 uint16_t bg_global_alpha_value; 690 enum rga_alpha_blend_mode mode; 691 }; 692 693 struct rga2_req { 694 /* (enum) process mode sel */ 695 u8 render_mode; 696 697 /* active window */ 698 struct rga_img_info_t src; 699 struct rga_img_info_t src1; 700 struct rga_img_info_t dst; 701 struct rga_img_info_t pat; 702 703 /* rop4 mask addr */ 704 unsigned long rop_mask_addr; 705 /* LUT addr */ 706 unsigned long LUT_addr; 707 708 u32 rop_mask_stride; 709 710 /* 0: SRC + DST => DST */ 711 /* 1: SRC + SRC1 => DST */ 712 u8 bitblt_mode; 713 714 /* [1:0] */ 715 /* 0 degree 0x0 */ 716 /* 90 degree 0x1 */ 717 /* 180 degree 0x2 */ 718 /* 270 degree 0x3 */ 719 /* [5:4] */ 720 /* none 0x0 */ 721 /* x_mirror 0x1 */ 722 /* y_mirror 0x2 */ 723 /* x_mirror + y_mirror 0x3 */ 724 u8 rotate_mode; 725 726 /* alpha rop process flag */ 727 /* ([0] = 1 alpha_rop_enable) */ 728 /* ([1] = 1 rop enable) */ 729 /* ([2] = 1 fading_enable) */ 730 /* ([3] = 1 alpha cal_mode_sel) */ 731 /* ([4] = 1 src_dither_up_enable) */ 732 /* ([5] = 1 dst_dither_up_enable) */ 733 /* ([6] = 1 dither_down_enable) */ 734 /* ([7] = 1 gradient fill mode sel) */ 735 u16 alpha_rop_flag; 736 737 struct rga_alpha_config alpha_config; 738 739 /* 0 1 2 3 */ 740 u8 scale_bicu_mode; 741 742 u32 color_key_max; 743 u32 color_key_min; 744 745 /* foreground color */ 746 u32 fg_color; 747 /* background color */ 748 u32 bg_color; 749 750 u8 color_fill_mode; 751 /* color fill use gradient */ 752 struct rga_color_fill_t gr_color; 753 754 /* Fading value */ 755 u8 fading_alpha_value; 756 u8 fading_r_value; 757 u8 fading_g_value; 758 u8 fading_b_value; 759 760 /* src global alpha value */ 761 u8 src_a_global_val; 762 /* dst global alpha value */ 763 u8 dst_a_global_val; 764 765 /* rop mode select 0 : rop2 1 : rop3 2 : rop4 */ 766 u8 rop_mode; 767 /* rop2/3/4 code */ 768 u16 rop_code; 769 770 /* (enum) color palette 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 771 u8 palette_mode; 772 773 /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 774 u8 yuv2rgb_mode; 775 776 u8 full_csc_en; 777 778 /* 0/little endian 1/big endian */ 779 u8 endian_mode; 780 781 u8 CMD_fin_int_enable; 782 783 /* mmu information */ 784 struct rga_mmu_info_t mmu_info; 785 786 u8 alpha_zero_key; 787 u8 src_trans_mode; 788 789 /* useless */ 790 u8 alpha_swp; 791 u8 dither_mode; 792 793 u8 rgb2yuv_mode; 794 795 /* RGA2 1106 add */ 796 struct rga_mosaic_info mosaic_info; 797 798 uint8_t yin_yout_en; 799 800 uint8_t uvhds_mode; 801 uint8_t uvvds_mode; 802 803 struct rga_osd_info osd_info; 804 }; 805 806 struct rga3_req { 807 /* (enum) process mode sel */ 808 u8 render_mode; 809 810 struct rga_win_info_t win0; 811 struct rga_win_info_t wr; 812 struct rga_win_info_t win1; 813 814 /* rop4 mask addr */ 815 unsigned long rop_mask_addr; 816 unsigned long LUT_addr; 817 818 u32 rop_mask_stride; 819 820 u8 bitblt_mode; 821 u8 rotate_mode; 822 823 u16 alpha_rop_flag; 824 825 struct rga_alpha_config alpha_config; 826 827 /* for abb mode presever alpha. */ 828 bool abb_alpha_pass; 829 830 u8 scale_bicu_mode; 831 832 u32 color_key_max; 833 u32 color_key_min; 834 835 u32 fg_color; 836 u32 bg_color; 837 838 u8 color_fill_mode; 839 struct rga_color_fill_t gr_color; 840 841 u8 fading_alpha_value; 842 u8 fading_r_value; 843 u8 fading_g_value; 844 u8 fading_b_value; 845 846 /* win0 global alpha value */ 847 u8 win0_a_global_val; 848 /* win1 global alpha value */ 849 u8 win1_a_global_val; 850 851 u8 rop_mode; 852 u16 rop_code; 853 854 u8 palette_mode; 855 856 u8 yuv2rgb_mode; 857 858 u8 endian_mode; 859 860 u8 CMD_fin_int_enable; 861 862 struct rga_mmu_info_t mmu_info; 863 864 u8 alpha_zero_key; 865 u8 src_trans_mode; 866 867 u8 alpha_swp; 868 u8 dither_mode; 869 870 u8 rgb2yuv_mode; 871 }; 872 873 struct rga_video_frame_info { 874 uint32_t x_offset; 875 uint32_t y_offset; 876 uint32_t width; 877 uint32_t height; 878 uint32_t format; 879 uint32_t vir_w; 880 uint32_t vir_h; 881 uint32_t rd_mode; 882 }; 883 884 struct rga_mpi_job_t { 885 struct dma_buf *dma_buf_src0; 886 struct dma_buf *dma_buf_src1; 887 struct dma_buf *dma_buf_dst; 888 889 struct rga_video_frame_info *src; 890 struct rga_video_frame_info *pat; 891 struct rga_video_frame_info *dst; 892 struct rga_video_frame_info *output; 893 894 int ctx_id; 895 }; 896 897 struct rga_user_request { 898 uint64_t task_ptr; 899 uint32_t task_num; 900 uint32_t id; 901 uint32_t sync_mode; 902 uint32_t release_fence_fd; 903 904 uint32_t mpi_config_flags; 905 906 uint32_t acquire_fence_fd; 907 908 uint8_t reservr[120]; 909 }; 910 911 int rga_mpi_commit(struct rga_mpi_job_t *mpi_job); 912 913 #endif /*_RGA_DRIVER_H_*/ 914