1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * BCM43XX PCIE core hardware definitions. 4 * 5 * Copyright (C) 1999-2017, Broadcom Corporation 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: pcie_core.h 673814 2016-12-05 06:10:24Z $ 29 */ 30 #ifndef _PCIE_CORE_H 31 #define _PCIE_CORE_H 32 33 #include <sbhnddma.h> 34 #include <siutils.h> 35 36 /* cpp contortions to concatenate w/arg prescan */ 37 #ifndef PAD 38 #define _PADLINE(line) pad ## line 39 #define _XSTR(line) _PADLINE(line) 40 #define PAD _XSTR(__LINE__) 41 #endif 42 43 /* PCIE Enumeration space offsets */ 44 #define PCIE_CORE_CONFIG_OFFSET 0x0 45 #define PCIE_FUNC0_CONFIG_OFFSET 0x400 46 #define PCIE_FUNC1_CONFIG_OFFSET 0x500 47 #define PCIE_FUNC2_CONFIG_OFFSET 0x600 48 #define PCIE_FUNC3_CONFIG_OFFSET 0x700 49 #define PCIE_SPROM_SHADOW_OFFSET 0x800 50 #define PCIE_SBCONFIG_OFFSET 0xE00 51 52 53 #define PCIEDEV_MAX_DMAS 4 54 55 /* PCIE Bar0 Address Mapping. Each function maps 16KB config space */ 56 #define PCIE_DEV_BAR0_SIZE 0x4000 57 #define PCIE_BAR0_WINMAPCORE_OFFSET 0x0 58 #define PCIE_BAR0_EXTSPROM_OFFSET 0x1000 59 #define PCIE_BAR0_PCIECORE_OFFSET 0x2000 60 #define PCIE_BAR0_CCCOREREG_OFFSET 0x3000 61 62 /* different register spaces to access thr'u pcie indirect access */ 63 #define PCIE_CONFIGREGS 1 /* Access to config space */ 64 #define PCIE_PCIEREGS 2 /* Access to pcie registers */ 65 66 #define PCIEDEV_HOSTADDR_MAP_BASE 0x8000000 67 #define PCIEDEV_HOSTADDR_MAP_WIN_MASK 0xFC000000 68 69 /* dma regs to control the flow between host2dev and dev2host */ 70 typedef volatile struct pcie_devdmaregs { 71 dma64regs_t tx; 72 uint32 PAD[2]; 73 dma64regs_t rx; 74 uint32 PAD[2]; 75 } pcie_devdmaregs_t; 76 77 #define PCIE_DB_HOST2DEV_0 0x1 78 #define PCIE_DB_HOST2DEV_1 0x2 79 #define PCIE_DB_DEV2HOST_0 0x3 80 #define PCIE_DB_DEV2HOST_1 0x4 81 82 /* door bell register sets */ 83 typedef struct pcie_doorbell { 84 uint32 host2dev_0; 85 uint32 host2dev_1; 86 uint32 dev2host_0; 87 uint32 dev2host_1; 88 } pcie_doorbell_t; 89 90 /* Flow Ring Manager */ 91 #define IFRM_FR_IDX_MAX 256 92 #define IFRM_FR_GID_MAX 4 93 #define IFRM_FR_DEV_MAX 8 94 #define IFRM_FR_TID_MAX 8 95 #define IFRM_FR_DEV_VALID 2 96 97 #define IFRM_VEC_REG_BITS 32 98 99 #define IFRM_FR_PER_VECREG 4 100 #define IFRM_FR_PER_VECREG_SHIFT 2 101 #define IFRM_FR_PER_VECREG_MASK ((0x1 << IFRM_FR_PER_VECREG_SHIFT) - 1) 102 103 #define IFRM_VEC_BITS_PER_FR (IFRM_VEC_REG_BITS/IFRM_FR_PER_VECREG) 104 105 /* IFRM_DEV_0 : d11AC, IFRM_DEV_1 : d11AD */ 106 #define IFRM_DEV_0 0 107 #define IFRM_DEV_1 1 108 109 #define IFRM_FR_GID_0 0 110 #define IFRM_FR_GID_1 1 111 #define IFRM_FR_GID_2 2 112 #define IFRM_FR_GID_3 3 113 114 #define IFRM_TIDMASK 0xffffffff 115 116 /* ifrm_ctrlst register */ 117 #define IFRM_EN (1<<0) 118 #define IFRM_BUFF_INIT_DONE (1<<1) 119 #define IFRM_COMPARE_EN0 (1<<4) 120 #define IFRM_COMPARE_EN1 (1<<5) 121 #define IFRM_COMPARE_EN2 (1<<6) 122 #define IFRM_COMPARE_EN3 (1<<7) 123 #define IFRM_INIT_DV0 (1<<8) 124 #define IFRM_INIT_DV1 (1<<9) 125 #define IFRM_INIT_DV2 (1<<10) 126 #define IFRM_INIT_DV3 (1<<11) 127 128 /* ifrm_msk_arr.addr, ifrm_tid_arr.addr register */ 129 #define IFRM_ADDR_SHIFT 0 130 #define IFRM_FRG_ID_SHIFT 8 131 132 /* ifrm_vec.diff_lat register */ 133 #define IFRM_DV_LAT (1<<0) 134 #define IFRM_DV_LAT_DONE (1<<1) 135 #define IFRM_SDV_OFFSET_SHIFT 4 136 #define IFRM_SDV_FRGID_SHIFT 8 137 #define IFRM_VECSTAT_MASK 0x3 138 #define IFRM_VEC_MASK 0xff 139 140 /* idma frm array */ 141 typedef struct pcie_ifrm_array { 142 uint32 addr; 143 uint32 data; 144 } pcie_ifrm_array_t; 145 146 /* idma frm vector */ 147 typedef struct pcie_ifrm_vector { 148 uint32 diff_lat; 149 uint32 sav_tid; 150 uint32 sav_diff; 151 uint32 PAD[1]; 152 } pcie_ifrm_vector_t; 153 154 /* idma frm interrupt */ 155 typedef struct pcie_ifrm_intr { 156 uint32 intstat; 157 uint32 intmask; 158 } pcie_ifrm_intr_t; 159 160 /* SB side: PCIE core and host control registers */ 161 typedef volatile struct sbpcieregs { 162 uint32 control; /* host mode only */ 163 uint32 iocstatus; /* PCIE2: iostatus */ 164 uint32 PAD[1]; 165 uint32 biststatus; /* bist Status: 0x00C */ 166 uint32 gpiosel; /* PCIE gpio sel: 0x010 */ 167 uint32 gpioouten; /* PCIE gpio outen: 0x14 */ 168 uint32 PAD[2]; 169 uint32 intstatus; /* Interrupt status: 0x20 */ 170 uint32 intmask; /* Interrupt mask: 0x24 */ 171 uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ 172 uint32 obffcontrol; /* PCIE2: 0x2C */ 173 uint32 obffintstatus; /* PCIE2: 0x30 */ 174 uint32 obffdatastatus; /* PCIE2: 0x34 */ 175 uint32 PAD[1]; 176 uint32 ctoctrl; /* PCIE2: 0x3C */ 177 uint32 errlog; /* PCIE2: 0x40 */ 178 uint32 errlogaddr; /* PCIE2: 0x44 */ 179 uint32 mailboxint; /* PCIE2: 0x48 */ 180 uint32 mailboxintmsk; /* PCIE2: 0x4c */ 181 uint32 ltrspacing; /* PCIE2: 0x50 */ 182 uint32 ltrhysteresiscnt; /* PCIE2: 0x54 */ 183 uint32 msivectorassign; /* PCIE2: 0x58 */ 184 uint32 intmask2; /* PCIE2: 0x5C */ 185 uint32 PAD[40]; 186 uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ 187 uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ 188 uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ 189 uint32 PAD[5]; 190 191 /* pcie core supports in direct access to config space */ 192 uint32 configaddr; /* pcie config space access: Address field: 0x120 */ 193 uint32 configdata; /* pcie config space access: Data field: 0x124 */ 194 union { 195 struct { 196 /* mdio access to serdes */ 197 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 198 uint32 mdiodata; /* Data to the mdio access: 0x12c */ 199 /* pcie protocol phy/dllp/tlp register indirect access mechanism */ 200 uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ 201 uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ 202 uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ 203 uint32 PAD[177]; 204 /* 0x400 - 0x7FF, PCIE Cfg Space, note: not used anymore in PcieGen2 */ 205 uint32 pciecfg[4][64]; 206 } pcie1; 207 struct { 208 /* mdio access to serdes */ 209 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 210 uint32 mdiowrdata; /* write data to mdio 0x12C */ 211 uint32 mdiorddata; /* read data to mdio 0x130 */ 212 uint32 PAD[3]; /* 0x134-0x138-0x13c */ 213 /* door bell registers available from gen2 rev5 onwards */ 214 pcie_doorbell_t dbls[PCIEDEV_MAX_DMAS]; /* 0x140 - 0x17F */ 215 uint32 dataintf; /* 0x180 */ 216 uint32 PAD[1]; /* 0x184 */ 217 uint32 d2h_intrlazy_0; /* 0x188 */ 218 uint32 h2d_intrlazy_0; /* 0x18c */ 219 uint32 h2d_intstat_0; /* 0x190 */ 220 uint32 h2d_intmask_0; /* 0x194 */ 221 uint32 d2h_intstat_0; /* 0x198 */ 222 uint32 d2h_intmask_0; /* 0x19c */ 223 uint32 ltr_state; /* 0x1A0 */ 224 uint32 pwr_int_status; /* 0x1A4 */ 225 uint32 pwr_int_mask; /* 0x1A8 */ 226 uint32 pme_source; /* 0x1AC */ 227 uint32 err_hdr_logreg1; /* 0x1B0 */ 228 uint32 err_hdr_logreg2; /* 0x1B4 */ 229 uint32 err_hdr_logreg3; /* 0x1B8 */ 230 uint32 err_hdr_logreg4; /* 0x1BC */ 231 uint32 err_code_logreg; /* 0x1C0 */ 232 uint32 PAD[7]; /* 0x1C4 - 0x1DF */ 233 uint32 clk_ctl_st; /* 0x1E0 */ 234 uint32 PAD[1]; /* 0x1E4 */ 235 uint32 powerctl; /* 0x1E8 */ 236 uint32 PAD[5]; /* 0x1EC - 0x1FF */ 237 pcie_devdmaregs_t h2d0_dmaregs; /* 0x200 - 0x23c */ 238 pcie_devdmaregs_t d2h0_dmaregs; /* 0x240 - 0x27c */ 239 pcie_devdmaregs_t h2d1_dmaregs; /* 0x280 - 0x2bc */ 240 pcie_devdmaregs_t d2h1_dmaregs; /* 0x2c0 - 0x2fc */ 241 pcie_devdmaregs_t h2d2_dmaregs; /* 0x300 - 0x33c */ 242 pcie_devdmaregs_t d2h2_dmaregs; /* 0x340 - 0x37c */ 243 pcie_devdmaregs_t h2d3_dmaregs; /* 0x380 - 0x3bc */ 244 pcie_devdmaregs_t d2h3_dmaregs; /* 0x3c0 - 0x3fc */ 245 uint32 d2h_intrlazy_1; /* 0x400 */ 246 uint32 h2d_intrlazy_1; /* 0x404 */ 247 uint32 h2d_intstat_1; /* 0x408 */ 248 uint32 h2d_intmask_1; /* 0x40c */ 249 uint32 d2h_intstat_1; /* 0x410 */ 250 uint32 d2h_intmask_1; /* 0x414 */ 251 uint32 PAD[2]; /* 0x418 - 0x41C */ 252 uint32 d2h_intrlazy_2; /* 0x420 */ 253 uint32 h2d_intrlazy_2; /* 0x424 */ 254 uint32 h2d_intstat_2; /* 0x428 */ 255 uint32 h2d_intmask_2; /* 0x42c */ 256 uint32 d2h_intstat_2; /* 0x430 */ 257 uint32 d2h_intmask_2; /* 0x434 */ 258 uint32 PAD[10]; /* 0x438 - 0x45F */ 259 uint32 ifrm_ctrlst; /* 0x460 */ 260 uint32 PAD[1]; /* 0x464 */ 261 pcie_ifrm_array_t ifrm_msk_arr; /* 0x468 - 0x46F */ 262 pcie_ifrm_array_t ifrm_tid_arr[IFRM_FR_DEV_VALID]; 263 /* 0x470 - 0x47F */ 264 pcie_ifrm_vector_t ifrm_vec[IFRM_FR_DEV_MAX]; 265 /* 0x480 - 0x4FF */ 266 pcie_ifrm_intr_t ifrm_intr[IFRM_FR_DEV_MAX]; 267 /* 0x500 - 0x53F */ 268 uint32 PAD[48]; /* 0x540 - 0x5FF */ 269 uint32 PAD[2][64]; /* 0x600 - 0x7FF */ 270 } pcie2; 271 } u; 272 uint16 sprom[64]; /* SPROM shadow Area : 0x800 - 0x880 */ 273 uint32 PAD[96]; /* 0x880 - 0x9FF */ 274 /* direct memory access (pcie2 rev19 and after) : 0xA00 - 0xAFF */ 275 uint32 PAD[16]; /* 0xA00 - 0xA3F */ 276 uint32 dm_errlog; /* 0xA40 */ 277 uint32 dm_erraddr; /* 0xA44 */ 278 uint32 PAD[37]; /* 0xA48 - 0xADC */ 279 uint32 dm_clk_ctl_st; /* 0xAE0 */ 280 uint32 PAD[1]; /* 0xAE4 */ 281 uint32 dm_powerctl; /* 0xAE8 */ 282 } sbpcieregs_t; 283 284 #define PCIE_CFG_DA_OFFSET 0x400 /* direct access register offset for configuration space */ 285 286 /* PCI control */ 287 #define PCIE_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ 288 #define PCIE_RST 0x02 /* Value driven out to pin */ 289 #define PCIE_SPERST 0x04 /* SurvivePeRst */ 290 #define PCIE_FORCECFGCLKON_ALP 0x08 291 #define PCIE_DISABLE_L1CLK_GATING 0x10 292 #define PCIE_DLYPERST 0x100 /* Delay PeRst to CoE Core */ 293 #define PCIE_DISSPROMLD 0x200 /* DisableSpromLoadOnPerst */ 294 #define PCIE_WakeModeL2 0x1000 /* Wake on L2 */ 295 #define PCIE_MULTIMSI_EN 0x2000 /* enable multi-vector MSI messages */ 296 #define PCIE_PipeIddqDisable0 0x8000 /* Disable assertion of pcie_pipe_iddq during L1.2 and L2 */ 297 #define PCIE_PipeIddqDisable1 0x10000 /* Disable assertion of pcie_pipe_iddq during L2 */ 298 #define PCIE_MSI_B2B_EN 0x100000 /* enable back-to-back MSI messages */ 299 #define PCIE_MSI_FIFO_CLEAR 0x200000 /* reset MSI FIFO */ 300 #define PCIE_IDMA_MODE_EN 0x800000 /* implicit M2M DMA mode */ 301 302 #define PCIE_CFGADDR 0x120 /* offsetof(configaddr) */ 303 #define PCIE_CFGDATA 0x124 /* offsetof(configdata) */ 304 #define PCIE_SWPME_FN0 0x10000 305 #define PCIE_SWPME_FN0_SHF 16 306 307 /* Interrupt status/mask */ 308 #define PCIE_INTA 0x01 /* PCIE INTA message is received */ 309 #define PCIE_INTB 0x02 /* PCIE INTB message is received */ 310 #define PCIE_INTFATAL 0x04 /* PCIE INTFATAL message is received */ 311 #define PCIE_INTNFATAL 0x08 /* PCIE INTNONFATAL message is received */ 312 #define PCIE_INTCORR 0x10 /* PCIE INTCORR message is received */ 313 #define PCIE_INTPME 0x20 /* PCIE INTPME message is received */ 314 #define PCIE_PERST 0x40 /* PCIE Reset Interrupt */ 315 316 #define PCIE_INT_MB_FN0_0 0x0100 /* PCIE to SB Mailbox int Fn0.0 is received */ 317 #define PCIE_INT_MB_FN0_1 0x0200 /* PCIE to SB Mailbox int Fn0.1 is received */ 318 #define PCIE_INT_MB_FN1_0 0x0400 /* PCIE to SB Mailbox int Fn1.0 is received */ 319 #define PCIE_INT_MB_FN1_1 0x0800 /* PCIE to SB Mailbox int Fn1.1 is received */ 320 #define PCIE_INT_MB_FN2_0 0x1000 /* PCIE to SB Mailbox int Fn2.0 is received */ 321 #define PCIE_INT_MB_FN2_1 0x2000 /* PCIE to SB Mailbox int Fn2.1 is received */ 322 #define PCIE_INT_MB_FN3_0 0x4000 /* PCIE to SB Mailbox int Fn3.0 is received */ 323 #define PCIE_INT_MB_FN3_1 0x8000 /* PCIE to SB Mailbox int Fn3.1 is received */ 324 325 /* PCIE MSI Vector Assignment register */ 326 #define MSIVEC_MB_0 (0x1 << 1) /* MSI Vector offset for mailbox0 is 2 */ 327 #define MSIVEC_MB_1 (0x1 << 2) /* MSI Vector offset for mailbox1 is 3 */ 328 #define MSIVEC_D2H0_DB0 (0x1 << 3) /* MSI Vector offset for interface0 door bell 0 is 4 */ 329 #define MSIVEC_D2H0_DB1 (0x1 << 4) /* MSI Vector offset for interface0 door bell 1 is 5 */ 330 331 /* PCIE MailboxInt/MailboxIntMask register */ 332 #define PCIE_MB_TOSB_FN0_0 0x0001 /* write to assert PCIEtoSB Mailbox interrupt */ 333 #define PCIE_MB_TOSB_FN0_1 0x0002 334 #define PCIE_MB_TOSB_FN1_0 0x0004 335 #define PCIE_MB_TOSB_FN1_1 0x0008 336 #define PCIE_MB_TOSB_FN2_0 0x0010 337 #define PCIE_MB_TOSB_FN2_1 0x0020 338 #define PCIE_MB_TOSB_FN3_0 0x0040 339 #define PCIE_MB_TOSB_FN3_1 0x0080 340 #define PCIE_MB_TOPCIE_FN0_0 0x0100 /* int status/mask for SBtoPCIE Mailbox interrupts */ 341 #define PCIE_MB_TOPCIE_FN0_1 0x0200 342 #define PCIE_MB_TOPCIE_FN1_0 0x0400 343 #define PCIE_MB_TOPCIE_FN1_1 0x0800 344 #define PCIE_MB_TOPCIE_FN2_0 0x1000 345 #define PCIE_MB_TOPCIE_FN2_1 0x2000 346 #define PCIE_MB_TOPCIE_FN3_0 0x4000 347 #define PCIE_MB_TOPCIE_FN3_1 0x8000 348 #define PCIE_MB_TOPCIE_D2H0_DB0 0x10000 349 #define PCIE_MB_TOPCIE_D2H0_DB1 0x20000 350 #define PCIE_MB_TOPCIE_D2H1_DB0 0x40000 351 #define PCIE_MB_TOPCIE_D2H1_DB1 0x80000 352 #define PCIE_MB_TOPCIE_D2H2_DB0 0x100000 353 #define PCIE_MB_TOPCIE_D2H2_DB1 0x200000 354 #define PCIE_MB_TOPCIE_D2H3_DB0 0x400000 355 #define PCIE_MB_TOPCIE_D2H3_DB1 0x800000 356 357 #define PCIE_MB_D2H_MB_MASK \ 358 (PCIE_MB_TOPCIE_D2H0_DB0 | PCIE_MB_TOPCIE_D2H0_DB1 | \ 359 PCIE_MB_TOPCIE_D2H1_DB0 | PCIE_MB_TOPCIE_D2H1_DB1 | \ 360 PCIE_MB_TOPCIE_D2H2_DB0 | PCIE_MB_TOPCIE_D2H2_DB1 | \ 361 PCIE_MB_TOPCIE_D2H3_DB0 | PCIE_MB_TOPCIE_D2H3_DB1) 362 363 #define SBTOPCIE0_BASE 0x08000000 364 #define SBTOPCIE1_BASE 0x0c000000 365 366 /* On chips with CCI-400, the small pcie 128 MB region base has shifted */ 367 #define CCI400_SBTOPCIE0_BASE 0x20000000 368 #define CCI400_SBTOPCIE1_BASE 0x24000000 369 370 /* SB to PCIE translation masks */ 371 #define SBTOPCIE0_MASK 0xfc000000 372 #define SBTOPCIE1_MASK 0xfc000000 373 #define SBTOPCIE2_MASK 0xc0000000 374 375 /* Access type bits (0:1) */ 376 #define SBTOPCIE_MEM 0 377 #define SBTOPCIE_IO 1 378 #define SBTOPCIE_CFG0 2 379 #define SBTOPCIE_CFG1 3 380 381 /* Prefetch enable bit 2 */ 382 #define SBTOPCIE_PF 4 383 384 /* Write Burst enable for memory write bit 3 */ 385 #define SBTOPCIE_WR_BURST 8 386 387 /* config access */ 388 #define CONFIGADDR_FUNC_MASK 0x7000 389 #define CONFIGADDR_FUNC_SHF 12 390 #define CONFIGADDR_REG_MASK 0x0FFF 391 #define CONFIGADDR_REG_SHF 0 392 393 #define PCIE_CONFIG_INDADDR(f, r) ((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \ 394 (((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF)) 395 396 /* PCIE protocol regs Indirect Address */ 397 #define PCIEADDR_PROT_MASK 0x300 398 #define PCIEADDR_PROT_SHF 8 399 #define PCIEADDR_PL_TLP 0 400 #define PCIEADDR_PL_DLLP 1 401 #define PCIEADDR_PL_PLP 2 402 403 #define PCIE_CORE_REG_CONTROL 0x00u /* Control */ 404 #define PCIE_CORE_REG_IOSTATUS 0x04u /* IO status */ 405 #define PCIE_CORE_REG_BITSTATUS 0x0Cu /* bitstatus */ 406 #define PCIE_CORE_REG_GPIO_SEL 0x10u /* gpio sel */ 407 #define PCIE_CORE_REG_GPIO_OUT_EN 0x14u /* gpio out en */ 408 #define PCIE_CORE_REG_INT_STATUS 0x20u /* int status */ 409 #define PCIE_CORE_REG_INT_MASK 0x24u /* int mask */ 410 #define PCIE_CORE_REG_SB_PCIE_MB 0x28u /* sbpcie mb */ 411 #define PCIE_CORE_REG_ERRLOG 0x40u /* errlog */ 412 #define PCIE_CORE_REG_ERR_ADDR 0x44u /* errlog addr */ 413 #define PCIE_CORE_REG_MB_INTR 0x48u /* MB intr */ 414 #define PCIE_CORE_REG_SB_PCIE_0 0x100u /* sbpcie0 map */ 415 #define PCIE_CORE_REG_SB_PCIE_1 0x104u /* sbpcie1 map */ 416 #define PCIE_CORE_REG_SB_PCIE_2 0x108u /* sbpcie2 map */ 417 418 /* PCIE Config registers */ 419 #define PCIE_CFG_DEV_STS_CTRL_2 0x0d4u /* "dev_sts_control_2 */ 420 #define PCIE_CFG_ADV_ERR_CAP 0x100u /* adv_err_cap */ 421 #define PCIE_CFG_UC_ERR_STS 0x104u /* uc_err_status */ 422 #define PCIE_CFG_UC_ERR_MASK 0x108u /* ucorr_err_mask */ 423 #define PCIE_CFG_UNCOR_ERR_SERV 0x10cu /* ucorr_err_sevr */ 424 #define PCIE_CFG_CORR_ERR_STS 0x110u /* corr_err_status */ 425 #define PCIE_CFG_CORR_ERR_MASK 0x114u /* corr_err_mask */ 426 #define PCIE_CFG_ADV_ERR_CTRL 0x118u /* adv_err_cap_control */ 427 #define PCIE_CFG_HDR_LOG1 0x11Cu /* header_log1 */ 428 #define PCIE_CFG_HDR_LOG2 0x120u /* header_log2 */ 429 #define PCIE_CFG_HDR_LOG3 0x124u /* header_log3 */ 430 #define PCIE_CFG_HDR_LOG4 0x128u /* header_log4 */ 431 #define PCIE_CFG_PML1_SUB_CAP_ID 0x240u /* PML1sub_capID */ 432 #define PCIE_CFG_PML1_SUB_CAP_REG 0x244u /* PML1_sub_Cap_reg */ 433 #define PCIE_CFG_PML1_SUB_CTRL1 0x248u /* PML1_sub_control1 */ 434 #define PCIE_CFG_PML1_SUB_CTRL3 0x24Cu /* PML1_sub_control2 */ 435 #define PCIE_CFG_TL_CTRL_5 0x814u /* tl_control_5 */ 436 #define PCIE_CFG_PHY_ERR_ATT_VEC 0x1820u /* phy_err_attn_vec */ 437 #define PCIE_CFG_PHY_ERR_ATT_MASK 0x1824u /* phy_err_attn_mask */ 438 439 /* PCIE protocol PHY diagnostic registers */ 440 #define PCIE_PLP_MODEREG 0x200u /* Mode */ 441 #define PCIE_PLP_STATUSREG 0x204u /* Status */ 442 #define PCIE_PLP_LTSSMCTRLREG 0x208u /* LTSSM control */ 443 #define PCIE_PLP_LTLINKNUMREG 0x20cu /* Link Training Link number */ 444 #define PCIE_PLP_LTLANENUMREG 0x210u /* Link Training Lane number */ 445 #define PCIE_PLP_LTNFTSREG 0x214u /* Link Training N_FTS */ 446 #define PCIE_PLP_ATTNREG 0x218u /* Attention */ 447 #define PCIE_PLP_ATTNMASKREG 0x21Cu /* Attention Mask */ 448 #define PCIE_PLP_RXERRCTR 0x220u /* Rx Error */ 449 #define PCIE_PLP_RXFRMERRCTR 0x224u /* Rx Framing Error */ 450 #define PCIE_PLP_RXERRTHRESHREG 0x228u /* Rx Error threshold */ 451 #define PCIE_PLP_TESTCTRLREG 0x22Cu /* Test Control reg */ 452 #define PCIE_PLP_SERDESCTRLOVRDREG 0x230u /* SERDES Control Override */ 453 #define PCIE_PLP_TIMINGOVRDREG 0x234u /* Timing param override */ 454 #define PCIE_PLP_RXTXSMDIAGREG 0x238u /* RXTX State Machine Diag */ 455 #define PCIE_PLP_LTSSMDIAGREG 0x23Cu /* LTSSM State Machine Diag */ 456 457 /* PCIE protocol DLLP diagnostic registers */ 458 #define PCIE_DLLP_LCREG 0x100u /* Link Control */ 459 #define PCIE_DLLP_LSREG 0x104u /* Link Status */ 460 #define PCIE_DLLP_LAREG 0x108u /* Link Attention */ 461 #define PCIE_DLLP_LAMASKREG 0x10Cu /* Link Attention Mask */ 462 #define PCIE_DLLP_NEXTTXSEQNUMREG 0x110u /* Next Tx Seq Num */ 463 #define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114u /* Acked Tx Seq Num */ 464 #define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118u /* Purged Tx Seq Num */ 465 #define PCIE_DLLP_RXSEQNUMREG 0x11Cu /* Rx Sequence Number */ 466 #define PCIE_DLLP_LRREG 0x120u /* Link Replay */ 467 #define PCIE_DLLP_LACKTOREG 0x124u /* Link Ack Timeout */ 468 #define PCIE_DLLP_PMTHRESHREG 0x128u /* Power Management Threshold */ 469 #define PCIE_DLLP_RTRYWPREG 0x12Cu /* Retry buffer write ptr */ 470 #define PCIE_DLLP_RTRYRPREG 0x130u /* Retry buffer Read ptr */ 471 #define PCIE_DLLP_RTRYPPREG 0x134u /* Retry buffer Purged ptr */ 472 #define PCIE_DLLP_RTRRWREG 0x138u /* Retry buffer Read/Write */ 473 #define PCIE_DLLP_ECTHRESHREG 0x13Cu /* Error Count Threshold */ 474 #define PCIE_DLLP_TLPERRCTRREG 0x140u /* TLP Error Counter */ 475 #define PCIE_DLLP_ERRCTRREG 0x144u /* Error Counter */ 476 #define PCIE_DLLP_NAKRXCTRREG 0x148u /* NAK Received Counter */ 477 #define PCIE_DLLP_TESTREG 0x14Cu /* Test */ 478 #define PCIE_DLLP_PKTBIST 0x150u /* Packet BIST */ 479 #define PCIE_DLLP_PCIE11 0x154u /* DLLP PCIE 1.1 reg */ 480 481 #define PCIE_DLLP_LSREG_LINKUP (1u << 16u) 482 483 /* PCIE protocol TLP diagnostic registers */ 484 #define PCIE_TLP_CONFIGREG 0x000u /* Configuration */ 485 #define PCIE_TLP_WORKAROUNDSREG 0x004u /* TLP Workarounds */ 486 #define PCIE_TLP_WRDMAUPPER 0x010u /* Write DMA Upper Address */ 487 #define PCIE_TLP_WRDMALOWER 0x014u /* Write DMA Lower Address */ 488 #define PCIE_TLP_WRDMAREQ_LBEREG 0x018u /* Write DMA Len/ByteEn Req */ 489 #define PCIE_TLP_RDDMAUPPER 0x01Cu /* Read DMA Upper Address */ 490 #define PCIE_TLP_RDDMALOWER 0x020u /* Read DMA Lower Address */ 491 #define PCIE_TLP_RDDMALENREG 0x024u /* Read DMA Len Req */ 492 #define PCIE_TLP_MSIDMAUPPER 0x028u /* MSI DMA Upper Address */ 493 #define PCIE_TLP_MSIDMALOWER 0x02Cu /* MSI DMA Lower Address */ 494 #define PCIE_TLP_MSIDMALENREG 0x030u /* MSI DMA Len Req */ 495 #define PCIE_TLP_SLVREQLENREG 0x034u /* Slave Request Len */ 496 #define PCIE_TLP_FCINPUTSREQ 0x038u /* Flow Control Inputs */ 497 #define PCIE_TLP_TXSMGRSREQ 0x03Cu /* Tx StateMachine and Gated Req */ 498 #define PCIE_TLP_ADRACKCNTARBLEN 0x040u /* Address Ack XferCnt and ARB Len */ 499 #define PCIE_TLP_DMACPLHDR0 0x044u /* DMA Completion Hdr 0 */ 500 #define PCIE_TLP_DMACPLHDR1 0x048u /* DMA Completion Hdr 1 */ 501 #define PCIE_TLP_DMACPLHDR2 0x04Cu /* DMA Completion Hdr 2 */ 502 #define PCIE_TLP_DMACPLMISC0 0x050u /* DMA Completion Misc0 */ 503 #define PCIE_TLP_DMACPLMISC1 0x054u /* DMA Completion Misc1 */ 504 #define PCIE_TLP_DMACPLMISC2 0x058u /* DMA Completion Misc2 */ 505 #define PCIE_TLP_SPTCTRLLEN 0x05Cu /* Split Controller Req len */ 506 #define PCIE_TLP_SPTCTRLMSIC0 0x060u /* Split Controller Misc 0 */ 507 #define PCIE_TLP_SPTCTRLMSIC1 0x064u /* Split Controller Misc 1 */ 508 #define PCIE_TLP_BUSDEVFUNC 0x068u /* Bus/Device/Func */ 509 #define PCIE_TLP_RESETCTR 0x06Cu /* Reset Counter */ 510 #define PCIE_TLP_RTRYBUF 0x070u /* Retry Buffer value */ 511 #define PCIE_TLP_TGTDEBUG1 0x074u /* Target Debug Reg1 */ 512 #define PCIE_TLP_TGTDEBUG2 0x078u /* Target Debug Reg2 */ 513 #define PCIE_TLP_TGTDEBUG3 0x07Cu /* Target Debug Reg3 */ 514 #define PCIE_TLP_TGTDEBUG4 0x080u /* Target Debug Reg4 */ 515 516 /* PCIE2 MDIO register offsets */ 517 #define PCIE2_MDIO_CONTROL 0x128 518 #define PCIE2_MDIO_WR_DATA 0x12C 519 #define PCIE2_MDIO_RD_DATA 0x130 520 521 522 /* MDIO control */ 523 #define MDIOCTL_DIVISOR_MASK 0x7fu /* clock to be used on MDIO */ 524 #define MDIOCTL_DIVISOR_VAL 0x2u 525 #define MDIOCTL_PREAM_EN 0x80u /* Enable preamble sequnce */ 526 #define MDIOCTL_ACCESS_DONE 0x100u /* Tranaction complete */ 527 528 /* MDIO Data */ 529 #define MDIODATA_MASK 0x0000ffff /* data 2 bytes */ 530 #define MDIODATA_TA 0x00020000 /* Turnaround */ 531 #define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */ 532 #define MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */ 533 #define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */ 534 #define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */ 535 #define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ 536 #define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */ 537 #define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */ 538 #define MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */ 539 #define MDIODATA_WRITE 0x10000000 /* write Transaction */ 540 #define MDIODATA_READ 0x20000000 /* Read Transaction */ 541 #define MDIODATA_START 0x40000000 /* start of Transaction */ 542 543 #define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */ 544 #define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */ 545 546 /* MDIO control/wrData/rdData register defines for PCIE Gen 2 */ 547 #define MDIOCTL2_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ 548 #define MDIOCTL2_DIVISOR_VAL 0x2 549 #define MDIOCTL2_REGADDR_SHF 8 /* Regaddr shift */ 550 #define MDIOCTL2_REGADDR_MASK 0x00FFFF00 /* Regaddr Mask */ 551 #define MDIOCTL2_DEVADDR_SHF 24 /* Physmedia devaddr shift */ 552 #define MDIOCTL2_DEVADDR_MASK 0x0f000000 /* Physmedia devaddr Mask */ 553 #define MDIOCTL2_SLAVE_BYPASS 0x10000000 /* IP slave bypass */ 554 #define MDIOCTL2_READ 0x20000000 /* IP slave bypass */ 555 556 #define MDIODATA2_DONE 0x80000000u /* rd/wr transaction done */ 557 #define MDIODATA2_MASK 0x7FFFFFFF /* rd/wr transaction data */ 558 #define MDIODATA2_DEVADDR_SHF 4 /* Physmedia devaddr shift */ 559 560 561 /* MDIO devices (SERDES modules) 562 * unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks. 563 * two layers mapping (blockidx, register offset) is required 564 */ 565 #define MDIO_DEV_IEEE0 0x000 566 #define MDIO_DEV_IEEE1 0x001 567 #define MDIO_DEV_BLK0 0x800 568 #define MDIO_DEV_BLK1 0x801 569 #define MDIO_DEV_BLK2 0x802 570 #define MDIO_DEV_BLK3 0x803 571 #define MDIO_DEV_BLK4 0x804 572 #define MDIO_DEV_TXPLL 0x808 /* TXPLL register block idx */ 573 #define MDIO_DEV_TXCTRL0 0x820 574 #define MDIO_DEV_SERDESID 0x831 575 #define MDIO_DEV_RXCTRL0 0x840 576 577 578 /* XgxsBlk1_A Register Offsets */ 579 #define BLK1_PWR_MGMT0 0x16 580 #define BLK1_PWR_MGMT1 0x17 581 #define BLK1_PWR_MGMT2 0x18 582 #define BLK1_PWR_MGMT3 0x19 583 #define BLK1_PWR_MGMT4 0x1A 584 585 /* serdes regs (rev < 10) */ 586 #define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ 587 #define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ 588 #define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ 589 /* SERDES RX registers */ 590 #define SERDES_RX_CTRL 1 /* Rx cntrl */ 591 #define SERDES_RX_TIMER1 2 /* Rx Timer1 */ 592 #define SERDES_RX_CDR 6 /* CDR */ 593 #define SERDES_RX_CDRBW 7 /* CDR BW */ 594 595 /* SERDES RX control register */ 596 #define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ 597 #define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ 598 599 /* SERDES PLL registers */ 600 #define SERDES_PLL_CTRL 1 /* PLL control reg */ 601 #define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ 602 603 /* Power management threshold */ 604 #define PCIE_L0THRESHOLDTIME_MASK 0xFF00u /* bits 0 - 7 */ 605 #define PCIE_L1THRESHOLDTIME_MASK 0xFF00u /* bits 8 - 15 */ 606 #define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ 607 #define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ 608 #define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */ 609 610 /* SPROM offsets */ 611 #define SRSH_ASPM_OFFSET 4 /* word 4 */ 612 #define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ 613 #define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */ 614 #define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */ 615 #define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */ 616 #define SRSH_L23READY_EXIT_NOPERST 0x8000u /* bit 15 */ 617 #define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */ 618 #define SRSH_CLKREQ_OFFSET_REV8 52 /* word 52 for srom rev 8 */ 619 #define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ 620 #define SRSH_BD_OFFSET 6 /* word 6 */ 621 #define SRSH_AUTOINIT_OFFSET 18 /* auto initialization enable */ 622 623 /* PCI Capability ID's 624 * Reference include/linux/pci_regs.h 625 * #define PCI_CAP_LIST_ID 0 // Capability ID 626 * #define PCI_CAP_ID_PM 0x01 // Power Management 627 * #define PCI_CAP_ID_AGP 0x02 // Accelerated Graphics Port 628 * #define PCI_CAP_ID_VPD 0x03 // Vital Product Data 629 * #define PCI_CAP_ID_SLOTID 0x04 // Slot Identification 630 * #define PCI_CAP_ID_MSI 0x05 // Message Signalled Interrupts 631 * #define PCI_CAP_ID_CHSWP 0x06 // CompactPCI HotSwap 632 * #define PCI_CAP_ID_PCIX 0x07 // PCI-X 633 * #define PCI_CAP_ID_HT 0x08 // HyperTransport 634 * #define PCI_CAP_ID_VNDR 0x09 // Vendor-Specific 635 * #define PCI_CAP_ID_DBG 0x0A // Debug port 636 * #define PCI_CAP_ID_CCRC 0x0B // CompactPCI Central Resource Control 637 * #define PCI_CAP_ID_SHPC 0x0C // PCI Standard Hot-Plug Controller 638 * #define PCI_CAP_ID_SSVID 0x0D // Bridge subsystem vendor/device ID 639 * #define PCI_CAP_ID_AGP3 0x0E // AGP Target PCI-PCI bridge 640 * #define PCI_CAP_ID_SECDEV 0x0F // Secure Device 641 * #define PCI_CAP_ID_MSIX 0x11 // MSI-X 642 * #define PCI_CAP_ID_SATA 0x12 // SATA Data/Index Conf. 643 * #define PCI_CAP_ID_AF 0x13 // PCI Advanced Features 644 * #define PCI_CAP_ID_EA 0x14 // PCI Enhanced Allocation 645 * #define PCI_CAP_ID_MAX PCI_CAP_ID_EA 646 */ 647 648 #define PCIE_CAP_ID_EXP 0x10 // PCI Express 649 650 /* PCIe Capabilities Offsets 651 * Reference include/linux/pci_regs.h 652 * #define PCIE_CAP_FLAGS 2 // Capabilities register 653 * #define PCIE_CAP_DEVCAP 4 // Device capabilities 654 * #define PCIE_CAP_DEVCTL 8 // Device Control 655 * #define PCIE_CAP_DEVSTA 10 // Device Status 656 * #define PCIE_CAP_LNKCAP 12 // Link Capabilities 657 * #define PCIE_CAP_LNKCTL 16 // Link Control 658 * #define PCIE_CAP_LNKSTA 18 // Link Status 659 * #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 // v1 endpoints end here 660 * #define PCIE_CAP_SLTCAP 20 // Slot Capabilities 661 * #define PCIE_CAP_SLTCTL 24 // Slot Control 662 * #define PCIE_CAP_SLTSTA 26 // Slot Status 663 * #define PCIE_CAP_RTCTL 28 // Root Control 664 * #define PCIE_CAP_RTCAP 30 // Root Capabilities 665 * #define PCIE_CAP_RTSTA 32 // Root Status 666 */ 667 668 669 /* Linkcapability reg offset in PCIE Cap */ 670 #define PCIE_CAP_LINKCAP_OFFSET 12 /* linkcap offset in pcie cap */ 671 #define PCIE_CAP_LINKCAP_LNKSPEED_MASK 0xf /* Supported Link Speeds */ 672 #define PCIE_CAP_LINKCAP_GEN2 0x2 /* Value for GEN2 */ 673 674 /* Uc_Err reg offset in AER Cap */ 675 #define PCIE_EXTCAP_ID_ERR 0x01 /* Advanced Error Reporting */ 676 #define PCIE_EXTCAP_AER_UCERR_OFFSET 4 /* Uc_Err reg offset in AER Cap */ 677 678 /* Linkcontrol reg offset in PCIE Cap */ 679 #define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ 680 #define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ 681 #define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ 682 #define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ 683 #define PCIE_LINKSPEED_MASK 0xF0000u /* bits 0 - 3 of high word */ 684 #define PCIE_LINKSPEED_SHIFT 16 /* PCIE_LINKSPEED_SHIFT */ 685 686 /* Devcontrol reg offset in PCIE Cap */ 687 #define PCIE_CAP_DEVCTRL_OFFSET 8 /* devctrl offset in pcie cap */ 688 #define PCIE_CAP_DEVCTRL_MRRS_MASK 0x7000 /* Max read request size mask */ 689 #define PCIE_CAP_DEVCTRL_MRRS_SHIFT 12 /* Max read request size shift */ 690 #define PCIE_CAP_DEVCTRL_MRRS_128B 0 /* 128 Byte */ 691 #define PCIE_CAP_DEVCTRL_MRRS_256B 1 /* 256 Byte */ 692 #define PCIE_CAP_DEVCTRL_MRRS_512B 2 /* 512 Byte */ 693 #define PCIE_CAP_DEVCTRL_MRRS_1024B 3 /* 1024 Byte */ 694 #define PCIE_CAP_DEVCTRL_MPS_MASK 0x00e0 /* Max payload size mask */ 695 #define PCIE_CAP_DEVCTRL_MPS_SHIFT 5 /* Max payload size shift */ 696 #define PCIE_CAP_DEVCTRL_MPS_128B 0 /* 128 Byte */ 697 #define PCIE_CAP_DEVCTRL_MPS_256B 1 /* 256 Byte */ 698 #define PCIE_CAP_DEVCTRL_MPS_512B 2 /* 512 Byte */ 699 #define PCIE_CAP_DEVCTRL_MPS_1024B 3 /* 1024 Byte */ 700 701 #define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */ 702 #define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */ 703 #define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */ 704 #define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */ 705 706 #define PCIE_ASPM_L11_ENAB 8 /* ASPM L1.1 in PML1_sub_control2 */ 707 #define PCIE_ASPM_L12_ENAB 4 /* ASPM L1.2 in PML1_sub_control2 */ 708 709 /* NumMsg and NumMsgEn in PCIE MSI Cap */ 710 #define MSICAP_NUM_MSG_SHF 17 711 #define MSICAP_NUM_MSG_MASK (0x7 << MSICAP_NUM_MSG_SHF) 712 #define MSICAP_NUM_MSG_EN_SHF 20 713 #define MSICAP_NUM_MSG_EN_MASK (0x7 << MSICAP_NUM_MSG_EN_SHF) 714 715 /* Devcontrol2 reg offset in PCIE Cap */ 716 #define PCIE_CAP_DEVCTRL2_OFFSET 0x28 /* devctrl2 offset in pcie cap */ 717 #define PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK 0x400 /* Latency Tolerance Reporting Enable */ 718 #define PCIE_CAP_DEVCTRL2_OBFF_ENAB_SHIFT 13 /* Enable OBFF mechanism, select signaling method */ 719 #define PCIE_CAP_DEVCTRL2_OBFF_ENAB_MASK 0x6000 /* Enable OBFF mechanism, select signaling method */ 720 721 /* LTR registers in PCIE Cap */ 722 #define PCIE_LTR0_REG_OFFSET 0x844u /* ltr0_reg offset in pcie cap */ 723 #define PCIE_LTR1_REG_OFFSET 0x848u /* ltr1_reg offset in pcie cap */ 724 #define PCIE_LTR2_REG_OFFSET 0x84cu /* ltr2_reg offset in pcie cap */ 725 #define PCIE_LTR0_REG_DEFAULT_60 0x883c883cu /* active latency default to 60usec */ 726 #define PCIE_LTR0_REG_DEFAULT_150 0x88968896u /* active latency default to 150usec */ 727 #define PCIE_LTR1_REG_DEFAULT 0x88648864u /* idle latency default to 100usec */ 728 #define PCIE_LTR2_REG_DEFAULT 0x90039003u /* sleep latency default to 3msec */ 729 730 /* Status reg PCIE_PLP_STATUSREG */ 731 #define PCIE_PLP_POLARITYINV_STAT 0x10 732 733 734 /* PCIE BRCM Vendor CAP REVID reg bits */ 735 #define BRCMCAP_PCIEREV_CT_MASK 0xF00u 736 #define BRCMCAP_PCIEREV_CT_SHIFT 8u 737 #define BRCMCAP_PCIEREV_REVID_MASK 0xFFu 738 #define BRCMCAP_PCIEREV_REVID_SHIFT 0 739 740 #define PCIE_REVREG_CT_PCIE1 0 741 #define PCIE_REVREG_CT_PCIE2 1 742 743 /* PCIE GEN2 specific defines */ 744 /* PCIE BRCM Vendor Cap offsets w.r.t to vendor cap ptr */ 745 #define PCIE2R0_BRCMCAP_REVID_OFFSET 4 746 #define PCIE2R0_BRCMCAP_BAR0_WIN0_WRAP_OFFSET 8 747 #define PCIE2R0_BRCMCAP_BAR0_WIN2_OFFSET 12 748 #define PCIE2R0_BRCMCAP_BAR0_WIN2_WRAP_OFFSET 16 749 #define PCIE2R0_BRCMCAP_BAR0_WIN_OFFSET 20 750 #define PCIE2R0_BRCMCAP_BAR1_WIN_OFFSET 24 751 #define PCIE2R0_BRCMCAP_SPROM_CTRL_OFFSET 28 752 #define PCIE2R0_BRCMCAP_BAR2_WIN_OFFSET 32 753 #define PCIE2R0_BRCMCAP_INTSTATUS_OFFSET 36 754 #define PCIE2R0_BRCMCAP_INTMASK_OFFSET 40 755 #define PCIE2R0_BRCMCAP_PCIE2SB_MB_OFFSET 44 756 #define PCIE2R0_BRCMCAP_BPADDR_OFFSET 48 757 #define PCIE2R0_BRCMCAP_BPDATA_OFFSET 52 758 #define PCIE2R0_BRCMCAP_CLKCTLSTS_OFFSET 56 759 760 /* definition of configuration space registers of PCIe gen2 761 * http://hwnbu-twiki.sj.broadcom.com/twiki/pub/Mwgroup/CurrentPcieGen2ProgramGuide/pcie_ep.htm 762 */ 763 #define PCIECFGREG_STATUS_CMD 0x4 764 #define PCIECFGREG_PM_CSR 0x4C 765 #define PCIECFGREG_MSI_CAP 0x58 766 #define PCIECFGREG_MSI_ADDR_L 0x5C 767 #define PCIECFGREG_MSI_ADDR_H 0x60 768 #define PCIECFGREG_MSI_DATA 0x64 769 #define PCIECFGREG_LINK_STATUS_CTRL 0xBCu 770 #define PCIECFGREG_DEV_STATUS_CTRL 0xB4u 771 #define PCIECFGGEN_DEV_STATUS_CTRL2 0xD4 772 #define PCIECFGREG_LINK_STATUS_CTRL2 0xDCu 773 #define PCIECFGREG_RBAR_CTRL 0x228 774 #define PCIECFGREG_PML1_SUB_CTRL1 0x248 775 #define PCIECFGREG_PML1_SUB_CTRL2 0x24C 776 #define PCIECFGREG_REG_BAR2_CONFIG 0x4E0 777 #define PCIECFGREG_REG_BAR3_CONFIG 0x4F4 778 #define PCIECFGREG_PDL_CTRL1 0x1004 779 #define PCIECFGREG_PDL_IDDQ 0x1814 780 #define PCIECFGREG_REG_PHY_CTL7 0x181c 781 #define PCIECFGREG_PHY_DBG_CLKREQ0 0x1E10 782 #define PCIECFGREG_PHY_DBG_CLKREQ1 0x1E14 783 #define PCIECFGREG_PHY_DBG_CLKREQ2 0x1E18 784 #define PCIECFGREG_PHY_DBG_CLKREQ3 0x1E1C 785 786 /* PCIECFGREG_PML1_SUB_CTRL1 Bit Definition */ 787 #define PCI_PM_L1_2_ENA_MASK 0x00000001 /* PCI-PM L1.2 Enabled */ 788 #define PCI_PM_L1_1_ENA_MASK 0x00000002 /* PCI-PM L1.1 Enabled */ 789 #define ASPM_L1_2_ENA_MASK 0x00000004 /* ASPM L1.2 Enabled */ 790 #define ASPM_L1_1_ENA_MASK 0x00000008 /* ASPM L1.1 Enabled */ 791 792 /* PCIe gen2 mailbox interrupt masks */ 793 #define I_MB 0x3 794 #define I_BIT0 0x1 795 #define I_BIT1 0x2 796 797 /* PCIE gen2 config regs */ 798 #define PCIIntstatus 0x090 799 #define PCIIntmask 0x094 800 #define PCISBMbx 0x98 801 802 /* enumeration Core regs */ 803 #define PCIH2D_MailBox 0x140 804 #define PCIH2D_DB1 0x144 805 #define PCID2H_MailBox 0x148 806 #define PCIH2D_MailBox_1 0x150 /* for dma channel1 */ 807 #define PCIH2D_DB1_1 0x154 808 #define PCID2H_MailBox_1 0x158 809 #define PCIH2D_MailBox_2 0x160 /* for dma channel2 which will be used for Implicit DMA */ 810 #define PCIH2D_DB1_2 0x164 811 #define PCID2H_MailBox_2 0x168 812 813 #define PCIMailBoxInt 0x48 814 #define PCIMailBoxMask 0x4C 815 #define PCIMSIVecAssign 0x58 816 817 #define I_F0_B0 (0x1 << 8) /* Mail box interrupt Function 0 interrupt, bit 0 */ 818 #define I_F0_B1 (0x1 << 9) /* Mail box interrupt Function 0 interrupt, bit 1 */ 819 820 #define PCIECFGREG_DEVCONTROL 0xB4 821 #define PCIECFGREG_BASEADDR0 0x10 822 #define PCIECFGREG_DEVCONTROL_MRRS_SHFT 12 823 #define PCIECFGREG_DEVCONTROL_MRRS_MASK (0x7 << PCIECFGREG_DEVCONTROL_MRRS_SHFT) 824 #define PCIECFGREG_DEVCTRL_MPS_SHFT 5 825 #define PCIECFGREG_DEVCTRL_MPS_MASK (0x7 << PCIECFGREG_DEVCTRL_MPS_SHFT) 826 #define PCIECFGREG_PM_CSR_STATE_MASK 0x00000003 827 #define PCIECFGREG_PM_CSR_STATE_D0 0 828 #define PCIECFGREG_PM_CSR_STATE_D1 1 829 #define PCIECFGREG_PM_CSR_STATE_D2 2 830 #define PCIECFGREG_PM_CSR_STATE_D3_HOT 3 831 #define PCIECFGREG_PM_CSR_STATE_D3_COLD 4 832 833 834 /* SROM hardware region */ 835 #define SROM_OFFSET_BAR1_CTRL 52 836 837 #define BAR1_ENC_SIZE_MASK 0x000e 838 #define BAR1_ENC_SIZE_SHIFT 1 839 840 #define BAR1_ENC_SIZE_1M 0 841 #define BAR1_ENC_SIZE_2M 1 842 #define BAR1_ENC_SIZE_4M 2 843 844 #define PCIEGEN2_CAP_DEVSTSCTRL2_OFFSET 0xD4 845 #define PCIEGEN2_CAP_DEVSTSCTRL2_LTRENAB 0x400 846 847 /* 848 * Latency Tolerance Reporting (LTR) states 849 * Active has the least tolerant latency requirement 850 * Sleep is most tolerant 851 */ 852 #define LTR_ACTIVE 2 853 #define LTR_ACTIVE_IDLE 1 854 #define LTR_SLEEP 0 855 #define LTR_FINAL_MASK 0x300 856 #define LTR_FINAL_SHIFT 8 857 858 /* pwrinstatus, pwrintmask regs */ 859 #define PCIEGEN2_PWRINT_D0_STATE_SHIFT 0 860 #define PCIEGEN2_PWRINT_D1_STATE_SHIFT 1 861 #define PCIEGEN2_PWRINT_D2_STATE_SHIFT 2 862 #define PCIEGEN2_PWRINT_D3_STATE_SHIFT 3 863 #define PCIEGEN2_PWRINT_L0_LINK_SHIFT 4 864 #define PCIEGEN2_PWRINT_L0s_LINK_SHIFT 5 865 #define PCIEGEN2_PWRINT_L1_LINK_SHIFT 6 866 #define PCIEGEN2_PWRINT_L2_L3_LINK_SHIFT 7 867 #define PCIEGEN2_PWRINT_OBFF_CHANGE_SHIFT 8 868 869 #define PCIEGEN2_PWRINT_D0_STATE_MASK (1 << PCIEGEN2_PWRINT_D0_STATE_SHIFT) 870 #define PCIEGEN2_PWRINT_D1_STATE_MASK (1 << PCIEGEN2_PWRINT_D1_STATE_SHIFT) 871 #define PCIEGEN2_PWRINT_D2_STATE_MASK (1 << PCIEGEN2_PWRINT_D2_STATE_SHIFT) 872 #define PCIEGEN2_PWRINT_D3_STATE_MASK (1 << PCIEGEN2_PWRINT_D3_STATE_SHIFT) 873 #define PCIEGEN2_PWRINT_L0_LINK_MASK (1 << PCIEGEN2_PWRINT_L0_LINK_SHIFT) 874 #define PCIEGEN2_PWRINT_L0s_LINK_MASK (1 << PCIEGEN2_PWRINT_L0s_LINK_SHIFT) 875 #define PCIEGEN2_PWRINT_L1_LINK_MASK (1 << PCIEGEN2_PWRINT_L1_LINK_SHIFT) 876 #define PCIEGEN2_PWRINT_L2_L3_LINK_MASK (1 << PCIEGEN2_PWRINT_L2_L3_LINK_SHIFT) 877 #define PCIEGEN2_PWRINT_OBFF_CHANGE_MASK (1 << PCIEGEN2_PWRINT_OBFF_CHANGE_SHIFT) 878 879 /* sbtopcie mail box */ 880 #define SBTOPCIE_MB_FUNC0_SHIFT 8 881 #define SBTOPCIE_MB_FUNC1_SHIFT 10 882 #define SBTOPCIE_MB_FUNC2_SHIFT 12 883 #define SBTOPCIE_MB_FUNC3_SHIFT 14 884 885 #define SBTOPCIE_MB1_FUNC0_SHIFT 9 886 #define SBTOPCIE_MB1_FUNC1_SHIFT 11 887 #define SBTOPCIE_MB1_FUNC2_SHIFT 13 888 #define SBTOPCIE_MB1_FUNC3_SHIFT 15 889 890 /* pcieiocstatus */ 891 #define PCIEGEN2_IOC_D0_STATE_SHIFT 8 892 #define PCIEGEN2_IOC_D1_STATE_SHIFT 9 893 #define PCIEGEN2_IOC_D2_STATE_SHIFT 10 894 #define PCIEGEN2_IOC_D3_STATE_SHIFT 11 895 #define PCIEGEN2_IOC_L0_LINK_SHIFT 12 896 #define PCIEGEN2_IOC_L1_LINK_SHIFT 13 897 #define PCIEGEN2_IOC_L1L2_LINK_SHIFT 14 898 #define PCIEGEN2_IOC_L2_L3_LINK_SHIFT 15 899 900 #define PCIEGEN2_IOC_D0_STATE_MASK (1 << PCIEGEN2_IOC_D0_STATE_SHIFT) 901 #define PCIEGEN2_IOC_D1_STATE_MASK (1 << PCIEGEN2_IOC_D1_STATE_SHIFT) 902 #define PCIEGEN2_IOC_D2_STATE_MASK (1 << PCIEGEN2_IOC_D2_STATE_SHIFT) 903 #define PCIEGEN2_IOC_D3_STATE_MASK (1 << PCIEGEN2_IOC_D3_STATE_SHIFT) 904 #define PCIEGEN2_IOC_L0_LINK_MASK (1 << PCIEGEN2_IOC_L0_LINK_SHIFT) 905 #define PCIEGEN2_IOC_L1_LINK_MASK (1 << PCIEGEN2_IOC_L1_LINK_SHIFT) 906 #define PCIEGEN2_IOC_L1L2_LINK_MASK (1 << PCIEGEN2_IOC_L1L2_LINK_SHIFT) 907 #define PCIEGEN2_IOC_L2_L3_LINK_MASK (1 << PCIEGEN2_IOC_L2_L3_LINK_SHIFT) 908 909 /* stat_ctrl */ 910 #define PCIE_STAT_CTRL_RESET 0x1 911 #define PCIE_STAT_CTRL_ENABLE 0x2 912 #define PCIE_STAT_CTRL_INTENABLE 0x4 913 #define PCIE_STAT_CTRL_INTSTATUS 0x8 914 915 /* cpl_timeout_ctrl_reg */ 916 #define PCIE_CTO_TO_THRESHOLD_SHIFT 0 917 #define PCIE_CTO_TO_THRESHHOLD_MASK (0xfffff << PCIE_CTO_TO_THRESHOLD_SHIFT) 918 919 #define PCIE_CTO_CLKCHKCNT_SHIFT 24 920 #define PCIE_CTO_CLKCHKCNT_MASK (0xf << PCIE_CTO_CLKCHKCNT_SHIFT) 921 922 #define PCIE_CTO_ENAB_SHIFT 31 923 #define PCIE_CTO_ENAB_MASK (0x1 << PCIE_CTO_ENAB_SHIFT) 924 925 #define PCIE_CTO_TO_THRESH_DEFAULT 0x58000 926 #define PCIE_CTO_CLKCHKCNT_VAL 0xA 927 928 /* ErrLog */ 929 #define PCIE_SROMRD_ERR_SHIFT 5 930 #define PCIE_SROMRD_ERR_MASK (0x1 << PCIE_SROMRD_ERR_SHIFT) 931 932 #define PCIE_CTO_ERR_SHIFT 8 933 #define PCIE_CTO_ERR_MASK (0x1 << PCIE_CTO_ERR_SHIFT) 934 935 #define PCIE_CTO_ERR_CODE_SHIFT 9 936 #define PCIE_CTO_ERR_CODE_MASK (0x3 << PCIE_CTO_ERR_CODE_SHIFT) 937 938 #define PCIE_BP_CLK_OFF_ERR_SHIFT 12 939 #define PCIE_BP_CLK_OFF_ERR_MASK (0x1 << PCIE_BP_CLK_OFF_ERR_SHIFT) 940 941 #define PCIE_BP_IN_RESET_ERR_SHIFT 13 942 #define PCIE_BP_IN_RESET_ERR_MASK (0x1 << PCIE_BP_IN_RESET_ERR_SHIFT) 943 944 #ifdef BCMDRIVER 945 void pcie_watchdog_reset(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs); 946 void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs); 947 void pcie_set_trefup_time_100us(si_t *sih); 948 #endif /* BCMDRIVER */ 949 950 /* DMA intstatus and intmask */ 951 #define I_PC (1 << 10) /* pci descriptor error */ 952 #define I_PD (1 << 11) /* pci data error */ 953 #define I_DE (1 << 12) /* descriptor protocol error */ 954 #define I_RU (1 << 13) /* receive descriptor underflow */ 955 #define I_RO (1 << 14) /* receive fifo overflow */ 956 #define I_XU (1 << 15) /* transmit fifo underflow */ 957 #define I_RI (1 << 16) /* receive interrupt */ 958 #define I_XI (1 << 24) /* transmit interrupt */ 959 960 #endif /* _PCIE_CORE_H */ 961