Home
last modified time | relevance | path

Searched defs:div (Results 1 – 18 of 18) sorted by relevance

/optee_os/core/drivers/clk/sam/
H A Dclk-sam9x60-pll.c56 uint8_t div; member
276 uint32_t div, in sam9x60_div_pll_set_div()
302 static TEE_Result sam9x60_div_pll_set(struct sam9x60_div *div) in sam9x60_div_pll_set()
323 struct sam9x60_div *div = hw->priv; in sam9x60_div_pll_prepare() local
330 struct sam9x60_div *div = hw->priv; in sam9x60_div_pll_unprepare() local
347 struct sam9x60_div *div = hw->priv; in sam9x60_div_pll_recalc_rate() local
356 struct sam9x60_div *div = hw->priv; in sam9x60_div_pll_set_rate() local
370 struct sam9x60_div *div = hw->priv; in sam9x60_div_pll_set_rate_chg() local
491 struct sam9x60_div *div = NULL; in sam9x60_clk_register_div_pll() local
H A Dat91_pll.c40 uint8_t div; member
65 uint8_t div = 0; in clk_pll_enable() local
117 uint32_t *div, uint32_t *mul, in clk_pll_get_best_div_mul()
232 uint32_t div = 1; in clk_pll_set_rate() local
H A Dat91_master.c27 uint8_t div; member
52 uint8_t div = 1; in clk_master_div_get_rate() local
215 unsigned long div = 0; in clk_sama7g5_master_set_rate() local
H A Dat91_usb.c63 unsigned long div = 1; in at91sam9x5_clk_usb_set_rate() local
H A Dat91_audio_pll.c46 #define AUDIO_PLL_QDPAD(qd, div) \ argument
67 uint8_t div; member
H A Dat91_peripheral.c25 uint32_t div; member
H A Dat91_programmable.c98 unsigned long div = parent_rate / rate; in clk_programmable_set_rate() local
H A Dat91_generated.c103 uint32_t div = 1; in clk_generated_set_rate() local
/optee_os/core/drivers/clk/
H A Dclk-stm32-core.c197 unsigned int div) in _get_table_val()
228 unsigned int div, unsigned long flags, in _get_val()
247 unsigned int div) in _is_valid_table_div()
259 unsigned int div, unsigned long flags) in _is_valid_div()
274 unsigned int div = 0U; in divider_get_val() local
326 unsigned int div = 0U; in stm32_div_get_rate() local
H A Dclk-stm32-core.h26 unsigned int div; member
47 const struct div_cfg *div; member
59 unsigned int div; member
H A Dclk-stm32mp13.c77 uint32_t div; member
H A Dclk-stm32mp21.c1846 uint32_t div = (data & OBS_DIV_MASK) >> OBS_DIV_SHIFT; in stm32_clk_configure_obs() local
H A Dclk-stm32mp25.c1850 uint32_t div = (data & OBS_DIV_MASK) >> OBS_DIV_SHIFT; in stm32_clk_configure_obs() local
/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp25-clksrc.h48 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
70 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
229 #define OBS_CFG(id, status, int_ext, div, inv, sel)\ argument
259 #define OBS_INT_CFG(id, status, div, inv, sel)\ argument
262 #define OBS_EXT_CFG(id, status, div, inv, sel)\ argument
H A Dstm32mp21-clksrc.h43 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
182 #define OBS_CFG(id, status, int_ext, div, inv, sel)\ argument
212 #define OBS_INT_CFG(id, status, div, inv, sel)\ argument
215 #define OBS_EXT_CFG(id, status, div, inv, sel)\ argument
H A Dstm32mp13-clksrc.h67 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
/optee_os/core/drivers/i2c/
H A Datmel_i2c.c217 long div = 0; in atmel_i2c_init_clk() local
/optee_os/core/drivers/
H A Dimx_i2c.c199 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps; in i2c_set_prescaler() local