1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 16 #ifndef __PHYDMDIG_H__ 17 #define __PHYDMDIG_H__ 18 19 /*#define DIG_VERSION "1.4"*/ /* 2017.04.18 YuChen. refine DIG code structure*/ 20 /*#define DIG_VERSION "2.0"*/ /* 2017.05.09 Dino. Move CCKPD to new files*/ 21 /*#define DIG_VERSION "2.1"*/ /* 2017.06.01 YuChen. Refine DFS condition*/ 22 #define DIG_VERSION "2.2" /* 2017.06.13 YuChen. Remove MP dig*/ 23 24 #define DIG_HW 0 25 26 /*--------------------Define ---------------------------------------*/ 27 28 /*=== [DIG Boundary] ========================================*/ 29 /*DIG coverage mode*/ 30 #define DIG_MAX_COVERAGR 0x26 31 #define DIG_MIN_COVERAGE 0x1c 32 #define DIG_MAX_OF_MIN_COVERAGE 0x22 33 /*DIG performance mode*/ 34 #if (DIG_HW == 1) 35 #define DIG_MAX_BALANCE_MODE 0x32 36 #else 37 #define DIG_MAX_BALANCE_MODE 0x3e 38 #endif 39 #define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a 40 41 #define DIG_MAX_PERFORMANCE_MODE 0x5a 42 #define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x2a /*from 3E -> 2A, refine by YuChen 2017/04/18*/ 43 44 #define DIG_MIN_PERFORMANCE 0x20 45 46 /*DIG DFS function*/ 47 #define DIG_MAX_DFS 0x28 48 #define DIG_MIN_DFS 0x20 49 50 /*DIG LPS function*/ 51 #define DIG_MAX_LPS 0x3e 52 #define DIG_MIN_LPS 0x20 53 54 /*=== [DIG FA Threshold] ======================================*/ 55 56 /*Normal*/ 57 #define DM_DIG_FA_TH0 500 58 #define DM_DIG_FA_TH1 750 59 60 /*LPS*/ 61 #define DM_DIG_FA_TH0_LPS 4 /* -> 4 lps */ 62 #define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */ 63 #define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */ 64 65 #define RSSI_OFFSET_DIG_LPS 5 66 67 /*LNA saturation check*/ 68 #define OFDM_AGC_TAB_0 0 69 #define OFDM_AGC_TAB_2 2 70 #define DIFF_RSSI_TO_IGI 10 71 #define ONE_SEC_MS 1000 72 73 /*--------------------Enum-----------------------------------*/ 74 enum dig_goupcheck_level { 75 DIG_GOUPCHECK_LEVEL_0, 76 DIG_GOUPCHECK_LEVEL_1, 77 DIG_GOUPCHECK_LEVEL_2 78 }; 79 80 enum phydm_dig_mode { 81 PHYDM_DIG_PERFORAMNCE_MODE = 0, 82 PHYDM_DIG_COVERAGE_MODE = 1, 83 }; 84 85 enum lna_sat_timer_state { 86 INIT_LNA_SAT_CHK_TIMMER, 87 CANCEL_LNA_SAT_CHK_TIMMER, 88 RELEASE_LNA_SAT_CHK_TIMMER 89 }; 90 /*--------------------Define Struct-----------------------------------*/ 91 92 struct phydm_dig_struct { 93 94 boolean is_ignore_dig; /*for old pause function*/ 95 boolean is_dbg_fa_th; 96 u8 dig_mode_decision; 97 u8 cur_ig_value; 98 u8 rvrt_val; 99 u8 igi_backup; 100 u8 rx_gain_range_max; /*dig_dynamic_max*/ 101 u8 rx_gain_range_min; /*dig_dynamic_min*/ 102 u8 dm_dig_max; /*Absolutly upper bound*/ 103 u8 dm_dig_min; /*Absolutly lower bound*/ 104 u8 dig_max_of_min; /*Absolutly max of min*/ 105 boolean is_media_connect; 106 u32 ant_div_rssi_max; 107 u8 *is_p2p_in_process; 108 u8 pause_lv_bitmap; /*bit-map of pause level*/ 109 u8 pause_dig_value[PHYDM_PAUSE_MAX_NUM]; 110 enum dig_goupcheck_level dig_go_up_check_level; 111 u8 aaa_default; 112 u16 fa_th[3]; 113 #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) 114 u8 rf_gain_idx; 115 u8 agc_table_idx; 116 u8 big_jump_lmt[16]; 117 u8 enable_adjust_big_jump:1; 118 u8 big_jump_step1:3; 119 u8 big_jump_step2:2; 120 u8 big_jump_step3:2; 121 #endif 122 u8 dig_upcheck_initial_value; 123 u8 dig_level0_ratio_reciprocal; 124 u8 dig_level1_ratio_reciprocal; 125 #ifdef PHYDM_TDMA_DIG_SUPPORT 126 u8 cur_ig_value_tdma; 127 u8 low_ig_value; 128 u8 tdma_dig_state; /*To distinguish which state is now.(L-sate or H-state)*/ 129 u8 tdma_dig_cnt; /*for phydm_tdma_dig_timer_check use*/ 130 u8 pre_tdma_dig_cnt; 131 u8 sec_factor; 132 u32 cur_timestamp; 133 u32 pre_timestamp; 134 u32 fa_start_timestamp; 135 u32 fa_end_timestamp; 136 u32 fa_acc_1sec_timestamp; 137 #endif 138 }; 139 140 struct phydm_fa_struct { 141 u32 cnt_parity_fail; 142 u32 cnt_rate_illegal; 143 u32 cnt_crc8_fail; 144 u32 cnt_mcs_fail; 145 u32 cnt_ofdm_fail; 146 u32 cnt_ofdm_fail_pre; /* For RTL8881A */ 147 u32 cnt_cck_fail; 148 u32 cnt_all; 149 u32 cnt_all_pre; 150 u32 cnt_fast_fsync; 151 u32 cnt_sb_search_fail; 152 u32 cnt_ofdm_cca; 153 u32 cnt_cck_cca; 154 u32 cnt_cca_all; 155 u32 cnt_bw_usc; 156 u32 cnt_bw_lsc; 157 u32 cnt_cck_crc32_error; 158 u32 cnt_cck_crc32_ok; 159 u32 cnt_ofdm_crc32_error; 160 u32 cnt_ofdm_crc32_ok; 161 u32 cnt_ht_crc32_error; 162 u32 cnt_ht_crc32_ok; 163 u32 cnt_ht_crc32_error_agg; 164 u32 cnt_ht_crc32_ok_agg; 165 u32 cnt_vht_crc32_error; 166 u32 cnt_vht_crc32_ok; 167 u32 cnt_crc32_error_all; 168 u32 cnt_crc32_ok_all; 169 boolean cck_block_enable; 170 boolean ofdm_block_enable; 171 u32 dbg_port0; 172 boolean edcca_flag; 173 }; 174 175 #ifdef PHYDM_TDMA_DIG_SUPPORT 176 struct phydm_fa_acc_struct { 177 u32 cnt_parity_fail; 178 u32 cnt_rate_illegal; 179 u32 cnt_crc8_fail; 180 u32 cnt_mcs_fail; 181 u32 cnt_ofdm_fail; 182 u32 cnt_ofdm_fail_pre; /*For RTL8881A*/ 183 u32 cnt_cck_fail; 184 u32 cnt_all; 185 u32 cnt_all_pre; 186 u32 cnt_fast_fsync; 187 u32 cnt_sb_search_fail; 188 u32 cnt_ofdm_cca; 189 u32 cnt_cck_cca; 190 u32 cnt_cca_all; 191 u32 cnt_cck_crc32_error; 192 u32 cnt_cck_crc32_ok; 193 u32 cnt_ofdm_crc32_error; 194 u32 cnt_ofdm_crc32_ok; 195 u32 cnt_ht_crc32_error; 196 u32 cnt_ht_crc32_ok; 197 u32 cnt_vht_crc32_error; 198 u32 cnt_vht_crc32_ok; 199 u32 cnt_crc32_error_all; 200 u32 cnt_crc32_ok_all; 201 u32 cnt_all_1sec; 202 u32 cnt_cca_all_1sec; 203 u32 cnt_cck_fail_1sec; 204 }; 205 206 #endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 207 208 struct phydm_lna_sat_info_struct { 209 u32 sat_cnt_acc_patha; 210 u32 sat_cnt_acc_pathb; 211 u32 check_time; 212 boolean pre_sat_status; 213 boolean cur_sat_status; 214 struct timer_list phydm_lna_sat_chk_timer; 215 u32 cur_timer_check_cnt; 216 u32 pre_timer_check_cnt; 217 }; 218 219 /*--------------------Function declaration-----------------------------*/ 220 void 221 odm_write_dig( 222 void *p_dm_void, 223 u8 current_igi 224 ); 225 226 void 227 phydm_set_dig_val( 228 void *p_dm_void, 229 u32 *val_buf, 230 u8 val_len 231 ); 232 233 void 234 odm_pause_dig( 235 void *p_dm_void, 236 enum phydm_pause_type pause_type, 237 enum phydm_pause_level pause_level, 238 u8 igi_value 239 ); 240 241 void 242 phydm_dig_init( 243 void *p_dm_void 244 ); 245 246 void 247 phydm_dig( 248 void *p_dm_void 249 ); 250 251 void 252 phydm_dig_lps_32k( 253 void *p_dm_void 254 ); 255 256 void 257 phydm_dig_by_rssi_lps( 258 void *p_dm_void 259 ); 260 261 void 262 odm_false_alarm_counter_statistics( 263 void *p_dm_void 264 ); 265 266 #ifdef PHYDM_TDMA_DIG_SUPPORT 267 void 268 phydm_set_tdma_dig_timer( 269 void *p_dm_void 270 ); 271 272 void 273 phydm_tdma_dig_timer_check( 274 void *p_dm_void 275 ); 276 277 void 278 phydm_tdma_dig( 279 void *p_dm_void 280 ); 281 282 void 283 phydm_tdma_false_alarm_counter_check( 284 void *p_dm_void 285 ); 286 287 void 288 phydm_tdma_dig_add_interrupt_mask_handler( 289 void *p_dm_void 290 ); 291 292 void 293 phydm_false_alarm_counter_reset( 294 void *p_dm_void 295 ); 296 297 void 298 phydm_false_alarm_counter_acc( 299 void *p_dm_void, 300 boolean rssi_dump_en 301 ); 302 303 void 304 phydm_false_alarm_counter_acc_reset( 305 void *p_dm_void 306 ); 307 308 #endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 309 310 void 311 phydm_set_ofdm_agc_tab( 312 void *p_dm_void, 313 u8 tab_sel 314 ); 315 316 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 317 u8 318 phydm_get_ofdm_agc_tab( 319 void *p_dm_void 320 ); 321 322 void 323 phydm_lna_sat_chk( 324 void *p_dm_void 325 ); 326 327 void 328 phydm_lna_sat_chk_timers( 329 void *p_dm_void, 330 u8 state 331 ); 332 333 void 334 phydm_lna_sat_chk_watchdog( 335 void *p_dm_void 336 ); 337 338 #endif /*#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/ 339 340 void 341 phydm_dig_debug( 342 void *p_dm_void, 343 char input[][16], 344 u32 *_used, 345 char *output, 346 u32 *_out_len, 347 u32 input_num 348 ); 349 350 #endif 351